ADC input buffer with constant bias circuit and ADC

Abstract

The present invention relates to the field of integrated circuit technology, and more particularly to an ADC input buffer with a constant bias circuit and an ADC. The ADC input buffer includes a buffer circuit and a constant bias circuit; the buffer circuit adopts a push-pull architecture; the constant bias circuit is used to provide a constant bias current for the buffer circuit, and includes a first reference voltage branch, a second reference voltage branch, a common-mode stabilization branch, and a replica branch; wherein the first reference voltage branch and the second reference voltage branch are used to provide a reference bias voltage; the replica branch is used to replicate the reference bias voltage in the first reference voltage branch and the second reference voltage branch through a proportional current mirror and a proportional resistor, and output the replicated voltage to the buffer circuit; the common-mode stabilization branch is used to shunt current when there is a current mismatch in the replica branch, so that the buffer circuit has a constant output common-mode level. The present invention provides a low-power, high-linearity input buffer with automatic compensation for PVT variations.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an ADC input buffer with a constant bias circuit and an ADC. Background Art

[0002] Time-interleaved analog-to-digital converters (ADCs) are widely used for their high speed, wide bandwidth, high power efficiency, and moderate accuracy. However, time-interleaving technology places higher demands on the input signal's drive capability and ability to suppress nonlinearity. Currently, this issue is typically addressed by integrating a high-linearity input buffer into the front end of the ADC. As the front-end circuit of the ADC, the linearity of the input buffer theoretically determines the maximum achievable linearity of the ADC.

[0003] Most circuits are currently implemented using CMOS (complementary metal-oxide-semiconductor) technology due to its lower cost compared to other processes. However, devices implemented using CMOS technology experience significant parameter variations due to process and temperature variations, significantly impacting circuit performance. Furthermore, variations in the power supply voltage can also affect circuit performance. Therefore, a circuit's ability to withstand PVT (process, voltage, and temperature) variations determines the chip's yield rate. Furthermore, the input buffer's inherent structure and operating characteristics also affect its linearity. Currently, low input buffer linearity hinders ADC performance optimization. Therefore, to address these shortcomings, a more linear ADC input buffer is needed. Summary of the Invention

[0004] An object of the present invention is to provide an ADC input buffer with higher linearity to address at least some of the above-mentioned deficiencies.

[0005] To achieve the above object, the present invention provides an ADC input buffer with a constant bias circuit, comprising:

[0006] Buffer circuit, using push-pull architecture;

[0007] A constant bias circuit, for providing a constant bias current for the buffer circuit, includes a first reference voltage branch, a second reference voltage branch, a common-mode stabilization branch, and a replication branch; wherein the first reference voltage branch and the second reference voltage branch each include a constant bias current source and a reference voltage bias tube connected in a diode configuration, for providing a reference bias voltage; the replication branch is configured to replicate the reference bias voltages in the first reference voltage branch and the second reference voltage branch through a proportional current mirror and a proportional resistor, and output the replicated voltages to the buffer circuit, thereby achieving proportional replication of the bias current in the buffer circuit and the constant bias currents in the first reference voltage branch and the second reference voltage branch; the common-mode stabilization branch is configured to shunt current when there is a current mismatch in the replication branch, so that the buffer circuit has a constant output common-mode level.

[0008] Optionally, the first reference voltage branch includes: a first constant bias current source I bias1 , the first reference voltage bias tube M N1c , the first operational amplifier opamp1, the first current source tube M P3c , the first cascode transistor M P3d and the first reference resistor R 2c ;

[0009] Among them, the first reference voltage bias tube M N1c is an NMOS tube, the first current source tube M P3c and the first cascode transistor M P3d It is a PMOS tube;

[0010] The first constant bias current source I bias1 The high potential end is connected to the power supply VDD, and the low potential end is connected to the positive input terminal of the first operational amplifier opamp1 and the first reference voltage bias transistor M. N1c The drain and gate of the first reference voltage bias tube M N1c The source and body of the device are connected to the common ground vss;

[0011] The first current source tube M P3c The source and body of the first cascode transistor M P3d The body of the first current source tube M is connected to the power supply VDD. P3c The gate of the first reference voltage branch is connected to the output end of the first operational amplifier opamp1, serving as the output end of the first reference voltage branch;

[0012] The first cascode transistor M P3d The source of the first current source tube M is connected P3c The drain of the first cascode transistor M P3d The gate of the first cascode bias voltage Vbp , the first cascode transistor M P3d The drain of the first operational amplifier opamp1 is connected to the negative input terminal and connected to the first reference resistor R 2c Connecting public ground vss;

[0013] The second reference voltage branch includes: a second constant bias current source I bias2 , the second reference voltage bias tube M P1c , the second operational amplifier opamp2, the second current source tube M N3c , the second cascode transistor M N3d and the second reference resistor R 3c ;

[0014] Among them, the second reference voltage bias tube M P1c is a PMOS tube, the second current source tube M N3c and the second cascode transistor M N3d It is an NMOS tube;

[0015] The second reference voltage bias tube M P1c The source and body are connected to the power supply VDD, and the gate and drain are connected to the second constant bias current source I bias2 and the positive input terminal of the second operational amplifier opamp2, the second constant bias current source I bias2 The low potential end is connected to the common ground vss;

[0016] The second reference resistor R 3c One end is connected to the power supply VDD, and the other end is connected to the negative input terminal of the second operational amplifier opamp2 and the second common-source common-gate transistor M N3d The drain;

[0017] The second cascode transistor M N3d The gate of the second cascode bias voltage V bn , the body and the second current source tube M N3c The source and body of the device are connected to the common ground vss;

[0018] The second current source tube M N3c The drain of the second cascode transistor M is connected N3d The source of the second current source tube M N3c The gate of the transistor is connected to the output end of the second operational amplifier opamp2, serving as the output end of the second reference voltage branch.

[0019] Optionally, the replica branch includes a third current source transistor M P3 , the fourth current source tube M N3 , and a first voltage dividing resistor R1 to a fourth voltage dividing resistor R4;

[0020] Among them, the third current source tube M P3 is a PMOS tube, the fourth current source tube M N3 It is an NMOS tube;

[0021] The third current source tube M P3 The source and body of the third current source tube M are connected to the power supply vdd. P3 The drain of the fourth current source tube M is connected to the first voltage dividing resistor R1 to the fourth voltage dividing resistor R4 in series. N3 The drain of the fourth current source tube M N3 The source and body of the device are connected to the common ground vss;

[0022] The third current source tube M P3 The gate of the fourth current source tube M is connected to the output end of the first reference voltage branch, N3 The gate is connected to the output end of the second reference voltage branch;

[0023] The third current source tube M P3 The drain voltage of the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2, the node voltage between the third voltage-dividing resistor R3 and the fourth voltage-dividing resistor R4, the fourth current source transistor M N3 The drain voltage is used as the first bias voltage of the output A , the second bias voltage V B , the third bias voltage V D , the fourth bias voltage V E The buffer circuit is connected.

[0024] Optionally, the common-mode stabilization branch includes a first shunt resistor R b1 and the second shunt resistor R b2 ;

[0025] The first shunt resistor R b1 and the second shunt resistor R b2 Connected in series between the power supply VDD and the common ground VSS, the first shunt resistor R b1 and the second shunt resistor R b2 The node between them is connected to the node between the second voltage-dividing resistor R2 and the third voltage-dividing resistor R3 in the replica branch.

[0026] Optionally, the common-mode stabilization branch includes a third constant bias current source I bias3 , the first bias resistor R b3 and the second bias resistor R b4 ;

[0027] The third constant bias current source I bias3 The high potential end is connected to the power supply vdd, and the low potential end is connected in series with the first bias resistor R b3 and the second bias resistor R b4 Connect the common ground vss, the first bias resistor R b3 and the second bias resistor R b4 The node between them is connected to the node between the second voltage-dividing resistor R2 and the third voltage-dividing resistor R3 in the replica branch.

[0028] Optionally, the buffer circuit includes: a first push-pull source follower transistor M N1a , the second push-pull source follower tube M P1a , the third push-pull source follower tube M N1b , the fourth push-pull source follower tube M P1b , the first bias tube M N2a , the second bias tube M P2a , the third bias tube M N2b , the fourth bias tube M P2b , first to eighth DC blocking capacitors, and first to eighth DC blocking resistors;

[0029] Among them, the first push-pull source follower tube M N1a , the third push-pull source follower tube M N1b , the first bias tube M N2a and the third bias tube M N2b It is an NMOS tube, and the second push-pull source follower tube M P1a , the fourth push-pull source follower tube M P1b , the second bias tube M P2a and the fourth bias tube M P2b It is a PMOS tube;

[0030] The first bias tube M N2a The drain is connected to the power supply VDD, and the source and body are connected to the first push-pull source follower tube M N1a The drain of the first push-pull source follower tube M N1a The source and body of the second push-pull source follower tube M are connected P1a The source and body of the second push-pull source follower tube M P1a The drain of the second bias tube M is connected P2a The source and body of the second bias tube M P2a The drain is connected to the common ground vss;

[0031] The first DC blocking capacitor is connected to the first bias transistor M N2a The gate of the first push-pull source follower tube M N1aThe second DC blocking capacitor and the third DC blocking capacitor are connected in series to the gate of the first push-pull source follower tube M. N1a The gate and the second push-pull source follower tube M P1a The fourth DC blocking capacitor is connected between the gates of the second push-pull source follower tube M P1a The gate of the second bias tube M P2a between the gates;

[0032] The first bias tube M N2a The gate is connected to the first bias voltage V through the first DC blocking resistor A , the first push-pull source follower tube M N1a The gate is connected to the second bias voltage V through the second DC blocking resistor B The second push-pull source follower tube M P1a The gate of the MOSFET is connected to the third bias voltage V via a third DC blocking resistor. D , the second bias tube M P2a The gate of the MOSFET is connected to the fourth bias voltage V via a fourth DC blocking resistor. E ;

[0033] The third bias tube M N2b The drain is connected to the power supply VDD, and the source and body are connected to the third push-pull source follower tube M N1b The drain of the third push-pull source follower tube M N1b The source and body of the fourth push-pull source follower tube M are connected P1b The source and body of the fourth push-pull source follower tube M P1b The drain of the fourth bias transistor M is connected P2b The source and body of the fourth bias tube M P2b The drain is connected to the common ground vss;

[0034] The fifth DC blocking capacitor is connected to the third bias transistor M N2b The gate of the third push-pull source follower tube M N1b The sixth and seventh DC blocking capacitors are connected in series between the gates of the third push-pull source follower transistor M. N1b The gate of the fourth push-pull source follower tube M P1b The eighth DC blocking capacitor is connected between the gates of the fourth push-pull source follower transistor M P1b The gate of the fourth bias tube M P2b between the gates;

[0035] The third bias tube M N2b The gate is connected to the first bias voltage V through the fifth DC blocking resistor b The third push-pull source follower tube MN1b The gate is connected to the second bias voltage V through the sixth DC blocking resistor B The fourth push-pull source follower tube M P1b The gate of the MOSFET is connected to the third bias voltage V via a seventh DC blocking resistor. D , the fourth bias tube M P2b The gate of the MOSFET is connected to the fourth bias voltage V via an eighth DC blocking resistor. E ;

[0036] The first differential signal input terminal V inn Connected between the second DC blocking capacitor and the third DC blocking capacitor, the second differential signal input terminal V inp Connected between the sixth DC blocking capacitor and the seventh DC blocking capacitor, the first differential signal output terminal V outn Connect the first push-pull source follower tube M N1a The source of the second differential signal output terminal V outp Connect the third push-pull source follower tube M N1b The source.

[0037] Optionally, the reference bias voltages in the first reference voltage branch and the second reference voltage branch are replicated by using a proportional current mirror and a proportional resistor, meeting the following requirements:

[0038] P(M P3c ) / P(M P3 )=R2 / R 2c =P(M N3c ) / P(M N3 )=R3 / R 3c

[0039] The following requirements are met between the replica branch and the buffer circuit:

[0040] V GS (M N2a / b ):V GS (M N1a / b ):V GS (M P1a / b ):V GS (M P2a / b )=R1:R2:R3:R4

[0041] Where P(M*) represents the aspect ratio of transistor M*, V GS (M*) represents the gate-source voltage of transistor M*.

[0042] The present invention further provides an ADC, comprising: an ADC input buffer with a constant bias circuit as described in any one of the above items.

[0043] The above technical solution of the present invention has the following advantages: the present invention provides an ADC input buffer with a constant bias circuit, which adopts a push-pull architecture buffer circuit with higher current efficiency and better linearity, effectively reducing power consumption and improving linearity. At the same time, the constant bias circuit is used to provide the buffer circuit with a constant bias current and output common-mode level that do not fluctuate with PVT, ultimately obtaining a highly linear, efficient, and robust input buffer.

[0044] The present invention also provides an ADC, which uses the above-mentioned ADC input buffer with a constant bias circuit to implement input buffering, and has the advantages of low power consumption, high linearity, and insensitivity to process, voltage deviation and temperature changes. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a schematic diagram of a constant bias circuit in an embodiment of the present invention;

[0046] Figure 2 is a schematic diagram of a common-mode stabilization branch in an embodiment of the present invention;

[0047] Figure 3 2 is a schematic diagram of a buffer circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0049] As mentioned earlier, as the front-end circuit of an ADC, the linearity of the input buffer theoretically determines the maximum linearity the ADC can achieve. Currently, most circuits are implemented using CMOS processes. However, due to process variations and temperature fluctuations, CMOS devices experience significant parameter variations, significantly impacting circuit performance. Furthermore, power supply voltage variations can also affect circuit performance. Therefore, the circuit's ability to withstand PVT variations determines the chip's yield.

[0050] The most basic input buffer structure is a source follower. For input signals with a certain amplitude, voltage fluctuations between the drain and source terminals of the source follower input transistor will severely degrade the linearity of the output signal. Furthermore, the source follower output must drive a load of a certain size, which draws current from the source follower, further degrading linearity.

[0051] In view of this, in order to overcome the shortcomings of the existing input buffer circuit that is easily affected by PVT fluctuations and has low linearity, the present invention provides a low-power and high-linearity input buffer with PVT compensation function.

[0052] like Figures 1 to 3 As shown, the present invention provides an ADC input buffer with a constant bias circuit, comprising: a buffer circuit and a constant bias circuit; specifically, the buffer circuit adopts a push-pull architecture; the constant bias circuit is used to provide a constant bias current for the buffer circuit, and comprises a first reference voltage branch, a second reference voltage branch, a common-mode stabilization branch 100 and a replica branch; wherein, the first reference voltage branch and the second reference voltage branch each comprise a constant bias current source and a reference voltage bias tube using a diode connection, for providing a reference bias voltage; the replica branch is connected to the first reference voltage branch and the second reference voltage branch. Both reference voltage branches are connected and used to replicate the reference bias voltages in the first reference voltage branch and the second reference voltage branch through a proportional current mirror and a proportional resistor, and output them to the buffer circuit to achieve proportional replication of the bias current in the buffer circuit and the constant bias current in the first reference voltage branch and the second reference voltage branch, ultimately ensuring that the bias current of the buffer circuit is not affected by PVT changes; the common-mode stabilization branch is connected to the replication branch and is used to shunt current when there is a current mismatch in the replication branch, so that the buffer circuit has a constant output common-mode level.

[0053] In the present invention, the buffer circuit adopts a push-pull architecture. The differential input signal is AC-coupled to the input of the source follower structure through a DC blocking capacitor. The DC operating level at the gate end is provided by a constant bias circuit. The source follower structure converts the level signal into an output signal to charge and discharge the output load sampling capacitor. The push-pull architecture is widely used in the design of modules such as amplifiers and source followers. It plays the role of multiplexing the transconductance of N-type devices and P-type devices. Under the same current consumption, the transconductance effect of the two is superimposed at the output end. Therefore, the push-pull architecture can theoretically achieve twice the current efficiency of the traditional unilateral structure, making the input buffer have lower power consumption and higher linearity. However, at the same time, the push-pull architecture is more prone to fluctuations due to PVT. If the input end uses a constant bias voltage, PVT fluctuations may cause up to 50% output current deviation. In this case, the linearity of the input buffer will be significantly deteriorated at high-frequency input. In order to solve the impact of PVT fluctuations on linearity performance in a push-pull architecture, the present invention adopts a constant bias circuit to input a bias voltage to the input end of the buffer circuit. The constant bias circuit generates a reference bias voltage through a reference voltage bias tube using a constant bias current that is independent of PVT, and generates an input bias voltage for the source follower in the buffer circuit through a proportional current mirror and a proportional resistor. This allows the bias current obtained by the buffer circuit to maintain good stability under PVT fluctuations, ultimately achieving low power consumption and a high-linearity input buffer with automatic compensation functions for process, voltage and temperature changes.

[0054] Alternatively, as Figure 1 As shown, the first reference voltage branch includes: a first constant bias current source I bias1 , the first reference voltage bias tube M N1c , the first operational amplifier opamp1, the first current source tube M P3c , the first cascode transistor M P3d and the first reference resistor R 2c ;

[0055] Among them, the first reference voltage bias tube M N1c It is an NMOS tube, that is, a reference voltage bias tube using a diode connection, and the first current source tube M P3c and the first cascode transistor M P3d It is a PMOS tube;

[0056] The first constant bias current source I bias1 Used to provide a constant bias current in the first reference voltage branch; the first constant bias current source I bias1 The high potential end is connected to the power supply VDD, and the low potential end is connected to the positive input terminal of the first operational amplifier opamp1 and the first reference voltage bias transistor M. N1c The drain and gate of the first reference voltage bias tube M N1cThe source and body of the device are connected to the common ground vss;

[0057] The first current source tube M P3c The source and body of the first cascode transistor M P3d The body electrodes are connected to the power supply vdd, the first current source tube M P3c The gate is connected to the output end of the first operational amplifier opamp1, serving as the output end of the first reference voltage branch;

[0058] The first cascode transistor M P3d The source of the first current source tube M is connected P3c The drain of the first cascode tube M P3d The gate of the first cascode bias voltage V bp , the first cascode transistor M P3d The drain of the first operational amplifier opamp1 is connected to the negative input terminal and connected to the first reference resistor R 2c Connecting public ground vss;

[0059] The second reference voltage branch includes: a second constant bias current source I bias2 , the second reference voltage bias tube M P1c , the second operational amplifier opamp2, the second current source tube M N3c , the second cascode transistor M N3d and the second reference resistor R 3c ;

[0060] Among them, the second reference voltage bias tube M P1c It is a PMOS tube, that is, a reference voltage bias tube using a diode connection, and the second current source tube M N3c and the second cascode transistor M N3d It is an NMOS tube;

[0061] The second constant bias current source I bias2 Used to provide a constant bias current in the first reference voltage branch; the second reference voltage bias tube M P1c The source and body of the tube are connected to the power supply vdd, and the second reference voltage bias tube M P1c The gate and drain of the bias2 and the positive input terminal of the second operational amplifier opamp2, the second constant bias current source I bias2 The low potential end is connected to the common ground vss;

[0062] The second reference resistor R 3c One end is connected to the power supply VDD, and the other end is connected to the negative input terminal of the second operational amplifier opamp2 and the second common source common gate transistor M N3d The drain;

[0063] The second cascode transistor M N3d The gate of the second cascode bias voltage V bn , the second cascode transistor M N3d The body of the second current source tube M N3c The source and body of the device are both connected to the common ground vss;

[0064] The second current source tube M N3c The drain of the second cascode transistor M N3d The source of the second current source tube M N3c The gate of is connected to the output end of the second operational amplifier opamp2, serving as the output end of the second reference voltage branch.

[0065] Among them, the first cascode transistor M P3d and the second cascode transistor M N3d It is a cascode tube, used to improve the current mirror replication accuracy. The first cascode bias voltage V bp and the second cascode bias voltage V bn is the corresponding bias voltage of the cascode tube. The first constant bias current source I bias1 , the second constant bias current source I bias2 The current is independent of PVT and can be generated using a bandgap reference circuit.

[0066] Furthermore, the replica branch includes a third current source transistor M P3 , the fourth current source tube M N3 , and a first voltage dividing resistor R1 to a fourth voltage dividing resistor R4;

[0067] Among them, the third current source tube M P3 is a PMOS tube, the fourth current source tube M N3 It is an NMOS tube;

[0068] The third current source tube M P3 The source and body of the third current source tube M are connected to the power supply vdd. P3 The drain of the fourth current source tube M is connected to the first voltage dividing resistor R1 to the fourth voltage dividing resistor R4 in series. N3 The drain of the fourth current source tube M N3 The source and body of the device are connected to the common ground vss;

[0069] The third current source tube M P3 The gate of the fourth current source tube M is connected to the output end of the first reference voltage branch, that is, connected to the output end of the first operational amplifier opamp1. N3 The gate is connected to the output end of the second reference voltage branch, that is, connected to the output end of the second operational amplifier opamp2;

[0070] The third current source tube MP3 The drain voltage of the first voltage-dividing resistor R1, the node voltage between the second voltage-dividing resistor R2, the node voltage between the third voltage-dividing resistor R3 and the fourth voltage-dividing resistor R4, the fourth current source transistor M N3 The drain voltage is used as the first bias voltage V of the corresponding output A , the second bias voltage V B , the third bias voltage V D , the fourth bias voltage V E Connect to the buffer circuit.

[0071] In the above embodiment, the first constant bias current source I bias1 and the second constant bias current source I bias2 The currents are respectively passed through the first reference voltage bias tube M connected in a diode structure. N1c and the second reference voltage bias tube M P1c , we get two reference tubes (i.e. M N1c and M P1c ) bias voltage, for convenience of explanation, M N1c and M P1c The bias voltages are named as the first reference voltage VN (VN = V GS (M N1c ), which is M N1c The gate-source voltage) and the first reference voltage VP (VP = V GS (M P1c ), which is M P1c The first reference voltage VN and the first reference voltage VP can be copied to the first reference resistor R respectively through two operational amplifiers with negative feedback structure (i.e., the first operational amplifier opamp1 and the second operational amplifier opamp2). 2c and the second reference resistor R 3c One end of the proportional current mirror first current source tube M P3c and the third current source tube M P3 , and the second current source tube M N3c and the fourth current source tube M N3 Respectively realize the proportional replication of current, at the same time, the first reference resistor R 2c and the second voltage divider resistor R2, and the second reference resistor R 3c The third voltage-dividing resistor R3 is matched in proportion to each other, satisfying the following relationship:

[0072]

[0073]

[0074] Among them, R 2c represents the resistance value of the first reference resistor, Represents the first current source tube M P3c The current in, R2 represents the resistance of the second voltage divider resistor, Represents the third current source tube M P3 The current in R 3c represents the resistance value of the second reference resistor, Represents the second current source tube M N3c The current in the circuit is R3, which represents the resistance of the third voltage divider resistor. Represents the fourth current source tube M N3 That is, the first current source tube M P3c , the second current source tube M N3c , the third current source tube M P3 and the fourth current source tube M N3 A proportional current mirror is formed, and the proportional resistor includes a first reference resistor R 2c , the second reference resistor R 3c , a second voltage-dividing resistor R2 and a third voltage-dividing resistor R3. MP3 =I MN3 , if there is a current mismatch, it will flow into the common-mode stabilization branch.

[0075] Furthermore, the reference bias voltages in the first reference voltage branch and the second reference voltage branch are replicated by using a proportional current mirror and a proportional resistor, meeting the following requirements:

[0076] P(M P3c ) / P(M P3 )=R2 / R 2c =P(M N3c ) / P(M N3 )=R3 / R 3c

[0077] The following requirements are met between the replica branch and the buffer circuit:

[0078] V GS (M N2a / b ):V GS (M N1a / b ):V GS (M P1a / b ):V GS (M P2a / b )=R1:R2:R3:R4

[0079] Where P(M*) represents the aspect ratio of transistor M*, V GS (M*) represents the gate-source voltage of transistor M*; M N1a / b Indicates M N1a or M N1b , V GS (MN1a )=V GS (M N1b );M N2a / b Indicates M N2a or M N2b , V GS (M N2a )=V GS (M N2b );M P1a / b Indicates M P1a or M P1b , V GS (M P1a )=V GS (M P1b );M P2a / b Indicates M P2a or M P2b , V GS (M P2a )=V GS (M P2b ), R1 to R4 represent the resistance values ​​of the first voltage-dividing resistor to the fourth voltage-dividing resistor respectively.

[0080] Finally, the input bias voltage of the source follower in the buffer circuit is generated to include the second bias voltage V B and the third bias voltage V D At this time, the buffer circuit only needs to proportionally amplify the reference voltage branch. Under the same bias voltage and threshold voltage, the source follower tube can proportionally copy the constant bias current in the reference voltage branch, and finally obtain a constant bias current that can maintain good stability under PVT fluctuations.

[0081] Alternatively, as Figure 1 As shown, the common-mode stabilization branch 100 includes a first shunt resistor R b1 and the second shunt resistor R b2 ; Among them, the first shunt resistor R b1 and the second shunt resistor R b2 Connected in series, between the power supply VDD and the common ground VSS, the first shunt resistor R b1 and the second shunt resistor R b2 The node between them is connected to the node between the second voltage-dividing resistor R2 and the third voltage-dividing resistor R3 in the replica branch.

[0082] Furthermore, the first shunt resistor R b1 and the second shunt resistor R b2 The resistance value satisfies R b2 / (R b1 +R b2 )=V cm / V dd , V dd Indicates the power supply voltage, Vcm The buffer circuit is designed to output the common mode voltage. The first shunt resistor R b1 , the second shunt resistor R b2 The resistance value of the first shunt resistor R1 to the fourth shunt resistor R4 is generally much smaller than that of the first shunt resistor R1 to the fourth shunt resistor R4, so that the first shunt resistor R b1 and the second shunt resistor R b2 The current in the resistor R1 is much larger than the current in the first to fourth voltage-dividing resistors R1 to R4.

[0083] The first shunt resistor R b1 and the second shunt resistor R b2 The purpose is to avoid the first reference resistor R 2c , the second reference resistor R 3c , the mismatch between the first voltage-dividing resistor R1 to the fourth voltage-dividing resistor R4, and the first current source transistor M P3c With the third current source tube M P3 , and the second current source tube M N3c With the fourth current source tube M N3 The mismatch of the input buffer affects the output common mode point. When the replica branch generates V C The voltage level (i.e., the node level between the second voltage divider resistor R2 and the third voltage divider resistor R3, also known as the output reference common mode level) deviates from the designed output common mode voltage V cm When the first shunt resistor R b1 and the second shunt resistor R b2 The design current is much larger than the above bias branch current, so V C The current of the level shift design value will flow from the first shunt resistor R b1 and the second shunt resistor R b2 The common mode stabilization branch 100 flows away and eventually forms V C The level is relatively stable and close to V cm .

[0084] Figure 1 The common-mode stabilization branch 100 shown in FIG is implemented by power supply voltage division, which can alleviate the influence of power supply voltage deviation on the linearity of the input buffer. However, at this time, the output common mode of the input buffer changes with the change of the power supply voltage.

[0085] If you need to achieve a fixed output common mode level design, you can use Figure 2 Another common-mode stabilization branch shown includes a third constant bias current source I bias3 , the first bias resistor R b3 and the second bias resistor R b4 ; Wherein, the third constant bias current source I bias3 The high potential end is connected to the power supply vdd, and the low potential end is connected to the first bias resistor Rb3 and the second bias resistor R b4 Connect the common ground vss, the first bias resistor R b3 and the second bias resistor R b4 The node between the second voltage divider resistor R2 and the third voltage divider resistor R3 in the replica branch is connected, that is, the node between V C level.

[0086] In the above embodiment, a third constant bias current source I is used which is independent of PVT. bias3 Achieve PVT constant output common mode I bias3 ·R b4 .

[0087] Alternatively, as Figure 3 As shown, the buffer circuit of the ADC input buffer includes: a first push-pull source follower transistor M N1a , the second push-pull source follower tube M P1a , the third push-pull source follower tube M N1b , the fourth push-pull source follower tube M P1b , the first bias tube M N2a , the second bias tube M P2a , the third bias tube M N2b , the fourth bias tube M P2b , first to eighth DC blocking capacitors, and first to eighth DC blocking resistors;

[0088] Among them, the first push-pull source follower tube M N1a , the third push-pull source follower tube M N1b , the first bias tube M N2a and the third bias tube M N2b It is an NMOS tube, and the second push-pull source follower tube M P1a , the fourth push-pull source follower tube M P1b , the second bias tube M P2a and the fourth bias tube M P2b It is a PMOS tube;

[0089] The first bias tube M N2a The drain of the first bias tube M is connected to the power supply VDD. N2a The source and body of the first push-pull source follower tube M N1a The drain of the first push-pull source follower tube M N1a The source and body of the second push-pull source follower tube M P1a The source and body of the second push-pull source follower tube M P1a The drain of the second bias tube M P2a The source and body of the second bias tube M P2a The drain is connected to the common ground vss;

[0090] The first DC blocking capacitor C 01a Connected to the first bias tube M N2a The gate of the first push-pull source follower tube M N1a The second DC blocking capacitor C 02a and the third DC blocking capacitor C 03a In series, connected to the first push-pull source follower tube M N1a The gate of the second push-pull source follower tube M P1a The fourth DC blocking capacitor C 04a Connect to the second push-pull source follower tube M P1a The gate and the second bias tube M P2a between the gates;

[0091] The first bias tube M N2a The gate of the 01a Connect the first bias voltage V A , the first push-pull source follower tube M N1a The gate of the 02a Connect the second bias voltage V B , the second push-pull source follower tube M P1a The gate of the 03a Connect the third bias voltage V D , the second bias tube M P2a The gate of the 04a Connect the fourth bias voltage V E That is, the first DC blocking resistor R 01a One end is connected to the first bias tube M N2a The other end is connected to the gate of the third current source tube M P3 The drain, the second DC blocking resistor R 02a One end is connected to the first push-pull source follower tube M N1a The other end is connected to the node between the first voltage divider resistor R1 and the second voltage divider resistor R2, and the third DC blocking resistor R 03a One end is connected to the second push-pull source follower tube M P1a The other end is connected to the node between the third voltage divider resistor R3 and the fourth voltage divider resistor R4, and the fourth DC blocking resistor R 04a One end is connected to the second bias tube M P2a The gate of the fourth current source tube M is connected to the other end. N3 The drain;

[0092] The third bias tube M N2b The drain of the third bias tube M is connected to the power supply VDD. N2b The source and body of the third push-pull source follower tube M N1b The drain of the third push-pull source follower tube M N1bThe source and body of the fourth push-pull source follower tube M P1b The source and body of the fourth push-pull source follower tube M P1b The drain of the fourth bias tube M is connected P2b The source and body of the fourth bias tube M P2b The drain is connected to the common ground vss;

[0093] Fifth DC blocking capacitor C 01b Connected to the third bias tube M N2b The gate of the third push-pull source follower tube M N1b The sixth DC blocking capacitor C 02b And the seventh DC blocking capacitor C 03b Series, connected to the third push-pull source follower tube M N1b The gate of the fourth push-pull source follower tube M P1b Between the gates, the eighth DC blocking capacitor C 04b Connect to the fourth push-pull source follower tube M P1b The gate of the fourth bias tube M P2b between the gates;

[0094] The third bias tube M N2b The gate of the 01b Connect the first bias voltage V b , the third push-pull source follower tube M N1b The gate of the 02b Connect the second bias voltage V B , the fourth push-pull source follower tube M P1b The gate of the 03b Connect the third bias voltage V D , the fourth bias tube M P2b The gate of the 04b Connect the fourth bias voltage V E ;

[0095] The first differential signal input terminal V inn Connect the second DC blocking capacitor C 02a and the third DC blocking capacitor C 03a Between the second differential signal input terminal V inp Connect the sixth DC blocking capacitor C 02b And the seventh DC blocking capacitor C 03b Between, the first differential signal output terminal V outn Connect the first push-pull source follower tube M N1a The source of the second differential signal output terminal V outp Connect the third push-pull source follower tube M N1b The source.

[0096] In the above embodiment, in order to improve the linearity of the source follower, the first bias transistor M N2a , the second bias tube M P2a , the third bias tube M N2b and the fourth bias tube M P2b Used to reduce the source follower tube (ie M N1a 、M N1b 、M P1a and M P1b ) of V DS (ie, drain-source voltage) fluctuates. The first bias transistor M N2a and the third bias tube M N2b The bias voltage (ie the first bias voltage V A ), and the second bias tube M P2a and the fourth bias tube M P2b The bias voltage (ie, the fourth bias voltage V E ) is determined by the ratio of the first voltage-dividing resistor R1 to the fourth voltage-dividing resistor R4.

[0097] In particular, the present invention further provides an ADC, comprising an ADC input buffer with a constant bias circuit as described in any of the above embodiments. The ADC input buffer provided by the present invention is used as the front-end circuit of the ADC to implement input buffering, thereby obtaining an ADC with better performance, low power consumption, high linearity, and insensitivity to process, voltage deviation, and temperature changes.

[0098] In summary, the present invention provides an ADC input buffer with a constant bias circuit and an ADC. The ADC input buffer adopts a push-pull architecture that has high current utilization but is sensitive to PVT. At the same time, a PVT constant bias circuit is used to compensate for the input buffer to achieve high linearity, high efficiency, and good robustness, providing technical support for achieving higher-performance ADCs.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. An ADC input buffer with a constant bias circuit, characterized in that: include: Buffer circuit, using push-pull architecture; a constant bias circuit for providing a constant bias current for the buffer circuit, comprising a first reference voltage branch, a second reference voltage branch, a common-mode stabilization branch, and a replication branch; wherein the first reference voltage branch and the second reference voltage branch each comprise a constant bias current source and a diode-connected reference voltage bias transistor for providing a reference bias voltage; the replication branch is configured to replicate the reference bias voltages in the first and second reference voltage branches via a proportional current mirror and a proportional resistor, and output the replicated values ​​to the buffer circuit, thereby achieving proportional replication of the bias current in the buffer circuit and the constant bias currents in the first and second reference voltage branches; the common-mode stabilization branch is configured to shunt current when there is a current mismatch in the replication branch, thereby ensuring that the buffer circuit has a constant output common-mode level; The first reference voltage branch includes: a first constant bias current source I bias1 , the first reference voltage bias tube M N1c , the first operational amplifier opamp1, the first current source tube M P3c , the first cascode transistor M P3d and the first reference resistor R 2c ; Among them, the first reference voltage bias tube M N1c is an NMOS tube, the first current source tube M P3c and the first cascode transistor M P3d It is a PMOS tube; The first constant bias current source I bias1 The high potential end is connected to the power supply VDD, and the low potential end is connected to the positive input terminal of the first operational amplifier opamp1 and the first reference voltage bias transistor M. N1c The drain and gate of the first reference voltage bias tube M N1c The source and body of the device are connected to the common ground vss; The first current source tube M P3c The source and body of the first cascode transistor M P3d The body of the first current source tube M is connected to the power supply VDD. P3c The gate of the first reference voltage branch is connected to the output end of the first operational amplifier opamp1, serving as the output end of the first reference voltage branch; The first cascode transistor M P3d The source of the first current source tube M is connected P3c The drain of the first cascode transistor M P3d The gate of the first cascode bias voltage V bp , the first cascode transistor M P3d The drain of the first operational amplifier opamp1 is connected to the negative input terminal and connected to the first reference resistor R 2c Connecting public ground vss; The second reference voltage branch includes: a second constant bias current source I bias2 , the second reference voltage bias tube M P1c , the second operational amplifier opamp2, the second current source tube M N3c , the second cascode transistor M N3d and the second reference resistor R 3c ; Among them, the second reference voltage bias tube M P1c is a PMOS tube, the second current source tube M N3c and the second cascode transistor M N3d It is an NMOS tube; The second reference voltage bias tube M P1c The source and body are connected to the power supply VDD, and the gate and drain are connected to the second constant bias current source I bias2 and the positive input terminal of the second operational amplifier opamp2, the second constant bias current source I bias2 The low potential end is connected to the common ground vss; The second reference resistor R 3c One end is connected to the power supply VDD, and the other end is connected to the negative input terminal of the second operational amplifier opamp2 and the second common-source common-gate transistor M N3d The drain; The second cascode transistor M N3d The gate of the second cascode bias voltage V bn , the body and the second current source tube M N3c The source and body of the device are connected to the common ground vss; The second current source tube M N3c The drain of the second cascode transistor M is connected N3d The source of the second current source tube M N3c The gate of the second reference voltage branch is connected to the output end of the second operational amplifier opamp2, serving as the output end of the second reference voltage branch; Among them, the first cascode transistor M P3d and the second cascode transistor M N3d It is a cascode tube, used to improve the current mirror replication accuracy; the first constant bias current source I bias1 , the second constant bias current source I bias2 The current is independent of PVT, and the constant bias circuit generates a reference bias voltage through a reference voltage bias tube using a constant bias current independent of PVT, and generates an input bias voltage of a source follower in a buffer circuit through a proportional current mirror and a proportional resistor, so that the bias current obtained by the buffer circuit is not affected by PVT fluctuations; The replica branch includes a third current source tube M P3 , the fourth current source tube M N3 , and a first voltage dividing resistor R1 to a fourth voltage dividing resistor R4; Among them, the third current source tube M P3 is a PMOS tube, the fourth current source tube M N3 It is an NMOS tube; The third current source tube M P3 The source and body of the third current source tube M are connected to the power supply vdd. P3 The drain of the fourth current source tube M is connected to the first voltage dividing resistor R1 to the fourth voltage dividing resistor R4 in series. N3 The drain of the fourth current source tube M N3 The source and body of the device are connected to the common ground vss; The third current source tube M P3 The gate of the fourth current source tube M is connected to the output end of the first reference voltage branch, N3 The gate is connected to the output end of the second reference voltage branch; The third current source tube M P3 The drain voltage of the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2, the node voltage between the third voltage-dividing resistor R3 and the fourth voltage-dividing resistor R4, the fourth current source transistor M N3 The drain voltage is used as the first bias voltage of the output A , the second bias voltage V B , the third bias voltage V D , the fourth bias voltage V E accessing the buffer circuit; The common mode stabilization branch includes a third constant bias current source I bias3 , the first bias resistor R b3 and the second bias resistor R b4 ; The third constant bias current source I bias3 The high potential end is connected to the power supply vdd, and the low potential end is connected in series with the first bias resistor R b3 and the second bias resistor R b4 Connect the common ground vss, the first bias resistor R b3 and the second bias resistor R b4 The node between the second voltage-dividing resistor R2 and the third voltage-dividing resistor R3 in the replica branch is connected; a third constant bias current source I is used which is independent of PVT. bias3 Further achieving a fixed output common mode level.

2. The ADC input buffer according to claim 1, wherein: The common mode stabilization branch includes a first shunt resistor R b1 and the second shunt resistor R b2 ; The first shunt resistor R b1 and the second shunt resistor R b2 Connected in series between the power supply VDD and the common ground VSS, the first shunt resistor R b1 and the second shunt resistor R b2 The node between them is connected to the node between the second voltage-dividing resistor R2 and the third voltage-dividing resistor R3 in the replica branch.

3. The ADC input buffer according to claim 1, wherein: The buffer circuit includes: a first push-pull source follower transistor M N1a , the second push-pull source follower tube M P1a , the third push-pull source follower tube M N1b , the fourth push-pull source follower tube M P1b , the first bias tube M N2a , the second bias tube M P2a , the third bias tube M N2b , the fourth bias tube M P2b , first to eighth DC blocking capacitors, and first to eighth DC blocking resistors; Among them, the first push-pull source follower tube M N1a , the third push-pull source follower tube M N1b , the first bias tube M N2a and the third bias tube M N2b It is an NMOS tube, and the second push-pull source follower tube M P1a , the fourth push-pull source follower tube M P1b , the second bias tube M P2a and the fourth bias tube M P2b It is a PMOS tube; The first bias tube M N2a The drain is connected to the power supply VDD, and the source and body are connected to the first push-pull source follower tube M N1a The drain of the first push-pull source follower tube M N1a The source and body of the second push-pull source follower tube M are connected P1a The source and body of the second push-pull source follower tube M P1a The drain of the second bias tube M is connected P2a The source and body of the second bias tube M P2a The drain is connected to the common ground vss; The first DC blocking capacitor is connected to the first bias transistor M N2a The gate of the first push-pull source follower tube M N1a The second DC blocking capacitor and the third DC blocking capacitor are connected in series to the gate of the first push-pull source follower tube M. N1a The gate and the second push-pull source follower tube M P1a The fourth DC blocking capacitor is connected between the gates of the second push-pull source follower tube M P1a The gate of the second bias tube M P2a between the gates; The first bias tube M N2a The gate is connected to the first bias voltage V through the first DC blocking resistor A , the first push-pull source follower tube M N1a The gate is connected to the second bias voltage V through the second DC blocking resistor B The second push-pull source follower tube M P1a The gate of the MOSFET is connected to the third bias voltage V via a third DC blocking resistor. D , the second bias tube M P2a The gate of the MOSFET is connected to the fourth bias voltage V via a fourth DC blocking resistor. E ; The third bias tube M N2b The drain is connected to the power supply VDD, and the source and body are connected to the third push-pull source follower tube M N1b The drain of the third push-pull source follower tube M N1b The source and body of the fourth push-pull source follower tube M are connected P1b The source and body of the fourth push-pull source follower tube M P1b The drain of the fourth bias transistor M is connected P2b The source and body of the fourth bias tube M P2b The drain is connected to the common ground vss; The fifth DC blocking capacitor is connected to the third bias transistor M N2b The gate of the third push-pull source follower tube M N1b The sixth and seventh DC blocking capacitors are connected in series between the gates of the third push-pull source follower transistor M. N1b The gate of the fourth push-pull source follower tube M P1b The eighth DC blocking capacitor is connected between the gates of the fourth push-pull source follower transistor M P1b The gate of the fourth bias tube M P2b between the gates; The third bias tube M N2b The gate is connected to the first bias voltage V through the fifth DC blocking resistor b The third push-pull source follower tube M N1b The gate is connected to the second bias voltage V through the sixth DC blocking resistor B The fourth push-pull source follower tube M P1b The gate of the MOSFET is connected to the third bias voltage V via a seventh DC blocking resistor. D , the fourth bias tube M P2b The gate of the MOSFET is connected to the fourth bias voltage V via an eighth DC blocking resistor. E ; The first differential signal input terminal V inn Connected between the second DC blocking capacitor and the third DC blocking capacitor, the second differential signal input terminal V inp Connected between the sixth DC blocking capacitor and the seventh DC blocking capacitor, the first differential signal output terminal V outn Connect the first push-pull source follower tube M N1a The source of the second differential signal output terminal V outp Connect the third push-pull source follower tube M N1b The source.

4. The ADC input buffer according to claim 3, wherein: The reference bias voltages in the first reference voltage branch and the second reference voltage branch are replicated by using a proportional current mirror and a proportional resistor, meeting the following requirements: P(M P3c ) / P(M P3 )=R2 / R 2c =P(M N3c ) / P(M N3 )=R3 / R 3c The following requirements are met between the replica branch and the buffer circuit: In GS (M N2a / b ):V GS (M N1a / b ):V GS (M P1a / b ):V GS (M P2a / b )=R1:R2:R3:R4 Where P(M*) represents the aspect ratio of transistor M*, V GS (M*) represents the gate-source voltage of transistor M*.

5. An ADC, characterized in that: include: An ADC input buffer with a constant bias circuit according to any one of claims 1 to 4.

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