A memristor associative memory neural network circuit and control method thereof

Abstract

The present invention relates to a memristor associative memory neural network circuit and a control method thereof, wherein the memristor associative memory neural network circuit comprises: a logic output circuit electrically connected in sequence, a synaptic circuit comprising a memristor cross array, and a neuron circuit electrically connected to the synaptic circuit, wherein: the logic output circuit generates a control voltage after receiving an unconditioned stimulus signal and / or a conditioned stimulus signal; the synaptic circuit adjusts the resistance of the memristors in the memristor cross array under the triggering of the control voltage to realize an associative memory function and / or an associative output function; the neuron circuit outputs an analog voltage signal for representing associated information according to the adjusted resistance of the memristors in the memristor cross array. At the same time, a forgetting function over time is realized by a timing voltage output circuit. The present invention associates corresponding information with the help of associative memory, and is expected to be applied to the field of intelligent robots to improve the service experience of intelligent robots.

Description

Technical Field

[0001] The present invention relates to the emerging field of circuit technology, and in particular to a memristor associative memory neural network circuit and a control method thereof. Background Art

[0002] The human brain has tens of billions of neurons, each of which is connected to other neurons through thousands of synapses. The human brain can quickly and efficiently complete a variety of delicate and complex tasks, while the overall power consumption is less than 20 watts. Therefore, using memristor neural network circuits to simulate the mechanisms and functions of the human brain can achieve hardware circuits that far exceed the performance of existing computers, greatly improving the performance of circuits. In summary, how to effectively use memristor neural network circuits to improve circuit performance has become a key difficulty in the field of emerging circuit technology.

[0003] In the prior art, an expert team used a microcontroller and an A / D converter to design a circuit that can simulate the behavior of a physical memristor, and applied this circuit in a memristor associative memory neural network circuit as a synaptic circuit to achieve the corresponding function; some scholars also used memristors as synaptic circuits based on the excellent characteristics of memristors, and designed corresponding neural network circuits according to associative memory, but the utilization rate of their memristors was very low, and only the memristors on the diagonal of the cross array could be effectively utilized; there was also a patent design of a corresponding memristor neural network circuit to simulate Pavlov's associative memory and its corresponding forgetting process, but it used discrete memristor devices, had poor expansion performance, and was difficult to achieve high-density integration. In short, in existing research or published patents, the utilization of the circuit is not high, and the overall information storage density is not enough, making it difficult to achieve high-density integrated manufacturing, resulting in certain defects in the performance of the entire memristor associative memory neural network circuit. Therefore, how to design a high-performance memristor associative memory neural network circuit is an urgent problem to be solved. Summary of the invention

[0004] In view of this, it is necessary to provide a memristor associative memory neural network circuit and a control method thereof to overcome the problems of low circuit utilization and insufficient overall information storage density of the memristor associative memory neural network circuit in the prior art.

[0005] In order to solve the above technical problems, the present invention provides a memristor associative memory neural network circuit, comprising a logic output circuit and a synaptic circuit electrically connected in sequence, and a neuron circuit electrically connected to the synaptic circuit, wherein the synaptic circuit comprises a memristor cross array, wherein:

[0006] The logic output circuit generates a control voltage after receiving an unconditioned stimulus signal and / or a conditioned stimulus signal; the synaptic circuit adjusts the resistance of the memristors in the memristor cross array under the triggering of the control voltage to realize an associative memory function and / or an associated output function; the neuron circuit outputs an analog voltage signal for representing associated information according to the adjusted resistance of the memristors in the memristor cross array.

[0007] Furthermore, the logic output circuit includes a logic conversion circuit and a voltage selection output circuit which are electrically connected in sequence, wherein:

[0008] The logic conversion circuit includes a first NOT gate and an OR gate, the conditional stimulus signal is connected to the input end of the first NOT gate, the unconditional stimulus signal is connected to the first input end of the OR gate, and the output end of the NOT gate is connected to the second input end of the OR gate.

[0009] Furthermore, the voltage selection output circuit includes a first analog switch and a second analog switch, the output end of the OR gate is electrically connected to the control end of the first analog switch, and the first input end of the first analog switch is connected to the first voltage, and the second input end is connected to the second voltage; the output end of the NOT gate is electrically connected to the control end of the second analog switch, and the first input end of the second analog switch is connected to the third voltage, and the second input end is connected to the fourth voltage.

[0010] Furthermore, the memristor cross array in the synaptic circuit includes M row signal lines and N column signal lines, and the row signal lines and the column signal lines cross each other but are not directly connected, wherein each row signal line and each column signal line are connected together at the intersection through a circuit unit including a memristor.

[0011] Further, the control voltage includes a first control voltage signal output by a first analog switch and a second control voltage signal output by a second analog switch, and the circuit unit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor and a memristor, wherein:

[0012] One end of the first MOS transistor is electrically connected to the row signal line for receiving the first control voltage signal, and the other end of the first MOS transistor is electrically connected to the positive electrode of the memristor;

[0013] One end of the second MOS tube is connected to one end of the first MOS tube, and the other end of the second MOS tube is connected to the negative electrode of the memristor;

[0014] One end of the third MOS tube is connected to the positive electrode of the memristor, and the other end of the third MOS tube is connected to the column signal line;

[0015] One end of the fourth MOS tube is connected to the negative electrode of the memristor, and the other end of the fourth MOS tube is connected to the column signal line;

[0016] The control end of the first MOS tube, the control end of the second MOS tube, the control end of the third MOS tube, and the control end of the fourth MOS tube are electrically connected to a first shunt point respectively, and the first shunt point is used to receive the second control voltage signal.

[0017] Further, the neuron circuit is electrically connected to the column signal line in the synapse circuit, and the neuron circuit includes an operational amplifier and a neuron resistor, wherein:

[0018] One end of the neuron resistor is electrically connected to the inverting input terminal of the operational amplifier, and the other end of the neuron resistor is electrically connected to the output terminal of the operational amplifier;

[0019] An inverting input terminal of the operational amplifier is electrically connected to the column signal line, a non-inverting input terminal of the operational amplifier is grounded, and an output terminal of the operational amplifier outputs the analog voltage signal.

[0020] Furthermore, the memristor associative memory neural network circuit also includes a timing voltage output circuit electrically connected to the synaptic circuit, and the timing voltage output circuit includes a clock pulse source, a binary counter, a monostable trigger, a second NOT gate, an AND gate, a third analog switch, and a fourth analog switch, wherein:

[0021] The clock pulse source is electrically connected to the binary counter, and is used to output a pulse signal to the binary counter;

[0022] The binary counter is electrically connected to the monostable trigger, and is used to output a logic indication level to the monostable trigger when the pulse signal is counted to a preset value;

[0023] The conditional stimulus signal is connected to the input end of the second NOT gate, the output end of the second NOT gate is connected to the first input end of the AND gate, the monostable trigger is connected to the second input end of the AND gate, and the AND gate is electrically connected to the control end of the third analog switch and the control end of the fourth analog switch respectively;

[0024] The first input terminal of the third analog switch is connected to the fifth voltage, the second input terminal is set to a high impedance state, and the output terminal of the third analog switch is electrically connected to the row signal line in the synaptic circuit;

[0025] The first input terminal of the fourth analog switch is connected to the sixth voltage, the second input terminal is set to a high impedance state, and the output terminal of the fourth analog switch is electrically connected to the first shunt point in the circuit unit of the synaptic circuit.

[0026] The present invention also provides a control method for a memristor associative memory neural network circuit. Based on the memristor associative memory neural network circuit as described above, the control method comprises:

[0027] Through the logic output circuit, the received unconditioned stimulus signal and / or conditioned stimulus signal is subjected to logic transformation to generate a control voltage;

[0028] By means of the synaptic circuit, under the triggering of the control voltage, the resistance values ​​of the memristors in the memristor cross array are adjusted to realize the associative memory function and / or the associative output function;

[0029] Through the neuron circuit, according to the adjusted resistance value of the memristor in the memristor cross array, an analog voltage signal for representing the associated information is output.

[0030] Furthermore, the control voltage includes a first control voltage signal output by the first analog switch and a second control voltage signal output by the second analog switch, and the logic output circuit performs a logic transformation on the received unconditioned stimulus signal and / or conditioned stimulus signal to generate the control voltage, including:

[0031] When the unconditioned stimulus signal and the conditioned stimulus signal are both at a high level, a logic conversion circuit performs a logic judgment, and the result of the logic judgment is input into a voltage selection output circuit, and a first control voltage signal output by a first analog switch in the voltage selection output circuit and a second control voltage signal output by a second analog switch form a first voltage combination, wherein the first voltage combination is used to trigger the synaptic circuit to realize an associative memory function and complete the storage of associated information;

[0032] When the unconditioned stimulus signal is at a low level and the conditioned stimulus signal is at a high level, a logic conversion circuit performs a logic judgment, and the result of the logic judgment is input into the voltage selection output circuit, and the first control voltage signal and the second control voltage signal form a second voltage combination, wherein the second voltage combination is used to trigger the synaptic circuit to realize an associated output function;

[0033] When the unconditioned stimulus signal and the conditioned stimulus signal are both at a low level, or the unconditioned stimulus signal is at a high level and the conditioned stimulus signal is at a low level, a logic judgment is performed through a logic conversion circuit, and the result of the logic judgment is input into the voltage selection output circuit, and the first control voltage signal and the second control voltage signal form a third voltage combination and a fourth voltage combination, wherein neither the third voltage combination nor the fourth voltage combination triggers the synaptic circuit to realize an associative memory function or an associated output function.

[0034] Furthermore, the synaptic circuit, under the triggering of the control voltage, adjusts the resistance of the memristors in the memristor cross array to realize the associative memory function and / or the associative output function, including:

[0035] When the synaptic circuit receives the first voltage combination, the first MOS tube and the fourth MOS tube in the circuit unit of the synaptic circuit are turned on, and the second MOS tube and the third MOS tube are turned off. When the first control voltage signal is greater than the threshold voltage of the memristor, the resistance of the memristor decreases continuously, thereby realizing the associative memory function.

[0036] When the synaptic circuit receives the second voltage combination, the first MOS tube and the fourth MOS tube are turned on, and the second MOS tube and the third MOS tube are turned off. When the first control voltage signal is less than the threshold voltage of the memristor, the resistance of the memristor remains unchanged, thereby realizing the associated output function.

[0037] When the synaptic circuit receives the third voltage combination or the fourth voltage combination, the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all disconnected;

[0038] The step of outputting an analog voltage signal for representing the associated information according to the adjusted memristor resistance in the memristor cross array through the neuron circuit includes:

[0039] Determine the synaptic weight based on the ratio of the neuron resistance and the adjusted memristor resistance;

[0040] The analog voltage signal is determined according to the synaptic weight and the first control voltage signal.

[0041] Furthermore, the control method further includes:

[0042] When the unconditioned stimulus signal and the conditioned stimulus signal are both at a high level, or the unconditioned stimulus signal is at a low level and the conditioned stimulus signal is at a high level, the third analog switch and the fourth analog switch in the timing voltage output circuit output a high impedance state;

[0043] When both the unconditioned stimulus signal and the conditioned stimulus signal are at a low level, or the unconditioned stimulus signal is at a high level and the conditioned stimulus signal is at a low level, if the timing voltage output circuit times to a preset time, the third control voltage signal output by the third analog switch and the fourth control voltage signal output by the fourth analog switch form a fifth voltage combination, so that the associated information is forgotten over time. By changing the device parameters in the monostable trigger circuit, the duration of the fifth voltage combination can be adjusted to change the forgetting rate over time;

[0044] When the synaptic circuit receives the fifth voltage combination, the second MOS tube and the third MOS tube in the circuit unit of the synaptic circuit are turned on, and the first MOS tube and the fourth MOS tube are turned off. When the third control voltage signal is greater than the threshold voltage of the memristor, the resistance of the memristor increases continuously, thereby realizing the function of forgetting associated information over time.

[0045] Compared with the prior art, the beneficial effects of the present invention include: in the memristor associative memory neural network circuit, the unconditioned stimulus signal and the conditioned stimulus signal are subjected to corresponding logic conversion by setting the logic output circuit to form the control voltage that triggers the synaptic circuit; by setting the synaptic circuit, the memristor cross array is used to adjust the resistance of the memristor under the action of different control voltages to realize the association of associative memory information, or output the associated information that has been memorized; by setting the neuron circuit to output the corresponding associated information, and the associated information is represented by the analog voltage signal output by the neuron. Moreover, under the control of the timing voltage output circuit, the stored associated information can realize the forgetting function over time. In the related control method, first, the unconditioned stimulus signal and the conditioned stimulus signal are subjected to corresponding logic judgment, and the corresponding control voltage is formed by the result of the logic judgment; then, after different control voltages form different voltage combinations, the resistance change of the memristor in the memristor cross array is adjusted, so as to realize the association of data and the extraction of associated information by combining the flexible and controllable characteristics of the synaptic circuit; finally, the analog voltage signal is output to represent the size of the data volume, represent different information, and effectively indicate the change of associated information. In addition, after the timing reaches the preset time, the timing voltage output circuit generates a corresponding voltage combination to control the reverse change of the memristor value to realize the forgetting function. Moreover, the forgetting rate can be set to different values. In summary, the present invention not only uses the memristor cross array as a carrier, increases the integration of the circuit and the density of memory information storage, and has good scalability. It also uses the analog signal output by the neuron to represent different information and indicate the change of related information, which has a good effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 A schematic diagram of the structure of an embodiment of a memristor associative memory neural network circuit provided by the present invention;

[0047] Figure 2 The present invention provides Figure 1 A schematic diagram of the structure of an embodiment of a logic output circuit;

[0048] Figure 3 The present invention provides Figure 1 A schematic diagram of the structure of a synaptic circuit in an embodiment;

[0049] Figure 4 The present invention provides Figure 1A schematic diagram of the structure of a neuron circuit in an embodiment;

[0050] Figure 5 The present invention provides Figure 1 A schematic diagram of the structure of an embodiment of a timing voltage output circuit;

[0051] Figure 6 A schematic diagram of a specific system structure of an embodiment of a memristor associative memory neural network circuit provided by the present invention;

[0052] Figure 7 A schematic diagram of a specific circuit structure of an embodiment of a memristor associative memory neural network circuit provided by the present invention;

[0053] Figure 8 A flow chart of an embodiment of a control method for a memristor associative memory neural network circuit provided by the present invention. DETAILED DESCRIPTION

[0054] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0055] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0056] In the description of the present invention, reference to an "embodiment" means that a particular feature, structure, or characteristic described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive of other embodiments. It is explicitly and implicitly understood by those skilled in the art that the described embodiments may be combined with other embodiments.

[0057] The present invention provides a memristor associative memory neural network circuit and a control method thereof, which utilizes a memristor cross array to form a synaptic circuit and utilizes an analog voltage signal output by the neuron circuit to represent related association information, thereby providing a new idea for further improving the circuit performance of the memristor associative memory neural network circuit.

[0058] Before describing the embodiments, the following definitions are given for the relevant terms:

[0059] Memristor: The full name is memory resistor (Memristor), which is a circuit device that represents the relationship between magnetic flux and charge. Memristor has the dimension of resistance, but unlike resistor, the resistance of memristor is determined by the charge flowing through it. Therefore, by measuring the resistance of memristor, we can know the amount of charge flowing through it, so it has the function of memorizing charge; it should be noted that in 2008, Chinese professor Leon.O.Chua first proposed memristor in theory from the perspective of the symmetry of basic circuit parameters. HP Labs first manufactured the physical device of memristor in 2008, which greatly promoted the development of memristor research. When the corresponding voltage is applied to the two ends of the memristor, the memristor value will change. When there is no voltage at both ends of the memristor, the resistance of the memristor remains unchanged. The change of resistance of memristor can well match the change of synaptic weight in neural network, so using memristor as synaptic circuit can not only reduce the number of electronic devices used, but also improve the working performance of synaptic circuit. Therefore, designing memristor neural network circuit has very good application prospects;

[0060] Associative memory: It is an important biological learning mechanism, which has been verified in Pavlov's associative memory experiment. Pavlov's associative memory experiment shows that dogs can establish a conditioned reflex between the bell and saliva secretion through associative learning. The experimental process is as follows: Under the initial conditions, only feeding the dog (unconditioned stimulus) will cause it to secrete saliva, while ringing the bell alone (conditioned stimulus) will not cause it to secrete saliva. Then, ring the bell while feeding the dog. The dog will form a conditioned reflex between the bell and saliva secretion through associative learning between food and the bell. After the learning process is over, ringing the bell alone will cause the dog to secrete saliva. Associative memory has also been verified in experiments such as the cheek retraction reflex of sea slugs and the blinking reflex of rabbits. There are two types of inputs in associative memory: unconditioned stimulus and conditioned stimulus. In the initial stage, the synaptic weight corresponding to the conditioned stimulus is very small. In the learning stage, this synaptic weight continues to increase with associative learning;

[0061] Based on the description of the above technical terms, in the prior art, the circuit structure of the memristor associative memory neural network circuit is not based on the memristor cross array, and high-density integrated manufacturing cannot be achieved; and the circuit unit control in the memristor cross array is complex, and each circuit unit cannot be flexibly controlled separately; at the same time, the existing memristor associative memory neural network circuit can only indicate the presence or absence of output, and there is no problem of using analog quantity to indicate the amount of data. In summary, the existing memristor associative memory neural network circuit lacks good circuit performance. Therefore, the present invention aims to propose a high-performance, novel memristor associative memory neural network circuit.

[0062] The specific embodiments are described in detail below:

[0063] The embodiment of the present invention provides a memristor associative memory neural network circuit, combined with Figure 1 Come and see, Figure 1 A schematic diagram of the structure of an embodiment of a memristor associative memory neural network circuit provided by the present invention includes a logic output circuit 101 electrically connected in sequence, a synaptic circuit 102 including a memristor cross array, and a neuron circuit 103 electrically connected to the synaptic circuit, wherein:

[0064] The logic output circuit 101 generates a control voltage after receiving an unconditioned stimulus signal and / or a conditioned stimulus signal; the synaptic circuit 102 adjusts the resistance of the memristors in the memristor cross array under the triggering of the control voltage to realize an associative memory function and / or an associated output function; the neuron circuit 103 outputs an analog voltage signal for representing associated information according to the adjusted resistance of the memristors in the memristor cross array.

[0065] In an embodiment of the present invention, in a memristor associative memory neural network circuit, a logic output circuit is set to perform corresponding logic conversion on an unconditioned stimulus signal and a conditioned stimulus signal to form a control voltage that triggers a synaptic circuit; by setting a synaptic circuit, using a memristor cross array therein, under the action of different control voltages, the resistance of the memristor therein is adjusted to realize associative memory information association, or output the memorized associated information; by setting a neuron circuit to output the corresponding associated information, and these associated information are represented by an analog voltage signal output by the neuron. It should be noted that the present invention is not completely based on the mechanism of biological Pavlov associative memory to conduct the circuit, but on the basic mechanism of Pavlov associative memory, combined with the application requirements of the circuit, a reasonable adjustment is made to the working mode, and therefore, it is a new type of memristor associative memory neural network circuit.

[0066] As a preferred embodiment, Figure 2 Come and see, Figure 2 The present invention provides Figure 1 A schematic diagram of the structure of an embodiment of a logic output circuit in FIG. 1 , wherein the logic output circuit comprises a logic conversion circuit and a voltage selection output circuit electrically connected in sequence, wherein:

[0067] The logic conversion circuit includes a first NOT gate and an OR gate, the conditional stimulus signal is connected to the input end of the first NOT gate, the unconditional stimulus signal is connected to the first input end of the OR gate, and the output end of the NOT gate is connected to the second input end of the OR gate.

[0068] In the embodiment of the present invention, the first NOT gate and the OR gate are used to perform effective logic judgment on the unconditioned stimulus signal (US) and the conditioned stimulus signal (CS).

[0069] In a specific embodiment of the present invention, Figure 2 From the above, the conditioned stimulus signal (CS) is connected to the input of the NOT gate U1, the output of the NOT gate U1 is connected to the second input of the OR gate U2, and the unconditioned stimulus signal (US) is connected to the first input of the OR gate U2.

[0070] As a preferred embodiment, still combined with Figure 2 From the perspective of FIG. 1 , the voltage selection output circuit includes a first analog switch and a second analog switch, the output end of the OR gate is electrically connected to the control end of the first analog switch, and the first input end of the first analog switch is connected to a first voltage, and the second input end is connected to a second voltage; the output end of the NOT gate is electrically connected to the control end of the second analog switch, and the first input end of the second analog switch is connected to a third voltage, and the second input end is connected to a fourth voltage.

[0071] In the embodiment of the present invention, under the triggering of the logic signal, the voltage selection output circuit uses the first analog switch and the second analog switch to output different voltage combinations, namely, the control voltage.

[0072] In a specific embodiment of the present invention, Figure 2 From the above, the output end of the NOT gate U1 is connected to the control end of the second analog switch S2, and the output end of the OR gate U2 is connected to the control end of the first analog switch S1. The first input end of the first analog switch S1 is connected to a 1V voltage, and the second input end of the first analog switch S1 is connected to a 0.4V voltage. The first input end of the second analog switch S2 is connected to a 0.5V voltage, and the second input end of the second analog switch S2 is connected to a -2V voltage.

[0073] As a preferred embodiment, Figure 3 Come and see, Figure 3 The present invention provides Figure 1 A structural schematic diagram of an embodiment of a synaptic circuit in the synaptic circuit, wherein the memristor cross array in the synaptic circuit includes M row signal lines and N column signal lines, the row signal lines and the column signal lines cross each other but are not directly connected, wherein each row signal line and each column signal line are connected together at the intersection through a circuit unit including a memristor.

[0074] In the embodiment of the present invention, based on the crossbar array structure, a synaptic circuit is involved, which ensures that each circuit unit can be flexibly and effectively controlled separately. It should be noted that M and N are preferably equal values.

[0075] As a preferred embodiment, still combined with Figure 3From the perspective of FIG. 1 , the control voltage includes a first control voltage signal output by a first analog switch and a second control voltage signal output by a second analog switch, and the circuit unit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor and a memristor, wherein:

[0076] One end of the first MOS transistor is electrically connected to the row signal line for receiving the first control voltage signal, and the other end of the first MOS transistor is electrically connected to the positive electrode of the memristor;

[0077] One end of the second MOS tube is connected to one end of the first MOS tube, and the other end of the second MOS tube is connected to the negative electrode of the memristor;

[0078] One end of the third MOS tube is connected to the positive electrode of the memristor, and the other end of the third MOS tube is connected to the column signal line;

[0079] One end of the fourth MOS tube is connected to the negative electrode of the memristor, and the other end of the fourth MOS tube is connected to the column signal line;

[0080] The control end of the first MOS tube, the control end of the second MOS tube, the control end of the third MOS tube, and the control end of the fourth MOS tube are electrically connected to a first shunt point respectively, and the first shunt point is used to receive the second control voltage signal.

[0081] In the embodiment of the present invention, a 4T1M memristor cross array structure (one memristor and four MOS tubes) is used as a synaptic circuit, which can flexibly control each circuit unit of the 4T1M to achieve corresponding functions, so that each circuit unit is utilized and the storage density of information is improved.

[0082] In a specific embodiment of the present invention, the circuit unit is a 4T1M circuit unit including: a first MOS transistor T1, a second MOS transistor T2, a third MOS transistor T3, a fourth MOS transistor T4 and a memristor Rm1. The connection method thereof is shown in Figure 3 , I will not go into details here.

[0083] As a preferred embodiment, Figure 4 Come and see, Figure 4 The present invention provides Figure 1 A schematic diagram of a structure of an embodiment of a neuron circuit in FIG. 1 , wherein the neuron circuit is electrically connected to a column signal line in the synapse circuit, and the neuron circuit includes an operational amplifier and a neuron resistor, wherein:

[0084] One end of the neuron resistor is electrically connected to the inverting input terminal of the operational amplifier, and the other end of the neuron resistor is electrically connected to the output terminal of the operational amplifier;

[0085] An inverting input terminal of the operational amplifier is electrically connected to the column signal line, a non-inverting input terminal of the operational amplifier is grounded, and an output terminal of the operational amplifier outputs the analog voltage signal.

[0086] In the embodiment of the present invention, a neuron circuit is used to use analog voltage to represent the size of the data amount, represent different information, and indicate the change of related information, which has a good effect.

[0087] As a preferred embodiment, Figure 5 Come and see, Figure 5 The present invention provides Figure 1 A schematic diagram of the structure of an embodiment of a timing voltage output circuit in the embodiment of FIG. 1 , wherein the memristor associative memory neural network circuit further includes a timing voltage output circuit electrically connected to the synaptic circuit, and the timing voltage output circuit includes a clock pulse source, a binary counter, a monostable trigger, a second NOT gate, an AND gate, a third analog switch, and a fourth analog switch, wherein:

[0088] The clock pulse source is electrically connected to the binary counter, and is used to output a pulse signal to the binary counter;

[0089] The binary counter is electrically connected to the monostable trigger, and is used to output a logic indication level to the monostable trigger when the pulse signal is counted to a preset value;

[0090] The conditional stimulus signal is connected to the input end of the second NOT gate, the output end of the second NOT gate is connected to the first input end of the AND gate, the monostable trigger is connected to the second input end of the AND gate, and the AND gate is electrically connected to the control end of the third analog switch and the control end of the fourth analog switch respectively;

[0091] The first input terminal of the third analog switch is connected to the fifth voltage, the second input terminal is set to a high impedance state, and the output terminal of the third analog switch is electrically connected to the row signal line in the synaptic circuit;

[0092] The first input terminal of the fourth analog switch is connected to the sixth voltage, the second input terminal is set to a high impedance state, and the output terminal of the fourth analog switch is electrically connected to the first shunt point in the circuit unit of the synaptic circuit.

[0093] In the embodiment of the present invention, a timing voltage output circuit is used, by means of which the forgetting speed over time can be arbitrarily adjusted.

[0094] In a specific embodiment of the present invention, Figure 5 From the above-mentioned timing voltage output circuit, it can be seen that the timing voltage output circuit includes a binary counter, a monostable trigger, a second NOT gate U3, an AND gate U4, a third analog switch S3, and a fourth analog switch S4;

[0095] The output of the binary counter is connected to the input of the monostable trigger, and when the counter reaches a preset count value, the monostable trigger is triggered. The conditional stimulus CS11 is connected to the input of the second NOT gate U3, the output of the second NOT gate U3 is connected to the first input of the AND gate U4, the output of the monostable trigger is connected to the second input of the AND gate U4, the output of the AND gate U4 is connected to the control end of the third switch S3, and the output of the AND gate U4 is also connected to the control end of the fourth switch S4;

[0096] The first input terminal of the third switch S3 is connected to a 1V voltage, the second input terminal of the third switch S3 is set to a high impedance state, and the output terminal of the third switch S3 is connected to the row signal line of the 4T1M memristor cross array. The first input terminal of the fourth switch S4 is connected to a 2V voltage, the second input terminal of the fourth switch S4 is set to a high impedance state, and the output terminal of the fourth switch S4 is connected to the control terminals of the four MOS transistors of the circuit unit in the 4T1M memristor cross array;

[0097] It should be noted that the first analog switch S1 to the fourth analog switch S4 are all two-choose-one analog switches.

[0098] Combine the following Figure 6 , Figure 7 A specific structure of a memristor associative memory neural network circuit is described in detail, wherein: Figure 6 A schematic diagram of a specific system structure of an embodiment of a memristor associative memory neural network circuit provided by the present invention, Figure 7 This is a schematic diagram of a specific circuit structure of an embodiment of a memristor associative memory neural network circuit provided by the present invention. The specific structure of the memristor associative memory neural network circuit is as follows:

[0099] like Figure 6 As shown, the unconditioned stimulus signal and the conditioned stimulus signal are converted by the logic conversion circuit to generate the control signal of the voltage selection output circuit. Different control signals connect and output different voltage combinations of the input end of the voltage selection output circuit. The circuit units in the 4T1M memristor cross array are controlled to work in different states to realize the associative memory function or the associated information output function. In addition, the timing voltage output circuit will output the corresponding voltage combination after a certain period of time according to the set forgetting rate over time, and control the circuit units in the 4T1M cross array to realize the forgetting update of the associated data;

[0100] Among them, it should be noted that Figure 7A new type of 4T1M memristor cross array structure is proposed as a synaptic circuit, which can flexibly control each 4T1M unit to realize the corresponding function. All circuit units in this memristor cross array have been applied, which improves the storage density of information. This memristor associative memory neural network circuit realizes the storage and extraction of associated information by performing logical transformation on unconditioned stimulus and conditioned stimulus signals, combined with the flexible and controllable characteristics of the 4T1M synaptic circuit. This memristor associative memory neural network circuit realizes the forgetting function over time through a timing voltage output circuit, and the forgetting rate can be arbitrarily adjusted. The analog voltage corresponding to the neuron output of this memristor associative memory neural network represents the amount of associated information.

[0101] The embodiment of the present invention provides a control method for a memristor associative memory neural network circuit, combining Figure 8 Come and see, Figure 8 A flow chart of an embodiment of a control method of a memristor associative memory neural network circuit provided by the present invention, based on the memristor associative memory neural network circuit as described above, includes steps S801 to S803, wherein:

[0102] In step S801, the received unconditioned stimulus signal and / or conditioned stimulus signal is subjected to logic transformation through a logic output circuit to generate a control voltage;

[0103] In step S802, the resistance values ​​of the memristors in the memristor crossbar array are adjusted by the synaptic circuit under the triggering of the control voltage to realize the associative memory function and / or the associative output function;

[0104] In step S803, an analog voltage signal for representing the associated information is outputted according to the adjusted resistance values ​​of the memristors in the memristor crossbar array through the neuron circuit.

[0105] In an embodiment of the present invention, first, corresponding logical judgments are performed on the unconditioned stimulus signal and the conditioned stimulus signal, and the corresponding control voltage is formed using the result of the logical judgment; then, after different control voltages form different voltage combinations, the memristor cross array in the synaptic circuit is triggered to adjust the resistance change of the memristor, thereby combining the flexible and controllable characteristics of the synaptic circuit to achieve the storage of associated information and the extraction of associated information; finally, the output analog voltage signal represents the size of the data volume, represents different information, and effectively indicates the change of associated information.

[0106] As a preferred embodiment, the control voltage includes a first control voltage signal output by a first analog switch and a second control voltage signal output by a second analog switch. The above step S802 specifically includes:

[0107] When the unconditioned stimulus signal and the conditioned stimulus signal are both at a high level, a logic conversion circuit performs a logic judgment, and the result of the logic judgment is input into a voltage selection output circuit, and a first control voltage signal output by a first analog switch in the voltage selection output circuit and a second control voltage signal output by a second analog switch form a first voltage combination, wherein the first voltage combination is used to trigger the synaptic circuit to realize an associative memory function and complete the storage of associated information;

[0108] When the unconditioned stimulus signal is at a low level and the conditioned stimulus signal is at a high level, a logic conversion circuit performs a logic judgment, and the result of the logic judgment is input into the voltage selection output circuit, and the first control voltage signal and the second control voltage signal form a second voltage combination, wherein the second voltage combination is used to trigger the synaptic circuit to realize an associated output function;

[0109] When the unconditioned stimulus signal and the conditioned stimulus signal are both at a low level, or the unconditioned stimulus signal is at a high level and the conditioned stimulus signal is at a low level, a logic judgment is performed through a logic conversion circuit, and the result of the logic judgment is input into the voltage selection output circuit, and the first control voltage signal and the second control voltage signal form a third voltage combination and a fourth voltage combination, wherein neither the third voltage combination nor the fourth voltage combination triggers the synaptic circuit to realize an associative memory function or an associated output function.

[0110] In the embodiment of the present invention, the signal output of different voltage combinations is realized through the logic conversion circuit and the voltage selection output circuit, thereby realizing different triggering of the synaptic circuit.

[0111] In a specific embodiment of the present invention, Figure 2 From the above, the unconditioned stimulus signal is represented by US, the conditioned stimulus signal is represented by CS, the logic conversion circuit is composed of a NOT gate U1 and an OR gate U2, CS is connected to the input of the NOT gate U1, the output of the NOT gate U1 is connected to the second input of the OR gate U2, and US is connected to the second input of the OR gate U2, where:

[0112] When both the unconditioned stimulus and the conditioned stimulus signal are at a low level, or the unconditioned stimulus signal is at a high level and the conditioned stimulus signal is at a low level, the memristor associative memory neural network circuit does not produce any output for these two input combination states. These two states have no specific functional meaning for this memristor associative memory neural network circuit;

[0113] When the unconditioned stimulus and conditioned stimulus signals are both at high level, the memristor associative memory neural network circuit enters the associative learning stage;

[0114] When the unconditioned stimulus is at a low level and the conditioned stimulus is at a high level, the memristor associative memory neural network circuit outputs the corresponding associated information;

[0115] The voltage selection output circuit is composed of a first analog switch S1 and a second analog switch S2. The output of the NOT gate in the logic conversion circuit is connected to the control terminal sc2 of the second analog switch S2, and the output of the OR gate in the logic conversion circuit is connected to the control terminal sc1 of the first analog switch S1. The first input terminal of the first analog switch S1 is connected to a 1V voltage, and the second input terminal of the first analog switch S1 is connected to a 0.4V voltage. The first input terminal of the second analog switch S2 is connected to a 0.5V voltage, and the second input terminal of the second analog switch S2 is connected to a -2V voltage. If the control terminal sc1 of the first analog switch S1 is a high level, the output voltage of the first analog switch S1 is 1V. If the control terminal sc1 of the first analog switch S1 is a low level, the output voltage of the first analog switch S1 is 0.4V. If the control terminal sc2 of the second analog switch S2 is a high level, the output voltage of the second analog switch S2 is 0.5V. If the control terminal sc2 of the second analog switch S2 is a low level, the output voltage of the second analog switch S2 is -2V. Therefore, in order to achieve the functions described above. The relationship between the input and output of the logic conversion circuit and the voltage selection output is shown in Table 1 below:

[0116] Table 1

[0117]

[0118] In Table 1, US and CS have different logic combinations, sc1 represents the output of the OR gate in the logic conversion circuit, and sc2 represents the output of the NOT gate in the logic conversion circuit. Vim represents the output of the first analog switch S1, and Vc represents the output of the second analog switch S2. The voltage selection output circuit outputs different voltage combinations and is connected to the 4T1M memristor crossbar array to complete the corresponding functions.

[0119] As a preferred embodiment, the above step S803 specifically includes:

[0120] When the synaptic circuit receives the first voltage combination, the first MOS tube and the fourth MOS tube in the circuit unit of the synaptic circuit are turned on, and the second MOS tube and the third MOS tube are turned off, and when the first control voltage signal is greater than the threshold voltage of the memristor, the resistance of the memristor decreases continuously, thereby realizing the associative memory function;

[0121] When the synaptic circuit receives the second voltage combination, the first MOS tube and the fourth MOS tube are turned on, and the second MOS tube and the third MOS tube are turned off. When the first control voltage signal is less than the threshold voltage of the memristor, the resistance value of the memristor remains unchanged, thereby realizing the associated output function.

[0122] When the synaptic circuit receives the third voltage combination or the fourth voltage combination, the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all disconnected.

[0123] In the embodiment of the present invention, different circuit combinations are used to trigger the 4T1M memristor crossbar array to achieve different functions.

[0124] In a specific embodiment of the present invention, Figure 3 From the perspective of 4T1M memristor crossbar array, Figure 3 As shown in the figure, it is a 4×4 memristor crossbar array. Each circuit unit in the array has the same structure, and these circuit units are connected to the corresponding row signal lines and column signal lines. The following takes the circuit unit M11 as an example to introduce the working principle of the 4T1M memristor crossbar array:

[0125] The circuit unit M11 includes: a first MOS transistor T1, a second MOS transistor T2, a third MOS transistor T3, a fourth MOS transistor T4 and a memristor Rm1. One end of the first MOS transistor T1 is connected to the row signal line H1 for receiving an input signal. The other end of the first MOS transistor T1 is connected to the positive electrode of the memristor Rm1; one end of the second MOS transistor T2 is connected to one end of the first MOS transistor T1, that is, the row signal line H1, to receive an input signal. The other end of the second MOS transistor T2 is connected to the negative electrode of the memristor Rm1. One end of the third MOS transistor T3 is connected to the positive electrode of the memristor Rm1, and the other end of the third MOS transistor T3 is connected to the column signal line L1; one end of the fourth MOS transistor T4 is connected to the negative electrode of the memristor Rm1, and the other end of the fourth MOS transistor T4 is connected to the column signal line L1; the gates of the first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3 and the fourth MOS transistor T4 are connected together and controlled by the control signal Vc11. In the circuit unit M11, the first MOS tube T1 and the fourth MOS tube T4 are P-type MOS tubes, and the second MOS tube T2 and the third MOS tube T3 are N-type MOS tubes. In this memristor associative memory neural network circuit, the threshold voltage of the P-type MOS tube is set to -0.6V, and the threshold voltage of the N-type MOS tube is set to 0.6V. In addition, the corresponding memristor is a voltage-controlled memristor, and the corresponding negative and positive threshold voltages are set to -0.5V and 0.5V. Here, the AIST model is taken as an example to illustrate the designed circuit, but the circuit design is not limited to the AIST model, and other voltage-controlled threshold memristor models are also applicable to this memristor associative memory neural network circuit. The AIST memristor model is described as follows:

[0126]

[0127]

[0128]

[0129] i off ,i on , i0 is a constant, D is the length of the memristor, u v is the average ion mobility in the memristor, R OFF and R ON Represent the maximum and minimum memristor values, x(t) represents the length of the doped region, V T+ , V T- denote the positive threshold voltage and the negative threshold voltage respectively, and f(x(t)) is the window function;

[0130] Among them, for the 4T1M circuit unit M11, if the voltage combination output by the voltage selection output circuit is that the voltage of Vim1 is 1V and the voltage of Vc11 is 0.5V, then the voltage connected to one end of the first MOS transistor T1 and the second MOS transistor T2 is 1V. Therefore, the voltage between the gate and the source of the first MOS transistor T1 and the second MOS transistor T2 is -0.5V. Because the first MOS transistor T1 is a P-type MOS transistor, the gate-source voltage of -0.5V is greater than the threshold voltage of the first MOS transistor T1, so the first MOS transistor T1 is disconnected. Because the second MOS transistor T2 is an N-type MOS transistor, the gate-source voltage of -0.5V is less than the threshold voltage of the second MOS transistor T2, so the second MOS transistor T2 is disconnected. Due to the virtual short effect of the operational amplifier, the voltage on the column line L1 is 0V. Therefore, the voltage between the gate and the source of the third MOS transistor T3 and the fourth MOS transistor T4 is 0.5V. Because the third MOS transistor T3 is an N-type MOS transistor, the gate-source voltage of 0.5V is less than the threshold voltage of the third MOS transistor T3, so the third MOS transistor T3 is disconnected. Because the fourth MOS transistor T4 is a P-type MOS transistor, the gate-source voltage of 0.5V is greater than the threshold voltage of the fourth MOS transistor T4, so the fourth MOS transistor T4 is disconnected. Therefore, in this state, the first MOS transistor T1, the second MOS transistor T2, the third MOS transistor T3, and the fourth MOS transistor T4 are all in a disconnected state, so the circuit unit M11 is disconnected from other circuits and does not affect the operation of other circuits.

[0131] Among them, for the 4T1M circuit unit M11, if the voltage combination output by the voltage selection output circuit is that the voltage of Vim1 is 1V and the voltage of Vc11 is -2V, then the voltage connected to one end of the first MOS transistor T1 and the second MOS transistor T2 is 1V. Therefore, the voltage between the gate and the source of the first MOS transistor T1 and the second MOS transistor T2 is -3V. Because the first MOS transistor T1 is a P-type MOS transistor, the gate-source voltage of -3V is less than the threshold voltage of the first MOS transistor T1, so the first MOS transistor T1 is turned on. Because the second MOS transistor T2 is an N-type MOS transistor, the gate-source voltage of -3V is less than the threshold voltage of the second MOS transistor T2, so the second MOS transistor T2 is turned off. Due to the virtual short effect of the operational amplifier, the voltage on the column line L1 is 0V. Therefore, the voltage between the gate and the source of the third MOS transistor T3 and the fourth MOS transistor T4 is -2V. Because the third MOS transistor T3 is an N-type MOS transistor, the gate-source voltage of -2V is less than the threshold voltage of the third MOS transistor T3, so the third MOS transistor T3 is turned off. Because the fourth MOS transistor T4 is a P-type MOS transistor, the gate-source voltage of -2V is less than the threshold voltage of the fourth MOS transistor T4, so the fourth MOS transistor T4 is turned on. Therefore, in this state, the current flows from Vim1 through the first MOS transistor T1 and the fourth MOS transistor T4 to the column line L1, forming a current path. Since the voltage of Vim1 is greater than the threshold voltage of the memristor, the resistance of the memristor continues to decrease in this state.

[0132] Among them, for the 4T1M circuit unit M11, if the voltage combination output by the voltage selection output circuit is that the voltage of Vim1 is 0.4V and the voltage of Vc11 is -2V, then the voltage connected to one end of the first MOS transistor T1 and the second MOS transistor T2 is 0.4V. Therefore, the voltage between the gate and the source of the first MOS transistor T1 and the second MOS transistor T2 is -2.4V. Because the first MOS transistor T1 is a P-type MOS transistor, the gate-source voltage of -2.4V is less than the threshold voltage of the first MOS transistor T1, so the first MOS transistor T1 is turned on. Because the second MOS transistor T2 is an N-type MOS transistor, the gate-source voltage of -2.4V is less than the threshold voltage of the second MOS transistor T2, so the second MOS transistor T2 is turned off. Due to the virtual short effect of the operational amplifier, the voltage on the column line L1 is 0V. Therefore, the voltage between the gate and the source of the third MOS transistor T3 and the fourth MOS transistor T4 is -2V. Because the third MOS tube T3 is an N-type MOS tube, the gate-source voltage of -2V is less than the threshold voltage of the third MOS tube T3, so the third MOS tube T3 is disconnected. Because the fourth MOS tube T4 is a P-type MOS tube, the gate-source voltage of -2V is less than the threshold voltage of the fourth MOS tube T4, so the fourth MOS tube T4 is turned on. Therefore, in this state, the current flows from Vim1 through the first MOS tube T1 and the fourth MOS tube T4 to the column line L1, forming a current path. Since the voltage of Vim1 is less than the threshold voltage of the memristor, the resistance of the memristor remains unchanged in this state. In this state, the resistance of the memristor remains unchanged, but there is a corresponding current path, so the relevant information stored in the synaptic circuit can be output to the corresponding neuron circuit.

[0133] It should be noted that, from the above description, it can be seen that since the circuit units in the 4T1M memristor crossbar array are flexible and controllable, the circuit units can be disconnected, the memristor value of the circuit units can be changed, and the corresponding associated information can be output through the corresponding voltage. The 4T1M units in the memristor crossbar array have the same structure, so their control circuits and methods are the same.

[0134] As a preferred embodiment, the above step S803 further includes:

[0135] Determine the synaptic weight based on the ratio of the neuron resistance and the adjusted memristor resistance;

[0136] The analog voltage signal is determined according to the synaptic weight and the first control voltage signal.

[0137] In the embodiment of the present invention, the neuron resistor and the operational amplifier are used to effectively output the analog voltage signal.

[0138] In a specific embodiment of the present invention, Figure 4From the above, the structure of all neuron circuits is the same. The neuron circuit contains an operational amplifier and a resistor. The in-phase terminal of the operational amplifier is grounded, the column line of the 4T1M memristor cross array is connected to the inverting terminal of the operational amplifier, one end of the resistor is also connected to the inverting terminal of the operational amplifier, and the other end of the resistor is connected to the output terminal of the operational amplifier to form a feedback structure. Assuming that only the circuit unit M11 in the 4T1M memristor cross array has a current path, connected to the corresponding column signal line L1, and the corresponding input voltage Vim1 is 0.4V, the corresponding neuron circuit output voltage Vo1 can be expressed as:

[0139]

[0140] According to the above formula, the corresponding synaptic weight w11 can be expressed as:

[0141]

[0142] According to the above formula, the smaller the resistance of the memristor, the larger the value of the synaptic weight; therefore, when the input voltage Vim1 is 0.4V, the analog voltage signal output by the neuron circuit can be used to represent the size of the associated information.

[0143] As a preferred embodiment, the above step S803 further includes:

[0144] When the unconditioned stimulus signal and the conditioned stimulus signal are both at a low level, or the unconditioned stimulus signal is at a high level and the conditioned stimulus signal is at a low level, if the timing voltage output circuit times to a preset time, the corresponding control voltage combination is connected to the synaptic circuit to realize the forgetting function over time.

[0145] In the embodiment of the present invention, the timing voltage output circuit is used to control the time when the corresponding voltage combination is connected to the memristor crossbar array, thereby changing the corresponding forgetting rate.

[0146] In a specific embodiment of the present invention, Figure 5 From the perspective of the timing voltage output circuit, the structure diagram is as follows Figure 5 As shown, a binary counter, a monostable trigger, a second NOT gate U3, an AND gate U4, a third analog switch S3, and a fourth analog switch S4. The function of the timing voltage output circuit is to realize the forgetting process of the memristor associative memory neural network circuit over time. For the present invention, the forgetting process is that after the timing circuit times to the set time, the corresponding voltage combination is controlled to access the memristor cross array, thereby increasing the resistance of the corresponding memristor and reducing the corresponding synaptic weight. The amount of increase in the resistance of the memristor is determined by the time when the corresponding voltage combination is connected to the memristor cross array. Therefore, the corresponding forgetting rate can be changed by controlling the time when the corresponding voltage combination is connected to the memristor cross array;

[0147] The output of the binary counter is connected to the input of the monostable trigger, and when the counter reaches a preset count value, the monostable trigger is triggered. The conditional stimulus CS11 is connected to the input of the second NOT gate U3, the output of the second NOT gate U3 is connected to the first input of the AND gate U4, the output of the monostable trigger is connected to the second input of the AND gate U4, the output of the AND gate U4 is connected to the control end of the third switch S3, and the output of the AND gate U4 is also connected to the control end of the fourth switch S4;

[0148] Among them, the first input terminal of the third analog switch S3 is connected to a 1V voltage, the second input terminal of the third analog switch S3 is set to a high impedance state, and the output terminal of the third analog switch S3 is connected to the row signal line of the 4T1M memristor cross array. The first input terminal of the fourth analog switch S4 is connected to a 2V voltage, the second input terminal of the fourth analog switch S4 is set to a high impedance state, and the output terminal of the fourth analog switch S4 is connected to the control terminals of the four MOS tubes of the circuit unit in the 4T1M memristor cross array;

[0149] Among them, the conditional stimulus CS11 is connected to the input end of the second NOT gate U3, and the output end of the second NOT gate U3 is connected to the first input end of the AND gate U4. If the conditional stimulus CS11 is a high level, the second NOT gate U3 outputs a low level, and the AND gate U4 is locked at this time. The output end of the monostable trigger is connected to the second input end of the AND gate U4, and no matter whether the second input of the AND gate U4 is a high level or a low level, the AND gate U4 always outputs a low level. If the conditional stimulus CS11 is a low level, the second NOT gate U3 outputs a high level, and the AND gate U4 is opened at this time. The output of the AND gate U4 follows the level change of the second input end.

[0150] Among them, when the conditional stimulus CS11 is at a low level, if the binary counter reaches the corresponding timing time, the monostable trigger circuit is triggered, and the monostable trigger circuit outputs a pulse. The high level duration of this pulse can be achieved by adjusting the parameters of the resistor and capacitor in the monostable trigger circuit. The AND gate U4 also outputs a pulse. When this pulse is at a high level, the output voltage Vim1 of the third analog switch S3 is 1V, and the output voltage Vc11 of the fourth analog switch S4 is 2V;

[0151] Wherein, when this voltage combination is connected to the circuit unit M11, the voltage connected to one end of the first MOS tube T1 and the second MOS tube T2 is 1V. Thus, the voltage between the gate and the source of the first MOS tube T1 and the second MOS tube T2 is 1V. Because the first MOS tube T1 is a P-type MOS tube, the gate-source voltage of 1V is greater than the threshold voltage of the first MOS tube T1, so the first MOS tube T1 is disconnected. Because the second MOS tube T2 is an N-type MOS tube, the gate-source voltage of 1V is greater than the threshold voltage of the second MOS tube T2, so the second MOS tube T2 is turned on. Due to the virtual short effect of the operational amplifier, the voltage on the column line L1 is 0V. Therefore, the voltage between the gate and the source of the third MOS tube T3 and the fourth MOS tube T4 is 2V. Because the third MOS tube T3 is an N-type MOS tube, the gate-source voltage of 2V is greater than the threshold voltage of the third MOS tube T3, so the third MOS tube T3 is turned on. Because the fourth MOS tube T4 is a P-type MOS tube, the gate-source voltage of 2V is greater than the threshold voltage of the fourth MOS tube T4, so the fourth MOS tube T4 is disconnected. Therefore, in this state, the current flows from Vim1 through the second MOS tube T2 and the third MOS tube T3 to the column line L1, forming a current path. Since the voltage of Vim1 is greater than the threshold voltage of the memristor, the resistance of the memristor increases in this state, indicating that the synaptic weight is decreasing. The increment of the resistance of the memristor can be changed by adjusting the parameters of the monostable trigger circuit and adjusting the time when the voltage combination is connected to the memristor cross array, thereby changing the forgetting rate over time. After the output of the monostable trigger circuit becomes a low level, the output voltage of the third analog switch S3 and the output voltage of the fourth analog switch S4 become high impedance, which does not affect the operation of the circuit unit M11.

[0152] The following is a more detailed description of the technical solution of the present invention in conjunction with a specific application scenario. The 4×4 4T1M cross array provided in the above embodiment is used to output the corresponding association information of the fruit. The specific application principle is as follows:

[0153] In the memristor associative memory neural network circuit, the unconditioned stimulus signal US represents the corresponding parameter information of the fruit: freshness, taste, texture, and edible date. The conditioned stimulus signal CS represents "visually identifying the fruit" or "recognizing the picture of the fruit name"; the input of the conditioned stimulus can be realized through the corresponding pre-neural network;

[0154] In the embodiment, the four circuit units in each row of the 4×4 4T1M memristive cross array respectively represent the four characteristics of a fruit: freshness, taste, texture, and edible date. For example, the four circuit units in the first row of the memristive cross array respectively represent the four characteristics of apples: freshness, taste, texture, and edible date. The second, third, and fourth rows of the memristive cross array respectively represent the four characteristics of pears, grapes, and oranges. For each circuit unit in the 4×4 4T1M memristive cross array in the embodiment, there is a corresponding logic conversion circuit, voltage selection output circuit, and timing output circuit;

[0155] Among them, when the corresponding unconditioned stimulus signal and the conditioned stimulus signal are both at high levels, the corresponding circuit unit enters the associative memory stage. The resistance of the memristor in the circuit unit decreases, indicating that the synaptic weight increases. The association between 'visually identifying the fruit' or 'identifying the picture of the fruit' and the freshness, taste, texture, and edible date of the fruit is established through associative memory. The information on the freshness, taste, texture, and edible date of the fruit is stored in the memristor associative memory neural network. Because each circuit unit has a separate control circuit, each circuit unit can perform associative memory separately and store the corresponding associated information. All circuit units in the 4×4 4T1M memristor crossbar array can store the corresponding associated information at the same time;

[0156] Among them, after the association information is stored in the memristor associative memory neural network circuit through associative learning, if the unconditioned stimulus signal is at a low level and the conditioned stimulus signal is at a high level, the corresponding circuit unit outputs the association information. When outputting the association information, according to the order of 'visually identifying the fruit' or 'identifying the picture of the fruit name', the association information of the fruit that is first identified is output first, and then the association information of the second fruit is output. The four characteristics of a fruit, namely, freshness, taste, texture, and edible date, are stored in the corresponding synaptic circuit. When the fruit is identified, a voltage of 0.4V is input to the 4T1M memristor cross array. Since each characteristic of the four fruits is quantized within a different range of memristor resistance, the corresponding Am1, Am2, Am3, and Am4 neuron circuits output analog voltages within the corresponding range, indicating the association information of the corresponding characteristics of the fruit. For example, the freshness characteristics of apples are quantified as memristors within 20kΩ-35kΩ, the freshness characteristics of pears are quantified as memristors within 35kΩ-50kΩ, the freshness characteristics of grapes are quantified as memristors within 50kΩ-65kΩ, and the freshness characteristics of oranges are quantified as memristors within 65kΩ-80kΩ. In this way, when the corresponding fruit is identified, the Am1 neuron will output a voltage within the corresponding range to indicate the corresponding associated characteristics. Similarly, taste, texture, and edible date can also represent the corresponding associated information through the analog voltage output by the Am2, Am3, and Am4 neuron circuits. At the same time, each feature can be further adjusted to a different voltage range by adjusting the resistors R1, R2, R3, and R4 in the Am1, Am2, Am3, and Am4 neuron circuits;

[0157] Among them, when the memristor associative memory neural network circuit is neither in the associative memory associated information storage stage nor in the associated output stage, when the timing voltage output circuit reaches the preset time, the memristor associative memory neural network enters the forgetting stage over time. Because each circuit unit in the 4T1M memristor cross array has an independent control circuit, it can specifically and meticulously reflect the changes in the freshness, taste, texture, and edible date of the fruit over time according to the different representations of the four characteristics of each fruit over time. When the timing voltage output circuit reaches the set timing time, the corresponding voltage combination is connected to the 4T1M cross array, and the control signal duration of each circuit unit can be adjusted, thereby changing the increase in the resistance of the memristor, that is, the decrease in the synaptic weight, and obtaining different rates of forgetting over time.

[0158] The present invention discloses a memristor associative memory neural network circuit and a control method thereof. In the memristor associative memory neural network circuit, a logic output circuit is set to perform corresponding logic conversion on an unconditioned stimulus signal and a conditioned stimulus signal to form a control voltage that triggers a synaptic circuit; a synaptic circuit is set to utilize a memristor cross array therein, and under the action of different control voltages, the resistance of the memristor therein is adjusted to realize associative memory information association, or output the associated information that has been memorized; a neuron circuit is set to output corresponding associated information, and these associated information are represented by an analog voltage signal output by the neuron. In a related control method, first, a corresponding logic judgment is performed on the unconditioned stimulus signal and the conditioned stimulus signal, and a corresponding control voltage is formed using the result of the logic judgment; then, after different circuit combinations are formed by different control voltages, the memristor cross array in the synaptic circuit is triggered to change, and the resistance value of the memristor is adjusted to change, thereby combining the flexible and controllable characteristics of the synaptic circuit to realize data association and extraction of associated information; finally, an analog voltage signal is output to represent the size of the data amount, represent different information, and effectively indicate the change of associated information.

[0159] The technical solution of the present invention proposes a new type of 4T1M cross array and a corresponding voltage combination strategy that can be applied to a memristor associative memory neural network. Furthermore, in order to achieve the connection between the unconditioned stimulus signal, the conditioned stimulus signal and the voltage combination strategy, a logic conversion circuit and a voltage selection output circuit are designed. Furthermore, a timing voltage output circuit is designed to realize the forgetting process over time, and through this circuit design, the forgetting rate can be flexibly adjusted. In summary, the technical solution of the present invention not only uses the memristor cross array as a carrier, but also increases the integration of the circuit and the density of memory information storage. The analog signal output by the neuron is also used to represent different information and indicate the change of the associated information, which has a good effect. It needs to be further explained that according to the speech recognition and image processing results of the pre-neural network, the corresponding associated information is obtained using this memristor neural network circuit, and a human-computer interaction system for fruit associated information extraction can be established, which is used in the field of intelligent robots to enhance the service experience of intelligent robots.

[0160] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A memristor associative memory neural network circuit, characterized in that: The invention comprises a logic output circuit, a synaptic circuit and a neuron circuit which are electrically connected in sequence, wherein the synaptic circuit comprises a memristor cross array, wherein: The logic output circuit generates a control voltage after receiving an unconditioned stimulus signal and / or a conditioned stimulus signal; the synaptic circuit adjusts the resistance of the memristors in the memristor cross array under the triggering of the control voltage to realize an associative memory function and / or an associative output function; the neuron circuit outputs an analog voltage signal for representing the associative information according to the adjusted resistance of the memristors in the memristor cross array; The logic output circuit includes a logic conversion circuit and a voltage selection output circuit which are electrically connected in sequence; the logic conversion circuit includes a first NOT gate and an OR gate, the conditional stimulus signal is connected to the input end of the first NOT gate, the unconditional stimulus signal is connected to the first input end of the OR gate, and the output end of the NOT gate is connected to the second input end of the OR gate; The voltage selection output circuit includes a first analog switch and a second analog switch, the output end of the OR gate is electrically connected to the control end of the first analog switch, and the first input end of the first analog switch is connected to a first voltage, and the second input end is connected to a second voltage; the output end of the NOT gate is electrically connected to the control end of the second analog switch, and the first input end of the second analog switch is connected to a third voltage, and the second input end is connected to a fourth voltage; The memristor crossbar array in the synaptic circuit includes M row signal lines and N column signal lines, the row signal lines and the column signal lines cross each other but are not directly connected, wherein each row signal line is connected to each column signal line at the intersection through a circuit unit including a memristor; The control voltage includes a first control voltage signal output by a first analog switch and a second control voltage signal output by a second analog switch, and the circuit unit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor and a memristor, wherein: One end of the first MOS transistor is electrically connected to the row signal line for receiving the first control voltage signal, and the other end of the first MOS transistor is electrically connected to the positive electrode of the memristor; One end of the second MOS tube is connected to one end of the first MOS tube, and the other end of the second MOS tube is connected to the negative electrode of the memristor; One end of the third MOS tube is connected to the positive electrode of the memristor, and the other end of the third MOS tube is connected to the column signal line; One end of the fourth MOS tube is connected to the negative electrode of the memristor, and the other end of the fourth MOS tube is connected to the column signal line; The control end of the first MOS tube, the control end of the second MOS tube, the control end of the third MOS tube, and the control end of the fourth MOS tube are electrically connected to a first shunt point respectively, and the first shunt point is used to receive the second control voltage signal.

2. The memristor associative memory neural network circuit according to claim 1, characterized in that: The neuron circuit is electrically connected to the column signal line in the synapse circuit, and the neuron circuit includes an operational amplifier and a neuron resistor, wherein: One end of the neuron resistor is electrically connected to the inverting input terminal of the operational amplifier, and the other end of the neuron resistor is electrically connected to the output terminal of the operational amplifier; An inverting input terminal of the operational amplifier is electrically connected to the column signal line, a non-inverting input terminal of the operational amplifier is grounded, and an output terminal of the operational amplifier outputs the analog voltage signal.

3. The memristor associative memory neural network circuit according to claim 1, characterized in that: The memristor associative memory neural network circuit further includes a timing voltage output circuit electrically connected to the synaptic circuit, wherein the timing voltage output circuit includes a clock pulse source, a binary counter, a monostable trigger, a second NOT gate, an AND gate, a third analog switch, and a fourth analog switch, wherein: The clock pulse source is electrically connected to the binary counter, and is used to output a pulse signal to the binary counter; The binary counter is electrically connected to the monostable trigger, and is used to output a logic indication level to the monostable trigger when the pulse signal is counted to a preset value; The conditional stimulus signal is connected to the input end of the second NOT gate, and the output end of the second NOT gate is connected to the first input end of the AND gate; the monostable trigger is connected to the second input end of the AND gate; the AND gate is electrically connected to the control end of the third analog switch and the control end of the fourth analog switch respectively; The first input terminal of the third analog switch is connected to the fifth voltage, the second input terminal is set to a high impedance state, and the output terminal of the third analog switch is electrically connected to the row signal line in the synaptic circuit; The first input terminal of the fourth analog switch is connected to the sixth voltage, the second input terminal is set to a high impedance state, and the output terminal of the fourth analog switch is electrically connected to the first shunt point in the circuit unit of the synaptic circuit.

4. A control method for a memristor associative memory neural network circuit, characterized in that: Based on the memristor associative memory neural network circuit according to any one of claims 1 to 3, the control method comprises: Through the logic output circuit, the received unconditioned stimulus signal and / or conditioned stimulus signal is subjected to logic transformation to generate a control voltage; By means of the synaptic circuit, under the triggering of the control voltage, the resistance values ​​of the memristors in the memristor cross array are adjusted to realize the associative memory function and / or the associative output function; Through the neuron circuit, according to the adjusted resistance value of the memristor in the memristor cross array, an analog voltage signal for representing the associated information is output.

5. The control method of the memristor associative memory neural network circuit according to claim 4, characterized in that: The control voltage includes a first control voltage signal output by the first analog switch and a second control voltage signal output by the second analog switch. The logic output circuit performs a logic transformation on the received unconditioned stimulus signal and / or conditioned stimulus signal to generate the control voltage, including: When the unconditioned stimulus signal and the conditioned stimulus signal are both at a high level, a logic conversion circuit performs a logic judgment, and the result of the logic judgment is input into a voltage selection output circuit, and a first control voltage signal output by a first analog switch in the voltage selection output circuit and a second control voltage signal output by a second analog switch form a first voltage combination, wherein the first voltage combination is used to trigger the synaptic circuit to realize an associative memory function and complete the storage of associated information; When the unconditioned stimulus signal is at a low level and the conditioned stimulus signal is at a high level, a logic conversion circuit performs a logic judgment, and the result of the logic judgment is input into the voltage selection output circuit, and the first control voltage signal and the second control voltage signal form a second voltage combination, wherein the second voltage combination is used to trigger the synaptic circuit to realize an associated output function; When the unconditioned stimulus signal and the conditioned stimulus signal are both at a low level, or the unconditioned stimulus signal is at a high level and the conditioned stimulus signal is at a low level, a logic judgment is performed through a logic conversion circuit, and the result of the logic judgment is input into the voltage selection output circuit, and the first control voltage signal and the second control voltage signal form a third voltage combination and a fourth voltage combination, wherein neither the third voltage combination nor the fourth voltage combination triggers the synaptic circuit to realize an associative memory function or an associated output function.

6. The control method of the memristor associative memory neural network circuit according to claim 5, characterized in that: The synaptic circuit, under the triggering of the control voltage, adjusts the resistance of the memristors in the memristor cross array to realize the associative memory function and / or the associative output function, including: When the synaptic circuit receives the first voltage combination, the first MOS tube and the fourth MOS tube in the circuit unit of the synaptic circuit are turned on, and the second MOS tube and the third MOS tube are turned off, and when the first control voltage signal is greater than the threshold voltage of the memristor, the resistance of the memristor decreases continuously, thereby realizing the associative memory function; When the synaptic circuit receives the second voltage combination, the first MOS tube and the fourth MOS tube are turned on, and the second MOS tube and the third MOS tube are turned off. When the first control voltage signal is less than the threshold voltage of the memristor, the resistance value of the memristor remains unchanged, thereby realizing the associated output function. When the synaptic circuit receives the third voltage combination or the fourth voltage combination, the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all disconnected; The step of outputting an analog voltage signal for representing the associated information according to the adjusted memristor resistance in the memristor cross array through the neuron circuit includes: Determine the synaptic weight based on the ratio of the neuron resistance and the adjusted memristor resistance; The analog voltage signal is determined according to the synaptic weight and the first control voltage signal.

7. The control method of the memristor associative memory neural network circuit according to any one of claims 3 to 6, further comprising: When the unconditioned stimulus signal and the conditioned stimulus signal are both at a high level, or the unconditioned stimulus signal is at a low level and the conditioned stimulus signal is at a high level, the third analog switch and the fourth analog switch in the timing voltage output circuit output a high impedance state; When both the unconditioned stimulus signal and the conditioned stimulus signal are at a low level, or the unconditioned stimulus signal is at a high level and the conditioned stimulus signal is at a low level, if the timing voltage output circuit times to a preset time, the third control voltage signal output by the third analog switch and the fourth control voltage signal output by the fourth analog switch form a fifth voltage combination, so that the associated information is forgotten over time. By changing the device parameters in the monostable trigger circuit, the duration of the fifth voltage combination can be adjusted to change the forgetting rate over time; When the synaptic circuit receives the fifth voltage combination, the second MOS tube and the third MOS tube in the circuit unit of the synaptic circuit are turned on, and the first MOS tube and the fourth MOS tube are turned off. When the third control voltage signal is greater than the threshold voltage of the memristor, the resistance of the memristor increases continuously, thereby realizing the function of forgetting associated information over time.

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