Drive circuit

Abstract

The present application provides a driving circuit, including: a driving unit, a pre-driving module and a resistance selection circuit. The pull-up resistor of the driving unit is adjustable; the pre-driving module is connected to M driving units, and the pull-up resistors and the resistance values ​​of the pull-up resistors of the M driving units are controlled by a driving control signal, wherein M is an integer greater than 1; the resistance selection circuit is connected to the pre-driving module, and is used to select one of a first encoding and a second encoding as a target encoding according to a selection signal, and the pre-driving module outputs the driving control signal according to the target encoding. The driving circuit of the present application can improve the speed, integrity and accuracy of DRAM data reading and writing.

Description

Technical Field

[0001] The present application relates to semiconductor technology, and in particular to a driving circuit. Background Art

[0002] In the use of dynamic random access memory (DRAM), the speed, integrity and accuracy of data reading and writing have always been important indicators for judging DRAM performance, and a very important factor that determines the speed, integrity and accuracy of DRAM data reading and writing is the resistance of the driving circuit in the DRAM chip. The driving circuit in the DRAM chip is electrically connected to the DRAM controller chip (DRAM Controller) and performs signal interaction. The output impedance of the driving circuit can affect the speed, integrity and accuracy of the signal from the DRAM chip to the DRAM controller chip, and the terminal resistance of the driving circuit can affect the speed, integrity and accuracy of the signal transmitted from the DRAM controller chip to the DRAM chip.

[0003] When reading a DRAM chip, the output impedance of the driver circuit in the DRAM chip is required to match the terminal resistance of the DRAM controller chip. When writing a DRAM chip, the output impedance of the DRAM controller chip is required to match the terminal resistance of the DRAM chip. As the operating frequency of DRAM increases, how to adjust the resistance of the DRAM driver circuit to improve the speed, integrity and accuracy of the data signal exchanged between the DRAM chip and the DRAM controller chip is still a problem that needs to be solved. Summary of the invention

[0004] The present application provides a driving circuit for improving the speed, integrity and accuracy of data signals exchanged between a DRAM chip and a DRAM controller chip.

[0005] A driving circuit, comprising:

[0006] A driving unit, wherein the pull-up resistor of the driving unit is adjustable;

[0007] A pre-driving module, connected to the M driving units, and controlling the pull-up resistors and the resistance values ​​of the pull-up resistors of the M driving units through a driving control signal, wherein M is an integer greater than 1;

[0008] The resistance selection circuit is connected to the pre-driving module and is used to select one of the first code and the second code according to the selection signal and output it as the target code. The pre-driving module outputs the driving control signal according to the target code.

[0009] In one of the embodiments, when the resistance selection circuit outputs a first code, the pull-up resistor of each of the driving units is smaller than a third resistor; when the resistance selection circuit outputs a second code, the pull-up resistor of each of the driving units is larger than the third resistor; and the resistance value of the third resistor is a preset resistance value.

[0010] In one of the embodiments, the driving unit includes a first pull-up transistor and a first pull-down transistor, the first ends of the first pull-up transistors of the M driving units are all connected to the power supply end, the second ends of the first pull-up transistors of the M driving units are all connected to the input-output end, the first ends of the first pull-down transistors of the M driving units are all connected to the input-output end, and the second ends of the first pull-down transistors of the M driving units are all connected to the ground end.

[0011] In one of the embodiments, the first pull-up transistor of each of the driving units is composed of N first transistors, the first ends of the N first transistors are all connected to the power supply end, and the second ends of the N first transistors are all connected to the input-output end; the first pull-down transistor of each of the driving units is composed of N second transistors, the first ends of the N second transistors are all connected to the input-output end, and the second ends of the N second transistors are all connected to the ground end; N is an integer greater than 1.

[0012] In one of the embodiments, the driving control signal is M groups, each group is N bits, the driving control signals of the M groups correspond one-to-one to the M driving units, and the driving control signals of the N bits correspond one-to-one to the N first transistors; each bit of the driving control signal is connected to the control end of the corresponding first transistor.

[0013] In one embodiment, the first transistor is a P-type transistor, and the second transistor is an N-type transistor.

[0014] In one embodiment, both the first transistor and the second transistor are N-type transistors.

[0015] In one embodiment, the selection signal is a read flag signal, when the read flag signal is at a high level, the target code is a first code, and when the read flag signal is at a low level, the target code is a second code.

[0016] In one embodiment, the resistance selection circuit further includes a calibration circuit, and the calibration circuit is used to generate the first code and the second code.

[0017] In one embodiment, the calibration circuit comprises:

[0018] A comparator, a first input terminal of which is connected to a reference voltage, and a second input terminal of which is connected to a calibration port;

[0019] a counter connected to the output terminal of the comparator and outputting the first code or the second code;

[0020] a pull-up module, wherein a first end of the pull-up module is connected to a power supply end, a second end of the pull-up module is connected to the calibration port, and a third end of the pull-up module is connected to the counter, wherein an equivalent resistance value of the pull-up module from the power supply end to the calibration port is controlled by the first code or the second code output by the counter;

[0021] An external calibration resistor has a first end connected to the calibration port and a second end connected to the ground.

[0022] In one embodiment, the pull-up module and the pull-up resistor of the driving unit have the same circuit structure.

[0023] In one embodiment, the first reference voltage is less than the second reference voltage.

[0024] In one of the embodiments, the reference voltage is a first reference voltage or a second reference voltage, the first reference voltage is less than half of the voltage value of the power supply end; the second reference voltage is greater than half of the voltage value of the power supply end.

[0025] In one of the embodiments, the voltage value of the power supply terminal is VDDQ, the resistance value of the external calibration resistor is RZQ, the first reference voltage is equal to VDDQ*(RZQ-b) / (2*RZQ-b), and the second reference voltage is equal to VDDQ*(RZQ+a) / (2*RZQ+a), where a and b are both preset deviation values.

[0026] On the other hand, the present application also provides a memory, including:

[0027] As in the driving circuit described in the first aspect, the selection signal comes from the control circuit inside the memory, the driving unit selects to receive the pre-output signal inside the memory as its own input signal according to the read enable signal from the control circuit, and the driving unit selects to receive the pre-input signal outside the memory as its own input signal according to the write enable signal from the control circuit.

[0028] The driving circuit provided by the present application includes the driving unit, the pre-driving module and the resistance selection circuit. The resistance selection circuit can select the first code or the second code as the target code according to the selection signal and output it to the pre-driving module, and the pre-driving module outputs the driving control signal according to the target code, and the driving control signal controls the pull-up resistors and the resistance values ​​of the pull-up resistors of the M driving units. When the DRAM is in the data writing state, the resistance value of the pull-up resistor of the driving unit increases to be greater than the third resistor under the control of the pre-driving module. When the DRAM is in the data reading state, the resistance value of the pull-up resistor of the driving unit decreases to a value less than another third resistor under the control of the pre-driving module. Therefore, the driving circuit provided by the present application can adjust its own resistance value for the read-write state of the DRAM, so that the impedance matching degree when reading and writing data between the DRAM controller chip and the DRAM chip can be flexibly adjusted within the prescribed allowable range to improve the speed, integrity and accuracy of DRAM data reading and writing. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0030] Figure 1 A schematic diagram of DRAM reading data provided in this application.

[0031] Figure 2 A schematic diagram of DRAM writing data provided in this application.

[0032] Figure 3 A schematic diagram of a driving circuit provided for one embodiment of the present application.

[0033] Figure 4 A schematic diagram of the structure of a drive unit provided for one embodiment of the present application.

[0034] Figure 5 A schematic diagram of a calibration circuit provided for one embodiment of the present application.

[0035] Figure 6 A schematic diagram of a driving circuit provided for one embodiment of the present application.

[0036] Figure 7 A schematic diagram of a memory provided for one embodiment of the present application.

[0037] Description of Reference Numerals

[0038] Driving circuit 10

[0039] Drive unit 100

[0040] The first pull-up transistor 110

[0041] The first transistor 111

[0042] The first pull-down transistor 120

[0043] The second transistor 121

[0044] Pre-driver module 200

[0045] Resistance selection circuit 300

[0046] Calibration circuit 310

[0047] Comparator 311

[0048] Counter 312

[0049] Pull-up module 313

[0050] External calibration circuit 314

[0051] Power supply terminal 20

[0052] Input and output terminal 30

[0053] Ground terminal 40

[0054] Calibration port 50

[0055] Power supply terminal 51

[0056] Memory 70

[0057] Control circuit 71

[0058] The above drawings show clear embodiments of the present disclosure, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0059] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0060] As the speed of DRAM reading and writing increases, for example, DDR4 can reach a reading and writing speed of 3.2GHz, and DDR5 can even reach a reading and writing speed of 6.4GHz. This requires that the DRAM controller chip and the DRAM chip must meet the impedance matching requirements when exchanging data. If the impedance matching is not met, the signal transmitted during the data exchange will be reflected, seriously affecting the quality of the transmitted signal, resulting in the DRAM controller chip being unable to distinguish the high or low level of the signal transmitted by the DRAM chip when the DRAM chip is read, and the DRAM chip being unable to distinguish the high or low level of the signal transmitted by the DRAM controller chip when the DRAM chip is written. The use specification of DRAM chips stipulates the requirements for impedance matching. For example, when a DRAM chip undergoes a write operation, the receiving circuit in the DRAM chip acts as a signal receiver (Receiver), the pull-up resistor of the driving circuit in the DRAM chip acts as a terminal resistor Rtt, and the DRAM controller chip acts as a signal transmitter (Transmit) with an output impedance Ron. Assuming that the output impedance Ron of the transmitter is 34 ohms, the terminal resistor Rtt must be 240 ohms, or a certain percentage deviation is allowed, for example, the terminal resistor Rtt allows a deviation of 10%, then the terminal resistor Rtt can be 216 ohms to 264 ohms; for another example, when a DRAM chip undergoes a read operation, the driving circuit in the DRAM chip acts as a signal transmitter, the pull-up resistor of the driving circuit in the DRAM chip acts as an output impedance Ron, and the DRAM controller chip acts as a signal receiver with a terminal resistor Rtt. Assuming that the terminal resistor Rtt is 240 ohms, the output impedance needs to be 34 ohms, or a certain percentage deviation is allowed, for example, the output impedance Ron allows a deviation of 10%, then the output impedance Ron can be 31 ohms to 37 ohms. The above is only for illustrative purposes, and specific impedance matching requirements may refer to the standards published by the Joint Electric Power Development Council (JEDEC).

[0061] It should be noted that, on the DRAM chip side, when the DRAM chip is written, the pull-up resistor of the DRAM chip's driving circuit serves as the terminal resistor Rtt, and when the DRAM chip is read, the pull-up resistor of the DRAM chip's driving circuit serves as the output impedance Ron. In addition, when the pull-up resistor of the driving circuit serves as the terminal resistor Rtt, the larger the value of the terminal resistor Rtt is within the specified range, the more conducive it is to improving the quality and integrity of signal transmission. For example, a terminal resistor Rtt of 264 ohms is more conducive to improving the quality and integrity of signal transmission than 240 ohms; when the pull-up resistor of the driving circuit serves as the output impedance Ron, the smaller the value of the output impedance Ron is within the specified range, the more conducive it is to improving the quality and integrity of signal transmission. For example, an output impedance Ron of 31 ohms is more conducive to improving the quality and integrity of signal transmission than 34 ohms.

[0062] For example, Figure 1 The schematic diagram of DRAM reading data is shown. The DRAM side includes a plurality of driving units 100. Each driving unit 100 includes a first pull-up transistor 110 and a first pull-down transistor 120. The data signal is from the DRAM to the DRAM Controller. The pull-up resistor on the DRAM side serves as the output impedance Ron. The output impedance Ron is composed of 7 240 ohms connected in parallel. The equivalent output impedance Ron is equal to 34 ohms. The pull-up resistor on the DRAM Controller side serves as the terminal resistance Rtt. The terminal resistance Rtt is composed of 1 240 ohms and 6 infinite ohms connected in parallel. The equivalent terminal resistance Rtt is equal to 240 ohms. The infinite ohm is the resistance equivalent to infinity caused by the disconnection of the switch. For the DRAM side, if the output impedance Ron is reduced to 31 ohms, the impedance matching requirement is still met within a certain range, but the driving capability of the DRAM side is improved, thereby improving the quality and integrity of signal transmission.

[0063] For example, Figure 2The schematic diagram of writing data to a DRAM is shown. The DRAM side includes a plurality of drive units 100. Each drive unit 100 includes a first pull-up transistor 110 and a first pull-down transistor 120. The data signal is from the DRAM Controller to the DRAM. The pull-up resistor on the DRAM Controller side serves as the output impedance Ron. The output impedance Ron is composed of 7 240 ohms connected in parallel. The equivalent output impedance Ron is equal to 34 ohms. The pull-up resistor on the DRAM side serves as the terminal resistor Rtt. The terminal resistor Rtt is composed of 1 240 ohms and 6 infinite ohms connected in parallel. The equivalent terminal resistor Rtt is equal to 240 ohms. The infinite ohm is the resistance equivalent to infinity caused by the disconnection of the switch. For the DRAM side, if the terminal resistor Ron is increased to 264 ohms, the impedance matching requirement is still met within a certain range, but the quality and integrity of the received signal on the DRAM side are improved.

[0064] Therefore, the present application provides a driving circuit 10, which can adjust its own resistance according to the read and write status of the DRAM and the resistance of the DRAM controller to flexibly adjust the impedance matching degree between the DRAM chip and the DRAM controller chip, wherein the DRAM controller can also be called a DRAM controller chip, or a DRAM Controller.

[0065] The structure and operation principle of the driving circuit 10 provided in the present application are described in detail below.

[0066] See also Figure 3 The driving circuit 10 provided in this embodiment includes a driving unit 100 , a pre-driving module 200 and a resistance selection circuit 300 .

[0067] There are M driving units 100 in total, where M is an integer greater than zero. The pre-driving module 200 is connected to the M driving circuits and controls the resistance of the pull-up resistors of the M driving units 100 through a driving control signal. When the DRAM is in a data writing state, the driving control signal controls the resistance of the pull-up resistor of each driving unit in the M driving units 100. Specifically, in order to improve the impedance matching between the DRAM and the controller of the DRAM, the driving control signal controls the resistance of the pull-up resistor of each driving unit in the M driving units 100 to increase, thereby improving the quality and integrity of the signal received by the DRAM. When the DRAM is in a data reading state, the driving control signal controls the resistance of the pull-up resistor of each driving unit 100 in the M driving units 100. Specifically, in order to improve the impedance matching between the DRAM and the controller of the DRAM, the driving control signal controls the resistance of the pull-up resistor of each driving unit 100 in the M driving units 100 to decrease, thereby enhancing the driving capability of the DRAM output signal and improving the integrity of the output signal.

[0068] The resistance selection circuit 300 is connected to the pre-driver module 200, and the resistance selection circuit 300 is used to receive an external input selection signal, and select one of the first code and the second code according to the selection signal to output as the target code, and then the pre-driver module 200 outputs the drive control signal according to the target code. Optionally, the selection signal is a read flag signal, and when the read flag signal is a high-level signal, the target code is the first code, and the DRAM is in a data reading state. When the read flag signal is a low-level signal, the target code is the second code, and the DRAM is in a data writing state. The function of the selection signal is to indicate whether the DRAM is in a data reading state or a data writing state. The function of the first coding is to reduce the resistance of the pull-up resistor of the driving unit 100, or the first coding is used to set a resistance of the pull-up resistor of the driving unit 100 that is smaller than the first preset resistance value. For example, if the first preset resistance value is 34 ohms, the first coding can set the resistance of the pull-up resistor of the driving unit 100 to 31 ohms. The function of the second coding is to increase the resistance of the pull-up resistor of the driving unit 100, or the second coding is used to set a resistance of the pull-up resistor of the driving unit 100 that is larger than the second preset resistance value. For example, if the second preset resistance value is 240 ohms, the second coding can set the resistance of the pull-up resistor of the driving unit 100 to 264 ohms. Optionally, the resistance selection circuit 300 can be a two-to-one selector.

[0069] When the DRAM is in a state of reading data, the target code is the first code, that is, when the resistance selection circuit 300 outputs the first code, the pre-driver module 200 controls the pull-up resistor of each driver unit 100 to be smaller than the third resistor according to the first code. When the DRAM is in a state of writing data, that is, when the resistance selection circuit 300 outputs the second code, the pre-driver module 200 controls the pull-up resistor of each driver unit 100 to be larger than the third resistor according to the second code. The resistance value of the third resistor is a preset resistance value, which is determined by the value of M. For example Figure 1 The DRAM is shown in the state of reading data, at this time M=7, the preset resistance value of the third resistor is 34 ohms, and the pre-driver module 200 controls the pull-up resistance of each driver unit 100 to be less than 34 ohms according to the second code, for example, the resistance value of each driver unit 100 in the 7 driver units 100 is 31 ohms. Figure 2 The DRAM is shown in a data writing state, where M=1, the preset resistance value of the third resistor is 240 ohms, and the pre-driver module 200 controls the pull-up resistance of each driver unit 100 to be greater than 240 ohms according to the second coding, for example, the resistance value of one driver unit 100 is 264 ohms.

[0070] In summary, the driving circuit 10 provided in this embodiment includes the driving unit 100, the pre-driving module 200 and the resistance selection circuit 300. The resistance selection circuit 300 can select the first code or the second code as the target code according to the selection signal and output it to the pre-driving module 200, and the pre-driving module 200 outputs the driving control signal according to the target code, and the driving control signal controls the resistance of the pull-up resistors of the M driving units 100. When the DRAM is in the data writing state, the resistance value of the pull-up resistor of the driving unit 100 increases to be greater than the third resistor under the control of the pre-driving module 200. When the DRAM is in the data reading state, the resistance value of the pull-up resistor of the driving unit 100 decreases to be less than another third resistor under the control of the pre-driving module 200. Therefore, the driving circuit 10 provided in this embodiment can adjust its own resistance value according to the read and write state of the DRAM, so that the impedance matching degree between the DRAM and the controller that controls the DRAM to read and write data can be adjusted to improve the speed, integrity and accuracy of DRAM data reading and writing.

[0071] See also Figure 4In one embodiment of the present application, the driving unit 100 includes a first pull-up transistor 110 and a first pull-down transistor 120, that is, one driving unit 100 includes one first pull-up transistor 110 and one first pull-down transistor 120. The first ends of the first pull-up transistors 110 of the M driving units 100 are all connected to the power supply terminal 20, and the second ends of the first pull-up transistors 120 of the M driving units 100 are all connected to the input-output terminal 30. The first ends of the first pull-down transistors 120 of the M driving units 100 are all connected to the input-output terminal 30, and the second ends of the first pull-down transistors 120 of the M driving units 100 are all connected to the ground terminal 40. Among them, the input-output terminal 30 is used to input or output current, the specifications and models of the first pull-up transistor 110 and the first pull-down transistor 120 can be selected according to actual needs, and the present application does not limit them. The voltage value of the power supply terminal 20 can be selected according to actual needs.

[0072] The first pull-up transistor 110 may be composed of one transistor or multiple transistors. Optionally, the first pull-up transistor 110 of each driving unit 100 is composed of N first transistors 111, the first ends of the N first transistors 111 are connected to the power supply terminal 20, and the second ends of the N first transistors 111 are connected to the input-output terminal 30. The first pull-down transistor 120 may be composed of one transistor or multiple transistors. Optionally, the first pull-down transistor 120 of each driving unit 100 is composed of N second transistors 121, the first ends of the N second transistors 121 are connected to the input-output terminal 30, and the second ends of the N second transistors 121 are connected to the ground terminal 40. Wherein, N is an integer greater than 1, the value of N is determined according to the resistance value of the first transistor 111, the number of the second transistors 121 is determined by the number of the first transistors 111, and the specifications and models of the first transistor 111 and the second transistor 121 can be selected according to actual needs, and the present application does not limit it. Optionally, the first transistor 111 may be a P-type transistor, the second transistor 121 may be an N-type transistor, or both the first transistor 111 and the second transistor are N-type transistors.

[0073] Correspondingly, the driving control signal is M groups, each of the M groups is N bits, the driving control signals of the M groups correspond one-to-one to the M driving units, the driving control signals of the N bits correspond one-to-one to the N first transistors 111, and each driving control signal is connected to the control end of the corresponding first transistor 111. That is, the driving control signal is first divided into M groups of control signals according to the number of each driving unit 100 and then given to each driving unit 100, and the driving control signals received by each driving unit 100 may be the same or different. The divided driving control signal is then divided again according to the number of the first transistors 111 in each group of the driving units 100 to control each first transistor 111, so that each first transistor 111 has a separate driving control signal, and each first transistor 111 can be controlled to be turned on or off, so as to achieve the purpose of adjusting the resistance value of the driving unit 100.

[0074] See also Figure 5 In one embodiment of the present application, the resistance selection circuit 300 further includes a calibration circuit 310, and the calibration circuit 310 is used to generate the first code and the second code. The calibration circuit 310 includes a comparator 311, a counter 312, a pull-up module 313 and an external calibration circuit 314.

[0075] The first input terminal of the comparator 311 is connected to a reference voltage, which is a first reference voltage or a second reference voltage, and the first reference voltage is less than the second reference voltage. The second input terminal of the comparator 311 is connected to the calibration port 50. The counter 312 is connected to the output terminal of the comparator 311, and the counter 312 is used to determine whether to output the first code or the second code according to the signal output by the comparator 311. Specifically, the first input terminal of the comparator 311 is the positive input terminal of the comparator 211, and the second input terminal of the comparator 311 is the negative input terminal of the comparator 311.

[0076] The first end of the pull-up module 313 is connected to the power supply terminal 51, the second end is connected to the calibration port 50, and the third end is connected to the counter 312. The equivalent resistance value of the pull-up module 313 from the power supply terminal 51 to the calibration port 50 is controlled by the first code or the second code output by the counter 311. The pull-up module 313 has the same circuit structure as the pull-up resistor of the drive unit 100, that is, the pull-up module 313 also includes a plurality of transistors. When the transistors in the pull-up module 313 are not turned on, the equivalent resistance value of the pull-up module 313 is infinite. As the transistors in the pull-up module 313 are turned on, the equivalent resistance value of the pull-up module 313 gradually decreases. The first end of the external calibration resistor 314 is connected to the calibration port 50, and the second end is connected to the ground terminal. When the equivalent resistance of the pull-up module 313 is infinite, the voltage of the calibration port is 0, and the corresponding voltage of the second input terminal of the comparator 311 is 0. When the equivalent resistance of the pull-up module 313 gradually decreases, the voltage of the second input terminal of the comparator 311 gradually increases.

[0077] When the first input terminal of the comparator 311 is connected to the first reference voltage, when the pull-up module 313 does not receive the code input by the counter 312, the logic signal output by the comparator 311 is 1. When the counter 312 receives the logic signal 1, it outputs the code to the pull-up module 313, so that the transistor in the pull-up module 313 is turned on, thereby increasing the voltage of the calibration port, and the cycle repeats until the voltage of the calibration port 50 is equal to or greater than the first reference voltage. At this time, the code output by the counter 312 is the first code. For example, when all transistors in the pull-up module 313 are not turned on, the code output by the counter 312 for the first time may be ZQ Code_Ron <110> ,ZQ Code_Ron <110> It may be used to turn on the first transistor in the pull-up module 313. When the counter 312 receives the output of the comparator 311 for the second time and the logic signal is 1, the code output by the counter 312 for the second time may be ZQ Code_Ron <101> ,ZQ Code_Ron <101> It may be used to turn on the third transistor in the pull-up module 313. At this time, assuming that the equivalent resistance value of the pull-up module 313 can make the voltage of the calibration port 50 equal to the first reference voltage, the logic signal output by the comparator 311 received by the counter 312 is 0, and ZQ Code_Ron <101> The pull-up module 313 can be understood as an analog module of the driving unit 100. After receiving the first code, the pre-driving module 200 generates the driving control signal according to the first code, and the driving control signal controls the resistance value of the pull-up resistor of the driving unit 100 to be equal to the equivalent resistance value finally adjusted by the pull-up module 313.

[0078] When the first input terminal of the comparator 311 is connected to the second reference voltage, the generation process of the second code is also as described above, that is, when the pull-up module 313 does not receive the code input by the counter 312, the logic signal output by the comparator 311 is 1, and the counter 312 outputs the code to the pull-up module 313 when receiving the logic signal 1, so that the transistor in the pull-up module 313 is turned on, thereby increasing the voltage of the calibration port, and the cycle is repeated until the voltage of the calibration port 50 is equal to or greater than the first reference voltage, at which time the code output by the counter 312 is the second code. For example, when all transistors in the pull-up module 313 are not turned on, the code output by the counter 312 for the first time may be ZQ Code_Ron <110> ,ZQ Code_Ron <110> It may be used to turn on the first transistor in the pull-up module 313. When the counter 312 receives the output of the comparator 311 for the second time and the logic signal is 1, the code output by the counter 312 for the second time may be ZQCode_Ron <100> ,ZQ Code_Ron <100> It may be used to turn on the first transistor and the second transistor in the pull-up module 313. At this time, assuming that the equivalent resistance value of the pull-up module 313 can make the voltage of the calibration port 50 equal to the second reference voltage, the logic signal output by the comparator 311 received by the counter 312 is 0, and ZQ Code_Ron <100> After receiving the second code, the pre-driver module 200 generates the driving control signal according to the second code, and the driving control signal controls the resistance value of the pull-up resistor of the driver unit 100 to be equal to the equivalent resistance value finally adjusted by the pull-up module 313.

[0079] Optionally, the first reference voltage is less than half of the voltage value of the power supply terminal 51, and the second reference voltage is greater than half of the voltage value of the power supply terminal 51. If the voltage value of the power supply terminal 51 is VDDQ, and the resistance value of the external calibration resistor 314 is RZQ, then the first reference voltage is equal to VDDQ*(RZQ-b) / (2*RZQ-b), and the second reference voltage is equal to VDDQ*(RZQ+a) / (2*RZQ+a), where a and b are both preset deviation values, and the preset deviation value is determined by the staff. Optionally, the resistance value of the external calibration resistor 314 can be 240 ohms, the first reference voltage is equal to VDDQ*(240-b) / (480-b), and the second reference voltage is equal to VDDQ*(240+a) / (240+a).

[0080] See also Figure 6The structure and operation principle diagram of the driving circuit 10 provided in the present application, multiple 240 ohm resistors in parallel in the DRAM form multiple driving units DRV100, which are specifically composed of several 240 ohm resistors in parallel, and are generated by the ODT control signal ODT_info and the read control signal READ_info through the pre-driving module Pre-DRV200. <n:0>…DRVm <n:0>To control. Among them, DRVm <n:0>The m in DRV determines that there are m 240 ohm resistors connected in parallel, that is, there are m drive units DRV100 connected in parallel. <n:0>In <n:0>The target code is generated by the ZQ calibration technology, and the target code is used to enable the pre-driver module Pre-DRV200 to adjust the effective resistance value of each 240 ohm resistor according to the target code. Figure 6 As shown, the resistance selection circuit receives the selection signal READ_sig, the first code Zqcode_Ron <n:0>and the second code Zqcode Rtt <n:0>.

[0081] The selection signal READ_sig is a read flag signal. When the DRAM is in the state of reading data, that is, when the pull-up resistor on one side of the DRAM serves as the output impedance Ron, the read flag signal is a high-level signal, and the target code is the first code Zqcode_Ron. <n:0>At this time, the target code received by the pre-driver module 200 is the first code Zqcode_Ron <n:0>The pre-driver module 200 combines ODT_info, READ_info and the first code Zqcode_Ron <n:0>, output drive control signal DRVm <n:0>, m determines that there are m 240 ohm resistors in parallel, <n:0>Derived from the first code Zqcode_Ron <n:0>,DRVm <n:0>Used to reduce the resistance of each 240 ohm resistor. For example, when m is 7, the pull-up resistor on the DRAM side acts as the output impedance Ron, DRVm <n:0>The m in the DRAM can make the output impedance Ron of the DRAM be formed by connecting seven first pull-up transistors 110 in parallel, DRVm <n:0>In <n:0>The equivalent output impedance Ron can be made equal to 31 ohms (the equivalent resistance of each first pull-up transistor 110 is 216 ohms), which still meets the impedance matching requirements within a certain range, but improves the driving capability on the DRAM side, thereby improving the quality and integrity of signal transmission.

[0082] When the DRAM is in the state of writing data, that is, when the pull-up resistor on one side of the DRAM is used as the terminal resistor Rtt, the read flag signal is a low-level signal, and the target code is the second code Zqcode Rtt <n:0>At this time, the target code received by the pre-driver module 200 is the second code Zqcode_Rtt <n:0>The pre-driver module 200 combines ODT_info, READ_info and the second code Zqcode_Rtt <n:0>, output drive control signal DRVm <n:0>, m determines that there are m 240 ohm resistors in parallel, <n:0>Derived from the first code Zqcode_Rtt <n:0>For example, when m is 1, the pull-up resistor on the DRAM side acts as the terminal resistor Rtt, DRVm <n:0>The m in the DRAM can make the terminal resistance Rtt of the DRAM consist of a first pull-up transistor 110, DRVm <n:0>In <n:0>The equivalent terminal resistance Rtt can be made equal to 264 ohms (the equivalent resistance of each first pull-up transistor 110 is 264 ohms), which still meets the impedance matching requirement within a certain range, but improves the quality and integrity of the received signal on the DRAM side.

[0083] See also Figure 7 , an embodiment of the present application further provides a memory 70, which includes the drive circuit 10 described in the above embodiments. The selection signal in the drive circuit 10 comes from the control circuit 71 inside the memory 70. When the memory 70 is in a state of reading data, the memory 70 outputs data, and the drive unit 100 selects to receive the pre-output signal inside the memory 70 as its own input signal according to the read enable signal from the control circuit 71. When the memory 70 is in a state of writing data, the memory 70 receives data, and the drive unit 100 selects to receive the pre-input signal outside the memory 70 as its own input signal according to the write enable signal from the control circuit 71. Among them, the pre-output signal and the pre-input signal are both the drive control signal.

[0084] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0085] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A driving circuit, characterized in that: Applied to memory, including: A driving unit, wherein the pull-up resistor of the driving unit is adjustable; A pre-driving module, connected to the M driving units, and controlling the pull-up resistors and the resistance values ​​of the pull-up resistors of the M driving units through a driving control signal, wherein M is an integer greater than 1; a resistance selection circuit, connected to the pre-driving module, for selecting one of the first code and the second code according to a selection signal and outputting it as a target code, and the pre-driving module outputs the driving control signal according to the target code; The resistance value selection circuit further includes a calibration circuit, and the calibration circuit is used to generate the first code and the second code; The calibration circuit comprises: A comparator, a first input terminal of which is connected to a reference voltage, and a second input terminal of which is connected to a calibration port; a counter connected to the output terminal of the comparator and outputting the first code or the second code; a pull-up module, wherein a first end of the pull-up module is connected to a power supply end, a second end of the pull-up module is connected to the calibration port, and a third end of the pull-up module is connected to the counter, wherein an equivalent resistance value of the pull-up module from the power supply end to the calibration port is controlled by the first code or the second code output by the counter; An external calibration resistor, a first end of which is connected to the calibration port, and a second end of which is connected to a ground terminal; The reference voltage is a first reference voltage or a second reference voltage, and the first reference voltage is lower than the second reference voltage.

2. The driving circuit according to claim 1, characterized in that: When the resistance selection circuit outputs the first code, the pull-up resistor of each of the driving units is smaller than the third resistor; when the resistance selection circuit outputs the second code, the pull-up resistor of each of the driving units is larger than the third resistor; the resistance value of the third resistor is a preset resistance value.

3. The driving circuit according to claim 1, characterized in that: The driving unit includes a first pull-up transistor and a first pull-down transistor, the first ends of the first pull-up transistors of the M driving units are all connected to the power supply end, the second ends of the first pull-up transistors of the M driving units are all connected to the input-output end, the first ends of the first pull-down transistors of the M driving units are all connected to the input-output end, and the second ends of the first pull-down transistors of the M driving units are all connected to the ground end.

4. The driving circuit according to claim 3, characterized in that: The first pull-up transistor of each of the driving units is composed of N first transistors, the first ends of the N first transistors are all connected to the power supply end, and the second ends of the N first transistors are all connected to the input and output ends; the first pull-down transistor of each of the driving units is composed of N second transistors, the first ends of the N second transistors are all connected to the input and output ends, and the second ends of the N second transistors are all connected to the ground end; N is an integer greater than 1.

5. The driving circuit according to claim 4, characterized in that: The driving control signals are M groups, each group is N bits, the driving control signals of the M groups correspond one-to-one to the M driving units, and the driving control signals of the N bits correspond one-to-one to the N first transistors; each bit of the driving control signal is connected to the control end of the corresponding first transistor.

6. The driving circuit according to claim 5, characterized in that: The first transistor is a P-type transistor, and the second transistor is an N-type transistor.

7. The driving circuit according to claim 5, characterized in that: The first transistor and the second transistor are both N-type transistors.

8. The driving circuit according to claim 1, characterized in that: The selection signal is a read flag signal. When the read flag signal is at a high level, the target code is a first code. When the read flag signal is at a low level, the target code is a second code.

9. The driving circuit according to claim 1, characterized in that: The pull-up module and the pull-up resistor of the driving unit have the same circuit structure.

10. The driving circuit according to claim 1, characterized in that: The first reference voltage is less than half of the voltage value of the power supply terminal; the second reference voltage is greater than half of the voltage value of the power supply terminal.

11. The driving circuit according to claim 10, characterized in that: The voltage value of the power supply terminal is VDDQ, the resistance value of the external calibration resistor is RZQ, the first reference voltage is equal to VDDQ*(RZQ-b) / (2*RZQ-b), and the second reference voltage is equal to VDDQ*(RZQ+a) / (2*RZQ+a), where a and b are both preset deviation values.

12. A memory, characterized in that: include: According to the driving circuit as described in any one of claims 1 to 11, the selection signal comes from the control circuit inside the memory, the driving unit selects to receive the pre-output signal inside the memory as its own input signal according to the read enable signal from the control circuit, and the driving unit selects to receive the pre-input signal outside the memory as its own input signal according to the write enable signal from the control circuit.

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