Semiconductor arrangement and method of forming the same

Abstract

A semiconductor arrangement is provided. The semiconductor arrangement comprises a dielectric layer defining an opening, an adhesive layer located in the opening, and a conductive layer located in the opening above the adhesive layer. The material of the conductive layer is the same material as the adhesive material of the adhesive layer. Embodiments of the invention also relate to a method of forming a semiconductor arrangement.

Description

TECHNICAL FIELD

[0001] Embodiments of the invention relate to semiconductor arrangements and methods of forming the same. BACKGROUND

[0002] Semiconductor arrangements are used in a variety of electronic devices, such as mobile phones, laptop computers, desktop computers, tablet computers, watches, gaming systems, and various other industrial, commercial, and consumer electronic products. As the density of components within semiconductor arrangements increases, the size of the components of the semiconductor arrangements decreases. Interconnects are configured to carry signals to or from different components within the semiconductor arrangements. SUMMARY

[0003] Embodiments of the invention provide a semiconductor arrangement comprising a dielectric layer defining an opening, an adhesive layer located in the opening, and a conductive layer located in the opening above the adhesive layer, wherein a material of the conductive layer is a same material as an adhesive material of the adhesive layer.

[0004] Another embodiment of the invention provides a method of forming a semiconductor arrangement comprising forming an opening in a dielectric layer, wherein the opening is defined by a first sidewall of the dielectric layer and a second sidewall of the dielectric layer, coating the first sidewall and the second sidewall with a material comprising a metal and oxygen, and removing oxygen from the material such that an adhesive layer comprising the metal is located on the first sidewall and the second sidewall.

[0005] Yet another embodiment of the invention provides a method of forming a semiconductor arrangement comprising forming an opening in a dielectric layer to expose a conductive component underneath the dielectric layer, wherein the opening is defined by a first sidewall of the dielectric layer and a second sidewall of the dielectric layer, coating the first sidewall and the second sidewall with an adhesive layer, and forming a conductive layer in the opening above the adhesive layer, wherein a ratio of oxygen to a material of the conductive component is less than 1 :2 at an interface of the conductive component and the conductive layer. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the invention can be best understood with reference to the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the components in the figures are not necessarily to scale. In fact, the dimensions can be arbitrarily increased or decreased for clarity of discussion.

[0007] Figures 1 to 6 is an illustration of a semiconductor arrangement at various stages of manufacture according to some embodiments.

[0008] Figures 7 to 11 is an illustration of a method for forming a semiconductor arrangement according to some embodiments.

[0009] Figure 12 These are images of a semiconductor arrangement structure according to some embodiments.

[0010] Figure 13 This is a diagram illustrating a semiconductor arrangement according to some embodiments.

[0011] Figure 14 This is an illustration of a method for manufacturing a semiconductor arrangement according to some embodiments.

[0012] Figure 15 Exemplary computer-readable media according to some embodiments are shown.

[0013] Figure 16 This is a table of example parameter values ​​for stages of manufacturing semiconductor arrangements, according to some embodiments. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. Moreover, relational terms such as “connected to,” “adjacent to,” and “coupled to” may be used herein to describe direct and indirect relationships. A “direct” connection, adjacency, or coupling may refer to a relationship in which no intermediate component, device, or structure exists. An “indirect” connection, adjacency, or coupling may refer to a relationship in which an intermediate component, device, or structure exists.

[0016] One or more semiconductor arrangements are provided herein. The semiconductor arrangement includes a dielectric layer formed over an underlying conductive component, such as a gate structure. An opening is formed in the dielectric layer to expose at least an upper surface of the underlying conductive component. An adhesion layer of an adhesion material, such as tungsten, is formed on sidewalls of the dielectric layer defining the opening and on the upper surface of the underlying conductive component. The adhesion layer is formed by a process that also removes oxide from the upper surface of the underlying conductive component, from the sidewalls defining the opening, and / or from the adhesion layer. A conductive layer of the same material as the adhesion material is formed in the opening and over the adhesion layer. The conductive layer can form a contact plug, a vertical interconnect access plug, or other conductive structure. Removing the oxide from the upper surface of the underlying conductive component, from the sidewalls defining the opening, and / or from the adhesion layer reduces electrical resistance at the interface of the underlying conductive component and the conductive layer for improved conductivity and / or signal strength through the interface. The removal of the oxide also improves reliability of the semiconductor arrangement and increases yield of the semiconductor arrangement due to, for example, sufficient conductivity.

[0017] Because the adhesion material is the same material as the material of the conductive layer, no diffusion barrier layer is needed between the adhesion layer and the conductive layer. Because no diffusion barrier layer is needed, the area of the conductive layer is larger than in arrangements where one or more diffusion barrier layers are present. In the disclosed semiconductor arrangement, the conductive layer is thicker than a conductive layer formed over a diffusion barrier layer. The thicker conductive layer has greater conductivity than a conductive layer formed within an opening that includes a diffusion barrier layer.

[0018] The process of forming the adhesion layer includes depositing a precursor of the adhesion material of the adhesion layer and a plasma into the opening. The plasma removes native oxide from the upper (contact) surface of the underlying conductive component to facilitate / improve conductivity at the interface of the underlying conductive component and the conductive layer. The precursor of the adhesion material is a gaseous form of the material of the conductive layer. For example, the precursor of the adhesion material is the material of the conductive layer, such as tungsten, with a ligand, such as a carbon monoxide molecule, attached to the material. After depositing the precursor of the adhesion material in the opening, bombarding atoms or molecules separate the ligand from the adhesion material. The adhesion material, no longer in gaseous form, forms the adhesion layer over the upper surface of the underlying conductive component and on the sidewalls of the opening. The process of depositing the precursor of the adhesion material and a plasma into the opening can be performed periodically until the adhesion layer is formed to a predetermined thickness.

[0019] Figures 1 to 6 FIGS. 1-8 are illustrations of semiconductor arrangements at various stages of fabrication in accordance with some embodiments. Some embodiments described herein are in the context of back end of line (BEOL) processing of a semiconductor arrangement. Some embodiments described herein are in the context of middle end of line (MEOL) processing of a semiconductor arrangement. Some embodiments described herein are in other contexts of a semiconductor arrangement.

[0020] Turning to Figure 1 At least some of the semiconductor arrangement 100 is formed on and / or includes a substrate 102. The substrate 102 includes at least one of an epitaxial layer, a silicon-on-insulator structure, a wafer, a die formed from a wafer, or other suitable structure. In some embodiments, the substrate 102 includes at least one of silicon, germanium, carbide, gallium, arsenide, germanium, arsenic, indium, oxide, sapphire, or other suitable material.

[0021] The first dielectric layer 104 is formed over the substrate 102 by at least one of physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable technique. The first dielectric layer 104 includes at least one of a metal nitride, a high-k dielectric, a rare earth oxide, an aluminate of a rare earth oxide, a silicate of a rare earth oxide, or other suitable material. According to some embodiments, the first dielectric layer 104 includes at least one of silicon nitride (SiN), Si3N4, silicon dioxide (SiO2), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), zirconium dioxide (ZrO2), yttrium oxide (Y2O3), hafnium dioxide (HfO2), or other suitable material.

[0022] The conductive component 106 is formed over the first dielectric layer 104. Suitable processes including photolithography and etching processes are used to form the conductive component 106. According to some embodiments, the conductive component 106 is a gate formed by disposing a gate material over the first dielectric layer 104 and the substrate 102. The gate material is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, MBE, LPE, flowable CVD (FCVD), or other suitable technique. A photoresist layer (not shown) is formed over the gate material. The photoresist layer is exposed to, for example, light, and subjected to one or more development processes to produce a patterned photoresist or mask element. The mask element protects portions of the gate material while an etching process forms the gate over the first dielectric layer 104 by removing portions of the gate material that are not protected by the mask element. The mask element is removed by at least one of etching or other suitable technique. In some embodiments, the conductive component 106 is a component of a metal oxide semiconductor field effect transistor (MOSFET), a fin field effect transistor (FinFET), a bipolar junction transistor, a diode, a resistor, a capacitor, or other electronic component, where the photoresist layer can be similarly implemented as described.

[0023] A second dielectric layer 108 is formed over the substrate 102. The second dielectric layer 108 can be formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, MBE, LPE, flowable CVD (FCVD), or other suitable techniques. In some embodiments, the second dielectric layer 108 includes at least one of metal nitride, high-k dielectric, rare earth oxide, aluminate of rare earth oxide, silicate of rare earth oxide, SiN, Si02, Si3N4, Ti02, Ta205, Zr02, Y203, La205, Hf02, or other suitable materials. The second dielectric layer can be formed after forming at least one of the first dielectric layer 104 or the conductive feature 106, with some of the second dielectric layer being removed, such as by etching, chemical mechanical polishing (CMP), or the like, over at least one of the first dielectric layer 104 or the conductive feature 106. The second dielectric layer can be formed before forming at least one of the first dielectric layer 104 or the conductive feature 106, with some of the second dielectric layer being removed, such as by etching, from where at least one of the first dielectric layer 104 or the conductive feature 106 will be formed.

[0024] A third dielectric layer 110 is formed over the substrate 102. The third dielectric layer 110 can be formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, MBE, LPE, or other suitable techniques. In some embodiments, the third dielectric layer 110 includes at least one of metal nitride, high-k dielectric, rare earth oxide, aluminate of rare earth oxide, silicate of rare earth oxide, SiN, Si02, Si3N4, Ti02, Ta205, Zr02, Y203, La205, Hf02, or other suitable materials.

[0025] An opening 116 is formed in the third dielectric layer 110. In some embodiments, the opening 116 is formed by removing portions of the third dielectric layer 110 by at least one of etching or other suitable techniques. The opening 116 is defined by one or more sidewalls 112 of the third dielectric layer 110 and an upper surface 114 of the conductive feature 106. The conductive feature 106 is exposed through the opening 116.

[0026] Reference Figure 2A first adhesive coating 118a of an adhesive material is formed over at least one of one or more of the sidewalls 112, the upper surface 114 of the conductive component 106, or the upper surface 113 of the third dielectric layer 110. According to some embodiments, the first adhesive coating 118a is formed in a processing chamber (not shown) by depositing a gaseous precursor of the adhesive material and at least one of a first plasma of a first processing material or a second plasma of a second processing material into the openings 116. At least one of the first plasma or the second plasma is formed by subjecting at least one of the first processing material or the second processing material to at least one of an electric field or a magnetic field over or in at least one of the openings 116. In some embodiments, the at least one of the electric field or the magnetic field is a radio frequency field (RF field). Within the at least one of the electric field or the magnetic field, at least one of the first processing material or the second processing material is ionized to form at least one of the first plasma or the second plasma. The first plasma includes the first processing material in an ionized state and electrons, and the second plasma includes the second processing material in an ionized state and electrons. As each of the precursor of the adhesive material, the first processing material, and the second processing material flow into the processing chamber and over the third dielectric layer 110 through the at least one of the electric field or the magnetic field, the first adhesive coating 118a of the adhesive material is formed over at least one of one or more of the sidewalls 112, the upper surface 114 of the conductive component 106, or the upper surface 113 of the third dielectric layer 110.

[0027] According to some embodiments, the precursor of the adhesive material includes a carbon monoxide (CO) ligand attached to an adhesive atom or molecule, the adhesive material is tungsten (W), the precursor of the adhesive material is tungsten hexacarbonyl (W(CO)6), the first processing material is argon gas (Ar), the second processing material is molecular hydrogen (H2), the first plasma includes ionized Ar, and the second plasma includes ionized H. Within the processing chamber, Ar atoms dislodge native oxides from at least one of one or more of the sidewalls 112, the upper surface 114 of the conductive component 106, or the upper surface 113 of the third dielectric layer 110, and H2molecules react with the dislodged native oxides to form H2O molecules. The H2O molecules are purged from the openings 116 under high pressure processing. In some embodiments, a flow rate of at least one of the first processing material or the second processing material is sufficient to bombard the precursor of the adhesive material. Energy from the bombarding processing material causes the ligand to detach from the adhesive material, and the detached adhesive material forms the first adhesive coating 118a. Other materials of the ligand, the precursor of the adhesive material, the adhesive material, the first processing material, the second processing material, the first plasma, and the second plasma are within the scope of the present disclosure.

[0028] Reference is made to Figure 3A second adhesive coating 118b of adhesive material is formed over the first adhesive coating 118a (including over at least one of one or more of the sidewalls 112, the upper surface 114 of the conductive component 106, or the upper surface 113 of the third dielectric layer 110). The second adhesive coating 118b is formed by depositing at least one of a precursor of adhesive material, adhesive material, a first processing material, a second processing material, a first plasma, or a second plasma into the opening 116. According to some embodiments, the second adhesive coating 118b is formed in a manner similar to the formation of the first adhesive coating 118a.

[0029] Referring to Figure 4 A third adhesive coating 118c of adhesive material is formed over the second adhesive coating 118b (including over at least one of one or more of the first adhesive coating 118a, the sidewalls 112, the upper surface 114 of the conductive component 106, or the upper surface 113 of the third dielectric layer 110). The third adhesive coating 118c is formed by depositing at least one of a precursor of adhesive material, adhesive material, a first processing material, a second processing material, a first plasma, or a second plasma into the opening 116. According to some embodiments, the third adhesive coating 118c is formed in a manner similar to the formation of the first adhesive coating 118a.

[0030] Additional adhesive coatings can be formed in the manner described above and / or in other suitable manners. In some embodiments, at least one of a predetermined number of adhesive coatings is formed to obtain a predetermined thickness of adhesive material, the layered adhesive coatings are formed within a predetermined time period, or other criteria are used to determine the amount of adhesive material for forming the overlapping adhesive coatings over the sidewalls 112 and the upper surface 114 of the conductive component 106.

[0031] Referring to Figure 5 The first adhesive coating 118a, the second adhesive coating 118b, and the third adhesive coating 118c together form an adhesive layer 122 of adhesive material positioned over the conductive component 106, the one or more sidewalls 112, and the upper surface 113 of the third dielectric layer 110. The adhesive layer 122 can be in direct or indirect contact with the conductive component 106. The adhesive layer 122 can be in direct or indirect contact with at least one of the first sidewall 112 or the second sidewall 112.

[0032] After forming the adhesive layer 122, a conductive layer 120 of adhesive material is formed in the openings 116. The adhesive layer 122 can be a seed layer for forming the conductive layer 120. The conductive layer 120 of adhesive material is formed in the openings 116 by a suitable process such as at least one of electroplating (ECP), CVD, PVD, atomic layer deposition (ALD), sputtering, or electron beam evaporation. In some embodiments, 55% to 75% of the volume of the openings 116 is occupied by the conductive layer 120.

[0033] Referring to Figure 6 , at least one of the planarized conductive layer 120, the adhesive layer 122, or the third dielectric layer 110 is planarized to form a planar topography. According to some embodiments, planarizing includes one or more of CMP, etching, or other suitable processes performed to remove material. The remaining conductive layer 120 can be a contact plug, a vertical interconnect access plug, or other conductive structure.

[0034] Figures 7 to 11 is an illustration of a method for forming a semiconductor arrangement according to some embodiments. Figures 7 to 10 Several components of the semiconductor arrangement 100 shown in Figures 1 to 6 are the same as or similar to components of the semiconductor arrangement 100 shown and described. Descriptions of the same or similar components and methods of formation are omitted Figures 7 to 10 in order to avoid duplicative disclosure.

[0035] Figures 7 to 10 Each of the illustrations in

[0036] Turning to Figure 7The controller 701 is programmable and / or configured to receive commands for forming the adhesion layer 122. The controller 701 is configured to communicate with at least one of the radio frequency (RF) signal generator 702, the pressure valve 704, or the heat source 706. The controller 701 regulates the power level provided by the RF signal generator 702. The RF signal generator 702 generates an electromagnetic field within the showerhead 708. The controller 701 regulates the power level output by the RF signal generator 702 according to the degree or amount of plasma formation sufficient to perform one or more stages of the adhesion layer 122 formation. For example, a stage of forming the adhesion layer 122 can utilize an amount of process material output from the showerhead 708 that is greater than an amount of plasma generated from the process material and output from the showerhead 708. Another stage can utilize an amount of plasma generated from the process material and output from the showerhead 708 that is greater than an amount of process material output from the showerhead 708. The controller 701 regulates the power level output by the RF signal generator 702 accordingly.

[0037] The controller 701 regulates the pressure valve 704 according to the degree or range of pressure sufficient to perform one or more stages of the adhesion layer 122 formation. For example, a stage of forming the adhesion layer 122 can be performed at a different pressure than another stage. The controller 701 can generate commands to control the pressure valve 704 accordingly.

[0038] The controller 701 regulates the heat source 706 according to the temperature or temperature range sufficient to perform one or more stages of the adhesion layer 122 formation. The controller 701 can also regulate the heat source 706 to maintain a temperature or temperature range in one or more or all stages of the adhesion layer 122 formation. For example, some stages can be performed within a first temperature range, while other stages can be performed within a second temperature range that is different from the first temperature range. The controller 701 can generate commands to control the heat source 706 accordingly.

[0039] The controller 701 can also include at least one of a timer or a cycle counter to control at least one of a duration of one or more stages and / or a number of cycles of the adhesion layer 122 formation time or performance to form the adhesion layer 122 to a predetermined thickness.

[0040] In some embodiments, the controller 701 regulates at least one of: the first flow regulator 710 to control a first flow of the first process material 712 into the showerhead 708; the second flow regulator 714 to control a second flow of the second process material 716 into the showerhead 708; the third flow regulator 718 to control a third flow of a precursor of the adhesion material 720 into the showerhead 708; or other flow regulators to control other flows of materials into the showerhead. According to some embodiments, the precursor of the adhesion material 720 is a metal-organic based precursor material 721, such as W(CO)6. When the adhesion material 720 is a metal-organic based precursor material, the corresponding molecule has, for example, one part tungsten and six parts carbon (C) and oxygen (O), where the tungsten serves as the adhesion material 728 and the carbon and oxygen are ligands 730.

[0041] Figure 7 is an illustration of a first stage 700 of a method for forming a semiconductor arrangement 100 according to some embodiments. In the first stage 700, the pressure in the deposition chamber is set to be higher relative to the pressure in the deposition chamber of other stages. The high pressure promotes a high deposition rate of the precursor of the adhesion material 720 into the openings 116 and over at least one of the one or more sidewalls 112, the upper surface 114 of the conductive feature 106, or the upper surface 113 of the third dielectric layer 110.

[0042] In the first stage 700, the RF signal generator 702 generates a lower power level relative to the power level of other stages. The low power level generates a weaker electromagnetic field within the showerhead 708 than the electromagnetic field generated within the showerhead 708 in other stages. The electromagnetic field generated in the first stage 700 generates a first plasma 722 (represented by a black dot with a small vertical line) from the first process material 712 and a second plasma 724 (represented by a shaded dot with a small vertical line) from the second process material 716. At least one of the first plasma 722 or the second plasma 724 reacts with the precursor of the adhesion material 720 and separates the ligands 730 from some of the precursor of the adhesion material 720. In some embodiments, at least one of the first flow of the first process material 712 or the second flow of the second process material 716 is set lower in the first stage 700 than in other stages. The low flow of at least one of the first process material 712 or the second process material 716 and the low power level limit the number of reactions that separate the ligands 730 from the adhesion material 728. According to some embodiments, the first process material 712 includes at least one of a carrier material 725 (such as Ar), a purge material 727 (such as H2), or the precursor of the adhesion material 720. In some embodiments, the second process material is H2. In some embodiments, the equation for the reaction between W(CO)6 and H2 to separate the ligands 730 from the adhesion material 728 is:

[0043] W(CO)6 + H2→ W + H2O + 6C + 5O

[0044] In Figure 7 , C and O atoms are byproducts 726, indicated by clear triangles. Individual atoms of a carrier material 725 (such as Ar), indicated by black dots (without vertical lines), and individual atoms of a purge material 727 and / or a second process material 716 (such as H), indicated by shaded dots (without vertical lines), are mixed with the first plasma 722 and the second plasma 724.

[0045] Figure 16 is a table 1600 including examples of parameter values for stages of fabricating a semiconductor arrangement 100, including a stage 1 1602 corresponding to the first stage 700, according to some embodiments.

[0046] Figure 8 is an illustration of a second stage 800 of a method for forming a semiconductor arrangement 100, according to some embodiments. In the second stage 800, the pressure in the deposition chamber is decreased from the pressure in the deposition chamber during the first stage 700, and a second flow of the second process material 716 is increased. Increasing the second flow of the second process material 716 increases a rate of removal of oxides, such as carbon monoxide (CO), from at least one of the one or more sidewalls 112, the upper surface 114 of the electrically conductive component 106, or the upper surface 113 of the third dielectric layer 110. In some embodiments, an equation for a reaction between the second process material 716 and the oxides at the upper surface 114 of the electrically conductive component 106 is:

[0047] H2 + CO → H2O + C

[0048] Decreasing the pressure between the first stage 700 and the second stage 800 purges H2O, C, and other byproducts, such as Figure 8 , from the opening 116.

[0049] Figure 9is an illustration of a third phase 900 of a method for forming a semiconductor arrangement 100 according to some embodiments. In the third phase 900, the third flow regulator 718 is closed to prevent a precursor of the adhesive material 720 from entering the showerhead 708. The RF signal generator 702 increases the power level output to the showerhead 708. Increasing the power level increases the strength of the electromagnetic field within the showerhead 708. Increasing the strength of the electromagnetic field within the showerhead 708 increases the generation (amount) of the first plasma 722 and the second plasma 724. The first flow regulator 710 maintains a relatively high flow rate of the first process material 712 in standard cubic centimeters per minute (seem1), and the second flow regulator 714 maintains a relatively high flow rate of the second process material 716 in standard cubic centimeters per minute (seem2).

[0050] In the third phase 900, the first plasma 722 dislodges native oxide 723 (indicated with a clear square) that naturally exists in at least one of the one or more sidewalls 112, the upper surface 114 of the conductive feature 106, or the upper surface 113 of the third dielectric layer 110, and the second plasma 724 reacts with the dislodged native oxide to form H2O molecules, such as Figure 9 indicated. Also, the first plasma 722 and the second plasma 724 bombard the precursor of the adhesive material 720 on at least one of the one or more sidewalls 112, the upper surface 114 of the conductive feature 106, or the upper surface 113 of the third dielectric layer 110. Due at least to the increase in the amount of the first plasma 722 and the increase in the amount of the second plasma 724, the energy of the bombardment separates a large amount of ligands 730 from a large amount of atoms or molecules of the adhesive material 728, such as tungsten.

[0051] Figure 10 is an illustration of a fourth phase 1000 of a method for manufacturing a semiconductor arrangement 100 according to some embodiments. As explained with reference to Figure 9 the first plasma 722 and the second plasma 724 bombard the precursor of the adhesive material 720, the results of the bombardment are illustrated in Figure 10 . Figure 10 It is shown that at least almost all of the ligands 730 and the byproducts 726 are removed, and a first adhesive coating 118a of the adhesive material 728 is formed over at least one of the one or more sidewalls 112, the upper surface 114 of the conductive feature 106, or the upper surface 113 of the third dielectric layer 110.

[0052] In the fourth phase 1000, the third flow regulator 718 is opened to allow the precursor of the adhesive material 720 to enter the showerhead 708. The first flow regulator 710 maintains the relatively high flow of the first process material 712 in standard cubic centimeters per minute (seem 1), and the second flow regulator 714 maintains the relatively high flow of the second process material 716 in standard cubic centimeters per minute (seem 2). In the region between the showerhead 708 and the semiconductor arrangement 100, the first plasma 722 and the second plasma 724 bombard the precursor of the adhesive material 720. The bombardment separates the ligand 730 from the adhesive material 728. The adhesive material 728 descends onto the semiconductor arrangement 100 and onto at least one of the one or more sidewalls 112, the upper surface 114 of the conductive feature 106, or the upper surface 113 of the third dielectric layer 110. The first adhesive coating 118a of the adhesive material 728 serves as a seed layer and bonds with the descending adhesive material 728 to have an increased thickness.

[0053] In some embodiments, the method is cycled through the first through fourth phases to form additional adhesive coatings, such as 118b, 118c, etc. described above. In some embodiments, a predetermined number of adhesive coatings are formed to obtain a predetermined thickness "T" of the adhesive material over at least one of the one or more sidewalls 112, the upper surface 113 of the third dielectric layer 110, or the upper surface 114 of the conductive feature 106. According to some embodiments, T = 30 Angstroms

[0054] Referring to Figure 11 , the one or more adhesive coatings form an adhesive layer 122 having a thickness T. The adhesive layer 122 serves as a seed layer and bonds with the conductive layer material 1100 forming the conductive layer 120( Figure 5 and Figure 6 ) to build a contact plug, a vertical interconnect access plug, or other conductive structure. The conductive layer material 1100 is the same material as the material of the adhesive layer 122.

[0055] Referring to Figures 7 to 11 , according to some embodiments, the precursor of the adhesive material 720 includes a CO ligand, the adhesive material 728 includes W, the precursor of the adhesive material 720 is W(CO)6, the first process material 712 includes at least one of a carrier material such as Ar, a purge material such as H2, or the precursor of the adhesive material 720, the second process material 716 is H2, the first plasma 722 includes ionized Ar, and the second plasma 724 includes ionized H. In some embodiments, the precursor of the adhesive material 720 and the conductive layer material 1100 include one or more of cobalt (Co), ruthenium (Ru), iridium (Ir), or other suitable materials.

[0056] Referring to Figure 12, an image of a conductive structure 1200 is shown. The conductive structure 1200 is formed by applying a material of a conductive layer (VG) 1202 (in Figure 12 this case, but not perceptible) that is the same material as the material of the adhesive layer. The conductive layer 1202 is formed over a metal gate (MG) 1204 at an interface 1206. At the upper surface of the metal gate 1204, the ratio of oxygen to the material of the metal gate (MG) 1204, such as titanium (Ti), is measured to be less than 0.5 (1 :2). In some embodiments, the conductive layer 1202 corresponds to the conductive layer 120 shown in Figure 5 and Figure 6 In some embodiments, the metal gate (MG) corresponds to the conductive component 106 shown in Figures 1 to 11 .

[0057] Figure 13 is an illustration of a semiconductor arrangement 1300 according to some embodiments. The semiconductor arrangement 1300 can include components of logic devices, memory devices, or other electronic devices. The semiconductor arrangement 1300 is formed on and / or includes a substrate 1302; a first dielectric or semiconductor layer 1304, a second dielectric layer 1306 formed over the first dielectric / semiconductor layer 1304, and at least one of a third dielectric layer 1318 formed between the first dielectric / semiconductor layer 1304 and the second dielectric layer 1306. According to some embodiments, the first dielectric / semiconductor layer 1304 includes at least one of a dielectric material or a semiconductor material. The first dielectric / semiconductor layer 1304 can include a silicon germanium channel.

[0058] A plasma enhanced silicon nitride layer 1320 is formed around the third dielectric layer 1318. The semiconductor arrangement 1300 includes a gate material 1308 formed over the first dielectric / semiconductor layer 1304 and a spacer 1310, such as SiON, SiOCN, formed adjacent to the gate material 1308. A mask layer 1312, such as SiN, is formed between the spacer 1310 and a vertical interconnect access (VIA) structure 1316. The VIA structure 1316 is formed over an adhesive layer 1314. The material of the adhesive layer 1314 is the same material as the material of the VIA structure 1316. The adhesive layer 1314 and the VIA structure 1316 can be formed according to intermediate stages of the method for forming the semiconductor arrangement 100 of Figures 7 to 10 .

[0059] Figure 14is an illustration of a method of manufacturing a semiconductor arrangement according to some embodiments. The method of manufacturing a semiconductor arrangement (1400) includes determining a number of deposition cycles "n" needed to form an adhesion layer of an adhesion material having a thickness "T" over a sidewall of a dielectric layer and over an upper surface of an exposed conductive feature at a bottom of an opening defined by the sidewall of the dielectric layer (1402). A cycle variable "m" is set to zero (1404). An opening is formed in the dielectric layer to expose an upper surface of the conductive feature at a bottom of the opening in the dielectric layer (1406). A precursor of the adhesion material and the adhesion material are deposited over the sidewall and over the upper surface of the conductive feature in a high pressure environment (1408). The precursor of the adhesion material and the adhesion material are deposited over the sidewall and over the upper surface of the conductive feature in a low pressure environment (1410). At least one of a first processing material or a second processing material is exposed to an electric field to form at least one of a first plasma or a second plasma (1412). The at least one of the first plasma or the second plasma is deposited at a high flux over the sidewall and over the upper surface of the conductive feature to convert the precursor of the adhesion material to the adhesion material and to remove oxides from the sidewall and from the upper surface of the conductive feature (1414). The at least one of the first processing material or the second processing material is exposed to the electric field to form the at least one of the first plasma or the second plasma (1416). The precursor of the adhesion material is flowed into the at least one of the first plasma or the second plasma to form the adhesion material and the adhesion material is deposited into the opening to form a coating of the adhesion material over the sidewall and over the upper surface of the conductive feature (1418). It is determined whether "m" is equal to "n" (1420). If "m" is equal to "n", the method can end (1422). If "m" is not equal to "n", "m" is incremented by 1 (1424) and the method continues (1408).

[0060] According to some embodiments, the precursor of the adhesion material includes a CO ligand attached to an adhesion material atom or molecule, such as W, the precursor of the adhesion material is W(CO)6, the first processing material is Ar, the second processing material is H2, the first plasma includes ionized Ar, and the second plasma includes ionized H2.

[0061] Figure 15 An example computer-readable medium according to some embodiments is shown. One or more embodiments are directed to a computer-readable medium comprising processor-executable instructions configured to implement one or more techniques presented herein. Figure 15An example computer-readable medium is shown in FIG. 15, in which embodiment 1500 includes a computer-readable medium 1506 (e.g., a CD-R, a DVD-R, a flash drive, a platter of a hard drive, etc.) having encoded thereon computer-readable data 1504. The computer-readable data 1504, in turn, includes a set of processor-executable computer instructions 1502 configured, when executed, to facilitate operations in accordance with one or more principles set forth herein. In some embodiments 1500, the processor-executable computer instructions 1502 are configured to facilitate performance of the method 1400, such as at least some of the aforementioned methods. In some embodiments, the processor-executable computer instructions 1502 are configured to facilitate implementation of a system, such as at least some of the aforementioned systems. A person of ordinary skill in the art can design many such computer-readable media configured to operate in accordance with the technology presented herein.

[0062] As disclosed, a width of a conductive layer formed over an adhesive layer of the same material as a material of the conductive layer can be greater than a width of a conductive layer formed over an adhesive layer of a different material than a material of the conductive layer. A conductive layer formed over an adhesive layer of a different material requires a barrier layer between the adhesive layer and the conductive layer. The barrier layer consumes volume of the opening in which the conductive layer is formed, thereby limiting the width of the conductive layer. In contrast, a conductive layer formed over an adhesive layer of the same material does not require a barrier layer between the adhesive layer and the conductive layer. Thus, the conductive layer can be formed directly over the adhesive layer with a thickness that is greater than a thickness of a conductive layer formed over an adhesive layer of a different material. Because a thicker conductive layer has greater conductivity, the device has higher performance, reliability, and yield compared to a device with a thinner conductive layer.

[0063] According to some embodiments, a semiconductor arrangement includes a dielectric layer defining an opening, an adhesive layer in the opening, and a conductive layer over the adhesive layer in the opening. A material of the conductive layer is the same material as an adhesive material of the adhesive layer.

[0064] According to some embodiments, a semiconductor arrangement includes a conductive component exposed through the opening, and the conductive layer is over the conductive component.

[0065] According to some embodiments, a ratio of oxygen to a material of the conductive component is less than 1 :2 at an interface of the conductive component and the conductive layer.

[0066] According to some embodiments, the conductive component is exposed through the opening, and the adhesive layer is over the conductive component.

[0067] According to some embodiments, the adhesive layer is in direct contact with the conductive component.

[0068] According to some embodiments, the opening is defined by a first sidewall of the dielectric layer and a second sidewall of the dielectric layer.

[0069] According to some embodiments, the adhesion layer is in direct contact with at least one of the first sidewall or the second sidewall.

[0070] According to some embodiments, the adhesion layer comprises tungsten and the conductive layer comprises tungsten.

[0071] According to some embodiments, the conductive layer occupies 55% to 75% of a volume of the opening.

[0072] According to some embodiments, a method of forming a semiconductor arrangement comprises forming an opening in a dielectric layer, wherein the opening is defined by a first sidewall of the dielectric layer and a second sidewall of the dielectric layer, coating the first sidewall and the second sidewall with a material comprising a metal and oxygen, and removing the oxygen from the material such that an adhesion layer comprising the metal is on the first sidewall and the second sidewall.

[0073] According to some embodiments, a method of forming a semiconductor arrangement comprises forming a conductive layer in the opening above the adhesion layer.

[0074] According to some embodiments, the metal is tungsten and forming the conductive layer comprises filling the opening with tungsten.

[0075] According to some embodiments, removing the oxygen comprises exposing the material to a plasma.

[0076] According to some embodiments, the plasma is generated from molecular hydrogen in an electric field.

[0077] According to some embodiments, the material comprises a molecule comprising a metal atom and an oxygen atom, and the plasma separates the oxygen atom from the metal atom.

[0078] According to some embodiments, the molecule is tungsten hexacarbonyl.

[0079] According to some embodiments, a method of forming a semiconductor arrangement comprises forming an opening in a dielectric layer to expose a conductive component underneath the dielectric layer, wherein the opening is defined by a first sidewall of the dielectric layer and a second sidewall of the dielectric layer, coating the first sidewall and the second sidewall with an adhesion layer, and forming a conductive layer in the opening above the adhesion layer, wherein at an interface of the conductive component and the conductive layer, a ratio of oxygen to a material of the conductive component is less than 1:2.

[0080] According to some embodiments, coating the first sidewall and the second sidewall comprises coating the first sidewall and the second sidewall with a material comprising a metal and oxygen, and removing the oxygen from the material to form the adhesion layer.

[0081] According to some embodiments, the adhesion layer comprises a metal and forming the conductive layer comprises filling the opening with the metal.

[0082] According to some embodiments, coating the first sidewall and the second sidewall includes exposing the dielectric layer to a gaseous material at a pressure of at least 12 Torr.

[0083] The foregoing summary of features of several embodiments has been presented for the purposes of illustration so that one skilled in the art can better understand the aspects of the application. It will be appreciated that those skilled in the art will be able to devise other processes and structures that, although perhaps not explicitly described or shown herein, embody the principles of the application and achieve the same results, that are within the spirit and scope of the application. Thus, those skilled in the art will readily recognize variations of the methods and structures disclosed herein, and will be able to devise equivalents to be within the spirit and scope of the application.

[0084] Although the subject matter has been described in language specific to structural features or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing at least some of the claims.

[0085] Various operations of embodiments are provided herein. The order in which some or all of the operations are described should not be construed as a limitation. Any number of the described operations can be combined in any order and / or can be left out. Additional or different operations can also be employed. The illustrations and associated descriptions are provided to aid in understanding the concepts and principles.

[0086] It should be understood that for simplicity and illustrative purposes, the layers, components, elements, etc. depicted in the figures have in some embodiments a particularized configuration such as a particularized size, orientation, etc. in relation to each other, for example, for simplicity and ease of understanding. In addition, there are a variety of techniques for forming the layers, regions, components, elements, etc. referred to herein, such as at least one of etching, planarization, implantation, doping, spin-on, sputtering, growth, or deposition techniques (such as CVD).

[0087] Also, “exemplary” is used herein to mean serving as an example, instance, or illustration, and not necessarily as advantageous. As used in this application, “or” is intended to mean an inclusive “or” rather than an exclusive “or”. In addition, “a” and “an” as used in this application and the appended claims are generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. Also, at least one of A and B and the like should generally be construed to mean A or B or both A and B. Further, to the extent that “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term “comprising”. Additionally, “first”, “second”, etc. unless otherwise specified, are not intended to imply a temporal aspect, a spatial aspect, an ordering, etc. Rather, such terms are merely used as identifiers, names, etc. for features, elements, items, etc. For example, a first element and a second element generally correspond to element A and element B or two different or two identical elements or two identical elements.

[0088] Also, although the application has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based on the foregoing description and accompanying drawings. The application includes all such modifications and alterations and is limited only by the scope of the following claims. In particular, with respect to the various functions performed by the above described components (e.g., elements, resources, etc.), the terms used to describe certain of these components are intended to correspond, unless otherwise indicated or unless it is clear from the context, to any component which performs the described functionality (e.g., that is functionally equivalent), regardless of physical structure, even though not structurally equivalent to the structure shown. Also, techniques, systems, subsystems, and methods described and illustrated in the various embodiments as discrete or separate can be combined or integrated with other systems, components, techniques, or methods without departing from the scope of the present disclosure. Other examples of changes, substitutions, and alterations are ascertainable by one skilled in the art and can be made without departing from the spirit and scope of the application.

Claims

1. A semiconductor arrangement comprising: a conductive component; a dielectric layer defining an opening; an adhesive layer in the opening and in direct contact with the conductive component; a conductive layer in the opening above the adhesive layer and covering the conductive component, wherein a material of the conductive layer is a same material as an adhesive material of the adhesive layer; wherein a ratio of oxygen to a material of the conductive component at an interface of the conductive component and the conductive layer is less than 1:

2.

2. The semiconductor arrangement of claim 1, wherein, a bottom surface of the adhesive layer is coplanar with a top surface of the conductive component.

3. The semiconductor arrangement of claim 2, further comprising a second dielectric layer below the conductive component.

4. The semiconductor arrangement of claim 1, wherein, the conductive component is exposed through the opening.

5. The semiconductor arrangement of claim 4, wherein, the adhesive layer is in direct contact with the conductive component.

6. The semiconductor arrangement of claim 1, wherein, the opening is defined by a first sidewall of the dielectric layer and a second sidewall of the dielectric layer.

7. The semiconductor arrangement of claim 6, wherein, the adhesive layer is in direct contact with at least one of the first sidewall or the second sidewall.

8. The semiconductor arrangement of claim 1, wherein, the adhesive layer comprises tungsten and the conductive layer comprises tungsten.

9. The semiconductor arrangement of claim 1, wherein, the conductive layer occupies between 55% and 75% of a volume of the opening.

10. A method of forming a semiconductor arrangement comprising: forming an opening in a dielectric layer, wherein the opening is defined by a first sidewall of the dielectric layer and a second sidewall of the dielectric layer; coating the first sidewall and the second sidewall with a material comprising a metal and oxygen; and removing oxygen from the material such that an adhesive layer comprising the metal is on the first sidewall and the second sidewall, wherein removing oxygen from the material produces a first adhesive coating, the method comprising: coating the first adhesive coating with a second instance of the material; and removing oxygen from the second instance of the material to produce a second adhesive coating, and the first adhesive coating and the second adhesive coating are part of the adhesive layer.

11. The method of claim 10, comprising forming a conductive layer in the opening above the adhesive layer.

12. The method of claim 11, wherein, the metal is tungsten and forming the conductive layer comprises filling the opening with tungsten.

13. The method of claim 10, wherein, removing the oxygen comprises exposing the material to a plasma.

14. The method of claim 13, wherein, the plasma is generated from molecular hydrogen in an electric field.

15. The method of claim 13, wherein, the material comprises molecules comprising metal atoms and oxygen atoms and the plasma separates the metal atoms from the oxygen atoms.

16. The method of claim 15, wherein, the molecules are tungsten hexacarbonyl.

17. A method of forming a semiconductor arrangement comprising: forming an opening in a dielectric layer to expose a conductive component below the dielectric layer, wherein the opening is defined by a first sidewall of the dielectric layer and a second sidewall of the dielectric layer; coating the first sidewall and the second sidewall with an adhesive layer; and forming a conductive layer in the opening above the adhesive layer, wherein a ratio of oxygen to a material of the conductive component at an interface of the conductive component and the conductive layer is less than 1:

2.

18. The method of claim 17, wherein, coating the first sidewall and the second sidewall comprises coating the first sidewall and the second sidewall with a material comprising a metal and oxygen, and removing the oxygen from the material to form the adhesive layer.

19. The method of claim 17, wherein, the adhesive layer comprises a metal and forming the conductive layer comprises filling the opening with the metal.

20. The method of claim 17, wherein, Coating the first sidewall and the second sidewall includes exposing the dielectric layer to the material in a gaseous state at a pressure of at least 12 Torr.

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