A brain-computer interface front-end device and brain electrode system

Abstract

The present invention relates to the technical field of brain-computer interface, and the present invention discloses a front-end device of brain-computer interface and a brain electrode system. The front-end device of the brain-computer interface includes a control chip, a stimulation module and a test module, wherein the stimulation module is used to generate a stimulation signal, and the stimulation signal is used to stimulate the cerebral cortex through the brain electrode structure, and the control chip is used to control the on-off of the channel of the brain electrode structure, as well as the switching input of the test signal and the stimulation signal; the test module is used to receive the test result signal sent by the control chip, and perform digital-to-analog conversion processing on the test result signal; the test result signal is a signal generated by the control chip based on the test signal. After the device is connected to the brain electrode structure, the stimulation and collection of brain electrodes can be realized based on the device, and the test of the control chip can be realized based on the above-mentioned test module.

Description

Technical Field

[0001] The present invention relates to the technical field of brain-computer interface, and in particular to a brain-computer interface front-end device and a brain electrode system. Background Art

[0002] Brain-computer interface is a multidisciplinary cross-technology involving neuroscience, signal detection and signal processing, and has important research significance and huge application potential in the fields of biomedicine, neurorehabilitation and intelligent robotics. It establishes a direct communication and control channel between the human brain and a computer or other electronic device, collects EEG signals from the cerebral cortex, and converts them into signals that can be recognized by the computer through amplification, filtering, A / D conversion, etc., then pre-processes the signals, extracts characteristic signals, and then uses these characteristics for pattern recognition, and finally converts them into specific instructions to control external devices, thereby achieving control of external devices.

[0003] Electrophysiological signals in the brain are distributed over a wide range of spatial and temporal scales. Simultaneously recording the spiking activities of many single neurons in brain circuits with high spatial and temporal resolution is essential to study how complex nervous systems process information from microscopic to mesoscopic spatial scales, decipher how brain circuits operate and possible dysfunctions that may arise in diseases.

[0004] However, the high-throughput electrodes in the existing technology have a single function and cannot realize signal acquisition under multiple states, which limits the development of brain-computer interface technology. Summary of the invention

[0005] The present invention aims to solve the technical problem of single function of the brain-computer interface front-end device in the prior art.

[0006] In order to solve the above technical problems, the present application discloses, on one hand, a brain-computer interface front-end device, which includes a control chip, a stimulation module and a test module;

[0007] The stimulation module and the test module are respectively connected to the control chip;

[0008] The pad area of ​​the control chip is connected correspondingly to the pad structure of the brain electrode structure;

[0009] The stimulation module is used to generate a stimulation signal, and the stimulation signal is used to stimulate the cerebral cortex through the brain electrode structure;

[0010] The control chip is used to control the on-off of the channel of the brain electrode structure, as well as the switching input of the test signal and the stimulation signal;

[0011] The test module is used to receive the test result signal sent by the control chip and perform digital-to-analog conversion on the test result signal; the test result signal is a signal generated by the control chip based on the test signal.

[0012] Optionally, it also includes a digital-to-analog conversion module and a power supply module;

[0013] The digital-to-analog conversion module is connected to the control chip;

[0014] The power module is connected to the control chip and the digital-to-analog conversion module;

[0015] The power supply module is used to supply power to the control chip and the digital-to-analog conversion module;

[0016] The power module includes a lithium battery, a first low voltage drop linear regulator and a second low voltage drop linear regulator;

[0017] The lithium battery is connected to the control chip via the first low voltage drop linear regulator;

[0018] The lithium battery is connected to the digital-to-analog conversion module via the second low voltage drop linear regulator;

[0019] The digital-to-analog conversion module is used to receive the EEG signal sent by the control chip and perform digital-to-analog conversion on the EEG signal.

[0020] Optionally, the voltage of the lithium battery includes 3.7 volts;

[0021] The voltage range output by the first low voltage drop linear regulator includes 0.5 to 3.3 volts;

[0022] The voltage output by the second low voltage drop linear regulator includes 1 to 1.8 volts.

[0023] Optionally, the channels of the control chip include 128×128 channels;

[0024] The pad structure includes 128×128 solder joints;

[0025] The pad area includes 128×128 solder joints;

[0026] The solder joints of the pad structure are connected to the solder joints of the pad area in a one-to-one correspondence through flip-chip bonding.

[0027] Optionally, a Field Programmable Gate Array (FPGA) chip is also included;

[0028] The field programmable gate array chip is connected to the control chip, the digital-to-analog conversion module, the test module and the stimulation module;

[0029] The field programmable gate array chip is used to supply power to the test module and the stimulation module, and to send the received EEG signal sent by the digital-to-analog converter to a signal acquisition device;

[0030] The voltage of the field programmable gate array chip includes 5 volts.

[0031] Optionally, the stimulation module outputs a stimulation voltage in the range of 0-3.3 volts;

[0032] The error range between the stimulation voltage value output by the stimulation module and the preset voltage value is 0-0.4 millivolts.

[0033] Optionally, the brain electrode structure includes a contact electrode structure connected to the pad structure;

[0034] The contact electrode structure collects brain electrical signals by contacting the scalp layer.

[0035] Optionally, the contact electrode structure includes N contact electrodes; N is an integer greater than or equal to 1;

[0036] The pad structure includes N solder joints;

[0037] The control chip includes a connected processor and N pixel circuits; the pixel circuits are connected to the N welding points in a one-to-one correspondence;

[0038] The processor is used to control the opening or closing of any one of the N contact electrodes by controlling the conduction or disconnection of any one of the N pixel circuits; and when any one of the pixel circuits is turned on, the processor controls any one of the pixel circuits to output a corresponding stimulation signal or a test signal through the received stimulation signal or the test signal, thereby realizing the stimulation of the target cerebral cortex of the brain by any one of the contact electrodes or the control of the test of the corresponding pixel circuit.

[0039] Optionally, the contact electrode structure includes M sub-contact electrode structures, where M is an integer greater than or equal to 1;

[0040] There is a preset interval between adjacent sub-contact electrode structures in the M sub-contact electrode structures;

[0041] The M sub-contact electrode structures are located on the same plane.

[0042] On the other hand, the present application discloses a brain electrode system, which includes the brain electrode structure and the above-mentioned brain-computer interface front-end device.

[0043] The brain-computer interface front-end device provided by the present application has the following beneficial effects: the brain-computer interface front-end device includes a control chip, a stimulation module and a test module, wherein the stimulation module is used to generate a stimulation signal, the stimulation signal is used to stimulate the cerebral cortex through the brain electrode structure, the control chip is used to control the on-off of the channel of the brain electrode structure, and the switching input of the test signal and the stimulation signal; the test module is used to receive the test result signal sent by the control chip, and perform digital-to-analog conversion processing on the test result signal; the test result signal is a signal generated by the control chip based on the test signal. After the device is connected to the brain electrode structure, the stimulation and collection of the brain electrodes can be realized based on the device, and the test module can be used to test the control chip. The above device has various functions and fills the gap in this field. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 A schematic diagram of the structure of an optional brain-computer interface front-end device for this application;

[0046] Figure 2 This is a schematic diagram of the structure of another optional brain-computer interface front-end device for this application;

[0047] Figure 3 This is a schematic diagram of the structure of an optional pixel circuit of the present application;

[0048] Figure 4 This is a schematic diagram of the structure of another optional pixel circuit of the present application;

[0049] Figure 5 This is a schematic diagram of the structure of an optional parallel pixel circuit of the present application;

[0050] Figure 6 This is a schematic diagram of the arrangement of the first optional contact electrodes of the present application;

[0051] Figure 7 This is the potential distribution model diagram of the contact electrode structure at time t1;

[0052] Figure 8 This is the potential distribution model diagram of the contact electrode structure at time t2;

[0053] Fig. 9 An optional equivalent circuit diagram of the present application when the contact electrode is inserted into the brain tissue in the working state;

[0054] Fig.10 This is a schematic diagram of the arrangement of the second optional contact electrodes of the present application;

[0055] Fig.11 This is a schematic diagram of the arrangement of the third optional contact electrodes of the present application;

[0056] Fig.12 The present invention is a flowchart of an optional control method of a brain electrode system.

[0057] The following is a supplementary description of the attached drawings:

[0058] 1-control chip; 2-brain electrode structure; 21-contact electrode structure; 211-first contact electrode; 212-second contact electrode; 22-pad structure; 3-stimulation module; 4-test module; 5-digital-to-analog conversion module; 6-power supply module; 7-field programmable gate array chip. DETAILED DESCRIPTION

[0059] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0060] The term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present application. In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "top", "bottom", etc. is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may include one or more of the features explicitly or implicitly. Moreover, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here.

[0061] Generally, a device for collecting EEG signals generally only has the function of collecting EEG signals, which makes the function single and cannot meet the needs of the increasingly developed brain-computer interface exploration. Based on this, the present application provides a brain-computer interface front-end device, see Figure 1 , Figure 1 This is a schematic structural diagram of an optional brain-computer interface front-end device of the present application, the brain-computer interface front-end device includes a control chip 1, a stimulation module 3 and a test module 4, the stimulation module 3 and the test module 4 are respectively connected to the control chip 1, the pad area of ​​the control chip 1 is correspondingly connected to the pad structure 22 of the brain electrode structure 2, the stimulation module 3 is used to generate a stimulation signal, and the stimulation signal is used to stimulate the cerebral cortex through the brain electrode structure 2; the control chip 1 is used to control the on-off of the channel of the brain electrode structure 2, and the switching input of the test signal and the stimulation signal; the test module 4 is used to receive the test result signal sent by the control chip 1, and perform digital-to-analog conversion on the test result signal; the test result signal is a signal generated by the control chip 1 based on the test signal.

[0062] Therefore, the brain-computer interface front-end device provided by the present application can not only realize the acquisition and stimulation of the cerebral cortex, but also can realize the test of the pixel circuit in the control chip 1 based on the cooperation of the control chip 1 and the test module 4. For example, it can be a test of the short circuit and open circuit of the pixel circuit below.

[0063] In order to better transmit information without distortion and compress data, it is necessary to perform analog-to-digital conversion on the analog signal directly collected by the electrode. Figure 2 , Figure 2This is a structural schematic diagram of another optional brain-computer interface front-end device of the present application. The brain-computer interface front-end device also includes a digital-to-analog conversion module 5 and a power module 6; the digital-to-analog conversion module 5 is connected to the control chip 1; the power module 6 is connected to the control chip 1 and the digital-to-analog conversion module 5; the power module 6 is used to supply power to the control chip 1 and the digital-to-analog conversion module 5; the power module 6 includes a lithium battery, a first low-voltage difference linear regulator and a second low-voltage difference linear regulator; the lithium battery is connected to the control chip 1 through the first low-voltage difference linear regulator; the lithium battery is connected to the digital-to-analog conversion module 5 through the second low-voltage difference linear regulator; the digital-to-analog conversion module 5 is used to receive the EEG signal sent by the control chip 1 and perform digital-to-analog conversion processing on the EEG signal. The use of lithium batteries can ensure the accuracy of electrical signals and has low noise, and can power some sensitive power supplies, such as some devices (corresponding pins) in the above-mentioned control chip 1 and some devices (corresponding pins) in the digital-to-analog conversion module 5. In addition, since the actual EEG signal is very weak, often only tens of μV to a few mV, it is seriously affected by noise, and therefore has very high requirements on noise. This application uses a low-voltage differential signal to transmit the signal, and adopts a low-voltage and low-current driving method to achieve low power consumption, low bit error rate, low crosstalk, low radiation, and low noise.

[0064] Generally, for low-density electrodes, the area and power restrictions can be relaxed, signal amplification and analog-to-digital conversion can be performed on-chip, and the generated digital data flows to the acquisition board through a serial peripheral interface. However, when high-density EEG devices are used, in order to prevent brain tissue damage during the recording process, the area and power of the implant in the brain are greatly limited. Therefore, for high-throughput electrodes, a series of processing such as the amplification of neural signals cannot be integrated on the electrode board like existing low-throughput active devices. An additional PCB board is required to integrate the neural signal amplification chip on the board, and then cooperate with ADC circuits for off-chip conversion. However, the chip integrated on the current external circuit board can only achieve a flux of 32 sites, which is relatively low.

[0065] The control chip in the present application may be MOKOTO. The brain-computer interface front-end device provided in the present application will be described in detail below using MOKOTO as an example of the control chip.

[0066] MOKOTO can include 128×128 pixel circuits, and the control chip 11 includes four signal control lines, each of which controls a sub-control line on the north and south sides, and each sub-control line has 128 pixel circuits in parallel, so only 4 signal inputs can achieve a maximum of 4×2×128=1024 stimulation channels. In other words, based on the chip structure in which pixel circuits are respectively arranged on the north and south sides, in order to improve the data conversion efficiency, the digital-to-analog conversion module 5 can include two sub-modules, and one sub-module can be arranged near the north and south sides of the control chip 1.

[0067] Correspondingly, the pad structure 22 includes 128×128 solder joints; the pad area includes 128×128 solder joints, that is, when the control chip 1 is a MOKOTO chip, the brain electrode structure 1 is a device with 2640 channels, and the pad structure 22 of the brain electrode structure 1 is a 30×88 solder joint array; the distance between adjacent solder joints is 200 microns, and the distance between adjacent pixel circuit units in the MOKOTO chip is 100 microns, so when the two can be flip-chip soldered, the integration can be improved and the signal quality can be guaranteed; since the distance between adjacent solder joints of the brain electrode structure 1 is twice the distance between adjacent pixel units, the adjacent solder joints can be connected to the spaced pixel units, so that the number of solder joints that can be connected to the pixel units of MOKOTO is 30×64, and since the MOKOTO chip has only 8 rows of arrays with corresponding signal lines, only 30×8=240 channels can be used for the stimulation part. However, by adjusting the distance between the solder joints, the corresponding number of channels can also be changed, and the above is only an example of an optional embodiment.

[0068] It should be noted that the number of channels of the above-mentioned control chip can be L times 64 channels, where L can be an integer greater than or equal to 2, for example, 64 channels, 128 channels, 256 channels, etc. This embodiment is mainly explained with the number of channels of the control chip 1 being 128×128.

[0069] Optionally, the acquisition rate of each channel of the control chip 1 is greater than or equal to 40 frames per second. Through multiplexing within the chip, there are 16 outputs on each of the north and south sides. Therefore, the sampling rate of each output channel is required to be no less than 128×64×40 / 16=20.48Msample / s. Furthermore, in order to make the quantization noise much lower than the thermal noise floor, a digital-to-analog conversion module 5 with a resolution of at least 12 bits is required. Therefore, the data transmission rate of the entire chip must be no less than 12bit×20.48M×16×2=7.86G bits / second.

[0070] In an optional embodiment, see Figure 2The brain-computer interface front-end device also includes a field programmable gate array (FPGA) chip; the field programmable gate array chip 7 is connected to the control chip 1, the digital-to-analog conversion module 5, the test module 4 and the stimulation module 3; the field programmable gate array chip 7 is used to power the test module 4 and the stimulation module 3, and send the received electroencephalogram signal sent by the digital-to-analog converter to the signal acquisition device.

[0071] Optionally, the voltage of the field programmable gate array chip 7 includes 5 volts. The field programmable gate array chip 7 can provide power for devices that do not require high accuracy of power supply signals, and can output different voltages by connecting it to different low voltage difference linear regulators.

[0072] Optionally, the field programmable gate array chip 7 can power the following modules of the digital-to-analog conversion module 5, the stimulation module 3 and the control chip 1, wherein the pins of the digital-to-analog conversion module 5 include DVDD_TI_ADC (1.2V), TI_ADC (1.8V), MISC (3.3V), the pins of the stimulation module 3 include VREF (3.5V), and the pins of the control chip 1 include VDDIO (3.3V) and VDDD (3.3V); it should be noted that VDDIO and VDDD are pins for powering the control chip 1, and VREF is used to power the chip in the stimulation module 3 that needs to generate a 3.3V reference voltage. Since the output level range of the control chip 1 is about 0-3.3V, and the input signal of the digital-to-analog conversion module 5 is required to be about 0-1.8V, a level conversion is required. Therefore, the MISC is used to power the level conversion module located in the digital-to-analog conversion module 5.

[0073] In an optional embodiment, the voltage of the lithium battery includes 3.7 volts; the voltage range output by the first low-voltage difference linear regulator includes 0.5 to 3.3 volts; and the voltage output by the second low-voltage difference linear regulator includes 1 to 1.8 volts.

[0074] Optionally, the test result signal output by the control chip 1 may be input via MBS_N MBS_S of the test module 4 .

[0075] In order to realize high-precision stimulation signals, in an optional embodiment, the stimulation module 3 can be a chip with a resolution of 12 bits and a DNL of only 0.5LSB. The stimulation voltage output by the stimulation module 3 is in the range of 0-3.3 volts, and the error range between the stimulation voltage value output by the stimulation module 3 and the preset voltage value is 0-0.4 millivolts. With extremely high precision, in addition to generating high-precision voltage stimulation, a grounding switch is also required, which is turned on and grounded after each stimulation cycle to promptly release the unbalanced charge accumulated due to impedance changes, power supply mismatch, etc., so that long-term cyclic stimulation can be performed, so that the electrode voltage is kept within the safety threshold, avoiding irreversible damage to the tissue due to charge accumulation.

[0076] It can be seen from the above examples that the design of the brain-computer interface front-end device provided by this application can provide a good solution for the acquisition and processing of high-throughput EEG signals, integrating the signal amplification, filtering, analog-to-digital conversion, and stimulation on an external PCB to realize the processing and conversion of high-throughput EEG signals; and integrating the signal amplification, filtering chip, analog-to-digital conversion, and stimulation module 3 in the same neural recording front end, separated from the probe, to relieve the pressure of implant noise, power and area, and to minimize the damage to the living detection object; at the same time, up to 1024 channels can be stimulated simultaneously, with a resolution of up to 12Bit, and the switch controls the ground short circuit to release the accumulated charge in the stimulation gap to achieve stimulation charge balance. By combining the above device with the brain electrode structure 2, the changes in neuronal electrical activity and neural molecules in physiological and pathological processes can be accurately recorded, based on which how the brain circuit works and the possible functional disorders in the disease can be deciphered, and the stimulation function is assisted, and the stimulation parameters are adjusted according to the feedback of the detected results, so as to cooperate with the early disputes and neuroregulatory treatment of brain diseases such as Parkinson's and epilepsy.

[0077] In an optional embodiment, the brain electrode structure 2 includes a contact electrode structure 21 connected to the pad structure 22; the contact electrode structure 21 collects brain electrical signals by contacting the scalp layer.

[0078] In an optional embodiment, the contact electrode structure 21 includes N contact electrodes; N is an integer greater than or equal to 1; the pad structure 22 includes N solder joints; the control chip 1 includes a connected processor and N pixel circuits; the pixel circuits are connected one-to-one with the N solder joints; the processor is used to control the on or off of any one of the N contact electrodes by controlling the on or off of any one of the N pixel circuits; and when any one of the pixel circuits is turned on, the processor controls any one of the pixel circuits to output a corresponding stimulation signal or test signal through the received stimulation signal or test signal, thereby achieving stimulation of the target cerebral cortex of the brain by any one of the contact electrodes or control of the corresponding pixel circuit test.

[0079] In an optional embodiment, the contact electrode structure includes M sub-contact electrode structures, where M is an integer greater than or equal to 1; there is a preset interval between adjacent sub-contact electrode structures in the M sub-contact electrode structures; and the M sub-contact electrode structures are located in the same plane. The N contact electrodes can be evenly distributed on the M sub-contact electrode structures, or unevenly distributed as needed, which is not limited here.

[0080] It should be noted that in order to isolate and protect adjacent sub-control lines, a separation circuit is provided between adjacent sub-control lines. The above-mentioned N pixel circuits are not necessarily all the solder joints of the control chip, but only correspond to the N contact electrodes. In fact, the control chip may include M pixel circuits, where M is an integer greater than N.

[0081] In a possible embodiment, see Figure 3 , Figure 3 This is a schematic diagram of the structure of an optional pixel circuit of the present application. Each pixel circuit includes a first capacitor C1, a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4, the first end of the first capacitor C1 is connected to the signal input line V0, the second end of the first capacitor C1 is connected to the first end of the second switch S2, the first end of the first switch S1 is connected to the second end of the first capacitor C1, the second end of the first switch S1 is connected to the signal input line V0, the signal input line V0 is connected to the processor, the second end of the second switch S2 is connected to the first end of the third switch S3, and the third end of the second switch S2 is connected to the horizontal control signal line S X[n] Connect the lateral control signal line S X[n] The second end of the third switch S3 is connected to the first end of the fourth switch S4, and the third end of the third switch S3 is connected to the longitudinal control signal line S Y[m] Connect the vertical control signal line S Y[m]The processor inputs a stimulation signal or a test signal to the pixel circuit through the signal input line V0; the processor controls the pixel circuit through the horizontal control signal line S X[n] Control the opening or closing of the second switch S2; the processor controls the vertical signal line S Y[m] Control the opening or closing of the third switch S3.

[0082] Optionally, the two selection signal lines, namely the horizontal control signal line S X[n] and the longitudinal control signal line S Y[m] The register in the processor controls the pixel circuit that needs to be operated, so that the pixel circuit that needs to be operated can be selected from the 128×128 pixel circuits, that is, the horizontal control signal line S X[n] and the longitudinal control signal line S Y[m] You can select the number of stimulation channels you want to achieve and select adjustable stimulation channels. Figure 3 S X[n] Indicates the nth row of horizontal control signal lines; S Y[m] Indicates the m-th column vertical control signal line.

[0083] Optionally, the opening or closing of the first switch S1 and the fourth switch S4 can be controlled based on the user's operation. Since the opening and closing of the first switch S1 and the fourth switch S4 will form different control signals, when the first switch S1 and the fourth switch S4 are closed, "0" will be output, so that the processor controls the voltage signal input to the signal input line V0 from the outside to flow to the output port as a stimulation signal, and then reaches the contact electrode; on the contrary, if the first switch S1 and the fourth switch S4 are closed, "1" will be output, so that the processor controls the voltage signal input to the signal input line V0 from the outside to flow to the amplification circuit as a test signal, and finally outputs the signal through other I / O ports of the chip to an externally connected signal analysis device for observation.

[0084] It should be noted that the test signal mentioned above and below means that when the control chip receives the test signal, it will test the target pixel circuit to determine whether the pixel circuit can operate normally, which can be determined according to different test result signals output by the control chip; in most cases, the control chip mainly collects EEG signals from the target brain. The collected EEG signals can be output by controlling the closing of the fourth switch S4.

[0085] Of course, it is also possible to directly control the first switch S1 and the fourth switch S4 based on an external trigger signal, so that the processor controls the opening or closing of the first switch S1 and the fourth switch S4 based on the trigger signal, thereby realizing the control of the two switches.

[0086] Similarly, other switches in the pixel circuit, such as the second switch S2, the third switch S3 and the fifth switch S5 described below, can be controlled by the above two methods, which are not limited here.

[0087] In a possible embodiment, see Figure 4 , Figure 4 This is a schematic diagram of the structure of an optional pixel circuit of the present application. To achieve more stimulation types and meet the analysis of neural signals under diversified stimulation. Each pixel circuit also includes a second capacitor C2 and a fifth switch S5; the first end of the second capacitor C2 is connected to the first end of the fourth switch S4, and the second end of the second capacitor C2 is connected to the corresponding solder joint; the first end of the fifth switch S5 is connected to the first end of the capacitor, and the second end of the fifth switch S5 is connected to the second end of the capacitor; the processor controls the pixel circuit to output DC or AC by controlling the opening or closing of the fifth switch S5. In other words, the second capacitor C2 can be controlled to be short-circuited by controlling the opening or closing of the fifth switch S5. It can be set that when the fifth switch S5 is disconnected, the output is "0", and the signal input line V0 will input AC, otherwise, when the fifth switch S5 is closed, the second capacitor C2 is short-circuited, and the output is "1", then the signal input line V0 will input DC.

[0088] Optional, see Figure 5 , Figure 5 This is a schematic diagram of the structure of an optional parallel pixel circuit of the present application. Figure 5 The two parallel pixel circuits shown belong to the same row, so they can be controlled by the same horizontal control signal line S X[n] The vertical control signal line of the first pixel circuit is S Y[m] , the vertical control signal line of the second pixel circuit is S Y[m+1] When multiple pixel units are connected in parallel, the same applies, including multiple vertical control signal lines S Y[m] Controlled pixel unit.

[0089] In a feasible embodiment, the contact electrode structure 21 also includes a flexible substrate and an insulating layer, N contact electrodes are arranged on the flexible substrate, the insulating layer is arranged on the N contact electrodes, and the insulating layer includes N electrode holes, and the N electrode holes correspond one-to-one to the N contact electrodes.

[0090] It should be noted that when different pixel circuits correspond to contact electrodes with different arrangements, since the contact electrodes may be located in different areas of the brain tissue and at different distances from the brain tissue, adjusting the correspondence between the contact electrodes and the pixel circuits will affect the area of ​​the stimulated tissue, the number of stimulation channels, the form of stimulation, and the intensity of stimulation, etc.; for example, when the contact electrode is far away from the corresponding site of the brain tissue, in order to achieve the required stimulation energy, it is necessary to increase the intensity of the stimulation voltage / current, and conversely, it is necessary to reduce the intensity of the stimulation voltage / current.

[0091] In order to achieve charge balance, reduce the complexity of external integrated circuits, and reduce the circuit area. Figure 6 , Figure 6 This is a schematic diagram of the arrangement of the first optional contact electrode of the present application. The top of the flexible substrate includes a first side and a second side relative to each other, the M first contact electrodes 211 are located on the first side, the M second contact electrodes 212 are located on the second side, and there is a second preset distance between adjacent first contact electrodes 211; the second preset distance is greater than or equal to the first preset distance, and there is the second preset distance between adjacent second contact electrodes 212. The first contact electrode 211 will subsequently input a first stimulation signal, and the second contact electrode 212 will input a second stimulation signal, and the first stimulation signal is a signal with the same amplitude, phase and shape as the second stimulation signal, so as to achieve charge balance in the corresponding brain tissue area.

[0092] It should be noted that the above-mentioned first stimulation signal and second stimulation signal are not instantaneous signals, but signals with equal amplitude, phase and shape formed in a relatively short period of time; the signals formed at time t1 and time t2 below are also signals with equal amplitude, phase and shape.

[0093] The following will be based on Figure 6 The principle of achieving charge balance with the contact electrode structure 21 is described below:

[0094] Figure 6 The contact electrode structure 21 includes 24 pairs of contact electrodes, each of which includes a first contact electrode 211 located on the first side and a second contact electrode 212 located on the second side; it should be understood that when the contact electrode receives a stimulation signal, the brain tissue it contacts will be injected with electric charge, so the surrounding electric potential will also change. Assuming that at time t0, there is no voltage signal input to the first signal input line V1 connected to the first contact electrode 211 and the second signal input line V2 connected to the second contact electrode 212, then the electric potential of the tissue connected to the contact electrode is equal everywhere and is in a relatively balanced state. Figure 7 , Figure 7is a potential distribution model diagram of the contact electrode structure at time t1. When at time t1, the first signal input line V1 inputs a signal with an amplitude of "1", and the second signal input line V2 inputs a signal with an amplitude of "0", the first contact electrode 211 on the first side forms a high potential due to the injection of charge, and the second contact electrode 212 on the second side forms a relatively low potential, and a potential difference is formed between the adjacent first contact electrode 211 and the second contact electrode 212, so there is I sti From the first contact electrode 211 to the second contact electrode 212, Figure 7 See Figure 8 , Figure 8 t2 is a potential distribution model diagram of the contact electrode structure. At time t2, the first signal input line V1 inputs a signal with an amplitude of "0", and the second signal input line V2 inputs a signal with an amplitude of "1". The first contact electrode 211 on the first side is at a low potential, and the second contact electrode 212 on the second side is at a high potential. sti From the second contact electrode 212 to the first contact electrode 211. Since the actual distance between the paired first contact electrodes 211 and the second contact electrodes 212 is very close, the current formed by the potential difference can be considered to flow only between the two electrodes and hardly diffuse outward. The equivalent schematic diagram of the loop formed by the first contact electrode 211-tissue-tissue-second contact electrode 212 is as follows: Fig. 9 As shown, Fig. 9 This is an optional equivalent circuit diagram of the present application when the contact electrode is inserted into the brain tissue. In a very short time, it can be considered that I with equal magnitude and opposite direction is generated at time t1 and time t2. sti Therefore, after time t2, the charges injected into the brain tissue due to stimulation are offset by each other, achieving charge balance. The present application not only solves the charge balance problem by alternately inputting stimulation through two signal lines, avoiding brain tissue damage and electrode electrolysis, but also improves integration and simplifies the external circuit.

[0095] It should be noted that Fig. 9 Re is the contact electrode resistance, R and Ci are the equivalent resistance and capacitance in the brain tissue, and Rs is the resistance between the two contact electrode paths.

[0096] In a possible embodiment, see Fig.10 , Fig.10This is a schematic diagram of the arrangement of the second optional contact electrodes of the present application. The N contact electrodes form a contact electrode set, which includes a first contact electrode set and a second contact electrode set, the first contact electrode set is located on the first side, the second contact electrode set is located on the second side, the first contact electrodes 211 and the second contact electrodes 212 in the first contact electrode set are staggered along the length direction of the flexible substrate, the sum of the number of the first contact electrodes 211 and the number of the second contact electrodes 212 in the first contact electrode set is equal to M, the first contact electrodes 211 and the second contact electrodes 212 in the second contact electrode set are staggered along the length direction of the flexible substrate, the sum of the number of the first contact electrodes 211 and the number of the second contact electrodes 212 in the second contact electrode 212 is equal to M, wherein the arrangement of the contact electrodes in the first contact electrode set is the same as the arrangement of the contact electrodes in the second contact electrode 212.

[0097] In another possible embodiment, see Fig.11 , Fig.11 This is a schematic diagram of a third optional arrangement of contact electrodes in the present application. The arrangement of the contact electrodes in the first contact electrode set is opposite to the arrangement of the contact electrodes in the second contact electrode 212 .

[0098] It should be noted that the above-mentioned brain electrode module can select the voltage control mode when stimulating brain tissue, and can achieve charge-balanced electrical stimulation by generating a balanced bidirectional voltage pulse in the external circuit and inputting it into the signal input line V0. This method can achieve a total of 1024-channel stimulation with 4 different stimulation waveforms.

[0099] In a feasible embodiment, the signal input line V0 includes three sub-signal input lines V0, and the phase difference between adjacent sub-signal input lines V0 arranged along a preset direction is 120 degrees. That is to say, when the electrode position controlled by the three signal lines just forms an angle of 120°, and the three external signal input ports give an initial stimulation with a phase difference of 120°, it is possible to form autonomous power generation, that is, there is no need to supply the stimulation signal from an external voltage generator, but to use the phase difference to make the signal continue. Similarly, using four signal lines to form a phase difference of 90° can also form a four-phase generator, which is an excellent development point in future wireless, sustainable, and energy-saving designs.

[0100] In summary, in the brain electrode module provided by this application, since the control chip 1 includes multiple pixel circuits, corresponding to the multiple contact electrodes of the brain electrode structure 1, it is possible to control the opening of different stimulation channels, realize the stimulation of adjustable sites, and configurable bipolar voltage stimulation to achieve charge balance, reduce the complexity of external integrated circuits, and reduce the circuit area; and the optional DC / AC stimulation can adapt to specific experimental scenarios. This application not only realizes high-channel stimulation, further fills the gap in high-channel stimulation on the market, but also can adapt to changes in different needs in the biomedical field, has higher flexibility, reduces R&D costs, and shortens the experimental cycle.

[0101] The present application also discloses a brain electrode system, which includes the brain electrode structure 2 and the above-mentioned brain-computer interface front-end device. For details, please refer to the above description.

[0102] Considering the crosstalk between 10,000-channel signals and the high requirements for noise quality, the contact electrodes of the brain electrode structure 2 provided by the present application will not integrate active circuits, but will only be responsible for the collection and transmission of EEG signals. A control chip 1 is required to amplify and filter the collected 10,000-channel signals. The processed signals are multiplexed at the north and south ends of the EEG signal processing chip and output through 16 I / O ports respectively. The circuits on the PCB board are then converted through a series of SPI and transmitted to the field programmable gate array chip 7 for data integration control. Finally, the field programmable gate array chip 7 transmits the signals to the client through a 10,000-gigabit cable for visualization processing. Based on the above-mentioned brain electrode system, the functions of collection, stimulation, and testing can be realized, and high-throughput signal transmission can be achieved.

[0103] See also Fig.12 , Fig.12 This is a flow chart of an optional control method of a brain electrode system of the present application. In another aspect, the present application also discloses a control method of a brain electrode system, which is applied to the above-mentioned brain electrode module, and the control method comprises the following steps:

[0104] S1101: Acquire a site control signal.

[0105] S1102: Controlling the pixel circuit at the corresponding site to be turned on based on the site control signal.

[0106] As described above, the horizontal control signal line S can be controlled by controlling the number of rows. X[n] The number of vertical control signal lines S Y[m] , thereby controlling the opening and closing of the corresponding second switch S2 and the third switch S3 to achieve the conduction of the corresponding pixel circuit as a whole.

[0107] S1103: Receive a function control signal.

[0108] Optionally, the functional control signal may include two types, one is a control signal for controlling the pixel circuit to output a stimulation / test signal; the other is a control signal for controlling the pixel circuit to output a direct current / alternating current.

[0109] S1104: Based on the functional control signal, the pixel circuit is controlled to output a stimulation signal or a test signal to achieve stimulation of the target brain by the contact electrode or control of the corresponding pixel circuit.

[0110] Referring to the above description, the input stimulation signal or test signal can be realized by the signals generated by the opening and closing of the first switch S1 and the fourth switch S4. When it is a stimulation signal, it is input into the brain tissue through the output port, and when it is a test signal, it is input into the amplifier circuit.

[0111] It is also possible to determine whether the stimulation signal input into the pixel circuit is AC or DC by controlling the fifth switch S5 to be turned on or off. The specific implementation method is described above and will not be repeated here.

[0112] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A brain electrode system, comprising a brain electrode structure (2) and a brain-computer interface front-end device, characterized in that: The brain-computer interface front-end device comprises a control chip (1), a stimulation module (3) and a test module (4); The stimulation module (3) and the testing module (4) are respectively connected to the control chip (1); The pad area of ​​the control chip (1) is connected correspondingly to the pad structure (22) of the brain electrode structure (2); The stimulation module (3) is used to generate a stimulation signal, and the stimulation signal is used to stimulate the cerebral cortex through the brain electrode structure (2); The control chip (1) is used to control the on / off of the channels of the brain electrode structure (2), as well as the switching input of the test signal and the stimulation signal; The test module (4) is used to receive the test result signal sent by the control chip (1) and perform digital-to-analog conversion processing on the test result signal; the test result signal is a signal generated by the control chip (1) based on the test signal; The brain electrode structure (2) comprises a contact electrode structure (21) connected to the pad structure (22); the contact electrode structure (21) collects brain electrical signals by contacting the scalp layer; The contact electrode structure (21) comprises N contact electrodes; N is an integer greater than or equal to 1; the pad structure (22) comprises N solder joints; The control chip (1) comprises a connected processor and N pixel circuits; the N pixel circuits are connected to the N welding points in a one-to-one correspondence; The N contact electrodes constitute a contact electrode set; the contact electrode structure comprises a first side and a second side opposite to each other; the contact electrode set comprises a first contact electrode set and a second contact electrode set, the first contact electrode set is located on the first side, and the second contact electrode set is located on the second side; the first contact electrode (211) and the second contact electrode (212) in the first contact electrode set are arranged in a staggered manner along the length direction of the contact electrode structure, and the second contact electrode set is arranged in the same or opposite manner as the first contact electrode (211) and the second contact electrode (212) in the first contact electrode set, or the first contact electrode set arranges a plurality of first contact electrodes (211) at intervals along the length direction of the contact electrode structure, and the second contact electrode set arranges a plurality of second contact electrodes (212) at intervals along the length direction of the contact electrode structure; the first contact electrode is connected to a first signal input line, and the second contact electrode is connected to a second signal input line; the processor is capable of controlling the first signal input line and the second signal input line to staggeredly input stimulation signals to achieve charge balance in the corresponding brain tissue area; Each of the pixel circuits includes a first capacitor C1, a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4, wherein a first end of the first capacitor C1 is connected to a signal input line V0, a ​​second end of the first capacitor C1 is connected to a first end of the second switch S2, a first end of the first switch S1 is connected to a second end of the first capacitor C1, a second end of the first switch S1 is connected to the signal input line V0, the signal input line V0 is connected to the processor, a second end of the second switch S2 is connected to a first end of the third switch S3, a third end of the second switch S2 is connected to a horizontal control signal line SX[n], and the horizontal control signal line SX[n] is connected to the processor; a second end of the third switch S3 is connected to a first end of the fourth switch S4, a third end of the third switch S3 is connected to a vertical control signal line SY[m], and the vertical control signal line SY[m] is connected to the processor; A first end of the fourth switch S4 is connected to the output port, the output port is connected to the corresponding solder joint, and a second end of the fourth switch S4 is connected to the test signal processing circuit.

2. The brain electrode system according to claim 1, characterized in that It also includes an analog-to-digital conversion module and a power supply module (6); The analog-to-digital conversion module is connected to the control chip (1); The power module (6) is connected to the control chip (1) and the analog-to-digital conversion module; The power supply module (6) is used to supply power to the control chip (1) and the analog-to-digital conversion module; The power module (6) comprises a lithium battery, a first low voltage dropout linear regulator and a second low voltage dropout linear regulator; The lithium battery is connected to the control chip (1) via the first low voltage drop linear regulator; The lithium battery is connected to the analog-to-digital conversion module via the second low voltage drop linear regulator; The analog-to-digital conversion module is used to receive the electroencephalogram signal sent by the control chip (1) and perform analog-to-digital conversion processing on the electroencephalogram signal.

3. The brain electrode system according to claim 2, characterized in that The voltage of the lithium battery includes 3.7 volts; The voltage output by the first low-dropout linear regulator ranges from 0.5 to 3.3 volts; The voltage output by the second low voltage drop linear regulator includes 1 to 1.8 volts.

4. The brain electrode system according to claim 1, characterized in that: The channels of the control chip (1) include 128×128 channels; The pad structure (22) includes 128×128 solder joints; The pad area includes 128×128 solder joints; The soldering points of the pad structure (22) are connected to the soldering points of the pad area in a one-to-one correspondence through flip-chip welding.

5. The brain electrode system according to claim 2, characterized in that: Also included are field programmable gate array chips; The field programmable gate array chip (7) is connected to the control chip (1), the analog-to-digital conversion module, the test module (4) and the stimulation module (3); The field programmable gate array chip (7) is used to supply power to the test module (4) and the stimulation module (3), and to send the received electroencephalogram signal sent by the analog-to-digital conversion module to a signal acquisition device; The voltage of the field programmable gate array chip (7) comprises 5 volts.

6. The brain electrode system according to claim 1, characterized in that: The stimulation module (3) outputs a stimulation voltage in the range of 0-3.3 volts; The error range between the stimulation voltage value output by the stimulation module (3) and the preset voltage value is 0-0.4 millivolts.

7. The brain electrode system according to claim 1, characterized in that: The processor is used to control the opening or closing of any one of the N contact electrodes by controlling the conduction or disconnection of any one of the N pixel circuits; and when any one of the pixel circuits is turned on, the processor controls any one of the pixel circuits to output a corresponding stimulation signal or test signal through the received stimulation signal or test signal, thereby achieving stimulation of the target cerebral cortex of the brain by any one of the contact electrodes or control of the test of the corresponding pixel circuit.

8. The brain electrode system according to claim 6, characterized in that The contact electrode structure (21) comprises M sub-contact electrode structures (21), wherein M is an integer greater than 1; There is a preset interval between adjacent sub-contact electrode structures (21) in the M sub-contact electrode structures (21); The M sub-contact electrode structures (21) are located on the same plane.

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