Apparatus and method for power switch status check

Abstract

Embodiments of the present disclosure relate to apparatuses and methods for power switch state checking. A power switch fault detector detects a fault in a current path of a power switch. A first operational amplifier detects a drain-source voltage of a first set of parallel field effect transistors in the current path. A second operational amplifier detects a drain-source voltage of a second set of parallel field effect transistors in the current path. A hardware or software processor is configured to compare a magnitude difference of the drain-source voltages to a threshold voltage to determine whether a field effect transistor in one of the first set or the second set is damaged. The current path is isolated and one of the first set of field effect transistors or the second set of field effect transistors is deactivated to determine whether the first set of field effect transistors or the second set of field effect transistors is a fixed open circuit or a short circuit.

Description

Technical Field

[0001] This disclosure generally relates to fault detection circuit devices. Background Technology

[0002] Vehicles providing driver assistance features require significant onboard power to power onboard computers, sensors, actuators, motors, drives, and many other electronic devices. Onboard power switches receive control signals to open and close the conductive path from the power source to the electronic equipment. In this respect, the onboard power switches control the power distribution to onboard devices as needed, on an operational basis, and / or on a functional basis. Summary of the Invention

[0003] This "Summary" is provided to introduce, in a simplified form, the selection of concepts further described in the "Detailed Description" below. This "Summary" is not intended to identify key elements or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0004] According to some embodiments, a method is provided. The method includes: determining the drain-source voltage of a first set of parallel field-effect transistors in a first current path, and determining the drain-source voltage of a second set of parallel field-effect transistors in the first current path. The method includes determining a difference between the drain-source voltage of the first set of parallel field-effect transistors and the drain-source voltage of the second set of parallel field-effect transistors. The method includes comparing the difference with a tolerance threshold. The method includes determining that a field-effect transistor in either the first set of parallel field-effect transistors or the second set of parallel field-effect transistors is damaged in response to the difference being greater than the tolerance threshold.

[0005] According to some embodiments, an apparatus is provided. The apparatus includes modules for determining the drain-source voltages of a first set of parallel field-effect transistors in a first current path, and modules for determining the drain-source voltages of a second set of parallel field-effect transistors in the first current path. The apparatus includes modules for determining a difference between the drain-source voltages of the first set of parallel field-effect transistors and the drain-source voltages of the second set of parallel field-effect transistors. The apparatus includes modules for comparing the difference with a tolerance threshold. The apparatus includes modules for determining that a field-effect transistor in either the first set of parallel field-effect transistors or the second set of parallel field-effect transistors is damaged in response to the difference being greater than the tolerance threshold.

[0006] According to some embodiments, an apparatus is provided. The apparatus includes a first set of parallel field-effect transistors (FETs) in a current path. The apparatus includes a first differential amplifier having input terminals coupled to the first set of parallel FETs and a first differential amplifier output terminal. The apparatus includes a second set of parallel FETs in a current path. The apparatus includes a second differential amplifier having input terminals coupled to the second set of parallel FETs and a second differential amplifier output terminal. The apparatus includes a processor coupled to the first and second differential amplifier output terminals and configured to determine whether a FET in the first or second set of parallel FETs is damaged.

[0007] According to some embodiments, an apparatus is provided. The apparatus includes a power supply coupled to a first current path and a second current path connected in parallel with the first current path. The apparatus includes a first set of parallel field-effect transistors (FETs) in the first current path. The apparatus includes a second set of parallel FETs in the first current path. The apparatus includes a first differential amplifier having input terminals coupled to the first set of parallel FETs and a first differential amplifier output terminal. The apparatus includes a second differential amplifier having input terminals coupled to the second set of parallel FETs and a second differential amplifier output terminal. The apparatus includes a processor coupled to the first and second differential amplifier output terminals and configured to disable the first current path and determine whether a FET in the first or second set of parallel FETs is short-circuited.

[0008] To achieve the foregoing and related objectives, the following description and accompanying drawings illustrate certain illustrative aspects and implementations. These merely indicate several of the various ways in which one or more aspects may be employed. Other aspects, advantages, and novel features of this disclosure will become apparent from the following detailed description when considered in conjunction with the accompanying drawings. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a power switch health check device according to some embodiments;

[0010] Figure 2 An embodiment of a processor for a power switch health check device according to some embodiments is shown;

[0011] Figure 3-4 This is a schematic diagram of a field-effect transistor block according to some embodiments;

[0012] Figure 5 A power switch health check method according to some embodiments is shown;

[0013] Figure 6 This is a schematic diagram of a power switch health check device according to some embodiments;

[0014] Figures 7A-7F A power switch health check method according to some embodiments is shown;

[0015] Figure 8 A power network system according to some embodiments is shown;

[0016] Figure 9 This is a table illustrating the states of field-effect transistor blocks in combinations of forward and blocking field-effect transistor blocks according to some embodiments; and

[0017] Figure 10 Exemplary computer-readable media according to some embodiments are shown. Detailed Implementation

[0018] The claimed subject matter will now be described with reference to the accompanying drawings, in which the same reference numerals are used throughout to refer to the same elements. In the following description, numerous specific details are set forth for purposes of explanation to provide a thorough understanding of the claimed subject matter. However, it will be apparent that the claimed subject matter can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form to facilitate the description of the claimed subject matter.

[0019] The reliability of battery and power network interconnects and switches is crucial for enabling Advanced Driver Assistance Systems (ADAS) and Autonomous Driving (AD) systems. For example, the field-effect transistors (FETs) of power switches should be inspected to detect faults such as short circuits or stuck-open current paths. In many cases, ADAS and AD functions should only be enabled if all involved power switch FETs are fault-free. Therefore, as described in this article, detecting faults in the current paths of power switch FETs can safely enable ADAS and AD devices, or, in the event of a detected fault, identify, bypass, disable associated devices, and / or activate alarms in real time.

[0020] Figure 1This is a schematic diagram of a power switch health check device 100 according to some embodiments. The power switch health check device 100 includes a first field-effect transistor (FET) block 102, which includes a first set of parallel FETs 104 in a current path 106. The first set of parallel FETs 104 includes FETs 108 coupled together in parallel between a first node 110 and a second node 112 in the current path 106. The first node 110 is coupled to a first region of the FET 108, and the second node 112 is coupled to a second region of the FET 108. In some embodiments, the first region of the FET 108 is a drain region, and the second region of the FET 108 is a source region.

[0021] The power switch health check device 100 includes a second FET block 114, which includes a second set of parallel FETs 116 in a current path 106. The second set of parallel FETs 116 includes FETs 118 coupled together in parallel between a third node 120 and a fourth node 122 along the current path 106. The third node 120 is coupled to a first region of FET 118, and the second node 112 is coupled to a second region of FET 118. In some embodiments, the first region of FET 118 is a drain region, and the second region of FET 118 is a source region. The drain region of FET 118 may be coupled to the drain region of FET 108. The drain region of FET 118 may be coupled to the source region of FET 108. The source region of FET 118 may be coupled to the drain region of FET 118. The source region of FET 118 can be coupled to the source region of FET 108. In some embodiments, the second node 112 is directly coupled to the third node 120, such that the first set of parallel FETs 104 is directly coupled to the second set of parallel FETs 116 in the current path 106.

[0022] The power switch health check device 100 includes a first differential amplifier 124 and a second differential amplifier 126. The first differential amplifier 124 includes a first input terminal 128 coupled to a first node 110, a second input terminal 130 coupled to a second node 112, and a first differential amplifier output terminal 132. The first differential amplifier output terminal 132 is coupled to a processor 134. The second differential amplifier 126 includes a third input terminal 136 coupled to a third node 120, a fourth input terminal 138 coupled to a fourth node 122, and a second differential amplifier output terminal 140. The second differential amplifier output terminal 140 is coupled to the processor 134. The processor 134 may include discrete components, hardware, software, firmware, a computer, or other suitable devices.

[0023] According to some embodiments, current path 106 is coupled to power domain source 142 and power domain load 144. Power domain source 142 may be a power source such as a primary battery, and power domain load 144 may be a motor, sensor, processor, actuator, DC-DC power supply, secondary battery, or other suitable load.

[0024] Figure 2 An embodiment of a processor 134 according to some embodiments is shown. Processor 134 includes a third differential amplifier 146 coupled to a first differential amplifier output terminal 132 and a second differential amplifier output terminal 140. The third differential amplifier 146 includes an output terminal 148 coupled to a first input terminal 158 of comparator 150. A voltage source 152 for a reference voltage “v” is coupled to a second input terminal 154 of comparator 150. Comparator 150 includes an output terminal 156. The signal level at output terminal 156 indicates whether FET 108 in a first set of parallel FETs 104 or FET 118 in a second set of parallel FETs 116 is damaged.

[0025] Therefore, the power switch health check device 100 determines whether the FETs of the first FET block 102 or the second FET block 114 are damaged. For example, if the FET 108 of the first FET block 102 is permanently open-circuited, the total resistance of the first set of parallel FETs 104 increases to a level greater than the resistance of the second set of parallel FETs 116. Thus, the first voltage at the output terminal 132 of the first differential amplifier is greater than the second voltage at the output terminal 140 of the second differential amplifier. This difference is detected by the power switch health check device 100. If the signal at the output terminal 156 of the comparator 150 indicates that the difference between the first and second voltages is greater than the reference voltage "v", it can be concluded that there is a significant difference between the resistance of the first set of parallel FETs 104 and the resistance of the second set of parallel FETs 116. The larger amplitude between the output signal of the first differential amplifier 124 and the output signal of the second differential amplifier 126 indicates which FET block of the first FET block 102 or the second FET block 114 has a permanently open-circuited FET. If the output signal of the first differential amplifier 124 is greater than the output signal of the second differential amplifier 126, then the first FET block 102 includes a fixed open-circuit FET. If the output signal of the second differential amplifier 126 is greater than the output signal of the first differential amplifier 124, then the second FET block 102 includes a fixed open-circuit FET.

[0026] Figures 3-4 This is a schematic diagram of field-effect transistor blocks 102 / 114 according to some embodiments.

[0027] refer to Figure 3 The field-effect transistor block 102 / 114 includes three forward FETs 160. Each forward FET 160 includes a gate 162, a source terminal 164, a drain terminal 166, and an intrinsic body diode 168. The anode 170 of the body diode 168 is coupled to the source terminal 164, and the cathode 172 of the body diode 168 is coupled to the drain terminal 166.

[0028] refer to Figure 4 The field-effect transistor block 102 / 114 includes three blocking FETs 174. Each blocking FET 174 includes a gate 176, a source terminal 178, a drain terminal 180, and an intrinsic body diode 182. The anode 184 of the body diode 182 is coupled to the source terminal 178, and the cathode 186 of the body diode 182 is coupled to the drain terminal 180.

[0029] In some embodiments, the first FET block 102 includes three forward FETs 160, and the second FET block 114 includes three blocking FETs 174, such that the cathodes 172 of the forward FETs 160 are coupled to the cathodes 186 of the blocking FETs 174. Other configurations of the first FET block 102 and the second FET block 114 are within the scope of this disclosure.

[0030] Figure 5 A power switch health check method (500) according to some embodiments is shown. The power switch health check method (500) is initiated at process block "Start Health Check #1" (502). The output (OD1) of the first differential amplifier is read (504). The output (OD2) of the second differential amplifier is read (506). The method includes determining whether a mismatch exists between OD1 and OD2 (508). If no mismatch exists, "Health Check #1" terminates (510) and the power switch health check method (500) is initiated at process block "Start Health Check #1" (502). If a mismatch exists, the mismatch is compared with a tolerance threshold (512). If the mismatch is not greater than the tolerance threshold (514), "No", no fixed open-circuit FET is detected, "Health Check #1" terminates (516), and the power switch health check method (500) is initiated at process block "Start Health Check #1" (502). If the mismatch is greater than the tolerance threshold (514) "Yes", then the mismatch is compared with the fixed open-circuit threshold (518). If the mismatch is not greater than the fixed open-circuit threshold (520) "No", then the power switch health check method (500) proceeds to "Health Check #2" (522) as described below. If the mismatch is greater than the fixed open-circuit threshold (520) "Yes", then OD1 is compared with OD2 (524). If OD1 is greater than OD2 (524 "Yes"), then the fixed open-circuit FET is located in the first group of FETs (528), such as the first FET block 102. If OD1 is not greater than OD2 (524 "No"), then the fixed open-circuit FET is located in the second group of FETs (526), ​​such as the second FET block 114. Regardless of whether OD1 is greater than OD2, "Health Check #1" terminates (510).

[0031] Figure 6 This is a schematic diagram of a power switch health check device 600 according to some embodiments.

[0032] The power switch health check device 600 includes a power domain source 602 coupled to a first current path 604 and a second current path 606 connected in parallel with the first current path 604. The power switch health check device 600 includes a first field-effect transistor (FET) block 608, which includes a first set of parallel FETs in the current path 604. The first set of parallel FETs includes FETs 604 coupled together in parallel between a first node 610 and a second node 612 in the current path. The first node 610 is coupled to a first region of the FET, and the second node 612 is coupled to a second region of the FET. In some embodiments, the first region of the FET is a drain region, and the second region of the FET is a source region.

[0033] The power switch health check device 100 includes a second FET block 614, which includes a second set of parallel FETs in a current path 106. The second set of parallel FETs includes FETs coupled together in parallel between a third node 616 and a fourth node 618 along a current path 604. The third node 616 is coupled to a first region of the FET, and the fourth node 618 is coupled to a second region of the FET. In some embodiments, the first region of the FET is a drain region, and the second region of the FET is a source region.

[0034] The drain region of the FET in the first FET block 608 can be coupled to the drain region of the FET in the second FET block 614. The drain region of the FET in the first FET block 608 can be coupled to the source region of the FET in the second FET block 614. The source region of the FET in the first FET block 608 can be coupled to the drain region of the FET in the second FET block 614. The source region of the FET in the first FET block 608 can be coupled to the source region of the FET in the second FET block 614. In some embodiments, the second node 612 is directly coupled to the third node 616, such that the first group of parallel FETs in the first FET block 608 is directly coupled to the second group of parallel FETs in the second FET block 614.

[0035] The power switch health check device 600 includes a first differential amplifier 620 and a second differential amplifier 622. The first differential amplifier 620 includes a first input terminal 624 coupled to a first node 610, a second input terminal 626 coupled to a second node 612, and a first differential amplifier output terminal 628. The first differential amplifier output terminal 628 is coupled to a processor 630. The second differential amplifier 622 includes a third input terminal 632 coupled to a third node 616, a fourth input terminal 634 coupled to a fourth node 618, and a second differential amplifier output terminal 636. The second differential amplifier output terminal 636 is coupled to the processor 630. The processor 630 may include discrete components, hardware, software, firmware, a computer, or other suitable devices. According to some embodiments, the processor 630 is configured to disable a first current path 604 and determine whether the FETs of the first FET block 608 or the second FET block 614 are short-circuited. The processor 630 can be configured to turn on and maintain the conduction of either the FET in the first FET block 608 or the FET in the second FET block 614 while the first current path 604 remains in a deactivated state. The power switch health check device 600 includes a first comparator 648 and a second comparator 652. The first comparator 648 includes an input terminal coupled to a terminal of the first differential amplifier output 628 and a terminal of the first reference voltage 650. The second comparator 652 includes an input terminal coupled to a terminal of the second differential amplifier output 636 and a terminal of the second reference voltage 654. In some embodiments, the first reference voltage 650 and the second reference voltage 654 are threshold voltages of the body diode.

[0036] According to some embodiments, current path 604 is coupled to power domain load / source 638. Power domain source 602 may be a power source such as a main battery, and power domain load / source 638 may be a motor, sensor, processor, actuator, DC-DC power supply, secondary battery, or other suitable load / power source.

[0037] The power switch health check device 100 includes a third FET block 640 and a fourth FET block 642. The third FET block 640 includes a third set of parallel FETs in a second current path 606, and the fourth FET block 642 includes a fourth set of parallel FETs in the second current path 606. A first switching unit 656 includes the third FET block 640 and the fourth FET block 642, and a second switching unit 658 includes a first FET block 608 and a second FET block 614. According to some embodiments, a first current or voltage source 644 is coupled to a fifth node 646 in the first current path 604 between the first FET block 608 and the second FET block 614, and a second current or voltage source 647 is coupled to a first node 649 in the second current path 606 between the third FET block 640 and the fourth FET block 642.

[0038] Figures 7A-7C A power switch health check method according to some embodiments is illustrated. The power switch health check method (700) is initiated from "Health Check #1" (522), and the method begins from "Start Health Check #2" (702). Current is maintained through switch unit #1 (704). The switch unit under check is turned off (706). A current source is coupled to the node between group #1 and group #2 (708). The output of a first differential amplifier is read (710). The method includes determining whether the output of the first differential amplifier is greater than a diode threshold (712). If the output is greater than the diode threshold, the FET in group #1 or group #2 is fixed open (714), and the method continues to... Figure 5 524. If the output is not greater than the diode threshold, then there is no FET fixed open in group #1 (716). The method includes determining whether the output of the first differential amplifier is less than the diode threshold (718). If the output is not less than the diode threshold, then there is no short-circuited closed FET in either group #1 or group #2 (720). If the output is less than the diode threshold, then there is a short-circuited closed FET in either group #1 or group #2 (722).

[0039] The method includes reading the output of differential amplifier #2 (723) and determining whether the output is greater than a diode threshold (724). If the output is greater than the diode threshold, the FET in group #1 or group #2 is always open (726) and the method continues to Figure 5 524. If the output is not greater than the diode threshold, there is no FET fixed open in group #2 (728). The method includes determining whether the output of the second differential amplifier is less than the diode threshold (730). If the output is not less than the diode threshold, there is no short-circuit closed FET in either group #1 or group #2 (732). If the output is less than the diode threshold, there is a short-circuit closed FET in either group #1 or group #2 (734). The current source is decoupled from the node between group #1 and group #2 (736). One of group #1 or group #2 is turned on (738) and the other of group #1 or group #2 is turned off (740). The drain-source voltage of the turned-on group is determined (742). If the drain-source voltage of the turned-on group is zero (744), there is no short-circuit closed FET in the turned-off group (746). If the drain-source voltage of the turned-on group is not zero, there is a short-circuit closed FET in the turned-off group (748).

[0040] Figure 7D-7FA power switch health check method according to some embodiments is shown. The power switch health check method (700) is initiated from "Health Check #1" (522) and the method begins from "Start Health Check #2" (750). Current is maintained through switch unit #1 (752). The switch unit being checked is turned off (754). A current source is coupled to a node between group #1 and group #2 (756). The method includes (766) proceeding in parallel as described below, and reading the output of a first differential amplifier (758). The method includes determining whether the output of the first differential amplifier is greater than a diode threshold (760). If the output is greater than the diode threshold, there is no short-circuit closed FET in group #1 or group #2 (762). If the output is not greater than the diode threshold, there is a short-circuit closed FET in one of group #1 or group #2, and the method continues to (774) as described below.

[0041] In parallel with reading the output of the first differential amplifier (758), the output of the second differential amplifier is read (766). This method includes determining whether the output is greater than a diode threshold (768). If the output is greater than the diode threshold, there is no short-circuit closed FET in either group #1 or group #2 (770). If the output is not greater than the diode threshold, there is a short-circuit closed FET in either group #1 or group #2 (772). The current source is decoupled from the node between group #1 and group #2 (774). One of group #1 or group #2 is turned on (776), and the other of group #1 or group #2 is turned off (778). The drain-source voltage of the turned-off group is determined (780). This method includes determining whether the drain-source voltage is zero (782). If the drain-source voltage of the turned-off group is zero, there is no short-circuit closed FET in the turned-off group (784). If the drain-source voltage of the turned-off group is not zero, there is a short-circuit closed FET in the turned-off group (786).

[0042] Figure 8 A power network system 800 according to some embodiments is illustrated. The location of a power switch health check device 100 within the power network system 800 is indicated by the symbol “X”. In some embodiments, the power switch health check device 100 is coupled to a battery (BP) 802, a voltage conversion and isolation device (VCI) 804, a power connection and isolation device (PCI) 806, a load protector (PSP) 808, a load control and self-protection device (LCSP) 810, a wire protection device 812 (WP), and other suitable devices.

[0043] Figure 9 This is a table showing the states of field-effect transistor blocks in combinations of forward and blocking field-effect transistor blocks according to some embodiments.

[0044] Figure 10Exemplary computer-readable media according to some embodiments are illustrated. One or more embodiments relate to a computer-readable medium including processor-executable instructions configured to implement one or more of the techniques presented herein. The exemplary computer-readable medium in... Figure 10 As shown, embodiment 1000 includes a computer-readable medium 1004 (e.g., a CD-R, DVD-R, flash drive, hard disk platter, etc.) on which computer-readable data 1003 is encoded. The computer-readable data 1003 further includes a set of processor-executable computer instructions 1002 that, when executed, are configured to facilitate operation according to one or more principles set forth herein. In some embodiments of 1000, the processor-executable computer instructions 1002, when executed, are configured to facilitate the execution of method 1001, such as at least some of the methods described above. In some embodiments, the processor-executable computer instructions 1002, when executed, are configured to facilitate the implementation of a system, such as at least some of one or more of the systems described above. Many such computer-readable media configured to operate according to the techniques presented herein can be designed by those skilled in the art.

[0045] The term "computer-readable medium" can include communication media. Communication media typically contain computer-readable instructions or other data in a "modulated data signal," such as a carrier chip or other transmission mechanism, and include any information transmission medium. The term "modulated data signal" can include a signal having one or more characteristics that are set or altered in a manner that encodes information in the signal.

[0046] The power switch health check device 100 monitors the voltage drop across at least two sets of power switches on the same current path. The voltage drops are compared in real time to detect damage to one set of various power switch groups, such as those with fixed open or short-circuit closed FETs. Because at least two sets of power switches are on the same current path, the power switches are monitored independently of temperature and current flow. Redundant power switches on a second current path connected in parallel with the current path under test allow the system to remain operational while the power switches are being tested.

[0047] According to some embodiments, a method is provided. The method includes: determining the drain-source voltage of a first set of parallel field-effect transistors in a first current path; determining the drain-source voltage of a second set of parallel field-effect transistors in the first current path; determining the difference between the drain-source voltage of the first set of parallel field-effect transistors and the drain-source voltage of the second set of parallel field-effect transistors; comparing the difference with a tolerance threshold; and determining that one of the field-effect transistors in the first set of parallel field-effect transistors or the second set of parallel field-effect transistors is damaged, in response to the difference being greater than the tolerance threshold.

[0048] According to some embodiments, the method includes: comparing the difference with a fixed open-circuit threshold greater than a tolerance threshold; and determining, in response to the difference being greater than the fixed open-circuit threshold, that a group of parallel field-effect transistors having the maximum drain-source voltage has a damaged transistor that is a fixed open-circuit transistor.

[0049] According to some embodiments, the method includes: comparing the difference with a fixed open-circuit threshold greater than a tolerance threshold; and maintaining the current in a second current path in parallel with a first current path in response to the difference being less than the fixed open-circuit threshold, wherein a third set of parallel field-effect transistors and a fourth set of parallel field-effect transistors are in the second current path.

[0050] According to some embodiments, the method includes: disabling a first current path in response to a difference less than a fixed open-circuit threshold; coupling a current source to a node in the first current path between a first group of parallel field-effect transistors and a second group of parallel field-effect transistors; determining the drain-source voltage of the first group of parallel field-effect transistors; determining the drain-source voltage of the second group of parallel field-effect transistors; determining that neither the first group nor the second group includes short-circuit closed-circuit field-effect transistors in response to the drain-source voltage of the first group of parallel field-effect transistors being greater than a diode threshold; and determining that neither the first group nor the second group includes short-circuit closed-circuit field-effect transistors in response to the drain-source voltage of the second group of parallel field-effect transistors being greater than a diode threshold.

[0051] According to some embodiments, the method includes: disabling a first current path in response to a difference less than a fixed open-circuit threshold; coupling a current source to a node in the first current path between a first group of parallel field-effect transistors and a second group of parallel field-effect transistors; determining the drain-source voltage of the first group of parallel field-effect transistors; determining the drain-source voltage of the second group of parallel field-effect transistors; determining that a field-effect transistor in either the first or second group of parallel field-effect transistors is short-circuited in response to determining that the drain-source voltage of either the first or second group is less than a diode threshold; decoupling the current source from the node; turning on one of the first or second group of parallel field-effect transistors and turning off the other; determining the drain-source voltage of the turned-off group; and determining that the turned-off group of parallel field-effect transistors does not contain a short-circuited field-effect transistor in response to determining that the drain-source voltage of the turned-off group is approximately zero.

[0052] According to some embodiments, the method includes: disabling a first current path in response to a difference less than a fixed open-circuit threshold; coupling a current source to a node in the first current path between a first group of parallel field-effect transistors and a second group of parallel field-effect transistors; determining the drain-source voltage of the first group of parallel field-effect transistors; determining the drain-source voltage of the second group of parallel field-effect transistors; determining that a field-effect transistor in the first or second group of parallel field-effect transistors is short-circuited in response to determining that the drain-source voltage of the first or second group is less than a diode threshold; decoupling the current source from the node; turning on one of the first or second group of parallel field-effect transistors and turning off the other; determining the drain-source voltage of the turned-off group; and determining that a field-effect transistor in the turned-off group of parallel field-effect transistors is short-circuited in response to determining that the drain-source voltage of the turned-off group is greater than zero.

[0053] According to some embodiments, an apparatus is provided. The apparatus includes: a first set of parallel field-effect transistors (FETs) in a current path; a first differential amplifier including an input terminal coupled to the first set of parallel FETs and an output terminal of the first differential amplifier; a second set of parallel FETs in the current path; a second differential amplifier including an input terminal coupled to the second set of parallel FETs and an output terminal of the second differential amplifier; and a processor coupled to the first and second differential amplifier output terminals and configured to determine whether one of the FETs in the first or second set of parallel FETs is damaged.

[0054] According to some embodiments, the processor includes: a third differential amplifier, the third differential amplifier including: an input terminal coupled to the output terminal of a first differential amplifier and the output terminal of a second differential amplifier; and a third differential amplifier output terminal; and a comparator including: a first input terminal coupled to the output terminal of the third differential amplifier; a second input terminal coupled to a terminal of a reference voltage; and a comparator output terminal, wherein the signal level at the comparator output terminal indicates whether a field-effect transistor in a first set of parallel field-effect transistors or a second set of parallel field-effect transistors is damaged.

[0055] According to some embodiments, the device includes: a power domain source coupled to a current path and a first set of parallel field-effect transistors; and a power domain load coupled to a current path and a second set of parallel field-effect transistors.

[0056] According to some embodiments, the power domain load is a DC-DC power supply.

[0057] According to some embodiments, the first set of parallel field-effect transistors is directly coupled to the second set of parallel field-effect transistors in the current path.

[0058] According to some embodiments, the drain terminal of the transistor in the first set of parallel field-effect transistors is directly coupled to the drain terminal of the transistor in the second set of parallel field-effect transistors.

[0059] According to some embodiments, the transistors in the first set of parallel field-effect transistors include a forward diode in the current path, the transistors in the second set of parallel field-effect transistors include a blocking diode in the current path, and the cathode of the forward diode is coupled to the cathode of the blocking diode.

[0060] According to some embodiments, an apparatus is provided. The apparatus includes: a power supply coupled to a first current path and a second current path connected in parallel with the first current path; a first set of parallel field-effect transistors (FETs) in the first current path; a second set of parallel FETs in the first current path; a first differential amplifier including an input terminal coupled to the first set of parallel FETs and a first differential amplifier output terminal; a second differential amplifier including an input terminal coupled to the second set of parallel FETs and a second differential amplifier output terminal; and a processor coupled to the first and second differential amplifier output terminals and configured to disable the first current path and determine whether a FET in the first or second set of parallel FETs is short-circuited.

[0061] According to some embodiments, the processor is configured to turn on and maintain the first set of parallel field-effect transistors or the second set of parallel field-effect transistors while the first current path remains in a deactivated state.

[0062] According to some embodiments, the third group of parallel field-effect transistors and the fourth group of parallel field-effect transistors are connected in series in the second current path.

[0063] According to some embodiments, the device includes a current source coupled to a node in a first current path between a first set of parallel field-effect transistors and a second set of parallel field-effect transistors.

[0064] According to some embodiments, the device includes: a first comparator with input terminals coupled to a first differential amplifier output terminal and a first reference voltage; and a second comparator with input terminals coupled to a second differential amplifier output terminal and a second reference voltage.

[0065] According to some embodiments, the first reference voltage and the second reference voltage are the threshold voltages of the diode.

[0066] According to some embodiments, the transistors in the first set of parallel field-effect transistors include a forward diode in a first current path, and the transistors in the second set of parallel field-effect transistors include a blocking diode in the first current path, with the cathode of the forward diode coupled to the cathode of the blocking diode.

[0067] Although the subject matter has been described in language specific to structural features or methodological actions, it should be understood that the subject matter of the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms of implementing at least some of the claims.

[0068] Various operations are provided in the embodiments herein. The order in which some or all of the operations are described should not be construed as implying that these operations necessarily depend on the order. Alternative orderings will be understood with the help of this specification. Furthermore, it will be understood that not all operations must exist in every embodiment provided herein. Additionally, it will be understood that in some embodiments, not all operations are necessary.

[0069] Furthermore, “exemplary” is used herein to mean as an example, instance, illustration, etc., and is not necessarily advantageous. As used herein, “or” is intended to mean an inclusive “or” rather than an exclusive “or.” Furthermore, “a” and “an” as used herein and in the appended claims are generally interpreted as meaning “one or more” unless otherwise stated or clearly indicated from the context as a singular form. Furthermore, at least one of A and B generally means either A or B or both A and B. Moreover, to the extent used, terms such as “includes,” “having,” “has,” “with,” or variations thereof are intended to be inclusive in a manner similar to the term “comprising.” Furthermore, unless otherwise stated, “first,” “second,” etc., are not intended to imply temporal, spatial, or sequential aspects. Rather, these terms are used only as identifiers, names, etc., of features, elements, items, etc. For example, a first element and a second element generally correspond to element A and element B, or two different elements, or two identical elements, or the same element.

[0070] Furthermore, while this disclosure has been shown and described with respect to one or more implementations, equivalent changes and modifications will be conceived by those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This disclosure includes all such modifications and changes and is limited only by the scope of the following claims. In particular, with respect to the various functions performed by the foregoing components (e.g., elements, resources, etc.), unless otherwise stated, the terminology used to describe such components is intended to correspond to any component performing the specified function of the described component (e.g., functionally equivalent), even if structurally not equivalent to the disclosed structure. Moreover, while a particular feature of this disclosure may be disclosed with respect to only one of several implementations, such features may be combined with one or more other features of other implementations, which may be desirable and advantageous for any given or particular application.

Claims

1. A method for checking the health of a power switch, comprising: Determine the drain-source voltage of the first group of parallel field-effect transistors in the first current path; Determine the drain-source voltage of the second group of parallel field-effect transistors in the first current path, wherein the second group of parallel field-effect transistors is connected in series with the first group of parallel field-effect transistors; Determine the difference between the drain-source voltage of the first group of parallel field-effect transistors and the drain-source voltage of the second group of parallel field-effect transistors; The difference is compared with a tolerance threshold. as well as In response to the difference being greater than the tolerance threshold, it is determined that a field-effect transistor in either the first group of parallel field-effect transistors or the second group of parallel field-effect transistors is damaged.

2. The method according to claim 1, comprising: The difference is compared with a fixed open-circuit threshold that is greater than the tolerance threshold; as well as In response to the difference being greater than the fixed open-circuit threshold, it is determined that a group of parallel field-effect transistors with the maximum drain-source voltage has a damaged transistor that is a fixed open-circuit transistor.

3. The method according to claim 1, comprising: The difference is compared with a fixed open-circuit threshold that is greater than the tolerance threshold; as well as In response to the difference being less than the fixed open-circuit threshold, the current in the second current path connected in parallel with the first current path is maintained, wherein The third group of parallel field-effect transistors and the fourth group of parallel field-effect transistors are in the second current path.

4. The method according to claim 3, comprising: In response to the difference being less than the fixed open-circuit threshold, the first current path is deactivated; Couple the current source to the node in the first current path between the first group of parallel field-effect transistors and the second group of parallel field-effect transistors; Determine the drain-source voltage of the first group of parallel field-effect transistors; Determine the drain-source voltages of the second group of parallel field-effect transistors; In response to the drain-source voltage of the first group of parallel field-effect transistors being greater than the diode threshold, it is determined that neither the first group nor the second group includes a short-circuit closed field-effect transistor. as well as In response to the drain-source voltage of the second group of parallel field-effect transistors being greater than the diode threshold, it is determined that neither the first group nor the second group includes a short-circuit closed field-effect transistor.

5. The method according to claim 3, comprising: In response to the difference being less than the fixed open-circuit threshold, the first current path is deactivated; Couple the current source to the node in the first current path between the first group of parallel field-effect transistors and the second group of parallel field-effect transistors; Determine the drain-source voltage of the first group of parallel field-effect transistors; Determine the drain-source voltages of the second group of parallel field-effect transistors; In response to determining that the drain-source voltage of the first group or the second group is less than the diode threshold, it is determined that the field-effect transistor in the first group of parallel field-effect transistors or the second group of parallel field-effect transistors is short-circuited; Decouple the current source from the node; Turn on one of the first group of parallel field-effect transistors or the second group of parallel field-effect transistors, and turn off the other of the first group of parallel field-effect transistors or the second group of parallel field-effect transistors; Determine the drain-source voltage of the cutoff group; as well as In response to the determination that the drain-source voltage of the cut-off group is approximately zero, it is determined that the cut-off group of parallel field-effect transistors does not contain a short-circuit field-effect transistor.

6. The method according to claim 3, comprising: In response to the difference being less than the fixed open-circuit threshold, the first current path is deactivated; Couple the current source to the node in the first current path between the first group of parallel field-effect transistors and the second group of parallel field-effect transistors; Determine the drain-source voltage of the first group of parallel field-effect transistors; Determine the drain-source voltages of the second group of parallel field-effect transistors; In response to determining that the drain-source voltage of the first group or the second group is less than the diode threshold, it is determined that the field-effect transistor in the first group of parallel field-effect transistors or the second group of parallel field-effect transistors is short-circuited; Decouple the current source from the node; Turn on one of the first group of parallel field-effect transistors or the second group of parallel field-effect transistors, and turn off the other of the first group of parallel field-effect transistors or the second group of parallel field-effect transistors; Determine the drain-source voltage of the cutoff group; as well as In response to the determination that the drain-source voltage of the cut-off group is greater than zero, it is determined that the field-effect transistors in the cut-off group of parallel field-effect transistors are short-circuited.

7. A power switch health check device, comprising: The first set of parallel field-effect transistors in the current path; The first differential amplifier includes: The input terminal is coupled to the first group of parallel field-effect transistors; and First differential amplifier output terminal; The second set of parallel field-effect transistors in the current path is connected in series with the first set of parallel field-effect transistors. The second differential amplifier includes: The input terminal is coupled to the second group of parallel field-effect transistors; and The output terminals of the second differential amplifier; and The processor is coupled to the output terminals of the first differential amplifier and the second differential amplifier and is configured to determine whether a field-effect transistor in the first set of parallel field-effect transistors or the second set of parallel field-effect transistors is damaged.

8. The apparatus of claim 7, wherein the processor comprises: The third differential amplifier includes: The input terminals are coupled to the output terminals of the first differential amplifier and the second differential amplifier; and The output terminals of the third differential amplifier; and A comparator, including: The first input terminal is coupled to the output terminal of the third differential amplifier; The second input terminal, coupled to the reference voltage; and Comparator output terminals, The signal level at the comparator output terminal indicates whether the field-effect transistors in the first group of parallel field-effect transistors or the second group of parallel field-effect transistors are damaged.

9. The apparatus according to claim 7, comprising: A power source is coupled to the current path and the first set of parallel field-effect transistors; as well as The power domain load is coupled to the current path and the second set of parallel field-effect transistors.

10. The apparatus of claim 9, wherein the power domain load is a DC-DC power supply.

11. The apparatus of claim 7, wherein the first set of parallel field-effect transistors is directly coupled to the second set of parallel field-effect transistors in the current path.

12. The apparatus of claim 7, wherein the drain terminal of the transistor in the first set of parallel field-effect transistors is directly coupled to the drain terminal of the transistor in the second set of parallel field-effect transistors.

13. The apparatus according to claim 7, wherein The transistors in the first group of parallel field-effect transistors include a forward diode in the current path. The transistors in the second group of parallel field-effect transistors include blocking diodes in the current path, and The cathode of the forward diode is coupled to the cathode of the blocking diode.

14. A power switch health check device, comprising: The power supply is coupled to a first current path and a second current path connected in parallel with the first current path. The first group of parallel field-effect transistors in the first current path; The second group of parallel field-effect transistors in the first current path are connected in series with the first group of parallel field-effect transistors. The first differential amplifier includes: The input terminal is coupled to the first group of parallel field-effect transistors; and First differential amplifier output terminal; The second differential amplifier includes: The input terminal is coupled to the second group of parallel field-effect transistors; and The output terminals of the second differential amplifier; and The processor, coupled to the output terminals of the first differential amplifier and the second differential amplifier, is configured to disable the first current path and determine whether a field-effect transistor in the first set of parallel field-effect transistors or the second set of parallel field-effect transistors is short-circuited.

15. The apparatus of claim 14, wherein the processor is configured to turn on and maintain the first set of parallel field-effect transistors or the second set of parallel field-effect transistors while the first current path remains in a deactivated state.

16. The apparatus of claim 14, comprising: The third and fourth sets of parallel field-effect transistors are connected in series in the second current path.

17. The apparatus of claim 14, comprising: A current source is coupled to a node in the first current path between the first set of parallel field-effect transistors and the second set of parallel field-effect transistors.

18. The apparatus of claim 14, comprising: The first comparator includes an input terminal coupled to the output terminal of the first differential amplifier and the terminal of the first reference voltage; as well as The second comparator includes an input terminal coupled to the output terminal of the second differential amplifier and the terminal of the second reference voltage.

19. The apparatus of claim 18, wherein the first reference voltage and the second reference voltage are threshold voltages of a diode.

20. The apparatus of claim 14, wherein The transistors in the first group of parallel field-effect transistors include forward diodes in the first current path. The transistors in the second group of parallel field-effect transistors include a blocking diode in the first current path, and The cathode of the forward diode is coupled to the cathode of the blocking diode.

Images