A method for integrating ONO photolithography rework process of SONOS memory

Abstract

The present invention provides a SONOS memory ONO photolithography rework process integration method, comprising: providing a wafer to be reworked, the wafer comprising a semiconductor substrate, an oxide layer and a silicon nitride layer and a photoresist layer to be stripped; using a dry process to remove most of the photoresist layer, and then using a wet process to remove the remaining photoresist layer; forming a photoresist layer for a second time, etching and removing the silicon nitride layer in the selection gate region and the peripheral logic region; using a wet etching process to remove the oxide layer in the selection gate region and the peripheral logic region, the etching amount of the chemical solution used is less than the reference etching amount; removing the photoresist layer formed for the second time, performing pre-cleaning, the cleaning amount of the chemical solution used is greater than the reference cleaning amount; growing a gate oxide layer and a barrier oxide layer. The present invention reduces the film layer damage caused by the side drilling of the chemical solution in the wet etching process of the reworked wafer by adjusting the etching amount of the wet etching process and the pre-cleaning amount of the gate oxide layer, thereby ensuring reliability. The rework process is stable and controllable, and is suitable for mass production.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a method for integrating an ONO photolithography rework process of a SONOS memory. Background Art

[0002] As the market continues to increase the integration requirements of FLASH memory devices, the contradiction between the reliability of data storage of traditional Flash devices and the working speed, power consumption, size, etc. of the devices has become increasingly prominent. SONOS memory has the characteristics of small unit size, low operating voltage, and compatibility with CMOS process. The continuous improvement of SONOS technology will promote the development of semiconductor memory towards miniaturization, high performance, large capacity, and low cost.

[0003] SONOS memory uses silicon (substrate)-tunneling oxide layer-silicon nitride-blocking oxide layer (blocking oxide)-polysilicon (Silicon-Oxide-Nitride-Oxide-Silicon, SONOS) gate stack layer to replace the floating gate structure in traditional FLASH memory devices. It is a charge trap type memory. Generally, the tunneling oxide layer-silicon nitride layer-blocking oxide layer (ONO) is grown using the In-sute (in-situ preparation) formation method. After the ONO is formed, only the SONOS area needs the ONO stack, and the select gate (select gate area pre) and the peripheral logic circuit area do not need the ONO stack. At this time, it is necessary to remove the ONO stack in the peripheral logic area and the select gate area through processes such as photolithography, wet etching, and dry etching, and then go through the gate oxide pre-cleaning step, and then use ISSG and other processes to grow the gate oxide layer. However, in the photolithography process, if the new product pi-run or machine shift causes the CD or OVL offset (i.e., dimensional accuracy or registration accuracy) to not meet the process requirements, it is necessary to strip the glue and rework and then re-perform the photolithography process. Specifically, a dry asher is first used to remove organic matter such as photoresist / anti-reflective coating by oxidation; then a chemical solution such as sulfuric acid is used to remove a small amount of photoresist residue that was not removed in the first step of rework, and organic matter such as polymer is removed. At this point, the stripping process is completed.

[0004] In the above rework process, sulfuric acid is inevitably the preferred chemical solution to remove polymer and avoid organic residues. However, even if there are subsequent cleaning steps such as pure water after sulfuric acid cleaning, there will inevitably be some residues. The water absorption of sulfuric acid or the sulfuric acid cleaning process itself has a certain impact on the silicon nitride on the surface. When the ONO photoresist is coated and developed again, the adhesion of the photoresist to the substrate becomes worse. The subsequent ONO wet etching process has a large etching amount to ensure that the bottom sacrificial oxide layer is completely removed. In this process, side drilling occurs on both sides of the photoresist-covered area, resulting in film damage and failure. The probability of failure further increases as the size decreases, and in severe cases, it will also cause device reliability problems. Therefore, wafers using this baseline rework process have a low-quality risk. Summary of the invention

[0005] In view of the shortcomings of the prior art described above, the object of the present invention is to provide an integrated method for ONO photolithography rework process of a SONOS memory, so as to solve the problem in the prior art that the rework process has sulfuric acid residue, resulting in poor adhesion of the photoresist, and further side drilling of the solution on both sides of the photoresist coverage area when wet etching the bottom oxide layer, resulting in film damage and failure.

[0006] To achieve the above-mentioned and other related purposes, the present invention provides a method for integrating a SONOS memory ONO lithography rework process, the method at least comprising:

[0007] 1) providing a wafer to be reworked by photolithography, the wafer comprising a semiconductor substrate having a SONOS region, a select gate region and a peripheral logic region, an oxide layer and a silicon nitride layer sequentially formed on a surface of the semiconductor substrate, and a photoresist layer to be stripped on a surface of the silicon nitride layer in the SONOS region;

[0008] 2) removing most of the photoresist layer by a dry ashing process, then removing the remaining photoresist layer by a wet process, and finally washing with deionized water to remove the residual chemical solution;

[0009] 3) forming a photoresist layer for a second time, wherein the photoresist layer covers the surface of the silicon nitride layer in the SONOS region, and etching away the silicon nitride layer in the select gate region and the peripheral logic region;

[0010] 4) using a wet etching process to remove the oxide layer in the select gate region and the peripheral logic region, wherein the etching amount of the chemical solution used in the wet etching process is less than a reference etching amount;

[0011] 5) removing the photoresist layer formed for the second time and performing pre-cleaning, wherein the cleaning amount of the chemical solution used in the pre-cleaning is greater than the reference cleaning amount;

[0012] 6) growing a gate oxide layer in the select gate region and the peripheral logic region, and forming a top blocking oxide layer on the surface of the silicon nitride layer in the SONOS region.

[0013] Optionally, in step 2), the chemical solution used in the wet process is sulfuric acid.

[0014] Optionally, in step 4), the chemical solution used in the wet etching process is BOE.

[0015] Optionally, in step 5), the chemical solution used for the pre-cleaning is HF.

[0016] Optionally, an anti-reflection coating is further formed between the photoresist layer and the silicon nitride layer in the SONOS region.

[0017] Optionally, the difference between the cleaning amount and the reference cleaning amount in step 5) is equal to the difference between the reference etching amount and the etching amount in step 4).

[0018] Optionally, in step 3), the step of secondary forming the photoresist layer includes coating and developing steps.

[0019] Optionally, in step 3), dry etching is used to remove the silicon nitride layer in the select gate region and the peripheral logic region.

[0020] As described above, the SONOS memory ONO lithography rework process integration method of the present invention has the following beneficial effects:

[0021] 1. The integrated photolithography rework process of the present invention improves the side drilling problem by flexibly adjusting the etching amount of the wet etching process and the cleaning amount of the pre-cleaning before the gate oxide layer growth, avoids the damage to the film layer in the SONOS area caused by the current rework process, solves the low-yield problem, and reduces the reliability risk of the device.

[0022] 2. The new rework process does not add any steps compared to the existing baseline conditions. By adjusting the etching amount of the wet etching process and the cleaning amount of the pre-cleaning before the gate oxide layer growth, the bottom oxide layer of the select gate area and the peripheral logic area is completely removed without affecting the step height of the select gate area and the peripheral logic area. The process risk is low and the process window is resolved. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic flow chart of the integrated method of the ONO photolithography rework process of the SONOS memory of the present invention;

[0024] Figure 2 to Figure 9It is a structural schematic diagram of each step of the ONO photolithography rework process integration method for a SONOS memory of the present invention.

[0025] Component number description

[0026] 1 Semiconductor substrate

[0027] 2 Oxide layer

[0028] 3 Silicon nitride layer

[0029] 4.5 Photoresist layer

[0030] 6 Gate Oxide

[0031] 7 Barrier oxide layer DETAILED DESCRIPTION

[0032] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] Please refer to the attached drawings. It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show the components related to the present invention rather than the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0034] like Figure 1 As shown, the present invention provides a method for integrating a SONOS memory ONO lithography rework process, the method at least comprising:

[0035] First, execute step S1, such as Figure 1 and Figure 2 As shown, a wafer to be reworked by photolithography is provided, wherein the wafer comprises a semiconductor substrate 1 having a SONOS region, a select gate region and a peripheral logic region, an oxide layer 2 and a silicon nitride layer 3 sequentially formed on the surface of the semiconductor substrate 1, and a photoresist layer 4 to be stripped located on the surface of the silicon nitride layer 3 in the SONOS region.

[0036] In this step, the surface of the semiconductor substrate 1 has at least one SONOS region, a select gate region and a peripheral logic region, and at this time, the ONO stack has been formed, and there is a shallow trench isolation region STI between the SONOS region, the select gate region and the peripheral logic region. Figure 2As shown, the surface of the SONOS region includes an ONO oxide layer 2 (or tunnel oxide layer) and an ONO silicon nitride layer 3, and the surfaces of the select gate region and the peripheral logic region also have an oxide layer 2 (or sacrificial oxide layer) and a silicon nitride layer 3. In addition, the surfaces of the SONOS region and the select gate region have a certain step height difference.

[0037] At this time, the development of the photoresist layer on the surface of the semiconductor substrate 1 has been completed, and the photoresist layers of the select gate region and the peripheral logic region have been opened, while the SONOS region is still covered by the photoresist layer 4. However, due to the deviation of factors such as dimensional accuracy or registration accuracy, the position of the photoresist layer 4 covering the surface of the SONOS region is inaccurate, and it needs to be stripped and reworked.

[0038] In this embodiment, the semiconductor substrate 1 may be a P-type silicon substrate, and the thickness of the oxide layer 3 is 4 nm. The following is a formal rework process.

[0039] Then proceed to step S2, such as Figure 1 and Figure 3 As shown, a dry ashing process is used to remove most of the photoresist layer 4. Figure 4 As shown, the remaining photoresist layer 4 is removed by a wet process, and finally the residual chemical solution is removed by washing with deionized water.

[0040] As a preferred solution, in this step, a chemical solution such as sulfuric acid is used for wet cleaning to remove the residual photoresist and the polymer generated during the dry ashing process. After the sulfuric acid cleaning, deionized water is used to clean the residual sulfuric acid.

[0041] Then execute step S3, such as Figure 1 and Figure 5 As shown, a photoresist layer 5 is formed for the second time, and the photoresist layer 5 covers the surface of the silicon nitride layer 3 in the SONOS region, as shown in FIG. Figure 6 As shown, the silicon nitride layer 3 in the select gate region and the peripheral logic region is removed by etching.

[0042] The step of forming the photoresist layer 5 for the second time includes coating and developing the photoresist. As a preferred solution, an anti-reflective coating (not shown) is also formed between the photoresist layer 5 and the silicon nitride layer 3 in the SONOS region. Through the coating and developing steps, the select gate region and the peripheral logic region are opened, and then the silicon nitride layer 3 in the select gate region and the peripheral logic region is removed by dry etching to expose the bottom oxide layer 2.

[0043] Then execute step S4, such as Figure 1 and Figure 7 As shown, a wet etching process is used to remove the oxide layer 2 in the select gate region and the peripheral logic region, and the etching amount of the chemical solution used in the wet etching process is less than the reference etching amount.

[0044] Since sulfuric acid and other chemical solutions are used to remove the residual photoresist and polymer in step 2), even if deionized water is used to perform a sulfuric acid cleaning and removal step afterwards, the sulfuric acid cannot be completely cleaned off. A small amount of residual sulfuric acid will affect the secondary photoresist layer, resulting in poor adhesion between the photoresist layer and the underlying silicon nitride layer. When performing the wet etching process of this step, solution side drilling is likely to occur on both sides of the photoresist coverage area, resulting in film damage and failure.

[0045] Therefore, the present invention needs to adjust the etching amount of the chemical solution used in the wet etching process. Specifically, the etching amount of the chemical solution is reduced relative to the baseline etching amount. It should be noted that the baseline etching amount is the data set by the standard process technology in the existing industry. The etching amount of the chemical solution used in the present invention is less than the baseline etching amount. While ensuring the complete removal of the oxide layer 2 in the select gate area and the peripheral logic area, the problem of film damage and failure due to side drilling is minimized. In this embodiment, the etching amount is reduced by 10% relative to the baseline etching amount, but it is not limited to this in other embodiments.

[0046] Preferably, chemical solutions with relatively high etching selectivity of silicon nitride and silicon oxide may be used. In this embodiment, BOE is taken as an example, but it is not limited to this in other embodiments.

[0047] Then execute step S5, such as Figure 1 and Figure 8 As shown, the photoresist layer 5 formed for the second time is removed, and a pre-cleaning is performed, wherein the cleaning amount of the chemical solution used in the pre-cleaning is greater than the reference cleaning amount.

[0048] The pre-cleaning step is to remove the chemical oxide layer and natural oxide layer generated on the surface of the structure, in preparation for growing the gate oxide layer in the select gate region and the peripheral logic region. Preferably, the chemical solution used in the pre-cleaning is HF or the like.

[0049] The cleaning amount of the pre-cleaning of the present invention needs to be adjusted in combination with the reduction in the etching amount of the chemical solution in step 4). Specifically, the cleaning amount of the chemical solution is increased relative to the reference cleaning amount. It should be noted that the reference cleaning amount is the data set by the standard process technology in the existing industry. The cleaning amount of the chemical solution used in the present invention is less than the reference cleaning amount, which ensures that the step height of the select gate area and the peripheral logic area is consistent with the step height under the reference process while ensuring that the chemical oxide layer and the natural oxide layer are removed cleanly.

[0050] As one implementation manner, the difference between the cleaning amount and the reference cleaning amount in this step is equal to the difference between the reference etching amount and the etching amount in step 4). That is, the increase in the cleaning amount is equal to the decrease in the etching amount.

[0051] In this embodiment, the cleaning amount is increased by 30% relative to the reference cleaning amount, but this is not limited to this in other embodiments.

[0052] Finally, step S6 is executed. Figure 1 and Fig. 9 As shown, a gate oxide layer 6 is grown in the select gate region and the peripheral logic region, and a top blocking oxide layer 7 is formed on the surface of the silicon nitride layer 3 in the SONOS region.

[0053] An ISSG process is adopted to grow a gate oxide layer 6 in the select gate region and the peripheral logic region and to oxidize the silicon nitride layer 3 in the SONOS region to form a top blocking oxide layer 7 of ONO.

[0054] In summary, the present invention provides a SONOS memory ONO photolithography rework process integration method, characterized in that the method at least comprises: firstly providing a wafer to be photolithography reworked, the wafer comprising a semiconductor substrate 1 having a SONOS region, a select gate region and a peripheral logic region, an oxide layer 2 and a silicon nitride layer 3 sequentially formed on the surface of the semiconductor substrate 1, and a photoresist layer 4 to be stripped located on the surface of the silicon nitride layer 3 in the SONOS region; then using a dry ashing process to remove most of the photoresist layer 4, then using a wet process to remove the remaining photoresist layer 4, and finally using deionized water to wash and remove the residual chemical solution; then secondary forming A photoresist layer 5 is formed, the photoresist layer 5 covers the surface of the silicon nitride layer 3 in the SONOS area, and the silicon nitride layer 3 in the select gate area and the peripheral logic area is etched and removed; then a wet etching process is used to remove the oxide layer 2 in the select gate area and the peripheral logic area, and the etching amount of the chemical solution used in the wet etching process is less than the reference etching amount; then the photoresist layer 5 formed for the second time is removed, and pre-cleaning is performed, and the cleaning amount of the chemical solution used in the pre-cleaning is greater than the reference cleaning amount; finally, a gate oxide layer 6 is grown in the select gate area and the peripheral logic area, and a top blocking oxide layer 7 is formed on the surface of the silicon nitride layer in the SONOS area. For a SONOS non-volatile memory, the present invention provides a new stripping rework process flow of an ONO photolithography process, which reduces the process problem of low-quality in special areas of a reworked wafer due to damage to the ONO film layer caused by side drilling of a chemical solution during the ONO wet etching process by adjusting the ONO wet etching amount and the gate oxide layer pre-cleaning amount, and reliability is guaranteed. The rework process is stable and controllable, and is suitable for mass production.

[0055] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0056] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A SONOS memory ONO lithography rework process integration method, characterized in that: The method at least comprises: 1) providing a wafer to be reworked by photolithography, the wafer comprising a semiconductor substrate having a SONOS region, a select gate region and a peripheral logic region, an oxide layer and a silicon nitride layer sequentially formed on a surface of the semiconductor substrate, and a photoresist layer to be stripped on a surface of the silicon nitride layer in the SONOS region; 2) removing most of the photoresist layer by a dry ashing process, then removing the remaining photoresist layer by a wet process, and finally washing with deionized water to remove the residual chemical solution; 3) forming a photoresist layer for a second time, wherein the photoresist layer covers the surface of the silicon nitride layer in the SONOS region, and etching away the silicon nitride layer in the select gate region and the peripheral logic region; 4) using a wet etching process to remove the oxide layer in the select gate region and the peripheral logic region, wherein the etching amount of the chemical solution used in the wet etching process is less than a reference etching amount; 5) removing the photoresist layer formed for the second time and performing pre-cleaning, wherein the cleaning amount of the chemical solution used in the pre-cleaning is greater than the reference cleaning amount; 6) growing a gate oxide layer in the select gate region and the peripheral logic region, and forming a top blocking oxide layer on the surface of the silicon nitride layer in the SONOS region.

2. The SONOS memory ONO lithography rework process integration method according to claim 1, characterized in that: In step 2), the chemical solution used in the wet process is sulfuric acid.

3. The SONOS memory ONO lithography rework process integration method according to claim 1, characterized in that: In step 4), the chemical solution used in the wet etching process is BOE.

4. The SONOS memory ONO lithography rework process integration method according to claim 1, characterized in that: In step 5), the chemical solution used for the pre-cleaning is HF.

5. The SONOS memory ONO lithography rework process integration method according to claim 1, characterized in that: An anti-reflection coating is also formed between the photoresist layer and the silicon nitride layer in the SONOS region.

6. The SONOS memory ONO lithography rework process integration method according to claim 1, characterized in that: The difference between the cleaning amount and the reference cleaning amount in step 5) is equal to the difference between the reference etching amount and the etching amount in step 4).

7. The SONOS memory ONO lithography rework process integration method according to claim 1, characterized in that: In step 3), the step of secondary forming the photoresist layer includes coating and developing steps.

8. The SONOS memory ONO lithography rework process integration method according to claim 1, characterized in that: In step 3), dry etching is used to remove the silicon nitride layer in the select gate area and the peripheral logic area.

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