Input common-mode compensation circuit, pipeline analog-to-digital converter and input common-mode compensation method

Abstract

The application provides an input common mode compensation circuit, a pipeline analog-to-digital converter and an input common mode compensation method, the input common mode compensation circuit comprises an energy storage module, a switching selection module and a feedback compensation module, in the reset stage of a residual amplifier, the energy storage module is charged under the action of a reset voltage, in the working stage of the residual amplifier, the energy storage module is feedback compensated through the feedback compensation module, through one-time charging in the reset stage and two-time compensation charging in the working stage, the common mode value of the input signal of the residual amplifier in the working stage can be compensated and adjusted, the input common mode attenuation phenomenon of the residual amplifier in the working state caused by the parasitic capacitance of the reset switch can be effectively inhibited without affecting the normal working of the residual amplifier, the stability of the common mode value of the residual amplifier is ensured, and then the performance stability of the pipeline analog-to-digital converter is ensured.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an input common-mode compensation circuit, a pipelined analog-to-digital converter, and an input common-mode compensation method. Background Technology

[0002] The residual amplifier in a high-speed pipelined analog-to-digital converter (ADC) typically employs a fully differential switched-capacitor amplifier structure. It generates the corresponding input and output signals by redistributing charge across the capacitors through a switching mechanism. This method inevitably introduces some deviation in signal generation due to parasitic capacitance. Particularly at the input of the residual amplifier, the parasitic capacitance on the reset switch causes attenuation of the common-mode signal during operation. This attenuation leads to a deviation of the residual amplifier's quiescent operating point from the reset value, resulting in deterioration of output swing, linearity, and other performance characteristics, ultimately worsening the performance of the pipelined ADC.

[0003] Therefore, there is an urgent need for a common-mode compensation technology for the input of the residual amplifier in a pipelined analog-to-digital converter. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an input common-mode compensation scheme for the residual amplifier in a pipelined analog-to-digital converter, so as to compensate for the common-mode attenuation caused by parasitic capacitance, so that the input common-mode value of the residual amplifier in the working state is as close as possible to the reset value without excessive attenuation, thereby preventing the performance degradation of the residual amplifier caused by common-mode attenuation.

[0005] To achieve the above and other related objectives, the technical solution provided by this invention is as follows.

[0006] An input common-mode compensation circuit is used to compensate for the common-mode value of the input signal of the residual amplifier in a pipelined analog-to-digital converter, comprising:

[0007] An energy storage module, one end of which is connected to the input terminal of the residual amplifier;

[0008] The switching selection module has its input terminal connected to the other end of the energy storage module, and its first output terminal grounded.

[0009] The feedback compensation module has its first input terminal connected to the end where the energy storage module is connected to the residual amplifier, its second input terminal connected to the reset voltage of the residual amplifier, and its output terminal connected to the second output terminal of the switching selection module.

[0010] In the reset stage of the residual amplifier, the input end of the switch selection module is connected with the first output end of the switch selection module, and the energy storage module is charged under the action of the reset voltage; in the working stage of the residual amplifier, the input end of the switch selection module is connected with the second output end of the switch selection module, and the energy storage module is feedback compensated through the feedback compensation module, so as to compensate and adjust the common-mode value of the input signal of the residual amplifier.

[0011] Optionally, the energy storage module comprises a first capacitor and a second capacitor, one end of the first capacitor is connected with the non-inverting input end of the residual amplifier, and one end of the second capacitor is connected with the inverting input end of the residual amplifier.

[0012] Optionally, the switch selection module comprises a first switch unit and a second switch unit; the first switch unit comprises a first switch and a second switch, the input end of the first switch is connected with the other end of the first capacitor, the output end of the first switch is connected with the ground, the input end of the second switch is connected with the other end of the second capacitor, and the output end of the second switch is connected with the ground; the second switch unit comprises a third switch and a fourth switch, the input end of the third switch is connected with the other end of the first capacitor, and the input end of the fourth switch is connected with the other end of the second capacitor.

[0013] Optionally, the feedback compensation module comprises a high-slew-rate amplifier, a first resistor and a second resistor, the non-inverting input end of the high-slew-rate amplifier is connected with the non-inverting input end of the residual amplifier through the first resistor in series connection, the non-inverting input end of the high-slew-rate amplifier is also connected with the inverting input end of the residual amplifier through the second resistor in series connection, the non-inverting input end of the high-slew-rate amplifier is connected with the reset voltage, and the output end of the high-slew-rate amplifier is connected with the output end of the third switch and the output end of the fourth switch respectively.

[0014] Optionally, in the reset stage of the residual amplifier, the first switch and the second switch are both closed, the third switch and the fourth switch are both disconnected, the first switch unit is connected, the second switch unit is disconnected, and the first capacitor and the second capacitor are charged under the action of the reset voltage respectively; in the working stage of the residual amplifier, the first switch and the second switch are both disconnected, the third switch and the fourth switch are both closed, the first switch unit is disconnected, the second switch unit is connected, and the common-mode value of the input signal of the residual amplifier is compensated and adjusted through the high-slew-rate amplifier.

[0015] Optionally, the capacitance value of the first capacitor is equal to the capacitance value of the second capacitor, and the resistance value of the first resistor is equal to the resistance value of the second resistor.

[0016] A pipeline analog-to-digital converter comprising the input common-mode compensation circuit according to any one of the preceding claims, wherein the input common-mode compensation circuit is connected to an input terminal of a residual amplifier in the pipeline analog-to-digital converter, and the input common-mode compensation circuit compensates and adjusts a common-mode value of an input signal of the residual amplifier.

[0017] An input common-mode compensation method for compensating and adjusting a common-mode value of an input signal of a residual amplifier in a pipeline analog-to-digital converter, comprising:

[0018] The input common-mode compensation circuit according to any one of the preceding claims is provided.

[0019] In a reset phase of the residual amplifier, the energy storage module is charged by a reset voltage of the input terminal of the residual amplifier.

[0020] In an operation phase of the residual amplifier, the energy storage module is feedback compensated by the feedback compensation module, so as to compensate and adjust the common-mode value of the input signal of the residual amplifier.

[0021] As described above, the input common-mode compensation circuit, the pipeline analog-to-digital converter and the input common-mode compensation method provided by the present application have at least the following beneficial effects:

[0022] The entire input common-mode compensation circuit is based on the structural design of "energy storage module + switching selection module + feedback compensation module". In the reset phase of the residual amplifier, the energy storage module is charged under the action of the reset voltage. In the operation phase of the residual amplifier, the energy storage module is feedback compensated by the feedback compensation module, so as to compensate and adjust the common-mode value of the input signal of the residual amplifier. Without affecting the normal operation of the residual amplifier, the input common-mode attenuation phenomenon of the residual amplifier in the working state caused by the parasitic capacitance of the reset switch can be effectively suppressed, the stability of the common-mode value of the residual amplifier is ensured, and the performance stability of the pipeline analog-to-digital converter is ensured. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 A circuit structure diagram of a residual amplifier in a high-speed pipeline analog-to-digital converter is shown.

[0024] Figure 2 A circuit diagram of an input common-mode compensation circuit in the present application is shown.

[0025] Figure 3 A simulation result diagram of a common-mode value of an input signal of a residual amplifier in a high-speed pipeline analog-to-digital converter without input common-mode compensation is shown.

[0026] Figure 4 A simulation result diagram of a common-mode value of an input signal of a residual amplifier in a high-speed pipeline analog-to-digital converter with input common-mode compensation is shown. Detailed Implementation

[0027] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] Please see Figures 1 to 4 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0029] The overall structure of the residual amplifier in a traditional high-speed pipelined analog-to-digital converter is as follows: Figure 1 As shown, it mainly consists of switches SWi1~SWi6, SW7~SW10, capacitors Cf1~Cf2, Ci1~Ci2, and residual amplifier AMP1. In order to achieve subtraction amplification, it uses N parallel sampling units, where N is an even number greater than or equal to 2, such as 4, 6, 8, etc. The specific number of N is related to the multiple of the residual amplifier. The i-th sampling unit includes switches SWi1~SWi6 and capacitors Ci1~Ci2, where i is 1~N.

[0030] In detail, such as Figure 1As shown, in the ith sampling unit, the high reference voltage VREFH is connected to one end of Cil through the series switch SWil, the low reference voltage VREFL is connected to one end of Cil through the series switch SWi2, the low reference voltage VREFL is connected to one end of C12 through the series switch SWi3, the high reference voltage VREFH is connected to one end of C12 through the series switch SWi4, the positive input signal VIP0 is connected to one end of the capacitor Cil through the series switch SWi5, the negative input signal VIN0 is connected to one end of the capacitor C12 through the series switch SWi6, the other end of the capacitor Cil is connected to the non-inverting input terminal of the residual amplifier AMP1, that is, the signal at the other end of the capacitor Cil is the non-inverting input terminal signal VIP of the residual amplifier AMP1, the capacitor Cil is also connected to the reset voltage VRST through the series switches SW7 and SW9, the other end of the capacitor C12 is connected to the inverting input terminal of the residual amplifier AMP1, that is, the signal at the other end of the capacitor C12 is the inverting input terminal signal VIN of the residual amplifier AMP1, and the capacitor C12 is also connected to the common terminal of the switches SW7 and SW9 through the series switch SW8.

[0031] In detail, as shown in Figure 1 , one end of the capacitor Cfl is connected to the non-inverting input terminal of the residual amplifier AMP1, the other end of the capacitor Cfl is connected to the inverting output terminal of the residual amplifier AMP1, the inverting output terminal of the residual amplifier AMP1 outputs a signal VON, one end of the capacitor Cf2 is connected to the inverting input terminal of the residual amplifier AMP1, the other end of the capacitor Cf2 is connected to the non-inverting output terminal of the residual amplifier AMP1, and the non-inverting output terminal of the residual amplifier AMP1 outputs a signal VOP. At the same time, the non-inverting output terminal of the residual amplifier AMP1 and the inverting output terminal of the residual amplifier AMP1 are connected in series through the switch SW10.

[0032] In more detail, as shown in Figure 1 , the working principle of the residual amplifier in the conventional high-speed pipeline type analog-to-digital converter is as follows:

[0033] 1) In the reset (sampling) phase, among the N parallel arranged sampling units, the switches SWi5 and SWi6 are turned on, the switches SWil, SWi2, SWi3 and SWi4 are turned off, and the switches SW7, SW8, SW9 and SW10 are turned on, and the residual amplifier AMP1 is in the reset state (i.e. not working). At this time, the common mode value of the signals VOP and VON is determined by the residual amplifier AMP1, which is VCMOUT. In order to facilitate understanding, it is assumed that the value of the input signal is the common mode value of the double-ended input signal (i.e. VIP0 = VIN0), and the charge conservation expression on the non-inverting input terminal of the residual amplifier AMP1 is as follows (the inverting input terminal of the residual amplifier AMP1 is analyzed in the same way)

[0034] (VIP0-VRST)CN1+(VCMOUT-VRST)Cf1=Q;

[0035] Wherein, assuming that the capacitance of N sampling units are equal, all are C0, that is, C11=C12=…=Ci1=Ci2=…=CN1=CN2=C0, then CN1=N*C0;

[0036] 2), in the working phase, the switches SWi5, SWi6 of the N parallel sampling units are disconnected, and each group of switches SWi1, SWi2, SWi3, SWi4 is reasonably turned on and off according to the results of the comparator. In the case that the value of the input signal is the common mode value of the double-ended input signal, the switches SWi1, SWi2, SWi3, SWi4 of N / 2 sampling units in the N parallel sampling units are disconnected, the switches SWi1, SWi2, SWi3, SWi4 of N / 2 sampling units are turned on, the switches SW7, SW8, SW9, SW10 are disconnected, and the residual amplifier AMP1 is in working state. Assuming that the signal at the non-inverting input terminal of the residual amplifier AMP1 is Vx, at this time, the charge conservation expression at the non-inverting input terminal of the residual amplifier AMP1 is as follows

[0037] (VREFH-Vx)CN1 / 2+(VREFL-Vx)CN1 / 2+(VCMOUT-Vx)Cf1=Q;

[0038] 3), according to the law of conservation of charge, the charge Q at the non-inverting input terminal of the residual amplifier AMP1 is equal in the sampling phase and the working phase, so the non-inverting input terminal voltage Vx of the residual amplifier AMP1 in the working state can be solved

[0039] Vx=[(CN1+Cf1)*VRST+CN1*(VREFH+VREFL) / 2-CN1*VIP0] / (CN1+Cf1);

[0040] Generally, the common mode value of the two reference voltages (i.e. high reference voltage VREFH and low reference voltage VREFL) during sampling, that is, (VREFH+VREFL) / 2, is the same as the common mode value of the input signal, so it is equal to VIP0 here, so finally

[0041] Vx=VRST;

[0042] Therefore, under normal circumstances, the common mode value of the input signal of the residual amplifier AMP1 should be equal to the reset voltage VRST.

[0043] However, due to the parasitic capacitance of the switches SW7, SW8, SW9 and the parasitic capacitance of the layout, such as Figure 1The parasitic capacitor Cp1 is connected to the non-inverting input terminal of the residual amplifier AMP1 at one end, and connected to the reset voltage VRST at the other end, and the parasitic capacitor Cp2 is connected to the inverting input terminal of the residual amplifier AMP1 at one end, and connected to the reset voltage VRST at the other end. In the working stage, the common-mode signal of the input terminal of the residual amplifier AMP1 will be attenuated due to the charge distribution on the parasitic capacitors Cp1-Cp2, and the expression is as follows: for the non-inverting input terminal of the residual amplifier AMP1 containing the parasitic capacitor Cp1 (for the inverting input terminal of the residual amplifier AMP1, the same analysis)

[0044] Vx = [(CN1+Cf1)*VRST+CN1*(VREFH+VREFL) / 2-CN1*VIP0] / (CN1+Cf1+Cp1);

[0045] Therefore, according to the above formula, when the parasitic capacitor Cp1 caused by the parasitic of the switch MOS tube and the layout parasitic cannot be ignored, in the working stage, the signal Vx of the non-inverting input terminal of the residual amplifier AMP1 will be attenuated, and then the common-mode value of the input signal of the residual amplifier AMP1 will be attenuated, as mentioned in the background in the foregoing, the attenuation of the common-mode value of the input signal will cause the static working point of the residual amplifier to deviate from the reset value, causing the deterioration of the output swing, linearity and other performances, and finally the performance of the pipeline analog-to-digital converter will be poor.

[0046] Based on this, the present application provides an input common-mode compensation technical scheme: in the reset stage of the residual amplifier, the energy storage module is charged for the first time by the reset voltage, in the working stage of the residual amplifier, the energy storage module is feedback compensated by the feedback compensation module to realize the second charging, so as to stabilize the common-mode value of the input signal of the residual amplifier in the working stage near the reset voltage, and suppress the input common-mode attenuation phenomenon of the residual amplifier in the working state caused by the parasitic capacitor of the reset switch.

[0047] First, as Figure 2 The present application provides an input common-mode compensation circuit for compensating the common-mode value of the input signal of the residual amplifier in the pipeline analog-to-digital converter, which comprises:

[0048] An energy storage module, one end of which is connected to the input terminal of the residual amplifier AMP1;

[0049] A switching selection module, the other end of the energy storage module is connected to the input terminal of the switching selection module, and the first output terminal of the switching selection module is connected to the ground AGND;

[0050] a feedback compensation module, a first input end of which is connected to one end of the energy storage module and the residual amplifier AMP1, a second input end of which is connected to the reset voltage VRST of the residual amplifier AMP1, and an output end of which is connected to the second output end of the switch selection module;

[0051] In the reset stage of the residual amplifier, the input end of the switch selection module is connected to the first output end of the switch selection module, and the energy storage module is charged under the action of the reset voltage VRST; in the working stage of the residual amplifier, the input end of the switch selection module is connected to the second output end of the switch selection module, and the energy storage module is feedback compensated by the feedback compensation module, so as to compensate and adjust the common-mode value of the input signal of the residual amplifier.

[0052] In detail, as shown in Figure 2 , the energy storage module includes a first capacitor Cc1 and a second capacitor Cc2, one end of the first capacitor Cc1 is connected to the non-inverting input end of the residual amplifier AMP1, and one end of the second capacitor Cc2 is connected to the inverting input end of the residual amplifier AMP1.

[0053] In detail, as shown in Figure 2 , the switch selection module includes a first switch unit and a second switch unit; the first switch unit includes a first switch SW11 and a second switch SW12, the input end of the first switch SW11 is connected to the other end of the first capacitor Cc1, the output end of the first switch SW11 is connected to the ground AGND, the input end of the second switch SW12 is connected to the other end of the second capacitor Cc2, and the output end of the second switch SW12 is connected to the ground AGND; the second switch unit includes a third switch SW13 and a fourth switch SW14, the input end of the third switch SW13 is connected to the other end of the first capacitor Cc1, and the input end of the fourth switch SW14 is connected to the other end of the second capacitor Cc2.

[0054] In detail, as shown in Figure 2 , the feedback compensation module includes a high-slew-rate amplifier AMP2, a first resistor R1 and a second resistor R2, the inverting input end of the high-slew-rate amplifier AMP2 is connected to the non-inverting input end of the residual amplifier AMP1 through the first resistor R1 in series, the inverting input end of the high-slew-rate amplifier AMP2 is also connected to the inverting input end of the residual amplifier AMP1 through the second resistor R2 in series, the non-inverting input end of the high-slew-rate amplifier AMP2 is connected to the reset voltage VRST, and the output end of the high-slew-rate amplifier AMP2 is connected to the output end of the third switch SW13 and the output end of the fourth switch SW14 respectively.

[0055] In more detail, as shown in Figure 2As shown, the input end of the first switch unit and the input end of the second switch unit are connected together, which is the input end of the whole switch selection module, the output end of the first switch unit is the first output end of the switch selection module, and the output end of the second switch unit is the second output end of the switch selection module; the inverting input end of the high-slew-rate amplifier AMP2 is the first input end of the feedback compensation module, the non-inverting input end of the high-slew-rate amplifier AMP2 is the second input end of the feedback compensation module, and the output end of the high-slew-rate amplifier AMP2 is the output end of the feedback compensation module.

[0056] In an optional embodiment of the present application, in order to balance and match the impedance of the non-inverting input end of the residual amplifier AMP1 and the impedance of the inverting input end of the residual amplifier AMP1, the capacitance value of the first capacitor Cc1 is equal to the capacitance value of the second capacitor Cc2, and the resistance value of the first resistor R1 is equal to the resistance value of the second resistor R2.

[0057] In more detail, as shown in the figure, Figure 2 in the reset phase of the residual amplifier AMP1, the first switch SW11 and the second switch SW12 are both closed, the third switch SW13 and the fourth switch SW14 are both open, the first switch unit is turned on, the second switch unit is turned off, and the first capacitor Cc1 and the second capacitor Cc2 are charged under the action of the reset voltage VRST; in the working phase of the residual amplifier AMP1, the first switch SW11 and the second switch SW12 are both open, the third switch SW13 and the fourth switch SW14 are both closed, the first switch unit is turned off, the second switch unit is turned on, and the common-mode value of the input signal of the residual amplifier AMP1 is compensated and adjusted by the high-slew-rate amplifier AMP2.

[0058] In more detail, as shown in the figure, Figure 2 the working principle of the input common-mode compensation circuit is as follows:

[0059] 1) in the reset phase of the residual amplifier AMP1, the first switch SW11 and the second switch SW12 are both closed, the third switch SW13 and the fourth switch SW14 are both open, the first switch unit is turned on, the second switch unit is turned off, and the first capacitor Cc1 and the second capacitor Cc2 are charged under the action of the reset voltage VRST at the input end of the residual amplifier AMP1, at this time, the charge conservation expression on the non-inverting input end of the residual amplifier AMP1 can be listed as follows (the same for the inverting input end of the residual amplifier AMP1)

[0060] (VIP0-VRST)CN1+(VCMOUT-VRST)Cf1-VRST*Cc1=Q;

[0061] 2), in the working phase of the residual amplifier AMP1, the first switch SW11 and the second switch SW12 are both disconnected, the third switch SW13 and the fourth switch SW14 are both closed, the first switch unit is turned off, the second switch unit is turned on, and the high-slew-rate amplifier AMP2 starts to work. Due to the existence of the parasitic capacitances Cp1-Cp2, the signals at the non-inverting input terminal and the inverting input terminal of the residual amplifier AMP1 are both pulled low, the common-mode value of the input signals loaded on the inverting input terminal of the high-slew-rate amplifier AMP2 is also pulled low, and is lower than the reset voltage VRST. Therefore, the output voltage VAMP of the high-slew-rate amplifier AMP2 changes from zero to a positive value. Since the high-slew-rate amplifier AMP2 is a high-slew-rate amplifier, it can adjust the value of the output voltage VAMP in a very short time. At the same time, one end of the first capacitor Cc1 (and the second capacitor Cc2) originally connected to the ground is connected to the voltage VAMP with a positive value, and the voltage at one end of the first capacitor Cc1 (and the second capacitor Cc2) connected to the residual amplifier AMP1 is lifted, so that the common-mode value of the input signals loaded on the inverting input terminal of the high-slew-rate amplifier AMP2 is also lifted by a certain amplitude. However, due to the pull-down of the parasitic capacitance Cp1, the common-mode value is still lower than the reset voltage VRST, and the positive value of the output voltage VAMP of the high-slew-rate amplifier AMP2 becomes smaller. The voltage at one end of the first capacitor Cc1 (and the second capacitor Cc2) connected to the residual amplifier AMP1 is lifted by a small amplitude, and the cycle is repeated. Under the action of the high-slew-rate amplifier AMP2, the voltage at one end of the first capacitor Cc1 (and the second capacitor Cc2) connected to the residual amplifier AMP1 is lifted by a small amplitude (the lifting amplitude becomes smaller and smaller) for many times in a certain time, and finally the common-mode value of the input signals loaded on the inverting input terminal of the high-slew-rate amplifier AMP2 tends to the reset voltage VRST, achieving the effect of suppressing attenuation. That is, the common-mode value of the input signals of the residual amplifier AMP1 is compensated and adjusted by the high-slew-rate amplifier AMP2. Considering the parasitic capacitance Cp1, the charge conservation expression on the non-inverting input terminal of the residual amplifier AMP1 can be listed as follows (the same for the inverting input terminal of the residual amplifier AMP1)

[0062] (VREFH-Vx)CN1 / 2+(VREFL-Vx)CN1 / 2+(VCMOUT-Vx)Cf1+(VAMP-Vx)Cc1-VxCp1=Q;

[0063] Due to the charge conservation, Vx can be solved as

[0064] Vx=[(CN1+Cf1+Cc1)*VRST+VAMP*Cc1] / (CN1+Cf1+Cc1+Cp1);

[0065] It can be seen that after the first capacitor Cc1 is added, the value of Vx can be compensated to a certain extent, so that it will not decay very sharply.

[0066] It is important to emphasize that in the above-mentioned input common-mode compensation circuit, during the reset phase, the energy storage module is charged for the first time by the reset voltage VRST, storing a portion of the charge to ensure partial compensation at the beginning of the working phase, so that the parasitic capacitance Cp1 does not pull down the common-mode value of the input signal too much. During the working phase, the energy storage module is compensated for the second time by the high slew rate amplifier AMP2 and the external reset voltage VRST, realizing the second charging and gradually pulling the common-mode value of the input signal towards the reset voltage VRST.

[0067] In an optional embodiment of the present invention, to further verify the advantages of the above-described input common-mode compensation circuit, a high-speed pipelined analog-to-digital converter (MDAC) is constructed using the above-described input common-mode compensation circuit in a 28nm CMOS process. The MDAC operates at 1GHz (i.e., the total sampling and operating time is 1 nanosecond), the closed-loop gain of the residual amplifier AMP1 is 4x, the number of sampling units is 8, and the type of switch is related to the signal it is connected to. The switch connected to the high reference voltage VREFH is a PMOS switch, the switch connected to the low reference voltage VREFL is an NMOS switch, the switch connected to ground is an NMOS switch, and the switch connected to the output voltage of the residual amplifier AMP1 is a transmission gate switch. The high slew rate amplifier AMP2 adopts a common OTA operational amplifier structure, which requires a relatively large current to meet the slew rate requirement, so that the output voltage VAMP reaches a suitable value within one clock cycle. The above-described input common-mode compensation circuit is constructed and simulated, with external input signals (VIP0 and VIN0) as common-mode signals and a reset voltage VRST of 800mV.

[0068] To compare with the input common-mode compensation circuit of this invention, a case without the input common-mode compensation circuit of this invention was added. Simulation results without the input common-mode compensation circuit of this invention are as follows: Figure 3 As shown, during the reset phase, the input common-mode value of the residual amplifier AMP1 is 800mV (799.97mV). During the operating phase, due to the parasitic capacitance of the reset switch, the input common-mode value attenuates to 760mV, a decrease of 40mV. Simulation results with the input common-mode compensation circuit of this invention added are shown below. Figure 4 As shown, the attenuation value is only 8mV, which fully demonstrates the suppressive effect of the input common-mode compensation circuit of this invention on the input common-mode attenuation caused by parasitic capacitance. At the same time, this input common-mode compensation circuit does not affect the normal amplification function of the residual amplifier AMP1 for differential-mode signals.

[0069] Secondly, the application further provides a pipeline analog-to-digital converter comprising the input common-mode compensation circuit, the input common-mode compensation circuit is connected with an input end of a residual amplifier in the pipeline analog-to-digital converter, and the input common-mode compensation circuit compensates and adjusts a common-mode value of a residual amplifier input signal, so as to suppress an input common-mode attenuation phenomenon of the residual amplifier in a working state caused by a parasitic capacitance of a reset switch, ensure the stability of the common-mode value of the residual amplifier, and further ensure the performance stability of the pipeline analog-to-digital converter.

[0070] Finally, the application further provides an input common-mode compensation method for compensating and adjusting the common-mode value of the residual amplifier input signal in the pipeline analog-to-digital converter, and the method comprises the following steps:

[0071] S1, providing the input common-mode compensation circuit;

[0072] S2, charging the energy storage module by using a reset voltage of the input end of the residual amplifier in a reset stage of the residual amplifier;

[0073] S3, performing feedback compensation on the energy storage module by using the feedback compensation module in a working stage of the residual amplifier, and further compensating and adjusting the common-mode value of the residual amplifier input signal.

[0074] In detail, in steps S2-S3, through the first charging of the energy storage module and the second compensation charging of the energy storage module by the feedback compensation module, the common-mode value of the residual amplifier input signal can be pulled up to be close to the reset voltage in the working stage of the residual amplifier, and the common-mode attenuation of the residual amplifier input signal is effectively suppressed.

[0075] In summary, in the input common-mode compensation circuit, the pipeline analog-to-digital converter and the input common-mode compensation method provided by the application, the energy storage module is charged under the action of the reset voltage in the reset stage of the residual amplifier, the energy storage module is feedback compensated by the feedback compensation module in the working stage of the residual amplifier, the common-mode value of the residual amplifier input signal in the working stage is compensated and adjusted through the first charging in the reset stage and the second compensation charging in the working stage, the input common-mode attenuation phenomenon of the residual amplifier in the working state caused by the parasitic capacitance of the reset switch is effectively suppressed without affecting the normal working of the residual amplifier, the stability of the common-mode value of the residual amplifier is ensured, and the performance stability of the pipeline analog-to-digital converter is further ensured.

[0076] The above embodiments are only illustrative of the principles of the present application and its efficacy, and are not intended to limit the present application. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.

Claims

1. An input common-mode compensation circuit for compensating the common-mode value of the input signal of the residual amplifier in a pipelined analog-to-digital converter, characterized in that, include: An energy storage module, one end of which is connected to the input terminal of the residual amplifier; The switching selection module has its input terminal connected to the other end of the energy storage module, and its first output terminal grounded. The feedback compensation module has its first input terminal connected to the end where the energy storage module is connected to the residual amplifier, its second input terminal connected to the reset voltage of the residual amplifier, and its output terminal connected to the second output terminal of the switching selection module. During the reset phase of the residual amplifier, the input terminal of the switching selection module is connected to the first output terminal of the switching selection module, and the energy storage module is charged under the action of the reset voltage. During the working phase of the residual amplifier, the input terminal of the switching selection module is connected to the second output terminal of the switching selection module, and the energy storage module is compensated by the feedback compensation module, thereby compensating and adjusting the common mode value of the input signal of the residual amplifier.

2. The input common-mode compensation circuit according to claim 1, characterized in that, The energy storage module includes a first capacitor and a second capacitor. One end of the first capacitor is connected to the non-inverting input of the residual amplifier, and one end of the second capacitor is connected to the inverting input of the residual amplifier.

3. The input common-mode compensation circuit according to claim 2, characterized in that, The switching selection module includes a first switch unit and a second switch unit; the first switch unit includes a first switch and a second switch, the input terminal of the first switch is connected to the other end of the first capacitor, the output terminal of the first switch is grounded, the input terminal of the second switch is connected to the other end of the second capacitor, and the output terminal of the second switch is grounded; the second switch unit includes a third switch and a fourth switch, the input terminal of the third switch is connected to the other end of the first capacitor, and the input terminal of the fourth switch is connected to the other end of the second capacitor.

4. The input common-mode compensation circuit according to claim 3, characterized in that, The feedback compensation module includes a high slew rate amplifier, a first resistor, and a second resistor. The inverting input of the high slew rate amplifier is connected to the non-inverting input of the residual amplifier via the first resistor connected in series. The inverting input of the high slew rate amplifier is also connected to the inverting input of the residual amplifier via the second resistor connected in series. The non-inverting input of the high slew rate amplifier is connected to the reset voltage. The output of the high slew rate amplifier is connected to the output of the third switch and the output of the fourth switch, respectively.

5. The input common-mode compensation circuit according to claim 4, characterized in that, During the reset phase of the residual amplifier, both the first and second switches are closed, while both the third and fourth switches are open. The first switch unit is turned on, and the second switch unit is turned off. The first capacitor and the second capacitor are charged under the action of the reset voltage. During the operating phase of the residual amplifier, both the first and second switches are open, while both the third and fourth switches are closed. The first switch unit is turned off, and the second switch unit is turned on. The common-mode value of the input signal of the residual amplifier is compensated and adjusted by the high slew rate amplifier.

6. The input common-mode compensation circuit according to claim 4, characterized in that, The capacitance of the first capacitor is equal to the capacitance of the second capacitor, and the resistance of the first resistor is equal to the resistance of the second resistor.

7. A pipelined analog-to-digital converter, characterized in that, The system includes the input common-mode compensation circuit as described in any one of claims 1-6, wherein the input common-mode compensation circuit is connected to the input terminal of the residual amplifier in the pipelined analog-to-digital converter, and the input common-mode compensation circuit compensates and adjusts the common-mode value of the input signal of the residual amplifier.

8. An input common-mode compensation method for compensating and adjusting the common-mode value of the input signal of the residual amplifier in a pipelined analog-to-digital converter, characterized in that, include: Provide an input common-mode compensation circuit as described in any one of claims 1-6; During the reset phase of the residual amplifier, the energy storage module is charged using the reset voltage at the input terminal of the residual amplifier. During the operation of the residual amplifier, the feedback compensation module is used to perform feedback compensation on the energy storage module, thereby compensating and adjusting the common-mode value of the input signal of the residual amplifier.

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