IGBT chip, driving method thereof, and storage medium

Abstract

The present invention provides an IGBT chip and a driving method and storage medium thereof. The IGBT chip includes a cell, which is formed by splicing two first structures; the first structure includes an N-type substrate, a first gate and a second gate; a groove is provided on the upper surface of the N-type substrate, the first gate is a first gate 510 arranged on the N-type substrate, at least part of the second gate extends into the groove, and the distance between the second gate and the projection of the first gate on the upper surface of the N-type substrate is d, and the value range of d is 100 angstroms to 200 angstroms; a first active area is provided below the first gate, and a second active area is provided on the side of the groove away from the first gate; the first active area and the second active area are both provided on the N-type substrate; the first metal layer in the first active area of ​​each cell and the second metal layer in the second active area are in contact with each other to form the emitter of the IGBT chip; the N-type substrates of each cell are in contact with each other to form an integrated structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to an IGBT chip and a driving method thereof, and a storage medium. The IGBT chip is a bipolar device using dual independent channels of a plane and a groove. Background Art

[0002] In the past thirty years, my country's IGBT technology has developed rapidly, from simple planar gate to trench gate IGBT, and then to the existing trench plane, fine trench, and composite gate technologies, the chip structure is constantly optimized to achieve the best effect. CEsat -E off The trade-off relationship between them becomes the focus of the research, that is, optimizing the compromise between turn-off loss and conduction loss while reducing the on-state voltage drop of the device.

[0003] The IGBT with planar gate structure has simple manufacturing process and good voltage resistance performance, but because its channel region is on the surface, the channel density is limited, resulting in weak conductivity modulation effect and high on-state voltage drop. Figure 1 As shown, the planar gate structure IGBT mainly includes: P+ collector layer 101, N-type buffer layer 102, N-drift region 103, N well region 104, P well region 105, N+ doping region 106, planar gate 107, gate oxide layer 108 and metal layer 109. The trench gate structure can eliminate the JFET effect and reduce the on-state voltage drop, but the chip saturation current is too large and the short-circuit capability is poor. Figure 2 As shown, the IGBT with a trench gate structure includes a P+ collector layer 201, an N-type buffer layer 202, an N-drift region 203, a trench gate 204, a gate oxide layer 205, an N-well region 206, a P-well region 207, an N+ doped region 208, an isolation layer 209 and a metal layer 210; someone has also proposed an IGBT chip with a planar gate structure with a trench, such as Figure 3 The structure shown can combine the advantages of planar gate and trench gate, introduce trenches on the basis of planar gate, form carrier accumulation layers on the sides of the trenches, enhance the conductivity modulation effect, and reduce the on-state loss of the device without reducing the breakdown voltage. It mainly includes: P+ collector layer 301, N-type buffer layer 302, N-drift region 303, N well region 304, P well region 305, N+ doping region 306, trench gate 307, gate oxide layer 308 and metal layer 309. However, the introduction of the trench increases the capacitance between the gate and the emitter (the location of the metal layer is the emitter), increases the switching time, and increases the switching loss.

[0004] In order to achieve low loss, some new composite gate structures have been proposed in recent years. The single channel structure, such as that proposed in patents CN104659088A, CN207097831U and CN104051509B, changes multiple gate forms, and the trench side is used for carrier accumulation to reduce the conduction voltage drop, but there is only one channel.

[0005] The dual-channel single-gate structure, such as the composite gate chip proposed in patent CN108598160B, combines the advantages of the planar gate and the trench gate. Figure 3 The structure shown has a large gate-emitter capacitance and the switching time is several times longer than Figure 1 , Figure 2 Patent CN108428740B proposes an IGBT chip with a composite gate structure containing a virtual gate based on the structure of CN108598160B, introducing a virtual gate, optimizing the input and output capacitance of the composite gate, optimizing the change rate of the chip turn-on current, and reducing switching losses; however, the optimization effect of only one gate is limited, and multiple grooves are introduced, which greatly increases the complexity and cost of the process. Summary of the invention

[0006] The problem to be solved by the present invention is to provide an IGBT chip in view of the problem that the existing IGBT chip has a slow switching speed and a large switching loss.

[0007] In order to solve the above technical problems, the technical solution adopted by the present invention is: an IGBT chip, comprising a cell, wherein the cell is formed by splicing two symmetrically arranged first structures;

[0008] The first structure includes an N-type substrate, a first gate and a second gate arranged at intervals; the first gate and the second gate are separated by an oxide layer;

[0009] The upper surface of the N-type substrate is provided with a groove extending downward into the N-type substrate along the height direction of the N-type substrate, the first gate is a first gate arranged on the N-type substrate, at least a portion of the second gate extends into the groove, and a value range of a thickness d of an oxide layer between the first gate and the second gate is not less than 100 angstroms;

[0010] A first active region is disposed below the first gate, and a second active region is disposed on a side of the groove away from the first gate;

[0011] The first active region and the second active region are both arranged on an N-type substrate;

[0012] The first metal layer in the first active area and the second metal layer in the second active area of ​​each cell are in contact with each other to form an emitter of the IGBT chip; the N-type substrates of each cell are in contact with each other to form an integrated structure.

[0013] In the present invention, by leading out the first gate and the second gate arranged at intervals, two independent drivable gates are arranged on each first structure, forming dual independent channels in both vertical and horizontal directions, so that the chip can be driven by multiple voltages at the same time, greatly enhancing the voltage driving ability of the chip, reducing the switch delay increased by introducing the groove, improving the switching speed of the chip, and greatly reducing the switching loss. The two gate drive signals act simultaneously, which can reduce the switching loss of the device.

[0014] In the above technical solution, the first active region includes a first N+ doped region and a first metal layer which are adjacently arranged; the first metal layer is located on a side of the first N+ doped region away from the second gate;

[0015] The first active region further includes a first N-well region formed in an N-type substrate, a first P-well region located on the first N-well region, a first N+ doped region and a first metal layer located on the first P-well region, the first P-well region is arranged around the outside of the first N+ doped region and the first metal layer, and the first N-well region is arranged around the outside of the first P-well region;

[0016] The upper end surface of the first N+ doped region, the upper end surface of the first P well region, and the upper end surface of the first N well region are all arranged toward the first gate;

[0017] The second active region includes a second N+ doped region, a second P well region, and a second N well region arranged in sequence from top to bottom in the height direction of the N-type substrate, and also includes a second metal layer arranged adjacent to the second N+ doped region and located on the second P well region; the second metal layer is located on a side of the second N+ doped region away from the first gate;

[0018] The wall surface of the second N+ doped region, the wall surface of the second P-well region, and the wall surface of the second N-well region at least form a part or all of the wall surface of the groove away from the first gate;

[0019] In a cell, the second metal layer, second P-well region and second N-well region of the second active region of one first structure are in contact with the second metal layer, second P-well region and second N-well region of the second active region of another first structure respectively.

[0020] Through the above arrangement, an active region corresponding to the first gate is arranged below the first gate, and an active region corresponding to the second gate is arranged on a side of the groove away from the first gate.

[0021] In a preferred embodiment, the height position of the bottom surface of the second N-well region is higher than the height position of the bottom of the groove.

[0022] In the present invention, through the above arrangement, the depth of the N-well region does not exceed the depth of the trench, thereby avoiding the problem of premature breakdown.

[0023] In a preferred embodiment, the first direction is defined as the direction in which the two first structures are spliced ​​together to form a cell, and the projection size c1 of the upper end surface of the first P-well region in the first direction is equal to the wall height c2 of the second P-well region forming the wall of the groove away from the first gate.

[0024] In the present invention, through the above arrangement, the length c1 of the first gate as the planar gate (the length of the inversion layer formed after being turned on) is equal to the length c2 of the second gate as the channel gate (the length of the inversion layer formed after being turned on), thereby achieving a better conduction state, which is beneficial to reducing the conduction voltage drop.

[0025] In a preferred embodiment, the groove depth is 6um-8um.

[0026] The applicant found during research that the greater the groove depth, the smaller the on-state voltage drop of the IGBT chip, and the breakdown voltage first increases and then decreases. By setting the value range of the groove depth, not only can the on-state voltage drop of the IGBT chip be smaller and the breakdown voltage be larger, but also the processing difficulty caused by making the groove depth too deep can be avoided as much as possible.

[0027] In a preferred embodiment, a dimension w1 of the groove in the first direction ranges from 4um to 6um, a dimension wd of the second N-well region in the first direction ranges from 2um to 4um, and a dimension of the first structure in the first direction ranges from 20um to 22um.

[0028] In the prior art, the size of a half-cell of a chip with a planar gate structure in the first direction is mostly 20um-30um, and the groove width is basically in the range of 1-3um. Compared with the planar gate structure, the present application introduces a groove structure to achieve a smaller cell size, and the increase in the groove width also facilitates its depth processing.

[0029] The applicant found during the research that the larger the wd is, the larger the on-state voltage drop is and the smaller the breakdown voltage is. The larger the spacing wm between the first N-well region and the groove in the first direction (i.e., the size in the first direction) is, the larger the on-state voltage drop is and the smaller the breakdown voltage is. By setting a larger w1 value (groove width) and making the size of the cell in the first direction smaller, a smaller wd value can be set and the wm value can be as small as possible, so that a smaller on-state voltage drop and a larger breakdown voltage can be achieved. Moreover, by setting a larger w1 value, i.e., increasing the width of the groove, the range of the carrier accumulation layer can be enlarged, and the on-state voltage drop can also be reduced to a certain extent.

[0030] In the above technical solution, the first structure further includes a P+ collector layer and an N-type buffer layer, and the P+ collector layer, the N-type buffer layer and the N-type substrate are arranged in sequence from bottom to top in the height direction of the N-type substrate.

[0031] In the above technical solution, the thickness of the oxide layer between the second gate and the bottom of the groove is greater than the thickness of the oxide layer between the second gate and the side wall of the groove.

[0032] In the present invention, the risk of premature breakdown can be reduced through the above arrangement.

[0033] In the above technical solution, the thickness of the oxide layer between the second gate and the bottom of the groove is greater than the thickness of the oxide layer between the first gate and the N-type substrate.

[0034] In the present invention, since the bottom of the groove goes deep into the chip and is easier to be penetrated, the thickness relationship is set as above, thereby reducing the risk of breakdown.

[0035] The present invention also provides a driving method for the IGBT chip as described above, wherein a driving voltage is applied to both the first gate and the second gate, and the driving voltage applied to the first gate is independent of the driving voltage applied to the second gate.

[0036] Through the above arrangement, when the IGBT chip is turned on, a driving signal can be applied to both gates, thereby increasing the driving capability of the chip.

[0037] In the above technical solution:

[0038] When the IGBT chip switches from the off state to the on state, a conduction voltage is applied to the first gate and the second gate at the same time;

[0039] When the IGBT chip switches from the on state to the off state, a turn-off voltage is applied to the first gate and the second gate at the same time.

[0040] In the present invention, a driving voltage is applied to both the first gate and the second gate, and two gate driving signals act simultaneously, thereby increasing the driving capability of the chip.

[0041] In the above technical solution:

[0042] When the IGBT chip switches from the off state to the on state, the time when the on voltage is applied to the first gate is earlier than the time when the on voltage is applied to the second gate by a first preset time t1.

[0043] When the IGBT chip switches from the on state to the off state, the time when the off voltage is applied to the second gate is earlier than the time when the off voltage is applied to the first gate by a second preset time t2.

[0044] In the present invention, by adopting the above technical solution, when shutting down, since the gate-emitter capacitance at the second gate as the trench gate is large, the second gate is turned off first, and a conductive channel is turned off, carrier injection is reduced, and the carriers inside the chip are reduced, thereby accelerating the shutdown process of the device.

[0045] Preferably, 0<t1≤5us, 0<t2≤10us.

[0046] In the above technical solution:

[0047] When the IGBT chip switches from the off state to the on state, a conduction voltage is applied to the first gate and the second gate at the same time;

[0048] When the IGBT chip switches from the on state to the off state, the moment when the off voltage is applied to the second gate is earlier than the moment when the off voltage is applied to the first gate by a third preset time t3. Preferably, 0<t3≤10us.

[0049] In the present invention, by adopting the above technical solution, when the IGBT chip is turned on, two conductive channels are injected with carriers at the same time, thereby accelerating the turn-on speed; when the IGBT chip is turned off, the gate drive signal is different, and the second gate is turned off first, reducing the injection of carriers, thereby increasing the turn-off speed and reducing losses.

[0050] The present invention also provides a storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the driving method of the IGBT chip as described above are implemented.

[0051] Compared with the prior art, the present invention may have the following advantages:

[0052] 1) In the present invention, the on-state voltage is low and the on-state loss is low; a major problem in the design of IGBT chips with a folded composite gate structure, namely, the switching delay caused by the increase in gate capacitance, is solved.

[0053] 2) The first gate and the second gate are driven independently to form two independent channels, which greatly enhances the voltage driving capability of the chip, thereby greatly reducing the switching delay caused by the introduction of the groove and achieving fast switching. The two gate drive signals act at the same time, greatly reducing the switching loss of the device. Since the carrier effect inside the bipolar device is much greater than that of the unipolar device, this design is especially important for high-voltage and high-power bipolar devices.

[0054] 3) In the present invention, applying different driving signals to the gate electrode will not affect the chip itself, and multiple driving methods can be applied, one is simultaneous driving, the second is time-sharing driving, and the third is compound driving; all three driving methods can significantly reduce losses. For turn-off losses, the effects of time-sharing driving and compound driving are more obvious; and the total loss of the compound driving method is the smallest. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0056] Figure 1 It is a cross-sectional schematic diagram of a half cell of an IGBT chip with a planar gate structure in the prior art;

[0057] Figure 2 It is a cross-sectional schematic diagram of a half cell of an IGBT chip with a trench gate structure in the prior art;

[0058] Figure 3 It is a cross-sectional schematic diagram of a half cell of an IGBT chip with a planar gate structure having a trench in the prior art;

[0059] Figure 4 It is a schematic diagram of the three-dimensional structure of the first gate and the second gate of Embodiment 1 of the present invention;

[0060] Figure 5 It is a schematic diagram of the three-dimensional structure of the first structure without the first gate and the second gate according to Embodiment 1 of the present invention;

[0061] Figure 6 It is a schematic diagram of the longitudinal section structure of the first structure of Example 1 of the present invention;

[0062] Figure 7 It is a schematic diagram of splicing two first structures of Example 1 of the present invention;

[0063] Figure 8 It is a partial schematic diagram of the first metal layer and the second metal layer of the first structure of Embodiment 1 of the present invention being connected to each other;

[0064] Fig. 9 The turn-off waveform comparison of the high-voltage and high-power planar and trench dual independent channel IGBT chip in Example 1 of the present invention and other structures in the accompanying drawings;

[0065] Fig.10 Schematic diagram of the driving circuit in Embodiment 2-4 of the present invention;

[0066] Fig.11 Schematic diagram of driving signals in Embodiment 2-4 of the present invention;

[0067] Fig.12 It is a comparative waveform diagram of the shutdown process driven in different ways in Embodiments 2-4 of the present invention;

[0068] Fig.13 A diagram showing the relationship between the shutdown delay time and the total shutdown time in Example 4 of the present invention;

[0069] Fig.14 A waveform diagram comparing the turn-on process driven in different ways in Embodiments 3-4 of the present invention;

[0070] Fig.15 Schematic diagram of the relationship between the groove depth, the on-state voltage drop and the breakdown voltage in the embodiment of the present invention;

[0071] Fig.16 Schematic diagram of the relationship between the wd value, the on-state voltage drop, and the breakdown voltage in the embodiment of the present invention;

[0072] Fig.17 Schematic diagram of the relationship curve between the w1 value, the on-state voltage drop and the breakdown voltage in the embodiment of the present invention. DETAILED DESCRIPTION

[0073] The following will be combined with the drawings of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0074] Example 1

[0075] The present invention provides an IGBT chip, comprising a cell, wherein the cell is formed by splicing two first structures (also referred to as half cells) that are arranged in mirror symmetry.

[0076] The first structure includes an N-type substrate 503, a first gate 510 and a second gate 508 that are spaced apart;

[0077] The upper surface of the N-type substrate 503 is provided with a groove 1 extending downward into the N-type substrate 503 along the height direction of the N-type substrate 503, the first gate 510 is a first gate 510 arranged on the N-type substrate 503, at least part of the second gate 508 extends into the groove 1, and the first gate 510 and the second gate 508 are separated by an oxide layer 509. The thickness d of the oxide layer between the first gate 510 and the second gate 508 is not less than 100 angstroms. d is preferably 100 angstroms-200 angstroms (that is, the thickness of the oxide layer 509 used for isolation between the first gate 510 and the second gate 508 is 100 angstroms-200 angstroms);

[0078] A first active region is disposed below the first gate 510, and a second active region is disposed on a side of the groove 1 away from the first gate 510;

[0079] The first active region and the second active region are both disposed on an N-type substrate 503;

[0080] The first metal layer 5061 in the first active region and the second metal layer 5062 in the second active region of each cell are in contact with each other to form the emitter of the IGBT chip; the N-type substrates 503 of each cell are in contact with each other to form an integrated structure.

[0081] The first active region includes a first N+ doped region 5071 and a first metal layer 5061 which are adjacently arranged; the first metal layer 5061 is located on a side of the first N+ doped region 5071 away from the second gate 508;

[0082] The first active region further includes a first N-well region 5041 formed in the N-type substrate 503, a first P-well region 5051 located on the first N-well region 5041, a first N+ doped region 5071 and a first metal layer 5061 located on the first P-well region 5051, the first P-well region 5051 is arranged around the outside of the first N+ doped region 5071 and the first metal layer 5061, and the first N-well region 5041 is arranged around the outside of the first P-well region 5051;

[0083] The upper end surface of the first N+ doping region 5071 , the upper end surface of the first P-well region 5051 , and the upper end surface of the first N-well region 5041 are all arranged toward the first gate 510 .

[0084] The second active region includes a second N+ doping region 5072, a second P-well region 5052, and a second N-well region 5042 arranged in sequence from top to bottom in the height direction of the N-type substrate 503, and also includes a second metal layer 5062 arranged adjacent to the second N+ doping region 5072 and located on the second P-well region 5052; the second metal layer 5062 is located on a side of the second N+ doping region 5072 away from the first gate 510;

[0085] The wall surface of the second N+ doped region 5072, the wall surface of the second P-well region 5052, and the wall surface of the second N-well region 5042 at least form a part or all of the wall surface of the groove 1 away from the first gate 510;

[0086] In one cell, the second metal layer 5062, the second P-well region 5052, and the second N-well region 5042 of the second active region of one first structure are in contact with the second metal layer 5062, the second P-well region 5052, and the second N-well region 5042 of the second active region of another first structure, respectively;

[0087] The height position of the bottom surface of the second N-well region 5042 is higher than the height position of the bottom of the groove 1;

[0088] The first direction is defined as the direction in which the two first structures are spliced ​​together to form a cell, and the projection size c1 of the upper end surface of the first P-well region 5051 in the first direction is equal to the wall height c2 of the second P-well region 5052 forming the wall of the groove 1 away from the first gate 510.

[0089] In the first structure, the first metal layer 5061 of the first gate 510 and the second metal layer 5062 of the second gate 508 are connected to each other via a bridging metal structure 5063 bridging above the first gate 510 and the second gate 508 .

[0090] In the first structure, the first P-well region 5051 of the first gate 510 and the second P-well region 5052 of the second gate 508 do not contact each other; the first N-well region 5041 of the first gate 510 and the second N-well region 5042 of the second gate 508 do not contact each other.

[0091] The first structure further includes a P+ collector layer 501 and an N-type buffer layer 502 . The P+ collector layer 501 , the N-type buffer layer 502 , and the N-type substrate 503 are sequentially arranged from bottom to top in the height direction of the N-type substrate 503 .

[0092] The thickness of the oxide layer 509 between the portion of the second gate 508 extending into the groove 1 and the bottom of the groove 1 is greater than the thickness of the oxide layer 509 between the portion of the second gate 508 and the sidewall of the groove 1 .

[0093] The thickness of the oxide layer 509 between the second gate 508 and the bottom of the groove 1 is greater than the thickness of the oxide layer 509 between the first gate 510 and the N-type substrate 503 .

[0094] Specifically, the present invention provides a high-voltage and high-power IGBT chip with dual independent channels of planar and trench and a driving method thereof.

[0095] The high-voltage and high-power IGBT chip provided by the present invention comprises an N-type substrate 503 and a plurality of parallel cells formed on the surface of the substrate. Taking a single cell as an example, the cell comprises a gate region and active regions located on both sides of the gate region.

[0096] The active area is N+ doped area, P well area, and N well area from top to bottom; the active area exists below the first gate 510 area and on both sides of the second gate 508 area. The gate area includes the first gate 510 on the surface of the substrate; and a groove etched downward at a specified position, in which the second gate 508 is arranged; the gate area and the N-type substrate are separated by an oxide layer, wherein the oxide layer thickness at the bottom of the second gate 508 is greater than the oxide layer thickness below the first gate 510; the first gate 510 and the second gate 508 are both made of polysilicon, and the first gate 510 and the second gate 508 are separated; through this implementation, the potentials between the plane and the second gate 508 will not affect each other, and can be driven independently.

[0097] In one embodiment, compared with an IGBT with a folded composite gate structure, the turn-off loss can be reduced by at least 30%.

[0098] The present invention also provides a driving method applicable to the chip. The two gate electrodes can be driven simultaneously, time-sharingly or even compositely, all of which can achieve the effect of reducing losses. In particular, composite driving can reduce total losses to the greatest extent.

[0099] In one embodiment, the thickness of the oxide layer at the bottom of the second gate 508 is greater than the thickness of the oxide layer under the first gate 510. Because the bottom of the trench is deep inside the chip and is easier to break through, it is set to be thicker.

[0100] The concentrations of the N+ doping region, P well region, and N well region of the active region of the first gate 510 are the same as those of the active region of the second gate 508. That is, the concentration of the trench gate N well region = the concentration of the planar gate N well region; the trench gate P well region = the concentration of the planar gate P well region; the trench gate N+ doping region = the concentration of the planar gate N+ doping region). This arrangement can reduce the complexity of the process doping and can make the turn-on voltage close. And the process is simpler.

[0101] The depth of the P-well region is greater than the depth of the N+ doping region. The P-well region wraps around the N+ region to form a channel.

[0102] Preferably, the depth of the N-well region does not exceed the depth of the trench. If the N-well region exceeds the trench, it will cause premature breakdown.

[0103] The channels of the first gate 510 and the second gate 508 are both in an open state, and carriers are injected into the two channels at the same time, so more carriers are injected into the chip than if only one channel is injected. The above technical effect can be achieved by isolating the plane and the groove, but the length of the first gate 510 affects the key parameter of the on-state voltage drop of the chip. Therefore, when the two gates 510 and 508 do not affect each other, the length of the first gate 510 is made as long as possible.

[0104] In one embodiment, the second gate 508 and the first gate 510 each apply a gate drive.

[0105] like Figure 6 As shown, the IGBT chip proposed in the present invention is characterized in that: a silicon wafer is doped with P-type impurities to obtain a P+ collector substrate 501, and an N-type buffer layer 502 and an N-drift region 503 are epitaxially grown on the basis of the P+ substrate 501. Specifically, implantation and etching are performed on the N-type substrate to form a gate region and an active region. The gate region includes a second gate 508, a first gate 510, and a gate oxide layer 509. Preferably, the gate oxide layer 509 at the bottom of the second gate 508 is slightly thicker than the side wall to prevent premature breakdown. The active region includes a trench gate active region and a planar gate active region, and the active regions are all realized by the same process steps. The active region of the first gate 510 includes a first N+ doped region 5071, a first P well region 5051, a first N well region 5041, and a first metal layer 5061 distributed from top to bottom. The active area of ​​the second gate 508 includes a second N+ doped region 5072, a second P well region 5052, a second N well region 5042, and a second metal layer 5062. Specifically, the polysilicon of the first gate 510 is not connected to the polysilicon of the second gate 508, and a gate drive is applied to each of the G1 and G2 terminals, such as Fig.10 As shown, the two gates are each equipped with an independent driver V gg and V gg '.

[0106] N+ doped region 507, P well region 505, and N well region 504 are located on both sides of the gate region and contact each other. Specifically, N+ doped region 507 is directly below the first gate 510 and forms an ohmic contact with the metal layer 506, P well region 505 contacts the gate oxide layer 509 under the first gate 510 and wraps the N+ doped region 507, and N well region 504 contacts the gate oxide layer 509 under the first gate 510 and wraps the P well region 505. Differently, the doped region of the second gate 508 is distributed downward in sequence, including N+ doped region 507, P well region 505, and N well region 504, and all stop at the sidewall of the trench. The depth of N well region 504 does not exceed the depth of the trench. If the N well region exceeds the trench, it will cause premature breakdown. N+ doped region 507 also forms an ohmic contact with the metal layer 506.

[0107] The same impurity dosage is injected into the P-well region 505, N-well region 504 and N+ doping region 507 in the trench doping region and the plane doping region, thereby ensuring that the threshold voltage is almost the same and the process is simpler. The junction depths of the P-well region 505, N-well region 504 and N+ doping region 507 in the trench doping region are reasonably set to ensure that the lengths of the plane channel 520 and the trench channel 530 are the same as much as possible.

[0108] The length of the planar channel 520 and the trench channel 530 refers to the length of the inversion layer formed after opening, that is, Figure 5 The first gate 510 / the second gate 508 is in contact with the P well, so that a better conduction state can be achieved, which is beneficial to reducing the conduction voltage drop.

[0109] In one embodiment, every two of the units form a cell in a mirror-symmetrical manner.

[0110] In one embodiment, the cell is a hexagonal cell structure, and a plurality of the cells are distributed in a honeycomb pattern on the N-type substrate; or, the cell is a square cell structure, and a plurality of the cells are distributed in a matrix pattern on the N-type substrate; or, the cell is a strip cell structure, and a plurality of the cells are distributed side by side on the N-type substrate.

[0111] The cell is a hexagonal cell structure, and a plurality of the cells are distributed in a honeycomb shape; or

[0112] The cell is a square structure, and a plurality of the cells are distributed in a matrix; or

[0113] The cell is a strip-shaped structure, and a plurality of the cells are arranged side by side.

[0114] In one embodiment, the IGBT chip further includes a back structure formed on the back of the N-type substrate, and the back structure is a punch-through type, a non-punch-through type, or a soft punch-through type. The non-punch-through type back structure is the collector P+ region, and the punch-through type back structure also adds an N-Buffer region; the soft punch-through type is SPT, and the difference is that the N-Buffer region is Gaussian doped (i.e., the concentration decreases successively)

[0115] Fig. 9 610 is the turn-off voltage waveform of the structure proposed by the present invention, 611 is the turn-off current waveform; 62 ...2 is the turn-off voltage waveform of the structure proposed by the present invention, 613 is the turn-off voltage waveform of the structure proposed by the present invention, 614 is the turn-off voltage waveform of the structure proposed by the present invention, 615 is the turn-off voltage waveform of the structure proposed by the present invention, 616 is the turn-off voltage waveform of the structure proposed by the present invention, 617 is the turn-off voltage waveform of the structure proposed by the present invention, 618 is the turn-off voltage waveform of the structure proposed by the present invention, 619 is the turn-off voltage waveform of the structure proposed by the present invention, 620 is the turn-off voltage waveform Figure 1 The turn-off voltage waveform of the planar gate structure shown in FIG. 621 is its turn-off current waveform; 630 is the turn-off voltage waveform of the folded composite gate structure in patent CN108598160B, and 631 is its turn-off current waveform; 640 is Figure 3641 is the turn-off voltage waveform of the planar gate structure with grooves, and 642 is the turn-off current waveform. Fig. 9 The waveform diagram shown in the figure enables the first gate 510 and the second gate 508 to be driven independently, which greatly speeds up the switching process of the device, reduces the switching delay of the folded composite gate structure due to the introduction of the trench, and greatly reduces the switching loss.

[0116] Example 2

[0117] like Fig.11 As shown, the present invention also provides a driving method for the IGBT chip as described above, wherein a driving voltage is applied to both the first gate 510 and the second gate 508, and the driving voltage applied to the first gate 510 and the driving voltage applied to the second gate 508 are independent of each other.

[0118] That is, in the circuit, the two gates of each IGBT are respectively connected to two signals to drive the second gate 508 and the first gate 510 respectively.

[0119] The driving method of the high-power plane and trench dual independent channel IGBT chip provided by the present invention is characterized in that:

[0120] In one embodiment, simultaneous driving is adopted, that is, the driving signals controlling the opening and closing of the two gates are exactly the same; the rising edge or the falling edge is connected to the first gate 510 and the second gate 508 at the same time, and the first gate 510 and the second gate 508 are synchronized in time and shut down, thereby increasing the driving capability of the chip.

[0121] In this embodiment, when the IGBT chip switches from the off state to the on state, the on voltage is applied to the first gate 510 and the second gate 508 at the same time; when the IGBT chip switches from the on state to the off state, the off voltage is applied to the first gate 510 and the second gate 508 at the same time.

[0122] The present invention also provides a storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the driving method of the IGBT chip as described above are implemented.

[0123] In this embodiment, the simultaneous driving mode is as follows Fig.11 As shown in 100, the positive and negative voltage transition moments 801 and 802 of the gate drive signals applied by the first gate 510 and the second gate 508 are the same, and the two gates are simultaneously applied with a voltage above the threshold and can be turned on or off at the same time.

[0124] Example 3

[0125] The difference between the present embodiment 3 and the embodiment 2 is that when the IGBT chip switches from the off state to the on state and from the on state to the off state, there is a difference in the order of applying the voltage to the first gate 510 and the second gate.

[0126] In this embodiment, when the IGBT chip switches from the off state to the on state, the time when the on voltage is applied to the first gate 510 is earlier than the time when the on voltage is applied to the second gate 508 by a first preset time t1;

[0127] In this embodiment, when the IGBT chip switches from the on state to the off state, the time when the off voltage is applied to the second gate 508 is earlier than the time when the off voltage is applied to the first gate 510 by a second preset time t2.

[0128] Preferably, t1≤5us, t2≤10us.

[0129] In this embodiment, time-sharing drive is adopted, that is, there are differences in the driving signals controlling the opening and closing of the two gates; during the opening and closing processes, the moments of the jump of the positive and negative voltages are different. When shutting down, due to the large gate-emitter capacitance at the second gate 508, the second gate 508 is turned off first, and a conductive channel is turned off, carrier injection is reduced, and the carriers inside the chip are reduced, thereby accelerating the shutdown process of the device.

[0130] In one embodiment, Fig.11 200 is a schematic diagram of a time-sharing drive signal, where different drive voltages are applied to the two gates. Specifically, when turned on, the first gate 510 is first applied with a turn-on signal 803, and the turn-on signal of the second gate 508 is delayed by t1. The delayed turn-on can reduce current overcharge and collector current rise rate, enhance the stability of the chip during the turn-on process, but the turn-on loss is slightly increased; when turned off, the second gate 508 is first applied with a turn-off signal 804, and the turn-off signal of the first gate 510 has a delay of t2. Turning off one gate in advance can reduce the carrier concentration inside the chip and shorten the time for extracting carriers during the turn-off process, thereby greatly reducing the turn-off loss and reducing the total switching loss.

[0131] Example 4

[0132] The difference between the present embodiment 4 and the embodiment 2 is that when the IGBT chip switches from the on state to the off state, there is a difference in the order of applying the voltage to the first gate 510 and the second gate.

[0133] In this embodiment, when the IGBT chip switches from the off state to the on state, the on voltage is applied to the first gate 510 and the second gate 508 at the same time; when the IGBT chip switches from the on state to the off state, the time when the off voltage is applied to the second gate 508 is earlier than the time when the off voltage is applied to the first gate (510) by a third preset time t3.

[0134] Preferably, t3≤10us.

[0135] In this embodiment, a composite driving method combining simultaneous driving and time-sharing driving is adopted, and its main feature is that when turning on, the two gate driving signals are completely consistent and turned on at the same time, and the two conductive channels are injected with carriers at the same time, which speeds up the turning-on speed. When turning off, the gate driving signals are different, and the second gate 508 is turned off first, which reduces the injection of carriers, increases the turning-off speed, and reduces the loss.

[0136] In one embodiment, Fig.11 300 is a schematic diagram of a composite drive signal. The composite drive's turn-on process is the same as the simultaneous drive mode, and the turn-off process is the same as the time-sharing drive mode. That is, in the turn-on process, the same drive signal is applied to the two gates, and the first gate 510 and the second gate 508 are simultaneously applied with a positive jump at the turn-on signal 805. Since the carrier concentration inside the chip is low before turning on, the simultaneous injection of carriers into the dual channels will speed up the turn-on speed. Compared with the time-sharing drive, this control method has a smaller turn-on loss; in the turn-off process, similarly, the second gate 508 is first applied with a turn-off signal 806, and the turn-off signal of the first gate 510 has a delay of t3; the turn-off of the groove side channel reduces the carriers injected into the chip, greatly reduces the carrier concentration in the chip, and improves the turn-off speed.

[0137] The effect of the driving method described in the above embodiment on the shutdown process is as follows: Fig.12 As shown, 920 is the collector voltage waveform of the structure proposed in the present invention using the simultaneous driving method, and 921 is the corresponding collector current waveform; 910 is the collector voltage waveform of the structure proposed in the present invention using the time-sharing driving method, and 911 is the corresponding collector current waveform; for comparison, 930 is the collector voltage waveform of the structure in patent CN108598160B, and 931 is the corresponding collector current waveform; it can be seen that compared with the folded-type composite gate IGBT chip, the solution of the present application greatly reduces the turn-off delay, and the turn-off speed of the embodiment using the time-sharing driving method 200 is faster than that using the simultaneous driving method 100, and the turn-off loss is also minimal.

[0138] Fig.13 is the relationship between the turn-off delay time t2 of the second gate relative to the first gate and the total turn-off time when the second gate is turned off, where toff It indicates the time required for shutdown, reflecting the influence of the length of t2 on the shutdown time. Specifically, the shutdown time 1002 of the device using time-sharing drive (i.e., the gate is turned off 10s earlier than the gate) is shorter than that of the simultaneous drive 1001 (i.e., the first gate and the second gate are turned off at the same time). As the delay time increases, the total shutdown time continues to decrease until it becomes constant after 10μs. The maximum shortening time is about 1μs, but for high-voltage and high-power chips, the loss is greatly reduced.

[0139] Fig.14 1101 is the collector voltage waveform of the composite drive mode, 1103 is the corresponding collector current waveform; 1102 is the collector voltage waveform of the time-sharing drive mode, 1104 is the corresponding collector current waveform. Fig.14 As shown in , the composite driving mode 300, i.e., the opening speed of two gates being opened at the same time, is faster than that of the time-sharing driving 200. Since the carrier concentration inside the chip is low before opening, the simultaneous injection of carriers into the dual channels will speed up the opening speed and reduce the loss.

[0140] Compared with the prior art, the present invention proposes an independently drivable first gate 510 and a second gate 508 to form dual independent channels in both vertical and horizontal directions, and adds gate drive to achieve the above functions, while retaining the optimal effect without increasing the process complexity; and for this chip, three applicable driving methods are proposed, among which the composite driving method can greatly reduce the loss of the device.

[0141] Example 5

[0142] In this embodiment, further, the groove depth is set to 6um-8um.

[0143] like Fig.15 As shown, the applicant found in the research that the larger the groove depth, the smaller the on-state voltage drop of the IGBT chip, and the breakdown voltage increases first and then decreases. By setting the value range of the groove depth, not only can the on-state voltage drop of the IGBT chip be smaller (thereby reducing power consumption) and the breakdown voltage be larger, but also the processing difficulty caused by making the groove depth too deep can be avoided as much as possible.

[0144] Example 6

[0145] In this embodiment, further, it is assumed that: the size w1 of the groove in the first direction ranges from 4um to 6um, the size wd of the second N-well region in the first direction ranges from 2um to 4um, and the size of the first structure (half cell) in the first direction is 20um to 22um.

[0146] like Fig.16 , Fig.17 As shown, the applicant found during the research that the larger the wd, the larger the on-state voltage drop and the smaller the breakdown voltage, and the larger the spacing wm between the first N-well region and the groove in the first direction (i.e., the size in the first direction), the larger the on-state voltage drop and the smaller the breakdown voltage. By setting a larger w1 value (groove width) and a smaller half-cell width (i.e., the size in the first direction), wd can take a smaller value and the wm value can be as small as possible, so as to achieve a smaller on-state voltage drop and a larger breakdown voltage. Moreover, increasing the width of the groove can enlarge the range of the carrier accumulation layer and reduce the on-state voltage drop to a certain extent. wd can be 2-4um, and the groove width w1 can be 4-6um, so that a higher withstand voltage can be achieved while maintaining a smaller on-state voltage drop.

[0147] In this embodiment, setting various size ranges has little effect on the switching delay and switching loss of the IGBT chip.

[0148] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0149] The embodiments of the present invention are described in detail above, but the contents are only preferred embodiments of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of this patent. After reading the present invention, modifications of various equivalent forms of the present invention by those skilled in the art all fall within the scope defined by the claims attached to this application. In the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.

Claims

1. An IGBT chip, comprising a cell, wherein the cell is formed by splicing two symmetrically arranged first structures; The first structure comprises an N-type substrate (503), a first gate (510), and a second gate (508); the first gate (510) and the second gate (508) are separated by an oxide layer (509); The upper surface of the N-type substrate (503) is provided with a groove (1) extending downward into the N-type substrate (503) along the height direction of the N-type substrate (503); the first gate (510) is a first gate (510) arranged on the N-type substrate (503); at least a portion of the second gate (508) extends into the groove (1); and a thickness d of an oxide layer between the first gate and the second gate is not less than 100 angstroms; A first active region is provided below the first gate (510), and a second active region is provided on a side of the groove (1) away from the first gate (510); The first active region and the second active region are both arranged on an N-type substrate (503); The first metal layer (5061) in the first active region and the second metal layer (5062) in the second active region of each unit cell are in contact with each other to form an emitter of the IGBT chip; the N-type substrates (503) of each unit cell are in contact with each other to form an integrated structure; The first active region comprises a first N+ doped region (5071) and a first metal layer (5061) which are arranged adjacent to each other; the first metal layer (5061) is located on a side of the first N+ doped region (5071) away from the second gate (508); The first active region further comprises a first N-well region (5041) formed in the N-type substrate (503), a first P-well region (5051) located on the first N-well region (5041), a first N+ doped region (5071) and a first metal layer (5061) located on the first P-well region (5051), the first P-well region (5051) being arranged around the outside of the first N+ doped region (5071) and the first metal layer (5061), and the first N-well region (5041) being arranged around the outside of the first P-well region (5051); The upper end surface of the first N+ doped region (5071), the upper end surface of the first P well region (5051), and the upper end surface of the first N well region (5041) are all arranged toward the first gate (510); The second active region comprises a second N+ doped region (5072), a second P-well region (5052), and a second N-well region (5042) which are arranged in sequence from top to bottom in the height direction of the N-type substrate (503), and also comprises a second metal layer (5062) which is arranged adjacent to the second N+ doped region (5072) and is located on the second P-well region (5052); the second metal layer (5062) is located on a side of the second N+ doped region (5072) away from the first gate (510); The wall surface of the second N+ doped region (5072), the wall surface of the second P-well region (5052), and the wall surface of the second N-well region (5042) at least form part or all of the wall surface of the groove (1) away from the first gate (510); In a cell, the second metal layer (5062), the second P-well region (5052), and the second N-well region (5042) of the second active region of one first structure are in corresponding contact with the second metal layer (5062), the second P-well region (5052), and the second N-well region (5042) of the second active region of another first structure.

2. The IGBT chip according to claim 1, characterized in that: The first direction is defined as the direction in which the two first structures are spliced ​​together to form a unit cell, and the projection dimension c1 of the upper end surface of the first P-well region (5051) in the first direction is equal to the wall height c2 of the second P-well region (5052) that forms the wall of the groove (1) away from the first gate (510).

3. The IGBT chip according to claim 1, characterized in that: The groove (1) has a depth of 6um-8um.

4. The IGBT chip according to claim 1, characterized in that: The dimension w1 of the groove in the first direction ranges from 4um to 6um, the dimension wd of the second N-well region (5042) in the first direction ranges from 2um to 4um, and the dimension of the first structure in the first direction ranges from 20um to 22um.

5. The IGBT chip according to claim 1, characterized in that: The first structure further comprises a P+ collector layer (501) and an N-type buffer layer (502), wherein the P+ collector layer (501), the N-type buffer layer (502) and the N-type substrate (503) are arranged in sequence from bottom to top in a height direction of the N-type substrate (503).

6. The IGBT chip according to claim 1, characterized in that: The thickness of the oxide layer (509) between the second gate (508) and the bottom of the groove (1) is greater than the thickness of the oxide layer (509) between the second gate (508) and the side wall of the groove (1).

7. The IGBT chip according to claim 1, characterized in that: The thickness of the oxide layer (509) between the second gate (508) and the bottom of the groove (1) is greater than the thickness of the oxide layer (509) between the first gate (510) and the N-type substrate (503).

8. A method for driving an IGBT chip according to any one of claims 1 to 7, characterized in that: A driving voltage is applied to both the first gate (510) and the second gate (508), and the driving voltage applied to the first gate (510) and the driving voltage applied to the second gate (508) are independent of each other.

9. The driving method of the IGBT chip according to claim 8, characterized in that: When the IGBT chip switches from an off state to an on state, a conduction voltage is simultaneously applied to the first gate (510) and the second gate (508); When the IGBT chip switches from an on state to an off state, an off voltage is simultaneously applied to the first gate (510) and the second gate (508).

10. The driving method of the IGBT chip according to claim 8, characterized in that: When the IGBT chip switches from the off state to the on state, the moment when the on voltage is applied to the first gate (510) is earlier than the moment when the on voltage is applied to the second gate (508) by a first preset time t1; When the IGBT chip switches from the on state to the off state, the moment when the off voltage is applied to the second gate (508) is earlier than the moment when the off voltage is applied to the first gate (510) by a second preset time t2.

11. The driving method of the IGBT chip according to claim 10, characterized in that: t1≤5us, t2≤10us.

12. The driving method of the IGBT chip according to claim 8, characterized in that: When the IGBT chip switches from an off state to an on state, a conduction voltage is simultaneously applied to the first gate (510) and the second gate (508); When the IGBT chip switches from the on state to the off state, the moment when the off voltage is applied to the second gate (508) is earlier than the moment when the off voltage is applied to the first gate (510) by a third preset time t3.

13. The driving method of the IGBT chip according to claim 12, characterized in that: t3≤10us.

14. A storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the driving method of the IGBT chip according to any one of claims 8 to 13 are implemented.

Images