Method for obtaining actual pixel size on unpatterned wafer

Abstract

The present invention discloses a method for obtaining the actual pixel size on a non-patterned wafer, comprising: placing the non-patterned wafer on a mechanical motion platform of a charged particle beam scanning imaging device; distinguishing the magnifications corresponding to all actual pixel sizes to be measured into a first magnification LM and a second magnification HM, both of which include one or more different magnification values; first measuring the actual pixel size in the first magnification LM, and then measuring the actual pixel size in the second magnification HM, both from relatively low to high magnifications; both collecting template images at the wafer notch, moving the wafer in a predetermined direction and distance, collecting target images, and calculating the actual pixel size with the actual moving distance and the target displacement obtained by matching. Thus, the measurement accuracy is improved, the problem that the current equipment is difficult to determine the actual pixel size when a large number of non-patterned wafers are used is solved, and the use cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor equipment, and in particular to a method for acquiring actual pixel size on a non-patterned wafer. Background Art

[0002] In the front-end manufacturing process of semiconductor large-scale integrated circuits (ICs), charged particle beam scanning imaging equipment is often required. Charged particle beam scanning imaging equipment is, for example, a scanning electron microscope (SEM) device, which is used for defect detection or re-inspection of wafers, or a focused ion beam (FIB) device. A common application is that the SEM device is an initial inspection (E-Beam Inspection, EBI) device, or a re-inspection (E-Beam Review, EBR) device. Taking the EBR device as an example, a quick and easy method is needed to obtain the actual pixel size of the device for wafer scanning imaging, which is used to estimate the actual physical size of the object to be tested (rather than the size in pixels), such as the defect size or some critical dimensions (Critical Dimension).

[0003] refer to Figure 1A , the EBR equipment 100 generally includes a mechanical motion platform 110, which can move and rotate in the X, Y, and Z directions, and has an electrostatic tray (Electro-Static Chuck, e-chuck) 120 on which a wafer can be placed, on which a wafer (Wafer) 111 can be placed. The EBR equipment generally also includes an optical microscope imaging system (Optical Microscope, OM) 130, which has a lower magnification but a larger field of view (Field of View, FOV), and is generally used for auxiliary work such as primary wafer alignment. The above equipment also includes a core task component - an electron optical imaging system 140, such as a SEM electron optical system (see Figure 1B , 180), which further includes functional components such as electron emission, focusing, beam limiting, deflector, and scanning control, and also includes the collection of electrons emitted from the wafer surface, mainly secondary electrons, and signal amplification and processing. The lens involved in focusing is an electron optical lens. The device also includes a computer 150, which can be used to process data and display images.

[0004] refer to Figure 2A and Figure 2B, the electron beam of the SEM system in the EBR device is 210 when imaging, the focal plane is 211, the focal depth is 212, the z direction is the density of the electron beam 210, and the x direction is the x coordinate direction on the wafer. When working, the SEM system scans a given area back and forth. During scanning, the sampling intervals in the X and Y directions on the wafer surface (and within its focal depth / range) are Δx and Δy, and the system needs to stay at each sampling point for a certain time to accumulate enough emitted electrons to achieve a certain signal-to-noise ratio. The obtained SEM image is theoretically roughly equivalent to the convolution of the beam spot shape (approximately Gaussian distribution) of the electron beam when it reaches the wafer surface and the wafer surface morphology (including different materials and structures). When the theoretical field of view (FOV) of the SEM system and the number of pixels in the image in the X and Y directions are determined, the pixel size in the X and Y directions, i.e., the nominal pixel size (NPS), is also determined. The theoretical pixel size is the theoretical field of view size divided by the image size (for example, when sampling, the width / height is 1024 / 2048 pixels), so the theoretical pixel size is Δx and Δy. The working parameters and state of the SEM system often drift during actual use of the equipment, for example, due to 1) a slight change in the actual beam spot size of the system or the scanning sampling interval determined by the equipment control circuit; 2) a change in the working distance from the objective lens to the wafer surface in the SEM system (due to, for example, drift in the Z direction of the mechanical motion platform or changes in the thickness of different types of wafers, thereby changing the actual sampling interval on the wafer), making the theoretical pixel size different from the actual pixel size. The combination of multiple factors makes the theoretical pixel size and the actual pixel size differ greatly, so in actual application of the equipment, it is often necessary to be able to obtain a more accurate actual pixel size.

[0005] Please refer to Figure 3A and Figure 3B , a commonly used method 1 for obtaining the actual pixel size in the prior art is: to take an image of a wafer or sample with an object of known size, and then calculate the actual pixel size. For example, in method 1, a special wafer is used with a measurement object of known size on it, or in method 2, a special sample 311 is placed on a mechanical motion platform 310, and an object 312 of known size is included in the image 314 collected on the sample, and has a known length, such as 5μm.

[0006] However, the disadvantages of methods 1 and 2 in the prior art are very obvious. In method 1, the special wafer will increase the cost, and the special wafer needs to be loaded and unloaded each time it is used, which takes up precious machine time. The cost of use is extremely high and it is difficult to achieve on the actual IC production line. In addition, the surface height and the height of the customer wafer surface, that is, the working distance from the two surfaces to the SEM objective lens may still be quite different; in method 2, the special sample will be damaged after long-term use, resulting in measurement errors, and the surface height and the height of the customer wafer surface, that is, the working distance from the two surfaces to the SEM objective lens may be quite different; in addition, there is method 3 in the industry, which is a method of directly using the customer wafer (limited to patterned wafers, i.e., Patterned Wafers) to obtain the actual pixel size, see Figure 4 , which shows a method for measuring the actual pixel size by collecting images before and after the wafer moves (a total of two frames of images) and performing template matching (also called image matching) (in the figure, not shown in actual proportion). The coordinate axes of the mechanical motion platform coordinate system are the x-axis and the y-axis, the wafer 401, and the field of view 402 when the SEM system collects images, and their positions are fixed. The principle is as follows: first collect the first frame of image, that is, the template image, select a region / sub-image therein as the template 403, and the template 403 is located at (Xm, Ym) in the image coordinate system. The displacement of the mechanical motion platform in the X and Y directions is dXs and dYs respectively. In the figure, dXs and dYs are marked as 404 and 405 respectively. Collect the second frame of image, that is, the target image, and perform template matching to determine the matching position (Xm′, Ym′), and the matching position (Xm′, Ym′) is also the coordinate in the image coordinate system. Among them, the coordinate origin of the image coordinate system is, for example, the upper left corner, the lower left corner or the center point of the image, but is not limited to this. Divide dXs by (Xm′-Xm) and dYs by (Ym′-Ym) to get the actual pixel size.

[0007] Usually, applications with different magnifications (corresponding to different fields of view) need to obtain the actual pixel size. For example, it can be divided into 1) low magnification (Low Magnification, referred to as LM) interval and high magnification (High Magnification, referred to as HM) interval, and both have multiple levels of different magnification values. Figure 5A For example, method 3 usually includes:

[0008] 1) Determine a certain position on the wafer, collect a template image 510, and select a template 511 in the template image 510;

[0009] 2) Move the mechanical moving platform, the wafer and the mechanical moving platform move synchronously, to another position to capture the target image 512, and record the relative displacement dXs, dYs of the mechanical moving platform; the moving position here is limited to ensure that the target is still in the target image (that is, located in the field of view of the SEM system) when the mechanical moving platform has a known error range;

[0010] 3) searching for a template in the target image, i.e. performing template matching, and obtaining a matching position 513;

[0011] 4) Obtain the distance dXm, dYm between the template 511 and the matching position 513, named as the target displacement, specifically:

[0012] dXm=Xm'-Xm

[0013] dYm=Ym'-Ym

[0014] Where (Xm, Ym) is the position of the template in the template image (initial position), and (Xm′, Ym′) is the position where the template is matched in the target image (matching position);

[0015] 5) Obtain the actual pixel sizes Px and Py, specifically:

[0016]

[0017]

[0018] Among them, the displacement of the mechanical motion platform is (dXs, dYs), which is determined by the mechanical motion platform (equipped with a precise code reader / laser interferometer that can give the actual arrival position. There may be a slight difference between the actual arrival position and the position that the system commands the mechanical motion platform to reach), usually with an accuracy of 0.5μm.

[0019] Please refer to Figure 5B The method is the same at high magnification HM, which is to collect template image 520, select template 521 from it, and then move the wafer to collect target image 522, perform template matching to obtain matching position 523.

[0020] However, the problem with method 3 is that the above equipment may be used entirely for blank wafers (BlankWafer / Un-patterned Wafer) in the IC production line for a period of time, and will not encounter patterned wafers. There is no pattern on the blank wafer that can be used for template matching, so either return to method 1 or 2, or when it is used entirely for blank wafers for a period of time, there is a lack of accurate and effective method to measure the actual pixel size. Therefore, an effective method to determine the actual pixel size on blank wafers is needed. Summary of the invention

[0021] The purpose of the present invention is to provide a method for obtaining the actual pixel size on a patternless wafer, so as to solve the problem in the prior art that the actual pixel size of the patternless wafer cannot be accurately and effectively measured, or the measurement requires the use of a special wafer or a special sample.

[0022] In order to achieve the above object, the present invention provides a method for obtaining the actual pixel size on a non-patterned wafer, comprising:

[0023] placing a plain wafer onto a mechanical motion platform of the charged particle beam scanning imaging device;

[0024] For the wafer, the magnifications corresponding to all actual pixel sizes to be measured are divided into a first magnification LM and a second magnification HM with a higher magnification, and the first magnification LM and the second magnification HM both include one or more different magnification values;

[0025] Firstly, measuring the actual pixel sizes in the first magnification LM, and then measuring the actual pixel sizes in the second magnification HM, and both measurements are performed in the order of relatively low to high magnification;

[0026] For each actual pixel size to be measured, a template image is collected at the notch of the wafer, the wafer is moved in a predetermined direction and distance by the mechanical motion platform, a target image is collected, a template is obtained from the template image, and the template is used to perform template matching in the target image, and then the actual pixel size is calculated based on the moving distance of the mechanical motion platform and the target displacement obtained by the template matching.

[0027] The present invention provides a method for acquiring the actual pixel size on a patternless wafer. The method collects a template image at a notch of the patternless wafer, acquires a template in the template image, and performs template matching between the template and a target image to further calculate the actual pixel size. The actual pixel size of the patternless wafer can be accurately and effectively measured, and there is no need to use a special wafer or a special sample to measure the actual pixel size, thereby reducing the use cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1A It is a schematic diagram of a semiconductor wafer re-inspection device based on charged particle beam scanning imaging in the prior art;

[0029] Figure 1B It is a schematic diagram of the electronic optical part of a charged particle beam scanning imaging device in the prior art;

[0030] Figure 2A It is a schematic diagram of density distribution and sampling of an electron beam in a SEM system in the prior art;

[0031] Figure 2B is a schematic diagram of the focal length and focusing depth of an electron beam in the prior art;

[0032] Figure 3A It is a schematic diagram of a specially prepared sample placed on a mechanical motion platform in the prior art;

[0033] Figure 3B It is a schematic diagram of a SEM image obtained from a specially prepared sample in the prior art;

[0034] Figure 4 It is a schematic diagram of a method for obtaining actual pixel size on a patterned wafer in the prior art;

[0035] Figure 5A is a schematic diagram of a method for obtaining actual pixel size using template matching at low magnification on a patterned wafer in the prior art;

[0036] Figure 5B is a schematic diagram of a method for obtaining actual pixel size using template matching at high magnification on a patterned wafer in the prior art;

[0037] Figure 6 is a flow chart of a method for obtaining an actual pixel size in an embodiment of the present invention;

[0038] Fig. 7A is a schematic diagram of obtaining the actual pixel size using a wafer notch image on a plain wafer in an embodiment of the present invention;

[0039] Figure 7B is a schematic diagram of performing template matching based on a wafer slot image in an embodiment of the present invention;

[0040] Figure 8 It is a schematic diagram of obtaining the actual pixel size by using the wafer notch image in combination with the displacement compensation bias method on a non-patterned wafer in an embodiment of the present invention;

[0041] Fig. 9 is a schematic diagram of the relative size relationship between the image field of view and the wafer notch at the second magnification HM involved in an embodiment of the present invention;

[0042] Fig.10 is a schematic diagram of a local offset and corresponding image stitching at a second magnification HM in an embodiment of the present invention;

[0043] Fig.11 is a schematic diagram of excluding a Don't Care Area (DCA) in a stitching template at a second magnification HM in an embodiment of the present invention;

[0044] Fig.12 is another schematic diagram of local bias and corresponding template selection and matching at a second magnification HM in an embodiment of the present invention;

[0045] Fig.13 It is another schematic diagram of two local offsets at the same position and corresponding image stitching in an embodiment of the present invention. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0047] In this embodiment, the charged particle beam scanning imaging device, still taking the EBR device as an example, like most semiconductor devices, the operation includes two main steps. First, the user prepares a work menu (recipe) in advance, and the work menu includes the steps of the main tasks of the device; then during normal operation, the device automatically repeats the work menu for the same type of wafer.

[0048] In this embodiment, it can be assumed that the above-mentioned device is in normal working state when determining the image pixel size, and all components have been calibrated, including focus (Focus) and image brightness and contrast (Brightness & Contrast) adjustment at each magnification.

[0049] In this embodiment, the wafer to be tested is a non-patterned wafer, including all mainstream wafers with a diameter of 300 mm and non-patterned wafers with a diameter of less than 300 mm and a groove. Customer non-patterned wafers can be used directly.

[0050] like Figure 6 As shown, this embodiment provides a method for obtaining the actual pixel size on a non-patterned wafer, comprising:

[0051] S1, placing a plain wafer on a mechanical motion platform of the charged particle beam scanning imaging device;

[0052] If the unpatterned wafer has been loaded onto the mechanical motion platform, there is no need to load it again. For example, when the charged particle beam scanning imaging device is performing its main work (e.g., defect review), the unpatterned wafer has been loaded onto the mechanical motion platform, and when obtaining the actual pixel size, there is no need to load the unpatterned wafer again.

[0053] S2. For the wafer, the magnifications corresponding to all actual pixel sizes to be measured are divided into a first magnification LM and a second magnification HM with a higher magnification, and the first magnification LM and the second magnification HM both include one or more (i.e., one or at least two) different magnification values;

[0054] S3, first measuring the actual pixel sizes in the first magnification LM, and then measuring the actual pixel sizes in the second magnification HM, and both measurements are performed in order from relatively low to high magnifications;

[0055] S4. For each actual pixel size to be measured, a template image is collected at the notch of the wafer, the wafer is moved in a predetermined direction and distance by the mechanical motion platform, a target image is collected, a template is obtained from the template image, and the template is used to perform template matching in the target image, and then the actual pixel size is calculated based on the moving distance of the mechanical motion platform and the target displacement obtained by the template matching.

[0056] It should be noted that the above S1-S4 are only the names of the steps, and do not limit the order of the steps. For example, when executing step S3, the content in step S4 needs to be executed to calculate the actual pixel size.

[0057] In the embodiment of the present invention, the first magnification LM and the second magnification HM are first distinguished, and the first magnification LM is used as the low magnification, and the second magnification HM is used as the high magnification. The basis for the distinction is the proportion of the notch of the non-patterned wafer in the image. When distinguishing the first magnification LM and the second magnification HM, the images of each magnification corresponding to the actual pixel size to be measured are collected, and the area proportion of the notch of the wafer in the images collected at each magnification is compared with a preset threshold, and the magnification when reaching or exceeding (i.e., greater than or equal to) the threshold is determined as the second magnification HM, otherwise it is the first magnification LM. For example, when the notch occupies an area of ​​1 / 2 in the image, it is regarded as the second magnification HM, otherwise it is the first magnification LM.

[0058] Currently, the most commonly used 300mm (12-inch) wafer notch is a circle with a diameter of 3mm cut out on the wafer. The depth of the cut into the wafer is 1mm, with an error of 0.25mm. The manufacturing process is relatively rough and its purpose is only to pre-align the wafer (usually there is a wafer pre-aligner in the EFEM, so that the angle deviation after the wafer is loaded is within ±1°), but it appears rough in the SEM image, and there are other interference factors, which will be discussed later.

[0059] In most applications, the notch is located directly below the wafer after it is mounted (notch down). The following example uses the notch located directly below as an example, and the results obtained are also applicable to notches located in other directions.

[0060] When measuring, you always go from lower magnification to higher magnification. The benefit is that it is more convenient when setting up templates (when creating recipes).

[0061] refer to Fig. 7A and Figure 7B When measuring the actual pixel size corresponding to a certain magnification under the first magnification LM, the following steps are included:

[0062] 1) Collect a template image 710 containing a defective groove at the position (x1, y1) on the unpatterned wafer 701, that is, collect the template image 710 with (x1, y1) on the wafer as the center of the field of view (FOV), and select a template 711 from it. Here, (x1, y1) is the position of the wafer defective groove in the field of view (FOV) of the electron optical system in the wafer coordinate system (for a reference point on the wafer, such as the center of a circle), and the corresponding position of the mechanical motion platform (for example, determined by the grating ruler and the code reader) is (SX1, SY1). The wafer coordinate system and the mechanical motion platform coordinate system have a fixed relative relationship, and the two are usually in a translation relationship after wafer alignment.

[0063] 2) Move the mechanical moving platform from position (SX1, SY1) to (SX2, SY2), the moving interval is the difference between the two (SX2-SX1, SY2-SY1), that is, (dSX1, dSY1), the wafer moves with the mechanical moving platform to the position (x2, y2) on the wafer to collect the target image 720, that is, to collect the image with (x2, y2) on the wafer as the FOV center. So that the target image 720 still contains the defect; at this time, (SX2, SY2) still maintains a fixed relationship with (x2, y2). SX2-SX1=x2-x1, SY2-SY1=y2-y1 are equal.

[0064] 3) Searching for a template in the target image 720, i.e. performing template matching, to obtain a matching position 721;

[0065] 4) Obtain the distance dMX, dMY between the template 711 and the matching position 721, named as the target displacement, specifically:

[0066] dMX=MX2-MX1

[0067] dMX=MY2-MY1

[0068] Where, (MX1, MY1) is the position of the template in the template image (initial position), (MX2, MY2) is the position of the template matched in the target image (matching position), and the unit is pixel;

[0069] 5) Obtain the actual pixel sizes Px and Py, specifically:

[0070]

[0071]

[0072] Among them, the displacement of the mechanical motion platform is (dSX1, dSY1). So far, the method used is basically the same as that described in the above background technology (using a patterned wafer), except that the template is no longer selected from a patterned wafer, but a wafer slot.

[0073] Although this is a feasible solution, in order to prevent the template from running out of the field of view (FOV), that is, outside the target image, the mechanical motion platform moves once and the distance is limited, so the relative error / error of the measurement result is relatively large. This is also a problem in the current existing technology when using patterned wafers for actual pixel size measurement. Let's take a look at the error analysis. The measurement result with error is:

[0074]

[0075]

[0076] Among them, δS is the maximum error of the mechanical motion platform, which is around 0.5μm or 500nm, and δM is the maximum error in image template matching, which is around 0.1 pixel. For example, when the magnification is low / FOV is large, at the first magnification LM, if the theoretical pixel size of the SEM image is 50nm, then δM is around 5nm, corresponding to the SEM image width and height of 512 / 1024 pixels, the value of dMX is at least 200 pixels, and the value of dMY is at least 300 pixels. Therefore, δM is 3 orders of magnitude different from dMX / dMY, and 2 orders of magnitude different from δS, so it can be ignored in the denominator of the above formula, and the actual pixel size is approximately:

[0077]

[0078]

[0079] The corresponding error is approximately:

[0080]

[0081]

[0082] The numerator is fixed, so the denominator can only be made larger to reduce the measurement error.

[0083] On the basis of the above embodiment, it is still the case of the first magnification LM. Furthermore, in the embodiment of the present invention, the electron optical system bias (also called deflection) is combined with a larger stroke of the mechanical motion platform to obtain the actual pixel size with a non-patterned wafer. The control of the bias has a theoretical formula in electron optics, which can be realized for a given electron optical parameter setting. Of course, in actual applications, corresponding calibration is also required to eliminate the influence of the beam spot / image quality after the bias, but its specific content is relatively complex and is a prior art, which is beyond the scope of the present invention and will not be described in detail.

[0084] In this embodiment, when measuring the actual pixel size in the first magnification LM, the deflector in the charged particle beam scanning imaging device is used to deflect the charged particle beam to achieve displacement compensation bias when acquiring the target image, and then the template matching is performed to calculate the actual pixel size. The purpose of achieving displacement compensation bias is to enable the mechanical motion platform to have a larger displacement, thereby reducing the measurement error.

[0085] Let's first look at the first magnification LM. Figure 8 , the process is as follows,

[0086] 1) Collecting a template image 810 containing a defect groove at the position (x1, y1) on the plain wafer 801, and selecting a template 811 from the template image 810; as above, (x1, y1) is the position of the wafer defect groove in the field of view (FOV) of the electron optical system in the wafer coordinate system (for a reference point on the wafer, such as the center of a circle), and the corresponding position of the mechanical motion platform (for example, determined by the grating ruler and the code reader) is (SX1, SY1);

[0087] 2) Move the mechanical motion platform, but not from position (x1, y1) on the wafer to (x2, y2), but let the mechanical motion platform move a longer distance to the position (x21, y21) on the wafer, and the corresponding mechanical motion platform coordinate position is (SX21, SY21). At this time:

[0088] dSX2=x21-x1=SX21-SX1>dSX1

[0089] dSY2=y21-y1=SY21-SY1>dSY1

[0090] At this point, if there is no bias (the SEM column position is fixed on the above equipment), the SEM image collected from (x21, y21) will not include the groove, so it is necessary to add bias to the SEM. Figure 1B The deflector in the invention, taking the electrostatic deflector as an example, can control the electric field in the X / Y direction to deflect the charged particle beam. The size of the offset (dEX, dEY) can just make the SEM contain a notch when collecting the image 821 at the wafer (x21, y21). The accurate determination of the offset can be achieved through calibration (which can be achieved by the existing technology and can be supplemented if necessary, which will not be repeated here). The accuracy can reach sub-pixel, and at least its maximum error δME<1 pixel. The offset is to enable the mechanical motion platform to have a larger displacement, so it can be called "displacement compensation offset" to distinguish it from another offset in the following text.

[0091] 3) Search for the template in the target image 821, that is, perform template matching to obtain the matching position 822. At this time, the actual pixel size measurement value including the error term is:

[0092]

[0093]

[0094] Among them, (dMEX, dMEY) is the pixel difference corresponding to this offset, as mentioned above, it can be obtained through system calibration (the relevant calibration process is beyond the scope of the present invention, if not necessary, no further description), and δME is the corresponding maximum error, as mentioned above, δME < 1 pixel, compared with dMX / dMY is also 2 orders of magnitude smaller, can also be ignored from the denominator. At this time, the actual pixel size is approximately:

[0095]

[0096]

[0097] Among them, (dMX, dMY) is still obtained by template matching. At this time, the error part is approximately:

[0098]

[0099]

[0100] Obviously, the error is smaller than when no bias is added, so the measurement result is more accurate. In addition, it can be seen from the above formula that when the bias increases, the measurement error is further reduced, provided that the maximum error δME caused by the bias does not increase significantly so that it is no longer very small relative to dMX / dMY and can be ignored in the denominator of the above formula, which also gives the limit of displacement compensation bias.

[0101] The above displacement compensation bias has an ideal range, which can be from no bias to the maximum allowable bias Dmax, that is, when measuring the actual pixel size in the first magnification LM, a displacement compensation bias within the range supported by the device is selected. In the present invention, Dmax is defined as the maximum possible system bias that keeps the maximum error dMEX / dMEY in the X / Y direction within a given threshold (e.g., 1 pixel). This is mainly determined by the performance of the device components, and usually can exceed the size of at least multiple image FOVs, micron level. In general, a displacement compensation bias equivalent to 5-10 FOVs is selected (even an offset equivalent to 2 FOVs is a significant improvement over the prior art). The Dmax value on a specific device can be obtained by system calibration (the specific calibration method is beyond the scope of the present invention).

[0102] In this embodiment, the actual pixel sizes of each level to be measured are measured one by one in the first magnification LM from large to small, and then the actual pixel sizes of each level under the second magnification HM are measured.

[0103] When entering the measurement of the actual pixel size of the second magnification HM, it also starts from the lower magnification / larger FOV to the highest magnification / smallest FOV.

[0104] When measuring the actual pixel size at the second magnification HM, the method can be similar to that at the first magnification LM, which is also based on the positioning / template matching of the wafer notch. However, the most common problem is that the FOV / image does not contain the entire wafer notch, refer to Fig. 9 , where images 910 , 911 , and 912 respectively include the middle, left, and right parts of the wafer notch instead of the entirety, making template matching difficult (no matching or inaccurate results).

[0105] To add, the reasons are as follows: 1) As mentioned above, the wafer notch appears rough in the SEM image with a higher magnification (this is determined by its production standard); 2) There is often irregular background pattern interference from the tray (e-chuck) on the edge of the wafer; 3) The wafer edge is made in different ways (mainly i. Blunt Nosed and ii. Bullet Shaped), which leads to different edge rings in the SEM image, making it difficult to locate the notch by simple curve / arc recognition / matching; 4) The noise in the image is enhanced under high magnification / small FOV, so the most reliable identification and positioning method is template matching of grayscale images (not excluding the use of edge / gradient images), such as the normalized cross correlation (NCC) algorithm. The NCC operation of a single frame image is as follows:

[0106]

[0107] The values ​​are between [0, 1]. Where T represents the width and height of the template part, which are w and h respectively, and the total number of pixels N = w×h; I represents the target image, with a width and height of W and H respectively; ∑T in the formula is abbreviation, j and i traverse j = 0, ... h + 1, i = = 0, ... w + 1, that is, all pixels in the template (here the loop starts from 0, which is the habit of C-type computer languages), ∑I is The abbreviation of ∑IT is In short, v and u finally traverse v=0,…,H–h+1 and u=0,…,W–w+1, and obtain all r[u,v], forming a cross-correlation surface graph R, whose width and height are (W-w+1,H-h+1), and the peak value corresponds to the best match. There are many other template matching methods similar to the NCC method for similarity, which will not be described here.

[0108] Taking into account that the wafer defect is often incomplete in the image at the second magnification HM, one embodiment of the present invention adopts a method of biasing the scanning electron beam, which is different from the aforementioned "displacement compensation bias". In addition, the bias added to the electron optical system here is smaller and local, hereinafter referred to as "local bias", and the displacement caused by the bias can be obtained through system calibration.

[0109] In this embodiment, for any magnification of the second magnification HM, images without bias and with bias are collected respectively, so that the two frames of images have different types of key parts of the notch, and the key parts include the arc top, left corner and right corner of the notch; the offset required for measuring the actual pixel size corresponding to the second magnification HM is determined according to the offset between the two frames of images. Fig. 9 In actual pixel measurement, the second magnification HM part may include multiple actual pixels to be measured / FOV, but no matter how large the FOV is, the size of the local offset is determined by the fact that at least two of the three key parts in the entire notch must be included in the image under the FOV. The three key parts are the arc top 915, the left corner 916 and the right corner 917 of the notch. For example, according to the theoretical pixel size, the known notch size and the position of the notch on the wafer, it is easy to make the unbiased template image include one of the above three key parts, such as the arc top 915, and the biased template image needs to be able to include its left corner 916 or right corner 917. Since the position requirement is very loose, a difference of dozens of pixels is not a problem, and as mentioned above, the actual size of the notch is always fixed, so the offset of the system calibrated at different theoretical magnifications is easy to calculate. As for why two key parts are needed instead of one, it is because when the key part is used alone as a template during HM, the features are insufficient and the curvature of the wafer edge is not large, that is, the change is relatively gentle, which is not conducive to template matching. The combination of template images can greatly improve the reliability and success rate of template matching.

[0110] Wherein, when obtaining the measurement of each actual pixel size in the second magnification HM, at least two frames of template images are collected each time, including at least one frame of unbiased template image and at least one frame of template image that is locally biased by deflecting the charged particle beam by a deflector in a charged particle beam scanning imaging device, and a corresponding number of target images are collected so that the number of unbiased target images and unbiased template images is the same, and the number of biased target images and biased template images is the same, and the degree of bias is kept the same as the degree of bias of the corresponding template image, and then the template is used to perform template matching in the target image to obtain the actual pixel size.

[0111] In one embodiment of the present invention, the template images are stitched together and a template is selected from the stitched template image as a stitching template, so that the stitching template includes the templates in the template images before stitching, the target images are stitched together, and the stitching template is used to perform template matching in the stitched target image to obtain the actual pixel size. Fig.10As a result, when capturing the template image or capturing the target image while moving the wafer (and possibly applying displacement compensation offset), two frames of images are captured, one of which is when the system does not apply a local offset, and the other is when a local offset is applied. For example, a template image 1010 without a local offset can be captured, in which there is a template area (i.e., template) 1011, and then a template image 1020 with a local offset can be captured, in which there is a template area 1021, and the template areas are spliced ​​to form a spliced ​​template 1030, which can be used for template matching (the target image also has a corresponding offset and splicing). When a situation similar to the first magnification LM mentioned above is encountered, that is, when the wafer is moved to the position (x2, y2) (without displacement compensation bias) or (x21, y21) (with displacement compensation bias, a better method), two frames of images are also captured as target images, wherein the first frame is a target image 1040 without local bias, and the second frame has a target image 1042 with the same degree of local bias as when the template image was captured, forming a stitched target image 1045. In this way, the search and matching is performed from the stitching template 1030 to the stitching target image 1045.

[0112] In this embodiment, the stitching template 1030 and the stitching target image 1045 in the figure are both rectangular. This is because the usual template matching, such as the aforementioned NCC algorithm, uses rectangles for convenient / fast calculation by computer. Taking the stitching target image 1045 as an example, in fact, in addition to the original target image 1040 and target image 1042 parts that are useful for template matching, there are other parts that are redundant and even dilute the truly useful feature parts in the image, which is not conducive to template matching. Therefore, when the stitching template is used to perform template matching in the stitching target image 1045, the non-template area in the stitching template is divided into a non-template matching area DCA, reference Fig.11 , the two parts of area 1111 and area 1112 in the splicing template 1110 can be eliminated, that is, defined as the Don't Care Area (DCA), where the pixels do not participate in template matching, and the number of DCAs is unlimited. Furthermore, according to the range of the useful part (slot-missing contour curve) in the figure, DCAs can be further increased, for example Fig.11 The regions 1112 and 1122 in FIG. 1112 and 1122 in FIG. 1112 may be regular geometric shapes such as rectangles, such as region 1112. Fig.10 Regions 1031 and 1032 in the stitched template 1030 do not belong to the template parts in the original separate template image and can also be used as DCA.

[0113] When performing template matching with DCA, taking NCC as an example, the range of all sums in the above NCC formula, such as ∑T, ∑I, ∑IT, does not include the pixels in DCA, that is, the traversal conditions in the above formula are modified to j=0,…h+1, i==0,…w+1, That is, the pixels in DCA do not participate in the summation calculations in r, and the final r(u, v) obtained is the cross-correlation result without DCA. Therefore, the contribution ratio of the feature (edge ​​part of the wafer notch) is higher and the matching result is more reliable.

[0114] In one embodiment of the present invention, the template stitching and the target image stitching do not necessarily require the actual images to be stitched and then template matched. Instead, the template matching can be performed separately first, and then the matching results can be stitched / integrated. This can reduce the error caused by the image stitching itself (since the stitching here cannot be based on the feature matching of the overlap and overlap in the image, and is also based on the bias), although it is also in the order of δME, which is relatively small. The method is to use the template in the unbiased template image to perform template matching in the corresponding unbiased target image, and use the template in the biased template image to perform template matching in the corresponding biased target image, respectively obtain independent template matching results, and then integrate the global template matching results, determine the target displacement based on the comparison result of the global template matching result and the preset matching threshold, and calculate the actual pixel size. The geometric mean of the independent template matching results is used as the global template matching result. Among them, two templates (one without local bias and one with local bias) are used, for example, template 1011 and template 1021 are used to match the corresponding target images 1040 and 1042 respectively, for example, the above-mentioned NCC method is used to obtain the respective results R1 and R2, and then the two are integrated, for example, the geometric mean R = √ (R1 × R2) is used to obtain the final cross-correlation surface graph R, and then the peak value in R is used as the best matching position, and its value is still between [0, 1]. This method is simpler and more flexible.

[0115] In addition, if Fig.12 As shown, the templates 1232 and 1242 in the template images 1230 and 1240 may have no overlapping portions.

[0116] Supplementary explanation: Based on the current wafer slot size and the maximum magnification / minimum FOV possible values ​​of the SEM image, it is generally not necessary to stitch the template area or the target image. Fig.13 As in the above, more than three frames of images 1310, 1320, and 1330 are stitched together, because the pixel size of the current device will not reach the sub-nanometer level. However, the present invention does not impose corresponding restrictions on the number of local stitching offsets / stitched images, and more than three frames of images can also be stitched together.

[0117] Based on the above calculation formula of actual pixel size Px, Py (including error), assuming that the template only involves one local offset, that is, limited to the splicing of two frames of images, and assuming that the maximum error caused by the local offset still does not exceed δME (still 2 orders of magnitude smaller than dMX / dMY), the actual pixel size measurement including the error term is

[0118]

[0119]

[0120] Among them, dMX and dMY are slightly different from the previous ones. They are the final matching results from the spliced ​​target image, regardless of whether the actual spliced ​​image is matched with the template or the template is matched first and then the matching results are integrated. Similar to the previous error analysis, because δME is still at least 2 orders of magnitude smaller than dMX / dMY, it is still close to the actual pixel size:

[0121]

[0122]

[0123] Same result as before, and an approximate error estimate:

[0124]

[0125]

[0126] The result is still the same as the previous one. The advantage of this method of using local displacement offset combined with template matching image stitching is that when the magnification of the second magnification HM is large / the FOV is small relative to the wafer slot size, effective template matching can still be performed to support the measurement of the actual pixel size.

[0127] In this way, the actual pixel sizes of each level in the second magnification HM are measured one by one from large to small according to the actual pixel size to be measured, thereby completing all the required actual pixel measurement tasks.

[0128] In summary, it can be seen from the above discussion that the method in the above embodiment of the present invention can successfully solve the problem of determining the actual pixel size of the charged particle beam scanning imaging device on the semiconductor IC production line when a large number of non-patterned wafers are used in the prior art, making it possible to accurately and effectively measure the actual pixel size of the non-patterned wafer, without the need for special wafers or special samples to measure the actual pixel size, greatly reducing the cost of use. It further improves the measurement accuracy and success rate under the second magnification HM, and also reduces the measurement error.

[0129] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A method for obtaining the actual pixel size on a non-patterned wafer, characterized in that: include: The unpatterned wafer is placed on a mechanical motion platform of a charged particle beam scanning imaging device; For the wafer, the magnifications corresponding to all actual pixel sizes to be measured are divided into a first magnification and a second magnification with a higher magnification, and the first magnification and the second magnification both include one or more different magnification values; Firstly, measuring the actual pixel sizes at the first magnification, and then measuring the actual pixel sizes at the second magnification, and both measurements are performed in the order of relatively low to high magnification; For each actual pixel size to be measured, a template image is collected at the notch of the wafer, the wafer is moved in a predetermined direction and distance by the mechanical motion platform, a target image is collected, a template is obtained from the template image, and the template is used to perform template matching in the target image, and then the actual pixel size is calculated based on the moving distance of the mechanical motion platform and the target displacement obtained by the template matching; When measuring the actual pixel size in the first magnification, the deflector in the charged particle beam scanning imaging device is used to deflect the charged particle beam to achieve displacement compensation bias when acquiring the target image, and then the template matching is performed to calculate the actual pixel size.

2. The method according to claim 1, characterized in that When distinguishing between the first magnification and the second magnification, images of each magnification corresponding to the actual pixel size to be measured are collected, and the area ratio of the defect of the wafer in the images collected at each magnification is compared with a preset threshold, and the magnification when the threshold is reached or exceeded is determined as the second magnification, otherwise it is the first magnification.

3. The method according to claim 1, characterized in that When measuring the actual pixel sizes in the first magnification, a displacement compensation bias within the range supported by the device is selected.

4. The method according to claim 1, characterized in that: When obtaining the measurement of each actual pixel size in the second magnification, at least two frames of template images are collected each time, including at least one frame of unbiased template image and at least one frame of template image that is biased by deflecting the charged particle beam by a deflector in a charged particle beam scanning imaging device, and a corresponding number of target images are collected so that the number of unbiased target images and unbiased template images is the same, and the number of biased target images and biased template images is the same, and the degree of bias is kept the same as the degree of bias of the corresponding template image, and then the template is used to perform template matching in the target image to obtain the actual pixel size.

5. The method according to claim 4, characterized in that The template images are stitched together and a template is selected from the stitched template images as a stitching template, so that the stitching template includes the templates in the template images before stitching, the target images are stitched together, and the stitching template is used to perform template matching in the stitched target image to obtain the actual pixel size.

6. The method according to claim 5, characterized in that When the stitching template is used to perform template matching in the stitched target image, the non-template area in the stitching template is divided into an area not participating in template matching, and the pixels in the area not participating in template matching do not participate in template matching.

7. The method according to claim 4, characterized in that For any magnification of the second magnification, images without bias and with bias are collected respectively, so that the two frames of images have different types of key parts of the defect, and the key parts include the arc top, left corner and right corner of the defect; the offset required for measuring the actual pixel size corresponding to the second magnification is determined according to the offset between the two frames of images.

8. The method according to claim 4, characterized in that Use the template in the unbiased template image to perform template matching in the corresponding unbiased target image, and use the template in the biased template image to perform template matching in the corresponding biased target image, respectively obtain independent template matching results, and then integrate the global template matching result, determine the target displacement according to the comparison result of the global template matching result and the preset matching threshold, and calculate the actual pixel size.

9. The method according to claim 8, characterized in that The geometric mean of the independent template matching results is used as the global template matching result.

Images