Method for manufacturing a printed circuit board

Abstract

A method for manufacturing a printed circuit board is disclosed. In the method, a slot is formed in a substrate having at least three layers, the slot extending through at least two of the layers. The slot has a length and a width, the length being greater than the width. The substrate is coated with a conductive layer around the sidewalls of the slot. Subsequently, the conductive layer is separated into at least two sections that are electrically insulated along the sidewalls of the substrate.

Description

[0001] This application is a divisional application of the Chinese invention patent application filed on August 21, 2017 with application number 201780064457.0.

[0002] Incorporation by reference

[0003] The entire contents of U.S. Provisional Patent Application No. 62 / 377,195, filed on August 19, 2016, are incorporated herein by reference. Background Art

[0004] Printed circuit boards (PCBs) are well known in the art and are used to form a wide variety of electrical devices. A printed circuit board is typically composed of multiple copper conductor layers interconnected by metallized holes. The metallized holes can be in different forms such as microvias, buried vias, blind vias, and through holes. In general, a hole has a single function: the plating in the hole connects all the copper layers exposed in the hole to each other, or the hole is used for component insertion.

[0005] Vias also have dual purposes such as providing interlayer interconnection and through-hole component mounting. However, the development of surface mount component technology has reduced the need to use holes for through-hole component mounting and has resulted in vias primarily providing interlayer interconnection, i.e., vias.

[0006] However, there has been a trend to provide PCBs with higher and higher circuit densities and higher and higher circuit speeds. Many of these designs group together some densely packed high input / output components. As a result, many PCBs will have very dense areas around the high input / output components, while the rest of the PCB typically has a lower density. These very dense areas result in an increase in the number of layers in the PCB, which increases the cost of the PCB.

[0007] To help meet the demand for increasing circuit density, it has been proposed to provide more than one independent signal path or connection in a single via. However, there are limitations on the via. The surface area of ​​the via is too large for the new generation of components, and the downward limitation of the hole size causes yield problems in drilling, cleaning and plating of the via. Therefore, there is a need for a structure with a reduced surface area having electrically isolated segments. The present invention is directed to such an improved method of manufacturing a PCB. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one or more embodiments described herein and, together with the description, explain these embodiments. The drawings are not intended to be drawn to scale, and certain features and certain views of the drawings may be exaggerated, shown in scale, or shown schematically for the sake of clarity and conciseness. Not every component is labeled in every drawing. The same reference numerals in the drawings may represent and refer to the same or similar elements or functions. In the drawings:

[0009] Figure 1 is a top plan view of a portion of a printed circuit board constructed in accordance with the present invention.

[0010] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H and Fig.2I Shown in the formation Figure 1 The sequential steps utilized in a method of printing a circuit board are shown.

[0011] Figure 3 is a top plan view of a portion of a printed circuit board constructed in accordance with the present invention.

[0012] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H and Fig. 4I Shown is the method for forming Figure 3 An exemplary sequential step of a printed circuit board is shown.

[0013] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F , Figure 5G and Figure 5H Shown in the formation Figure 3 The sequential steps utilized in yet another method of printing a circuit board are shown.

[0014] Figures 6 to 16 are various partial perspective views of an exemplary substrate having a vertical conductive structure (VCS) constructed in accordance with the present disclosure.

[0015] Fig.17is another example of a substrate having a vertical conductive structure constructed according to the present invention, wherein the vertical conductive structure has conductive segments extending to different layers and depths within the substrate. The conductive segments extending to a certain layer are blind structures. The vertical conductive structure also has conductive segments extending through the substrate, which are through structures. Fig.17 When a vertical conductive structure is formed, a slot is formed having portions extending to certain layers and other portions extending through the substrate, which enhances the flow of fluid through the slot when plating and other materials are applied to the substrate within the slot.

[0016] Fig.18 is yet another example of a substrate having a vertical conductive structure constructed in accordance with the present disclosure, wherein the vertical conductive structure has one or more traces extending along a sidewall in a non-linear configuration.

[0017] Fig.19 is yet another example of a substrate having a vertical conductive structure constructed in accordance with the present disclosure, wherein the vertical conductive structure has a plurality of traces extending along the sidewalls in a non-parallel configuration, and at least one of the traces extends at an angle less than or greater than 90 degrees relative to the upper surface.

[0018] Fig. 20 is a cross-sectional view of a substrate having a slot in which a router bit is arranged and guided to form a Fig.18 or Fig.19 The milling cutter in this example may have a spherical front end, but it may also have any other shaped front end extending outwardly from the shaft of the milling cutter so that when the front end engages the side wall, the shaft of the milling cutter does not touch the side wall of the VCS. The side walls of the VCS do not need to be perpendicular to the upper surface of the substrate, or the side walls of the VCS do not need to be parallel to each other, but can be angled to each other in the form of a tapered slot.

[0019] Fig.21 yes Fig. 20 FIG. 1 is a top plan view of a base plate showing a milling cutter positioned within a slot of the base plate.

[0020] Fig. 22 is a cross-sectional view of another example of a substrate having a vertical conductive structure constructed according to the present disclosure, wherein the vertical conductive structure is constructed as a blind structure (blind configuration) having a bottom, which is constructed of a dielectric material so as to electrically insulate a first conductive segment and a second conductive segment of the vertical conductive structure.

[0021] Fig.23 yes Fig. 22The cross-sectional view of the substrate and the vertical conductive structure shown in FIG. 1 has a filling material in the vertical conductive structure and one or more layers covering the vertical conductive structure so that Fig.23 The vertical conductive structure in the embodiment is in a buried configuration.

[0022] Fig.24 is a top plan view of another example of a substrate having a vertical conductive structure constructed according to the present disclosure, wherein the vertical conductive structure is constructed as a blind structure with a bottom and is provided with a nonlinear shape.

[0023] 25a-25e are partial perspective views of another example of a printed circuit board having vertical conductive structures including several blind structures to different depths into the printed circuit board and a through structure on the right side.

[0024] Fig.26 is a partial perspective view of an exemplary embodiment of a printed circuit board having a vertical conductive structure according to the present disclosure.

[0025] Fig. 27 yes Fig.26 A partial perspective view of a vertical conductive structure.

[0026] Fig.28 is a partial top perspective view of an exemplary embodiment of a vertical conductive structure according to the present disclosure.

[0027] Fig.29 is a partial top perspective view of an exemplary embodiment of a printed circuit board having a combination of vertical conductive structures according to the present disclosure.

[0028] Fig.30 yes Fig.29 An end perspective view of a combination of vertical conductive structures.

[0029] Fig.31 is a partial perspective view of an exemplary embodiment of a printed circuit board having a combination of vertical conductive structures according to the present disclosure.

[0030] Fig.32 is a schematic diagram of an exemplary embodiment of a process for forming a slot in a circuit board according to the present disclosure.

[0031] Fig.33 is a schematic diagram of an exemplary embodiment of another process for forming a slot in a circuit board according to the present disclosure.

[0032] Fig.34 is a schematic diagram of an exemplary embodiment of yet another process for forming a slot in a circuit board according to the present disclosure.

[0033] Fig.35is a schematic plan view of a circuit board having multiple vertical conductive structures attached to a component using a ball grid array.

[0034] Fig.36 is a schematic plan view of a circuit board having a plurality of diagonally disposed vertical conductive structures attached to a component using a ball grid array in accordance with the present disclosure.

[0035] Fig.37 is a schematic plan view of a circuit board in which vertical conductive structures are diagonally arranged in accordance with the present disclosure.

[0036] Fig.38 is another schematic plan view of a circuit board having diagonally arranged conductive structures according to the present disclosure.

[0037] Fig.39 is a schematic plan view of another example of a circuit board in which conductive structures are diagonally arranged in accordance with the present disclosure.

[0038] Fig.40 is a schematic plan view of another example of a circuit board in which the conductive structures are arranged diagonally according to the present invention.

[0039] Fig.41 is a partial perspective view of a circuit board constructed in accordance with the present disclosure, wherein filler material (discussed below) is not shown in order to more clearly illustrate other components.

[0040] Fig.42 yes Fig.41 A top partial perspective view of a circuit board of FIG. 1 , wherein filler material (discussed below) is not shown in order to more clearly illustrate other components.

[0041] Fig.43 yes Fig.41 A top plan view of a circuit board showing the fill material. DETAILED DESCRIPTION

[0042] Before explaining at least one embodiment of the inventive concept disclosed in detail herein, it should be understood that the inventive concept is not limited in its application to the details of the arrangement and construction of the components, or the steps, or methods set forth in the following description or shown in the accompanying drawings. The inventive concept disclosed herein can have other embodiments, or can be practiced or implemented in various ways. Moreover, it should be understood that the words and terms used herein are for descriptive purposes and should not be construed as limiting in any way the inventive concept disclosed and claimed herein.

[0043] In the following detailed description of the embodiments of the inventive concept, many specific details are set forth to provide a more comprehensive understanding of the inventive concept. However, it will be apparent to one of ordinary skill in the art that the inventive concept of the present invention can be practiced without these specific details. In other cases, well-known features are not described in detail to avoid unnecessarily complicating the present invention.

[0044] As used herein, the terms "comprises," "comprising," "includes," "having," "having," and any variations thereof are intended to cover a non-exclusive inclusion. For example, a process, method, article, or apparatus that includes a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherently present therein.

[0045] Unless expressly stated otherwise, "or" refers to an inclusive or rather than an exclusive or. For example, the condition A or B satisfies any of the following conditions: A is true (or exists) and B is false (or does not exist), A is false (or does not exist) and B is true (or exists), and both A and B are true (or exist).

[0046] In addition, "a" or "an" is used to describe elements and components of the embodiments disclosed herein. This is only for convenience and to give a general sense of the inventive concept. The description should be understood to include one or at least one, and unless it is obvious that it is otherwise meant, the singular also includes the plural.

[0047] As used herein, qualifiers such as "substantially," "about," "approximately," and combinations and variations thereof are intended to include not only the exact quantities or values ​​they qualify, but also some slight deviations from the exact quantities or values ​​that may occur due to, for example, manufacturing tolerances, measurement errors, wear and tear, stresses exerted on various components, and combinations thereof.

[0048] Finally, as used herein, any reference to "one embodiment" or "an embodiment" means that a particular element, feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

[0049] As used herein, the term "conductive material" refers to a type of material that allows electric current to flow in one or more directions. In metals such as copper or aluminum, the flow of electric current is generated by the movement of mobile charged particles called electrons. In other types of conductive materials, the flow of electric current is generated by the movement of positive charges such as the cationic electrolytes of batteries or mobile protons such as proton conductors in fuel cells. Examples of conductive materials include copper, aluminum, gold, silver, carbon, palladium, nickel, zinc, and combinations thereof.

[0050] Referring now to the drawings, and in particular to Figure 1 The printed circuit board constructed according to the present disclosure is Figure 1 The printed circuit board 10 is shown in FIG. 1 and is indicated by the general reference numeral 10. The printed circuit board 10 is provided with a substrate 12, a plurality of contact pads 14, and a plurality of vertical conductive structures 16 (for clarity, the vertical conductive structures 16 are shown in FIG. 1 ). Figure 1 16a, 16b and 16c are indicated in the vertical conductive structure 16). The structure and function of each of the vertical conductive structures 16a, 16b and 16c are similar. Therefore, only the vertical conductive structure 16a is described in detail herein. The vertical conductive structure 16a is provided with at least two electrically insulated conductive segments 18a and 18b. Although each of the conductive segments 18a and 18b is connected to the spaced contact pads 14 via traces 20, the conductive segments 18a and 18b may also be directly connected to the contact pads 14. The conductive segments 18a and 18b are electrically insulated by a non-conductive filling material 22 centrally arranged between the conductive segments 18a and 18b. As will be discussed in more detail below, the conductive segments 18a and 18b are typically formed by a conductive plating layer that has been separated or cut apart by forming at least two spaced apart holes 24 and 26 (which may also be referred to as first holes 24 and second holes 26 herein).

[0051] Substrate 12 may be any material or device that can be used to support electrical components, conductors, etc. In a preferred embodiment, substrate 12 includes multiple layers of interleaved conductive paths (or traces) and insulators.

[0052] The contact pad 14 may be any type of material or device capable of providing an electrical connection or joint with an external component such as an integrated circuit. For example, the contact pad 14 may be a surface mount contact, or a ball grid array contact, or a common mode contact defined by a solder mask. Depending on the optimal routing and bonding criteria, the shape of the contact pad 14 may be circular, oval, or polygonal.

[0053] The vertical conductive structure (VCS) 16a can be used to transmit various types of signals including differential or common mode signals, for example. Exemplary types of signals include analog signals, digital signals, fixed voltage signals, or power grounding. In some cases, pairs of conductive segments 18 can be used together to transmit differential or common mode signals. In the case of differential type signals, the paths or parallel transmission of two signals using conventional technology will be distorted due to the separation of the signal by the path. In the case of the vertical conductive structure 16, the signal / trace is kept close together and has the minimum distortion of the signal. Through the matching dielectric filling material, the coupling effect can simulate the wide side coupling circuit. This, combined with the signal impedance on the inner and outer layers, can potentially significantly reduce the impact of the interference of the via stub on the inductance and capacitance. Compared with the traditional single signal through the hole-type path, the use of controlled depth drilling or blind via structure to reduce the columnar part in the Z direction of the vertical conductive structure will further reduce the interference of the vertical conductive structure 16a. An example of a system for reducing stub portions in the Z direction of a via is disclosed in US Patent Application No. 10 / 944,583, filed September 17, 2004, the entire contents of which are incorporated herein by reference.

[0054] The typical drilling size for through-hole and buried hole is in the range of 0.35mm to 0.2mm, and the current trend in the field of printed circuit board manufacturing is to reduce the drilling size to further adapt to smaller pin spacing in the new generation of components. In addition, due to the increasing number of I / O, the current trend in the field of printed circuit board manufacturing is to increase the number of layers in the printed circuit board, which makes the printed circuit board thicker. The combination of thicker printed circuit boards and smaller holes makes the yield process of traditional printed circuit board manufacturing technology lower. In the art, the ratio of PCB thickness to drilling size is called aspect ratio. When using an aspect ratio greater than 12, it is difficult for traditional printed circuit board manufacturing processes to plate the passage. However, if the surface area of ​​the through-hole passage constructed according to the traditional printed circuit board manufacturing process is compared with the surface area of ​​the vertical conductive structure 16, it will be found that the difference in A / R (by surface area) is very large, which shows an advantage of the vertical conductive structure 16.

[0055]

[0056] *Since VCS components do not have a diameter, A / R by diameter cannot be calculated to compare to through holes, so surface area is used as a comparison.

[0057] In practice, in order to accommodate more conductive elements, the vertical conductive structure 16 can be longer than listed in the above table. This will create a larger surface area that makes plating easier, and a larger surface area also makes the plating system simpler and more productive, thereby reducing the overall cost.

[0058] Conductive segments 18a and 18b may be constructed of any type of conductive material suitable for providing an electrical connection between an internal trace or conductive path and another internal or external conductive path or trace, with or without external contact pads. Typically, conductive segments 18a and 18b are constructed of copper. However, it should be understood that other materials and / or alloys of materials and / or combinations of different materials may also be used in forming conductive segments 18a and 18b.

[0059] Traces 20 are constructed of a conductive material such as gold or copper.

[0060] Filling material 22 is optional, but is helpful when space is an issue because it allows contact pad 14 to be positioned above conductive segment 18a and conductive segment 18b. When filling material 22 is used, it acts as a dielectric between the two conductive segments 18a and 18b. The dielectric between the two conductive segments 18a and 18b can be adjusted by changing the size of the channel or slot connecting hole 24 and hole 26 or by changing the material forming filling material 22.

[0061] The filling material 22 may be formed of a material that is chemically and thermally compatible with respect to the substrate 12 manufacturing process and materials, and is desirably compatible with the various plating solutions used. Furthermore, the filling material 22 should exhibit flow characteristics sufficient to fill a small aspect ratio plated through hole (or blind via), and have the ability to transform, solidify, or convert to a solid material with minimal volume change after filling. The thermal expansion of the filling material 22 should be compatible with the rest of the substrate 12. In addition, the filling material 22 should exhibit good adhesion to the conductive segment 18.

[0062] Now refer to FIG. 2A to FIG. 2IDescribe the sequential steps followed to accurately form vertical conductive structures 16a, 16b and 16c in substrate 12. FIG. 2a shows an insulator substrate 40 such as a printed circuit board or a flexible film substrate. As shown in FIG. 2a, two spaced holes 41 and 43 are formed in the insulator substrate 40 at a desired position and a desired angle relative to the upper surface of the insulator substrate 40. For example, the holes 41 and 43 can be formed at an angle substantially perpendicular to the upper surface of the insulator substrate 40. The holes 41 and 43 include a diameter D1, which can be the same or different for each of the holes 41 and 43. The holes 41 and 43 can be formed by using a drilling method, but any conventional method such as milling, punching, laser drilling, water cutting, or light definition can also be used. The diameter D1 of the holes 41 and 43 can be any size compatible with other design requirements of the insulator substrate 40. In an embodiment, the diameter D1 of the holes 41 and 43 can be in a range between about 0.05 mm and about 0.5 mm. In some embodiments, the diameter D1 of the holes 41 and 43 can be in a range between about 0.1 mm and about 0.5 mm. Depending on the accuracy of the processing, the spacing between the holes 41 and 43 can be 0.1 mm to 0.5 mm, or smaller or larger. All or substantially all of the openings or holes in the insulator substrate 40 can be formed at the same time, regardless of whether the openings or holes are ultimately formed as the vertical conductive structure 16 described below. This avoids misalignment between the spaced-apart hole forming process and the subsequently formed wiring pattern, especially from tolerance accumulation, which is formed by using one or more masks that must be aligned with the vertical conductive structure 16. As the wiring patterns of printed circuit boards become increasingly fine, this factor is particularly important.

[0063] Afterwards, if Figure 2B and Figure 2C As shown, at least a portion of the material between holes 41 and 43 is removed by forming slot 45 in substrate 40 . Figure 2C It is along Figure 2B 4. The narrow groove 45 can have a width W that is smaller than the diameter D1 of the two spaced holes 41 and 43. However, the width W of the narrow groove 45 and the diameter D1 of the two spaced holes 41 and 43 can be the same. In an embodiment, the diameter D1 of the two spaced holes 41 and 43 can be smaller than the width W of the narrow groove 45 and can be used as a guide hole. The narrow groove 45 intersects with the two spaced holes 41 and 43 in a manner such that the side wall 46 is formed with a dog-bone-shaped periphery. The narrow groove 45 can be formed by using a drilling method, but any conventional method such as routing, milling, punching, laser drilling / cutting / ablation, water cutting, or light definition can also be used.

[0064] Afterwards, if Figure 2D The cross-sectional view and Figure 2E As shown in the top plan view of , a conductive seed layer (not shown) is added, followed by a conductive layer 47 formed of a first conductive material, which is deposited on the surface of the substrate 40 and the sidewalls 46 to leave an opening in the substrate 40 surrounded by the conductive layer 47. In an embodiment, the first conductive material is copper and can be deposited to a thickness in a range between about 2.54 microns and about 25 microns, deposited to a thickness greater than about 5 microns, and deposited to a thickness of about 15 to 25 microns. For a through structure, the thickness can be in the range of about 20 to 25 microns, while for a blind structure, the thickness can be, for example, about 15 microns. The conductive layer 47 on the sidewalls 46 can be thick enough to provide a robust mechanical structure that can withstand the thermal fluctuations and aggressive treatments to which the printed circuit board is subjected during subsequent component assembly and use.

[0065] In an embodiment, the conductive layer 47 is deposited using an electrolytic plating process. The electrolytic process may be followed by a surface treatment step involving a direct metallization process or an electroless process. The surface treatment step includes depositing a thin layer of conductive seed that sensitizes the surface and facilitates adhesion of the conductive layer 47 to the sidewalls 46. Direct metallization includes depositing a thin layer of conductive molecules (not shown) on the substrate surface and vertical conductive structure sidewalls 46 before depositing the conductive layer 47. The conductive layer 47 may also be palladium or platinum. The process avoids the typical catalytic deposition of copper, making the device more economically feasible.

[0066] The electroless surface treatment process includes depositing a thin conductive seed layer (not shown), which may be copper, on the surface of substrate 40 and sidewalls 46 to a thickness in a range between about 30 microns and about 200 microns, and in one embodiment, to a thickness in a range between about 70 microns and about 80 microns before depositing conductive layer 47.

[0067] The surface treatment prior to the electrolytic deposition may result in a non-linear distribution of the conductive layer 47 on the sidewall 46 due to the natural tendency of the thickness of the conductive layer 47 to decrease with increasing depth of the sidewall 46 .

[0068] Then, if Figure 2FAs shown, first hole 24 and second hole 26 are formed in substrate 40, each hole 24 and 26 overlapping sidewall 46 and conductive layer 47. Each hole 24 and 26 removes a portion of conductive layer 47 on sidewall 46 so that holes 24 and 26 cooperate to form segments 18a and 18b electrically insulated from conductive layer 47. First hole 24 and second hole 26 may be concentric with hole 41 and hole 43, but diameter D2 thereof is preferably greater than diameter D1 of hole 41 and hole 43. When drilling, using a drill bit having a diameter D2 greater than diameter D1 allows the drill bit to be substantially evenly supported by substrate 40 when conductive layer 47 is removed, thereby helping to prevent lateral deflection during drilling, and eliminating the need to fill the void surrounded by conductive layer 47 with a filler material prior to drilling.

[0069] The chamber 48 can be formed by the substrate 40 and the electrically insulated segments 18a and 18b. The first hole 24, the second hole 26 and the chamber 48 cooperate to form a final slot 50. In a non-exclusive embodiment, the final slot 50 can have one of the following width-to-length ratios: 1 to 2; 1 to 3; 1 to 1.5; and, 1 to 1.6. In a non-exclusive embodiment, the final slot 50 has one of the following width-to-length dimensions and ratios:

[0070] The final length of the slot 50 The final width of the slot 50 is ratio 0.30mm 0.15mm 2 0.45mm 0.15mm 3 0.30mm 0.20mm 1.5 0.40mm 0.25mm 1.6 0.75mm 0.25mm 3 0.50mm 0.25mm 2

[0071] like Figure 2G As shown, after the first hole 24 and the second hole 26 are formed in the substrate 40, the filler material 22 (filler material 22 is optional since air is used as a dielectric) can be introduced into the cavity 48 formed by the substrate 40 and the electrically insulated segments 18a and 18b. The filler material 22 can be introduced into the cavity 48 by any suitable process. For example, the filler material 22 can be introduced into the cavity 48 by a squeegee or a stencil or screen with or without a pattern. Other means of introducing the filler material 22 into the cavity 48 such as a roller, a pressurized head that introduces a pressurized supply of the filler material 22 into the cavity 48, a syringe with a needle inserted into the cavity 48, inkjet printing, or any other means capable of filling the cavity 48 with the filler material 22 can also be used. The filler material 22 can be located within the cavity 48 so as to avoid the formation of bubbles or pits.

[0072] If fill material 22 is introduced into cavity 48 and fill material 22 has cured, an abrasive, brush, or other type of planarization device may be used to planarize substrate 40 so that the outer ends of fill material 22 are substantially coplanar with the outer surface of conductive layer 47 .

[0073] Then, if Figure 2HAs shown, one or more pattern plates 60 are disposed on the first surface 62 and / or the second surface 64 of the substrate 40. When plating on the surface of the cured fill material 22 and the electrically insulated segments 18a and 18b, the one or more pattern plates 60 include a second conductive layer. This will be necessary when the surface mount contact area overlaps the area of ​​the substrate 40 having the cured fill material 22 and the electrically insulated segments 18a and 18b. Once the area is plated to the optimal thickness, the substrate 40 is passed through a process commonly referred to as a strip-etch-strip (SES) line. n An example of a "strip-etch-strip" line is disclosed in U.S. Pat. No. 6,074,561, the entire contents of which are incorporated herein by reference. Fig.2I As shown, the strip-etch-strip process removes portions of one or more pattern plates 60, portions of layer 47, and the base copper from the laminate / copper foil.

[0074] Subsequently, the substrate 40 may be processed with a solder mask, a surface finish such as ENIG (Electroless Nickel Immersion Gold), etc., thereby manufacturing the printed circuit board 10. The solder mask may be any suitable solder mask such as a smooth type.

[0075] Reference now Figure 3 According to a second embodiment of the printed circuit board constructed according to the present invention, Figure 3 1 and indicated by the general reference numeral 10a. The printed circuit board 10a is provided with a substrate 12a, a plurality of contact pads 14a, and a plurality of vertical conductive structures 16 (for clarity, in Figure 3 16d, 16e and 16f are indicated in the vertical conductive structure 16). The structure and function of each of the vertical conductive structures 16d, 16e and 16f are similar. Therefore, only the vertical conductive structure 16d is described in detail herein. The vertical conductive structure 16d is provided with at least two electrically insulated conductive segments 18c and 18d. Although each of the conductive segments 18c and 18d is connected to the spaced contact pads 14a via traces 20a, the conductive segments 18c and 18d can also be directly connected to the contact pads 14a. The conductive segments 18c and 18d are electrically insulated by a non-conductive filling material 22a (non-conductive) arranged centrally between the conductive segments 18c and 18d. As will be discussed in more detail below, the conductive segments 18c and 18d are typically formed by conductive plating that has been separated or cut open by forming at least one hole 24a.

[0076] The substrate 12a may be any material or device that can be used to support electrical components, conductors, etc. In a preferred embodiment, the substrate 12a includes multiple layers of interleaved conductive paths (or traces) and insulators.

[0077] The contact pad 14a can be any type of material or device capable of providing an electrical connection or joint with an external component such as an integrated circuit. For example, the contact pad 14a can be a surface mount contact, or a ball grid array contact, or a common mode contact defined by a solder mask. Depending on the optimal routing and bonding criteria, the shape of the contact pad 14a can be in the form of a circle, an ellipse, or a polygon.

[0078] The vertical conductive structure (VCS) 16d can be used to transmit differential or common mode type signals, wherein each of the conductive segments 18c and 18d can be coupled to different portions of the differential or common mode signals. In the case of differential type signals, transmitting the two signals in parallel or in a path using conventional techniques will be distorted due to the path separating the signals. The following table shows exemplary values ​​of the aspect ratio of the vertical conductive structure 16d by surface area.

[0079]

[0080]

[0081] *Since VCS components do not have a diameter, A / R by diameter cannot be calculated to compare to through holes, so surface area is used as a comparison.

[0082] In practice, in order to accommodate more conductive elements, the vertical conductive structure 16d can be longer than listed in the above table. This will produce a larger surface area that makes plating easier, and a larger surface area also makes the plating system simpler and more productive, thereby reducing the overall cost.

[0083] Conductive segments 18c and 18d may be constructed of any type of conductive material suitable for providing an electrical connection between an internal trace or conductive path and another internal or external conductive path or trace, with or without external contact pads. Typically, conductive segments 18c and 18d will be constructed of copper. However, it should be understood that other materials and / or alloys of materials and / or combinations of different materials may also be used in forming conductive segments 18c and 18d.

[0084] Trace 20a is constructed of a conductive material such as gold or copper. Any conductive material may be used as long as it includes a suitably low resistance for the particular application of trace 20a and can be structured to form trace 20a. In addition, trace 20a may be constructed of a combination of conductive materials. For example, gold may be applied to an underlying material such as copper and used as a protective layer to protect the underlying material from corrosion.

[0085] The filling material 22a serves as a dielectric between the two conductive segments 18c and 18d. The dielectric between the two conductive segments 18c and 18d can be adjusted by changing the size of the hole 24a or by changing the material forming the filling material 22a.

[0086] The filler material 22a is optional and can be formed of a material that is chemically and thermally compatible with respect to the substrate 12a manufacturing process and materials, and is desirably compatible with the various plating solutions used. In addition, the filler material 22a should exhibit flow characteristics sufficient to fill a small aspect ratio plated through hole (or blind hole), and have the ability to transform, solidify, or convert into a solid material with minimal volume change after filling. The thermal expansion of the filler material 22a should be compatible with the rest of the substrate 12a. In addition, the filler material 22a should exhibit good adhesion to the conductive segments 18c and 18d.

[0087] Two exemplary methods for manufacturing the printed circuit board 10a will be described below.

[0088] Example 1

[0089] Now refer to FIG. 4A to FIG. 4I Described on the substrate 12a ( Figure 3 16d, 16e and 16f in order to accurately form the vertical conductive structures 16d, 16e and 16f. Figure 4A An insulator substrate 40a such as a printed circuit board or a flexible film substrate is shown. Figure 4A As shown, at least one hole 41a is formed in an insulator substrate 40a at a desired position and a desired angle relative to the upper surface of the insulator substrate 40a. For example, the hole 41a can be formed at an angle substantially perpendicular to the upper surface of the insulator substrate 40a. The hole 41a includes a diameter D3. The hole 41a can be formed by using a drilling method, but any conventional method such as milling, punching, laser drilling, water cutting or light definition can also be used. The diameter D3 of the hole 41a can be any size compatible with other design requirements of the insulator substrate 40a. In an embodiment, the diameter D3 of the hole 41a can be in the range between about 0.1 mm and about 0.5 mm. All or substantially all of the openings or holes in the insulator substrate 40a can be formed simultaneously, regardless of whether the opening or hole is ultimately formed as a vertical conductive structure 16d as described below. This avoids misalignment, especially from tolerance accumulation, between the spaced hole forming process and the subsequently formed wiring pattern, which is formed by using one or more masks that must be aligned with the vertical conductive structure 16d. This factor is particularly important as the wiring patterns of printed circuit boards become increasingly finer.

[0090] Afterwards, if Figure 4B and Figure 4C As shown, a slot 45a is formed in the substrate 40a so that the hole 41a is used to move the drill bit into the substrate 40a, preferably without contacting the substrate 40a. Subsequently, the drill bit can be reciprocated in a lateral direction to remove material outside the limit of the hole 41a, thereby forming the slot 45a. The width W3 of the slot 45a is less than the diameter D3 of the hole 41a. The slot 45a intersects the hole 41a in a manner such that the side wall 46a is formed with a perimeter. The slot 45a can be formed by using a routing method with a drill bit as described herein, but any conventional method such as milling, punching, laser drilling / cutting / ablation, water cutting, or light definition can also be used.

[0091] Afterwards, if Figure 4D As shown, a conductive seed layer (not shown) is added, followed by a conductive layer 47a formed of a first conductive material, which is deposited on the surface of the substrate 40a and the sidewall 46a to leave an opening in the substrate 40a surrounded by the conductive layer 47a. In an embodiment, the first conductive material is copper and can be deposited to a thickness in a range between about 2.54 microns and about 25 microns, to a thickness between 15 microns and 25 microns, or to a thickness of about 15 microns. The conductive layer 47a on the sidewall 46a can be thick enough to provide a robust mechanical structure that can withstand the thermal fluctuations and corrosive treatments to which the printed circuit board is subjected during subsequent component assembly and use. For a through structure, the thickness can be in the range of about 20 microns to 25 microns, while for a blind structure, the thickness can be, for example, about 15 microns.

[0092] In an embodiment, the conductive layer 47a is deposited using an electrolytic plating process. The electrolytic process may be followed by a surface treatment step involving a direct metallization process or an electroless process. The surface treatment step includes depositing a conductive seed thin layer that sensitizes the surface and helps the conductive layer 47a to adhere to the sidewalls 46a. Direct metallization includes depositing a thin layer of conductive molecules (not shown) on the substrate surface and the vertical conductive structure sidewalls 46a before depositing the conductive layer 47a. The conductive layer 47a may also be palladium or platinum. The process avoids typical catalytic deposition of copper, making the device more economical and feasible.

[0093] The electroless surface treatment process includes depositing a thin conductive seed layer (not shown), which may be copper, on the surface of substrate 40a and sidewall 46a to a thickness in a range between about 3 microns and about 20 microns, and in one embodiment, to a thickness in a range between about 70 microns and about 80 microns before depositing conductive layer 47a.

[0094] The surface treatment prior to the electrolytic deposition may result in a non-linear distribution of the conductive layer 47a on the sidewall 46a due to the natural tendency of the thickness of the conductive layer 47a to decrease with increasing depth of the sidewall 46a.

[0095] Then, if Figure 4E As shown, hole 24a is formed in substrate 40a, hole 24a is concentric with hole 41a and also overlaps sidewall 46a and conductive layer 47a. Hole 24a removes a portion of conductive layer 47a on sidewall 46a so that hole 24a forms segments 18c and 18d electrically insulated from conductive layer 47a. Diameter D4 of hole 24a may preferably be greater than diameter D3 of hole 41a. When drilling, using a drill bit having a diameter D4 greater than diameter D3 allows the drill bit to be substantially uniformly supported by substrate 40a when conductive layer 47a is removed, thereby helping to prevent the drill bit from lateral deviation during drilling, and eliminating the need to fill the void surrounded by conductive layer 47a with a filler material before drilling.

[0096] like Figure 4F As shown, after the hole 24a is formed in the substrate 40a, the filling material 22a can be introduced into the chamber 48a formed by the substrate 40a and the electrically insulated segments 18c and 18d. The filling material 22a can be introduced into the chamber 48a by any suitable process. For example, the filling material 22a can be introduced into the chamber 48a by a squeegee or a stencil or a screen with or without a pattern. Other means such as a roller, a pressurized supply of the filling material 22a introduced into the chamber 48a, a syringe with a needle inserted into the chamber 48a, inkjet printing, or any other means capable of filling the chamber 48a with the filling material 22a can also be used to introduce the filling material 22a into the chamber 48a. The filling material 22a can be located in the chamber 48a to avoid forming bubbles or pits.

[0097] Once fill material 22a is introduced into cavity 48a and fill material 22a has cured, an abrasive, brush, or other type of planarization device may be used to planarize substrate 40a so that the outer ends of fill material 22a are substantially coplanar with the outer surface of conductive layer 47a.

[0098] Then, if Figure 4G and Figure 4H As shown, one or more pattern plates 60a are disposed on the first surface 62a or the second surface 64a of the substrate 40a. When plating is performed on the surface of the cured fill material 22a and the electrically insulated segments 18c and 18d, one or more pattern plates (the pattern plates can be implemented as panels or a combination of the two, which is applicable to all plating processes) 60a include a second conductive layer. This will be necessary when the surface mount contact area overlaps the area of ​​the substrate 40a with the cured fill material 22a and the electrically insulated segments 18c and 18d. Once the area is plated to the optimal thickness, the substrate 40a is passed through a process commonly referred to as a strip-etch-strip (SES) line.n An example of a "strip-etch-strip" line is disclosed in U.S. Pat. No. 6,074,561, the entire contents of which are incorporated herein by reference. Fig. 4I As shown, the strip-etch-strip process removes portions of one or more pattern sheets 60a, portions of layer 47a, and the base copper from the laminate / copper foil.

[0099] Subsequently, the substrate 40a may be processed with a solder mask, a surface finish such as ENIG, etc., thereby manufacturing the printed circuit board 10a. The solder mask may be any suitable solder mask such as a smooth type.

[0100] Example 2

[0101] Now refer to FIG. 5A to FIG. 5H Another example of sequential steps followed to accurately form vertical conductive structures 16d, 16e, and 16f in substrate 12a is described. Figure 5A An insulator substrate 40b such as a printed circuit board or a flexible film substrate is shown. Figure 5A and Figure 5B As shown, at least one slot 45b is formed in an insulator substrate 40b at a desired position and a desired angle relative to the upper surface of the insulator substrate 40b. For example, the slot 45b can be formed at an angle substantially perpendicular to the upper surface of the insulator substrate 40b. The slot 45b is formed in the substrate 40b in such a way that the sidewall 46b is formed with a periphery. The slot 45b includes a length L5 and a width W5. The slot 45b can be formed by using a milling method, but any conventional method such as milling, punching, laser drilling, water cutting or light definition can also be used. The length L5 and width W5 of the slot 45b can be any size compatible with other design requirements of the insulator substrate 40b. All or substantially all of the openings or holes in the insulator substrate 40b can be formed simultaneously, regardless of whether the openings or holes are ultimately formed as vertical conductive structures 16d, 16e and 16f as described below. This avoids misalignment, particularly from tolerance stack-up, between the spaced hole forming process and the subsequently formed wiring pattern formed using one or more masks that must be aligned with the vertical conductive structures 16. This factor is particularly important as printed circuit board wiring patterns become increasingly finer.

[0102] Afterwards, if Figure 5CAs shown, a conductive seed layer (not shown) is added, followed by a conductive layer 47b formed of a first conductive material, which is deposited on the surface of the substrate 40b and the sidewall 46b to leave an opening in the substrate 40b surrounded by the conductive layer 47b. In an embodiment, the first conductive material is copper and can be deposited to a thickness in a range between about 2.54 microns and about 25 microns, or deposited to a thickness in a range of about 5 microns to about 25 microns, or deposited to a thickness of about 15 microns. The conductive layer 47b on the sidewall 46b can be thick enough to provide a robust mechanical structure that can withstand the thermal fluctuations and corrosive treatments to which the printed circuit board is subjected during subsequent component assembly and use. As described above, for a through structure, the thickness can be in the range of about 20 microns to 25 microns, while for a blind structure, the thickness can be, for example, about 15 microns.

[0103] In an embodiment, the conductive layer 47b is deposited using an electrolytic plating process. The electrolytic process may be followed by a surface treatment step involving a direct metallization process or an electroless process. The surface treatment step includes depositing a conductive seed thin layer that sensitizes the surface and helps the conductive layer 47b to adhere to the sidewall 46b. Direct metallization includes depositing a thin layer of conductive molecules (not shown) on the substrate surface and the vertical conductive structure sidewall 46b before depositing the conductive layer 47b. The conductive layer 47b may also be palladium or platinum. The process avoids typical catalytic deposition of copper, thereby making the device more economical and feasible.

[0104] The electroless surface treatment process includes depositing a thin conductive seed layer (not shown), which may be copper, on the surface of substrate 40b and sidewall 46b to a thickness in a range between about 30 microns and about 200 microns, and in one embodiment, to a thickness in a range between about 70 microns and about 80 microns before depositing conductive layer 47b.

[0105] The surface treatment before the electrolytic deposition makes the conductive layer 47b on the side wall 46b highly linearly distributed.

[0106] Then, if Figure 5D As shown, hole 24a is formed in substrate 40b, and hole 24a overlaps sidewall 46b and conductive layer 47b. Hole 24a removes a portion of conductive layer 47b on sidewall 46b so that hole 24a forms segments 18c and 18d that are electrically insulated from conductive layer 47b. Diameter D6 of hole 24a may preferably be greater than width W5 of slot 45b. When drilling, using a drill bit having a diameter D6 greater than diameter W5 allows the drill bit to be substantially uniformly supported by substrate 40b when conductive layer 47b is removed, to help prevent the drill bit from lateral deviation during drilling, and eliminates the need to fill the void surrounded by conductive layer 47b with a filler material before drilling.

[0107] like Figure 5EAs shown, after hole 24a is formed in substrate 40b, filling material 22b can be introduced into chamber 48b formed by substrate 40b and electrically insulated segments 18c and 18d. Filling material 22b can be introduced into chamber 48b by any suitable process. For example, filling material 22b can be introduced into chamber 48b by a squeegee or stencil or screen with or without pattern. Other means such as roller, pressurized supply of filling material 22b introduced into chamber 48b, syringe with needle inserted into chamber 48b, inkjet printing, or any other means capable of filling chamber 48b with filling material 22b can also be used to introduce filling material 22b into chamber 48b. Filling material 22b can be located in chamber 48b to avoid forming bubbles or pits.

[0108] Once fill material 22b is introduced into cavity 48b and fill material 22b has cured, an abrasive, brush, or other type of planarization device may be used to planarize substrate 40b so that the outer ends of fill material 22b are substantially coplanar with the outer surface of conductive layer 47b.

[0109] Then, if Fig. 5F and Figure 5G As shown, one or more pattern plates 60b are disposed on the first surface 62b or the second surface 64b of the substrate 40b. When plating is performed on the surface of the cured filler material 22b and the electrically insulated segments 18c and 18d, the one or more pattern plates 60b include a second conductive layer. This will be necessary when the surface mount contact area overlaps the area of ​​the substrate 40b having the cured filler material 22b and the electrically insulated segments 18c and 18d. Once the area is plated to the optimal thickness, the substrate 40b is subjected to a stripping-etching-stripping (SES) line. n Typically used as a resist, but other materials may be used) process. U.S. Patent No. 6,074,561 discloses an example of a "strip-etch-strip" line, the entire contents of which are incorporated herein by reference. Figure 5H As shown, the strip-etch-strip process removes portions of one or more pattern plates 60b and portions of layer 47b. Figure 5G As shown by the dashed line in FIG. 4 , the conductive layer 47 b on the sidewall 46 b of the vertical conductive structure 42 b and the edge 66 b formed by the conductive layer 47 b define the periphery of the vertical conductive structure 42 b.

[0110] Subsequently, the substrate 40b may be processed with a solder mask, a surface finish such as ENIG, etc., thereby manufacturing the printed circuit board 10a. The solder mask may be any suitable solder mask such as a smooth type.

[0111] Figures 6 to 16 Various examples of substrate 12 having a vertical conductive structure 16 and traces 20 interconnecting selected ones of the conductive segments 18 of the vertical conductive structure 16 are shown. Figures 6 to 16 are partial perspective views of examples of substrate 12 and are not intended to show multiple views of the same example. Figures 6 to 16 are numbered to generally show where an element is located in the figure, but Figures 6 to 16 The same reference numerals in the drawings, such as 16a, are not intended to indicate identical elements.

[0112] Figure 6 1 is a partial perspective view showing a plurality of VCSs 16a-h extending vertically through multiple layers of an exemplary multi-layer substrate 12, and the electrically insulated conductive segments of the VCSs 16a-h are connected to traces 20 at three different layers (not all traces are numbered for clarity). Those skilled in the art will appreciate that the techniques disclosed herein for forming the plurality of VCSs 16a-h create more routing space under a BGA type component and more space for the traces 20 used to transmit power and ground signals to be positioned directly under the BGA type component.

[0113] Figure 7 is a partial perspective view of an exemplary multi-layer substrate 12 with traces 20 extending from the VCSs 16 a - f through the inner layers of the substrate 12 .

[0114] Figure 8 is a partial perspective view of substrate 12 showing a ball grid array having a plurality of VCSs 16a-f having electrically insulated conductive segments connected to traces 20 and extending through multiple layers. Figure 8 The ball grid array can be a 0.5mm ball grid array.

[0115] Fig. 9 is a partial perspective view of substrate 12 showing a ball grid array shown as fill material 22 over six vertical conductive structures 16a-f, with internal traces and various layers omitted. Fig. 9 The ball grid array may be a 0.5 mm ball grid array.

[0116] Fig.10 is a partial perspective view of the substrate 12 showing traces 20 extending from a plurality of VCSs 16a - h .

[0117] Fig.11 is a partial perspective view of substrate 12 showing traces 20 extending from VCS 16a-f at multiple layers.

[0118] Fig.12is a partial perspective view of substrate 12 with traces 20 extending from VCS 16a-f in multiple layers of substrate 12.

[0119] Fig.13 is another partial perspective view of substrate 12 , with traces electrically connected and extending from VCS 16 a - d at multiple layers.

[0120] Fig.14 is another partial perspective view of the substrate 12 having a 0.7 mm ball grid array shown positioned over a plurality of VCSs 16a-h, with traces not shown.

[0121] Fig.15 is another partial perspective view of substrate 12 with a ball grid array showing VCS 16 a - f , illustrating electrically isolated conductive segments connected to traces 20 and extending from VCS 16 a - f . Fig.15 The ball grid array can be a 0.7mm ball grid array.

[0122] Fig.16 is another partial perspective view of the substrate 12 showing traces 20 extending from a plurality of VCSs 16a - k at a plurality of layers of the substrate 12 .

[0123] Although the vertical conductive structures 16a-f have been shown and described herein as through structures, it should be understood that the vertical conductive structures 16 may also be formed as blind structures, buried structures, and combinations thereof. Fig.17 A cross-sectional diagram of a circuit board 100 having a BGA type component 102 mounted to one or more vertical conductive structures 110 in accordance with the present invention is shown. The circuit board 100 includes eight layers 112 numbered 112a, 112b, 112c, 112d, 112e, 112f, 112g, and 112h.

[0124] One or more vertical conductive structures 110 can be constructed similarly to the vertical conductive structures 16 described above, except that when the final slot 50 is formed in the substrate 12, the final slot 50 is formed with a first region of the final slot 50 extending through a first number of layers of the substrate 12, and a second region of the final slot 50 extending through a second number of layers of the substrate 12, and the first number of layers is different from the second number of layers. In some cases, the substrate has N layers, eight layers in this example, and the first number of layers can be equal to the N layers. In this case, the first region will extend through the entire substrate 12.

[0125] For example, as shown, the vertical conductive structure 110 may include seven regions 120, 122, 124, 126, 128, 130, and 132. Each of the regions 120, 122, 124, 126, 128, 130, and 132 has one or more conductive segments 116 (only a few are numbered for clarity) extending to a preselected depth within the circuit board 100, which may be the same or different than the depth to which one or more conductive segments 116 extend in the other regions 120, 122, 124, 126, 128, 130, and 132. For example, region 120 includes five conductive segments 116 extending (through layers 112a and 112b) to the same depth as the five conductive segments 116 in region 132, i.e., the five conductive segments 116 pass through two layers of the circuit board 100 and have the same function as a conventional blind via. Additionally, the conductive segments 116 in region 122 extend only through a single layer of the circuit board 100 and have the same function as blind vias. The conductive segments 116 in region 126 extend through the circuit board 100 and have the same function as conventional through vias. Additionally, forming the slots through the circuit board 100 before forming the conductive segments 116 enhances the ability of the fluid to flow into the slots, thereby facilitating the formation of the conductive vias described above with reference to FIG. Figure 2D , Figure 4D and Figure 5E The conductive layers 47, 47a and 47b described above. The circuit board 100 can be formed in the manner described above so that the circuit board 10 is machined using controlled depth milling (i.e., milling at different depths) to form the chambers, the chambers are then plated, and then the chambers are subjected to separate drilling, milling or other operations to remove preselected portions of the conductive layer to form the conductive segments 116, and to remove any conductive material or resist at the bottom of the slots to electrically insulate the conductive segments 116.

[0126] Fig.18 and Fig.19 A vertical conductive structure 136a ( Fig.18 ) and 136b( Fig.19) of the substrate 134 of the multilayer circuit board. The vertical conductive structures 136a and 136b include a plurality of traces 138a-1, 138a-2, 138b-1 and 138b-2 extending on the sidewalls 139a and 139b. As shown, the traces 138a-1 and 138a-2 have two first portions 140a-1 and 140a-2 extending vertically on the sidewall 139a, and one second portion 141a-1 and 141a-2 extending horizontally on the sidewall 139a. The traces 138b-1 and 138b-2 extend on the sidewall 139b in a non-parallel manner to each other, and are also at a non-90 degree angle relative to the upper surface 142 of the substrate 134. The configuration of the traces 138a-1, 138a-2, 138b-1, and 138b-2 is shown by way of example, but it should be understood that the traces 138a-1, 138a-2, 138b-1, and 138b-2 may have a variety of shapes including linear portions, curved portions, and combinations of linear portions and curved portions connected to traces (not shown) inside or outside the substrate 134. The vertical conductive structure 136a ( Fig.18 ) and 136b( Fig.19 ) is shown as a through-hole structure, but the vertical conductive structure 136a ( Fig.18 ) and 136b( Fig.19 ) can also be constructed as a blind structure.

[0127] Fig. 20 and Fig.21Shown is an exemplary method for forming traces 138a-1, 138a-2, 138b-1 and 138b-2. As described above, vertical conductive structures 136a and 136b can be formed by forming a slot 143a in a substrate 134 and then applying a coating of a conductive material 143b to the sidewalls 139a and 139b of the slot 143a. As described above, the conductive material 143b can be, for example, gold or copper. Subsequently, a milling cutter 144 having a shaft 145a and a cutting end 145b is arranged in the slot 143a. The cutting end 145b extends outwardly beyond the periphery of the shaft 145a so that the cutting end 145b can engage and cut a predetermined portion of the conductive material 143b to remove an undesirable portion of the conductive material 143b, thereby forming traces 138a-1, 138a-2, 138b-1 and 138b-2. The cutting end 145b can have any suitable shape, such as a spherical shape as shown. The milling cutter 144 can be connected to a computerized guidance system (not shown) having a motor, a mechanical structure, and a guide for rotating, supporting, and moving the milling cutter 144 in at least three different directions, such as along the X-axis, the Y-axis, and the Z-axis, to engage the cutting end 145b with the conductive material 143b so as to remove the undesirable portion of the conductive material 143b. In this example, the slot 143a has a longitudinal axis 147a and a lateral axis 147b extending perpendicular to the longitudinal axis 147a. The longitudinal axis 147a can be aligned with the Y-axis of the computerized guidance system, the lateral axis 147b can be aligned with the X-axis of the computerized guidance system, and the Z-axis of the computerized guidance system can be perpendicular to the upper surface 142. In another embodiment, the predetermined portion of the vertical conductive structures 136a and 136b can be removed using an imaging process to form traces 138a-1, 138a-2, 138b-1 and 138b-2. In the present embodiment, the vertical conductive structures 136a and 136b are plated with a positive or negative photoresist (photoresist) material. Thereafter, the predetermined portion of the photoresist material is exposed, and then an etching process is used to remove the undesired portion of the vertical conductive structures 136a and 136b to form traces 138a-1, 138a-2, 138b-1 and 138b-2.

[0128] The predetermined portion of the photoresist material can be exposed by using a laser connected to an optical fiber tip (not shown) and emitting light through the optical fiber tip. The optical fiber tip can be sized and configured to be positioned in the slot 143a and can rotate and / or move along multiple axes, such as two, three, four, five or more axes. The optical fiber tip can be connected to a computerized guidance system having a motor, a mechanical structure and a guide for rotating, supporting and moving the optical fiber tip in at least three different directions, such as along the X-axis, the Y-axis and the Z-axis, to arrange the optical fiber tip into the slot 143a and aim the light emitted by the optical fiber tip at the desired and / or undesirable portion of the photoresist material to allow a subsequent etching process to remove the undesirable portion of the conductive material 143b.

[0129] After forming the traces 138a-1, 138a-2, 138b-1, and 138b-2, the slot 143a may be filled and covered.

[0130] Fig. 22 1 is a cross-sectional view of another example of a substrate 148 having a vertical conductive structure 150 constructed according to the present invention, wherein the vertical conductive structure 150 is constructed as a blind structure with a bottom 152. The bottom 152 is constructed of a dielectric material so that the first conductive segment 154 of the vertical conductive structure 150 is electrically insulated from the second conductive segment 156. The vertical conductive structure 150 can be constructed in a manner similar to the construction of the vertical conductive structure 16 described above, and further process steps are used to avoid plating the bottom 152 with conductive material or completely removing the conductive material from the bottom 152. The conductive material can be removed from the bottom 152 using an optical fiber tip by an imaging process, wherein a photoresist is applied to the conductive material on the bottom 152, and the photoresist is exposed using any suitable light source such as a laser that emits light through the optical fiber tip and an etching process. The vertical conductive structure 150 also includes a sidewall 158 that supports the first conductive segment 154 and the second conductive segment 156.

[0131] Fig.23 yes Fig. 22 The cross-sectional view of the substrate 148 and the vertical conductive structure 150 shown in FIG. 1 has a filling material 160 in the vertical conductive structure 150, and one or more layers 162 of printed circuit board material cover the vertical conductive structure 150, so that Fig.23 The vertical conductive structure 150 is in a buried configuration.

[0132] Fig.241 is a top plan view of another example of a substrate 183 having a vertical conductive structure 184 constructed in accordance with the present invention, wherein the vertical conductive structure 184 is constructed as a blind structure having a bottom 185 and a sidewall 186, the sidewall 186 being partially coated with a conductive material to form a first conductive segment 192, a second conductive segment 194, a third conductive segment 200, and a fourth conductive segment 202. In this example, the sidewall 186 is formed in the form of a hockey stick, however it should be understood that the sidewall 186 may also be formed in many shapes including an elongated linear slot, a cross, a bend, an arc, or a torus shape as described above.

[0133] 25a to 25e are partial perspective views of another example of a printed circuit board 300 constructed according to the above embodiment, wherein the printed circuit board 300 has a vertical conductive structure 302, the vertical conductive structure 302 includes a plurality of blind structures having conductive segments 306, 308, 310, 312, 314, 316, and 318, and the conductive segments 306, 308, and 314 pass into the printed circuit board 300 to a different depth than the conductive segments 310, 312, 316, and 318. The vertical conductive structure 302 also includes a through structure having a conductive segment 319. As described above, the conductive segments 306, 308, 310, 312, 314, 316, and 318 can be constructed of any suitable conductive material such as copper, silver, or gold. The printed circuit board 300 includes a first side 330 and a second side 332 opposite the first side 330. The printed circuit board 300 also includes a plurality of traces 340a, 340b, 340c, 340d, 340e, 340f, 340g, 340h, 340i, and 340j extending between the first side 330 and the second side 332. The traces 340a, 340b, 340c, 340d, 340e, 340f, 340g, 340h, 340i, and 340j may be made of any suitable conductive material such as copper, silver, or gold as described above. The conductive segment 308 is electrically connected to the trace 340a, the conductive segment 310 is electrically connected to the trace 340b, and the conductive segment 312 is electrically connected to the trace 340c. The traces 340d-340i are electrically insulated from the conductive segments 306, 308, 310, 312, 314, 316, and 319.

[0134] Conductive segments 306, 308, 310, 312, 314, 316 intersect and extend from first side 330 and terminate before intersecting second side 332. Conductive segment 319 intersects both first side 330 and second side 332 and extends between first side 330 and second side 332. Optionally, filler material may be located between adjacent pairs of conductive segments 306, 308, 310, 312, 314, 316, and 319 to provide structural support for contact pads and to help electrically insulate conductive segments 306, 308, 310, 312, 314, 316, and 319.

[0135] Reference now Figure 26 to Figure 28 In one embodiment, a printed circuit board constructed according to embodiments disclosed herein may have a plurality of conductive structures 16 having one or more configurations. In one embodiment, a printed circuit board has a vertical conductive structure 402 including one or more blind structures 404 having one or more conductive segments 418, such as conductive segments 418a, 418b, 418c, 418d, and 418e. Conductive segments 418a, 418b, 418c, 418d, and 418e may extend to one or more different depths within the printed circuit board, thereby reaching one or more different layers within the printed circuit board. In one embodiment, conductive segments 418a-418e intersect and extend from a first side of the circuit board and terminate before intersecting a second side of the circuit board. In one embodiment, blind structure 404 is a stepped blind structure 404a, wherein at least two conductive elements 418 extend to different depths within the printed circuit board.

[0136] In one embodiment, one or more of the conductive segments 418a-418e of the blind structure 404 and / or the stepped blind structure 404a intersects a first side of a circuit board and extends from the first side to intersect a second side of the circuit board (e.g., to improve plating capabilities by enhancing fluid exchange of the vertical conductive structure 402).

[0137] Although five conductive segments 418a-418e extending to different depths are shown in the figure for exemplary purposes, it should be understood that more or fewer conductive segments 418 extending to greater or lesser depths and / or extending to intersect the second side of the circuit board may be used.

[0138] As described in the present disclosure, the blind structure 404 may be formed with one or more slots 445 (e.g., Figure 32 to Figure 34 The slots shown and / or Figure 2FThe final slot 50 is shown. The depth of the slot 445 affects the application of the conductive layer 47 in the slot 445. The depth to which the conductive layer 47 can be applied is based at least in part on the width-to-length ratio of the slot 445 dimensions, with wider slots 445 generally allowing for a greater application depth. Thus, a slot-based blind structure can be deeper than a round hole-based blind structure while maintaining the ability to apply the conductive layer 47 to the structure.

[0139] like Fig. 27 As shown, in one embodiment, one or more of the conductive segments 418a-418e each have a first side 420, a second side 422, and a bottom plate 424 between and electrically connecting the first side 420 and the second side 422, such that the conductive layer 47 is substantially continuous from the first side 420 to the second side 422. In one embodiment, as Fig.28 As shown, one or more of the first side 420 and the second side 422 of the conductive segments 418a-418e are disconnected (electrically insulated). In this case, for example, at least a portion of the conductive layer 47 can be removed from the bottom plate 424 of the conductive segment 418 so that the conductive layer 47 no longer connects the first side 420 and the second side 422.

[0140] Return to Fig.26 , the circuit board may also include one or more through structures 406 having one or more conductive segments 418f. The conductive segments 418f intersect the first side and the second side and also extend between the first side and the second side. In one embodiment, the through structure 406 may be separated from the blind structure 404 and / or the stepped blind structure 404a. In one embodiment, the through structure 406 may be connected to the blind structure 404 and / or the stepped blind structure 404a.

[0141] Conductive segments 418a-418f can be constructed of any suitable conductive material (or materials) such as copper, silver, or gold as described above. The printed circuit board also includes a plurality of traces 440 extending within the circuit board. Traces 440 can be made of any suitable conductive material (or materials) such as copper, silver, or gold as described above. Conductive segments 418a-418f can be electrically connected to one or more of the traces 440 and electrically insulated from another one or more of the traces 440.

[0142] Optionally, fill material may be positioned between adjacent pairs of conductive segments 418a-418f to provide structural support to the contact pads and also help electrically isolate the conductive segments 418a-418f.

[0143] It should be appreciated that vertical conductive structure 402 may have other structures besides those shown in the exemplary embodiment to accommodate desired pinouts in a ball grid array (BGA) based at least in part on reference voltages (power and ground) and signals.

[0144] In one embodiment, Fig.29 and Fig.30 As shown, a combination of one or more step-shaped blind structures 404a, one or more blind structures 404, and / or one or more through structures 406 can be used. For example, a circuit board can have a step-shaped blind structure 404a positioned between two first blind structures 404, the two first blind structures 404 having a conductive element 418 extending to a first depth, the two first blind structures 404 being positioned between two second blind structures 404, the two second blind structures 404 having a conductive element 418 extending to a second depth different from the first depth. The second depth can be greater than the first depth. The first blind structure 404 and the second blind structure 404 can be parallel. The circuit board can also have one or more through structures 406. In this way, the routing space within the circuit board below and adjacent to the step-shaped blind structure 404a and the two first blind structures 404 having the conductive element 418 extending to the first depth can be used to route the trace 440.

[0145] In one embodiment, Fig.31 As shown, a combination of two or more step-shaped blind structures 404a may be used. In this non-exclusive example, a first step-shaped blind structure 404a descends from a first side of a circuit board, and a second step-shaped blind structure 404a descends from a second side of the circuit board, opposite and aligned with the first step-shaped blind structure 404a. Fig.31 The configuration shown enables to increase the density of components in the circuit board. The circuits on both sides of the circuit board can then be independent of each other, but can also be connected by connecting the first second step-shaped blind structure and the second step-shaped blind structure 404a (for example, by using through holes or buried vias or through-connections in the conductive structure 16).

[0146] Now refer to Figure 32 to Figure 34 Further variations of the conductive structure 16 and methods for making the conductive structure 16 are described. It should be understood that these variations can be used in conjunction with the previous description of the conductive structure 16. Figure 1 and Figure 3 Any circuit board 10, 10a described above can be used for other circuit boards. Fig.32 As shown, in one embodiment, the hole 41 can be formed in the insulator substrate 40 at a desired position and a desired angle relative to the upper surface of the insulator substrate 40. For example, the hole 41 can be formed at an angle substantially perpendicular to the upper surface of the insulator substrate 40.

[0147] The hole 41 may be formed by using a drilling method, but any conventional method such as milling, punching, laser drilling, water cutting or photodefinition may also be used. The diameter D1 of the hole 41 may be any size compatible with other design requirements of the insulator substrate 40. In one embodiment, the diameter D1 of the hole 41 may be in a range between about 0.05 mm and about 0.5 mm. In some embodiments, the diameter D1 of the hole 41 may be in a range between about 0.1 mm and about 0.5 mm.

[0148] Subsequently, at least a portion of the material of the insulator substrate 40 is removed by forming a slot 445 in the substrate 40 starting from the hole 441. The slot 445 has a peripheral sidewall 446. The width W of the slot 445 may be substantially equal to the diameter D1 of the hole 41. The slot 445 may have a rounded end, the diameter of the rounded end being substantially equal to the diameter D1 of the hole 41. In one embodiment, one of the rounded ends is a semicircle produced by forming the hole 41. In one embodiment, two holes 41 are formed spaced apart from each other, and the slot 445 is formed between the two holes 41, and one of the holes 41 extends to the other hole 41.

[0149] The slot 445 may have a floor 424a (not shown) at the base of the sidewall 446. In one embodiment, the floor 424a is inclined. The larger angle of the floor 424a enhances fluid exchange and flow of materials inserted into the slot 445.

[0150] The slots 445 may be formed using a straight mill (with or without end milling), but any conventional method may be used, such as drilling, routing, milling, punching, laser drilling / cutting / ablation, waterjet cutting, or photodefinition.

[0151] Thereafter, a conductive seed layer (not shown) is added, followed by a conductive layer 447 formed of a first conductive material that is deposited on the surface of the substrate 40 and the sidewalls 446 to leave an opening in the substrate 40 surrounded by the conductive layer 447. In one embodiment, the first conductive material is copper and can be deposited to a thickness in a range between about 2.54 microns and about 25 microns, to a thickness greater than about 5 microns, to a thickness of about 15 to 25 microns. For example, for a through structure, the thickness can be in a range of about 20 to 25 microns, while for a blind structure, the thickness can be about 15 microns. The conductive layer 447 on the sidewalls 446 can be thick enough to provide a robust mechanical structure that can withstand thermal fluctuations and aggressive treatments to which the printed circuit board is subjected during subsequent component assembly and use.

[0152] In one embodiment, the conductive layer 447 is deposited using an electrolytic plating process. The electrolytic process may be followed by a surface treatment step involving a direct metallization process or an electroless process. The surface treatment step includes depositing a thin layer of conductive seed that sensitizes the surface and facilitates adhesion of the conductive layer 447 to the sidewalls 46. Direct metallization includes depositing a thin layer of conductive molecules (not shown) on the substrate surface and the sidewalls 446 of the narrow grooves 445 of the vertical conductive structure before depositing the conductive layer 447. The conductive layer 447 may also be palladium or platinum. The process avoids the typical catalytic deposition of copper, making the device more economically feasible.

[0153] The electroless surface treatment process includes depositing a thin conductive seed layer (not shown), which may be copper, on the surface of substrate 40 and sidewalls 446 to a thickness in a range between about 30 microns and about 200 microns, and in one embodiment, to a thickness in a range between about 70 microns and about 80 microns before depositing conductive layer 447.

[0154] The surface treatment prior to the electrolytic deposition may result in a non-linear distribution of the conductive layer 447 on the sidewall 446 due to the natural tendency of the thickness of the conductive layer 447 to decrease with increasing depth of the sidewall 446 .

[0155] Subsequently, one or more oblong holes, hereinafter referred to as cross-cut slots 448, are formed in the sidewall 446 of the insulator substrate 40. In one embodiment, the cross-cut slots 448 are milled with a straight milling cutter (not shown), but it should be understood that punching, laser drilling, water cutting, or drilling can be used to form the cross-cut slots 448. The milling cutter / milling tool is sized and configured to be positioned in the slot 445 and can be rotated and / or moved along multiple axes, such as two, three, four, five or more axes.

[0156] In one embodiment, a milling tool having a diameter less than the width of slot 445 is lowered into slot 445 and articulated through a first portion of conductive layer 447 into a first portion of sidewall 446 of insulator substrate 40, thereby removing the first portion of conductive layer 447. In one embodiment, the milling tool may articulate across the width of slot 445 into a second portion of sidewall 446.

[0157] The one or more cross-cut slots 448 cooperate with the slots 445 to form electrically isolated conductive segments 18. In one embodiment, the cross-cut slots 448 extend into the insulator substrate 40 by an amount that can disrupt longitudinal strands in the insulator substrate 40 that, when uninterrupted, allow electrical bridging between conductive segments 18 (known as the conductive anode wire effect). In a non-exclusive example, the cross-cut slots extend into the insulator substrate 40 by an amount equal to or greater than about 0.1 mm.

[0158] In one embodiment, Fig.32 As shown, the length of the one or more transverse slots 448 extends generally vertically across the slot 445. In one embodiment, the one or more transverse slots 448 are two or more transverse slots 448 spaced apart from each other along the length of the slot 445. In one embodiment, the two or more transverse slots 448 are spaced apart from each other generally equidistantly along the length of the slot 445.

[0159] In one embodiment, Fig.33 As shown, the one or more cross-cutting slots 448 are formed generally perpendicular to the slot 445, but do not extend across the slot 445. For example, in this embodiment, a milling tool can be lowered into the slot 445 and articulated across the width of the slot 445, through the conductive layer 47 and into the side wall 446 of the insulator substrate 40. Subsequently, the milling tool can be articulated back into the slot 445, offset along the length of the slot 445, and then articulated again across the width of the slot 445 at a different location along the length of the slot 445, through the conductive layer 47 and into the side wall 446 of the insulator substrate 40. In one embodiment, the one or more cross-cutting slots 448 are two or more cross-cutting slots 448 that cooperate to form a staggered offset between two or more vertical conductive segments 18.

[0160] In one embodiment, Fig.34 As shown, the one or more transverse slots 448 may be positioned at a non-90 degree angle relative to the slot 445 .

[0161] In one embodiment, a drill bit forms one or more holes in the insulator substrate 40 proximate the slot 445 and the milling tool is then activated in the drilled hole and then articulated into the slot 445 and / or across the width of the slot 445 .

[0162] Now refer to Figures 35 to 40 The arrangement of the conductive structure 16 on the circuit board is described, such as a surface array component (e.g., a ball grid array). Fig.35 As shown, the conductive structures can be arranged in an orthogonal pattern on the circuit board (across the width and length). According to the inventive concept of the present disclosure, as Figures 36 to 40 As shown, one or more of the vertical conductive structures 16 can be aligned diagonally relative to the circuit board 10b. The diagonal arrangement can widen the routing channel, thereby achieving higher efficiency. For example, positioning the conductive structure 16 at an angle of about 45 degrees forms a routing channel that is twice as wide as the root of two (i.e., about 2.8 times) as the structure arranged orthogonally. The diagonal arrangement can allow more signals per channel, or allow more space between the traces 40 (the traces 40 are only a few of which are marked for clarity purposes), and allow more space for the power / ground plane.

[0163] In one embodiment, Fig.37 1, a diagonal arrangement of conductive structures 16 is shown with a 0.5 mm pitch ball grid array (also referred to as a BGA) 10c. In one embodiment, the conductive structures 16 can be formed diagonally relative to pads on a circuit board (e.g., a BGA). In one embodiment, the conductive structures 16 can be spaced apart such that parallel diagonal conductive structures 16 are spaced apart a greater distance than orthogonally arranged conductive structures 16. When arranged at a 45 degree angle, the distance between the conductive structures 16 is equal to 2*(BGA pitch)*(root 2).

[0164] like Fig.39 As shown, the diagonal arrangement of the conductive structures 16 is shown with a 0.4 mm pitch BGA 10d. In one embodiment, for such a BGA 10d, the trace width and spacing may be 0.040 mm (eight traces per channel). In one embodiment, the width of the slots 45, 445 of the diagonal conductive structures 16 may be approximately 0.25 mm.

[0165] like Fig.40 As shown, the diagonal arrangement of the conductive structures 16 is shown with a BGA 10e having a pitch of 0.35 mm. In one embodiment, for such a BGA 10e, the trace width and spacing may be 0.040 mm (seven traces per channel). In one embodiment, the width of the slots 45, 445 of the diagonal conductive structures 16 may be approximately 0.20 mm.

[0166] Of course, it will be appreciated that the diagonal arrangement of the conductive structures 16 and the width of the slots 45 , 445 of the diagonal conductive structures 16 may vary depending on the type and configuration of the circuit board.

[0167] Now refer to Figure 41 to Figure 43 Other variations of the conductive structure 16, and methods of making the conductive structure 16 are described. It should be understood that these variations can be used in conjunction with the previous descriptions of the conductive structure 16. Figure 1 and Figure 3 Any of the circuit boards 10, 10a described may be used with other circuit boards. Fig.41 Shown is a partial perspective view of a circuit board 500 constructed according to the present disclosure, wherein filler material (discussed below) is not shown to more clearly illustrate other components. The circuit board 500 is provided with a substrate 502 having a first side 504, a second side 506, and at least one shielded vertical conductive structure 508, i.e., a through structure, extending from the first side 504 to the second side 506. It should be understood that such shielded vertical conductive structure 508 can also be configured as a blind configuration or an embedded configuration.

[0168] Substrate 502 may be any material or device that can be used to support electrical components, conductors, etc. In a preferred embodiment, substrate 502 includes multiple layers of interleaved conductive paths (or traces) and insulators.

[0169] The printed circuit board 500 may also be provided with a plurality of contact pads and one or more traces (not shown) as discussed herein. The shielded vertical conductive structure 508 is provided with at least two spaced-apart and electrically insulated conductive segments 518a and 518b, and in the example shown, the shielded vertical conductive structure 508 is provided with six electrically insulated conductive segments 518a-f. Although each of the conductive segments 518a-f may be connected to spaced-apart contact pads, components (not shown), etc. via traces (not shown), the conductive segments 518a-f may also be directly connected to the contact pads. The conductive segments 518a-f are connected to the conductive segments 518a-f by a non-conductive fill material 522 (not shown) centrally disposed between the conductive segments 518a-f. Fig.41 shown in Fig.43 As will be discussed in more detail below, conductive segments 518a and 518b are typically formed from a continuous conductive plating that has been separated or cut as described above.

[0170] The shielded vertical conductive structure 508 is provided with a vertical conductive structure 528 and at least one electromagnetic shield 530, which is positioned between at least two of the conductive segments 518a-f. The vertical conductive structure 528 can be structurally the same as the vertical conductive structures 16, 110, 136a, 136b, 150 and 184 described herein (and made the same as the vertical conductive structures 16, 110, 136a, 136b, 150 and 184 described herein). The electromagnetic shield 530 is used to reduce the electromagnetic field in the space surrounded by the vertical conductive structure 528 by blocking the electromagnetic field with a barrier made of conductive or magnetic material. In this case, the electromagnetic shield 530 is designed to reduce undesirable capacitive, inductive or conductive coupling from the first group of conductive segments 518a-f to the second group of conductive segments 518a-f. In Fig.41 In FIG. 5 , the vertical contact 518 b is connected to the shield 530 . Fig.41 , shielding is substantially effective between vertical contacts 518c and 518d. In this example, the first group includes conductive segment 518c, while the second group includes conductive segment 518d. Electromagnetic shield 530 does not extend between conductive segments 518a and 518f. Therefore, conductive segments 518a and 518f are not shielded relative to each other.

[0171] The electromagnetic shield 530 may be positioned in the slots used to form the vertical conductive structures 528 (in Fig.43In some embodiments, electromagnetic shield 530 is positioned entirely within boundary 540. In other embodiments, electromagnetic shield 530 may extend beyond boundary 540. Or, in other words, electromagnetic shield 530 may have a first portion positioned within boundary 540 and a second portion positioned outside boundary 540.

[0172] The boundary 540 of the vertical conductive structure 528 has a length 544 and a width 546. The electromagnetic shield 530 is also provided with a length 548 and a width 550. Fig.43 When shown fully within boundary 540, length 548 is less than length 544 and width 550 is less than width 546. When electromagnetic shield 530 extends beyond boundary 540, length 548 may be greater than length 544 and / or width 550 may be greater than width 546.

[0173] In some embodiments, electromagnetic shield 530 is electrically insulated from conductive segments 518a-f. Electrical isolation may be achieved in a variety of ways, such as by positioning non-conductive fill material 522 between electromagnetic shield 530 and conductive segments 518a-f.

[0174] In the illustrated example, the electromagnetic shield 530 is coextensive with the conductive segments 518a-f to shield the conductive segments 518a-f from each other. For example, each of the conductive segments 518a-f has a first end 560 and a second end 562 (for clarity, only the conductive segment 518a has been labeled with reference numerals 560 and 562). The electromagnetic shield 530 is provided with a first end 564 and a second end 566. The first end 564 of the electromagnetic shield 530 can be positioned coplanar with the first end 560 of the conductive segments 518a-f, and the second end 566 of the electromagnetic shield 530 can be positioned coplanar with the second end 562 of the conductive segments 518a-f. In some embodiments, the electromagnetic shield 530 extends beyond the first end 560 and / or the second end 562 to provide additional shielding capabilities. This can be achieved, for example, when the electromagnetic shield 530 is in a through configuration and the conductive segments 518a-f are in a buried structure and / or a blind configuration.

[0175] exist Fig.41 In the example of the electromagnetic shield 530 depicted, the electromagnetic shield 530 extends in a substantially linear direction. However, it should be understood that the electromagnetic shield 530 can be provided in a variety of shapes, including a cross shape, an a+ shape, a T shape, etc., so as to shield one or more of the conductive segments 518a-f from one or more other conductive segments of the conductive segments 518a-f.

[0176] The electromagnetic shield 530 can be constructed as follows. After the vertical conductive structure 528 has been formed and the slot has been filled with the non-conductive filling material 522, at least a portion of the non-conductive filling material 522 is removed by forming a second slot 570 within the boundary 540, and electroplating is performed. The second slot 570 has a peripheral sidewall 572 and can extend parallel to the boundary 540 of the slot used to form the vertical conductive structure 528. The second slot 570 can have a width 550 and can also have rounded ends. In one embodiment, the ends of the second slot 570 can be formed by drilling perpendicular to the first side 504, and the remainder of the second slot 570 can be removed by reciprocating a milling cutter between the ends of the second slot 570. In this embodiment, the two holes are formed spaced apart from each other, and the second slot 570 is formed between the two holes and extends from one of the holes to the other hole.

[0177] When the second slot 570 is formed in a blind configuration, the second slot 570 may have a floor (not shown).

[0178] The second slot 570 may be formed using a straight mill (with or without end milling), but any conventional method may be used, such as drilling, routing, milling, punching, laser drilling / cutting / ablation, waterjet cutting or photodefinition, or electrical discharge machining.

[0179] Thereafter, the peripheral sidewall 572 of the substrate 502 defining the second slot 570 may be plated to form the electromagnetic shield 530. As described above, this may be achieved by providing a conductive seed layer (not shown) and then adding a conductive layer. The electromagnetic shield 530 is preferably a continuous conductive layer. In other embodiments, the second slot 570 may be filled with a conductive material to form the electromagnetic shield 530. In one embodiment, the conductive layer is copper and may be deposited on the peripheral sidewall 572 to a thickness in the range between about 2.54 microns and about 25 microns, to a thickness greater than about 5 microns, or to a thickness of about 15 to 25 microns. For example, for a through structure, the thickness may be in the range of about 20 to 25 microns, and for a blind structure, the thickness may be about 15 microns. The electromagnetic shield 530 may be thick enough to provide a robust mechanical structure that can withstand the thermal fluctuations and corrosive treatments to which the printed circuit board is subjected during subsequent component assembly and use.

[0180] In one embodiment, the conductive layer forming electromagnetic shield 530 is deposited using an electrolytic plating process. The electrolytic process may be followed by a surface treatment step involving a direct metallization process or an electroless process. The plated layer may be a conductive material such as silver or copper paste.

[0181] The surface treatment step includes depositing a thin layer of conductive seed that sensitizes the surface and facilitates adhesion of the electromagnetic shield 530 to the peripheral sidewall 5. Direct metallization includes depositing a thin layer of conductive molecules (not shown) on the substrate surface and the sidewalls of the second slot 570 before depositing the electromagnetic shield 530. The electromagnetic shield 530 can also be palladium or platinum. This process avoids the typical catalytic deposition of copper, making the device more economically feasible.

[0182] The electroless surface treatment process includes depositing a thin conductive seed layer (not shown), which may be copper, on the surface of the sidewalls prior to depositing the electromagnetic shield 530 to a thickness in a range between about 30 microns and about 200 microns, and in one embodiment, to a thickness in a range between about 70 microns and about 80 microns.

[0183] The surface treatment prior to the electrolytic deposition may result in a non-linear distribution of the electromagnetic shield 530 on the peripheral sidewall 572 due to the natural tendency of the thickness of the electromagnetic shield 530 to decrease with increasing depth of the sidewall.

[0184] The electromagnetic shield 530 is preferably a continuous layer of conductive material. After formation, the electromagnetic shield 530 is preferably not divided into conductive segments. In some embodiments, the electromagnetic shield 530 can be connected to a reference voltage such as ground. Further, in some embodiments, after the electromagnetic shield 530 is formed, the second slot 570 can be filled with a conductive or non-conductive filling material, such as a conductive paste or polymer. In these embodiments, the filling material can engage the electromagnetic shield 530. In addition, the electromagnetic shield 530 serves as a shielding and signal conducting element. The electromagnetic shield 530 is disposed in the slot (in the vertical conductive structure 528) used to form the vertical conductive structure 528. Fig.43 A capacitance and inductance structure for the vertical traces 518 (c, d, e) is created within the boundary 540 (shown by a dashed line in FIG. 1 ). The distance of the electromagnetic shield 530 to the vertical traces (c, d, e) can be changed to adjust the impedance of the vertical traces (c, d, e) to a desired value.

[0185] It should be further understood that although the vertical conductive structures discussed herein are shown as linear or straight structures, they may also be curved, arcuate, or any other shape that supports the present design.

[0186] As can be understood from the foregoing description, without departing from the true spirit of the present invention, various modifications and changes can be made to the preferred and alternative embodiments of the present invention.For example, embodiments of the present invention can be combined with high density interconnect (HDI) technology.Because the vertical conductive structure is formed into many different structures of through-holes, blind holes and / or buried holes as known to standard PCB technology, vertical conductive structures 16, 110, 136a, 136b, 150 and 184 can also be so.Therefore, the process described herein can be used in combination with including but not limited to known PCB technology and multiple sequential / high density interconnection build-up structures that passive components and / or active components are embedded in PCB.Any sequential or high density interconnection structure using through-holes or any buried holes and blind holes / microvias can be turned into a structure using vertical conductive structures 16, 110, 136a, 136b, 150 and 184. Furthermore, the processes described herein for forming vertical conductive structures 16, 110, 136a, 136b, 150, and 184 may be used to construct single chip modules, multi-chip modules, and printed circuit boards including back planes and mid-planes.

[0187] It is clear from the above description that the inventive concept disclosed and claimed herein is well adapted to achieve the objects mentioned herein and to obtain the advantages mentioned herein and inherent in the present invention. Although exemplary embodiments of the inventive concept have been described for the purposes of this disclosure, it should be understood that many changes that will occur to those skilled in the art can be made within the spirit of the disclosed inventive concept and / or as defined in the appended claims.

Claims

1. A method for manufacturing a printed circuit board, comprising the steps of: forming a slot in a substrate with a milling machine, the substrate having multiple layers of traces including an internal trace and an insulator, the substrate having a first side and a second side and having at least three layers, the slot extending from the first side of the substrate through at least two of the at least three layers and terminating before intersecting the second side of the substrate such that the slot is blind, the slot having a length and a width, the length being greater than the width, the slot having a bottom and a peripheral sidewall surrounding the slot, wherein at least a portion of the peripheral sidewall is linear along the length of the slot; applying laser light to the bottom of the slot; coating the peripheral sidewall of the substrate with a conductive layer; separating the conductive layer into at least two electrically isolated conductive segments along the peripheral sidewall of the substrate to provide electrical connection between the inner trace and other inner or outer traces; filling the slot with a non-conductive fill material; and An electromagnetic shield is formed in the slot.

2. The method according to claim 1, characterized in that The step of separating the conductive layer into at least two electrically isolated segments is further defined as forming at least one transverse slot by removing a first portion of the conductive layer and the substrate and a second portion of the conductive layer and the substrate.

3. The method according to claim 2, characterized in that The first portion and the second portion are aligned and located on opposite sides of the slot.

4. The method according to claim 2, characterized in that: The first portion and the second portion are spaced apart along the length of the slot.

5. The method according to claim 1, characterized in that The step of separating the conductive layer into at least two electrically insulated segments is further defined as positioning a tool having a diameter smaller than the slot into the slot so as to avoid contact with the conductive layer when the tool is positioned within the slot, and moving the tool laterally into the conductive layer and the peripheral sidewall to form at least one transverse slot separating the conductive layer into the at least two conductive segments.

6. The method according to claim 1, characterized in that The slot has a floor, and the method further includes coating the floor with the conductive layer, and separating the conductive layer is further defined as removing a portion of the conductive layer on the floor of the slot.

7. The method according to claim 1, characterized in that Forming the electromagnetic shield within the slot includes forming the electromagnetic shield between the at least two conductive segments within the non-conductive fill material.

8. The method according to claim 1, characterized in that The slot is a first slot, and forming the electromagnetic shield is further defined as forming a second slot within the non-conductive fill material, and positioning a conductive material within the second slot to form the electromagnetic shield.

9. The method according to claim 8, characterized in that Positioning the conductive material within the second slot is further defined as plating peripheral sidewalls forming a boundary of the second slot with the conductive material.

10. The method according to claim 8, characterized in that Positioning the conductive material within the second slot is further defined as filling the second slot with the conductive material.

11. The method according to claim 10, characterized in that The conductive material is a conductive paste.

12. The method according to claim 1, characterized in that The method also includes covering the slot in the substrate with one or more additional layers such that the slot is in a buried configuration.

13. The method according to claim 1, characterized in that Forming the slot in the substrate with the milling machine further includes forming the slot with a tool head that is movable in at least two different lateral directions within the substrate to remove portions of the conductive layer and / or the substrate.

14. The method according to claim 1, characterized in that The method also includes introducing a fill material into the slot.

15. The method according to claim 1, characterized in that The substrate is a flexible film substrate.

16. The method according to claim 1, characterized in that The step of separating the conductive layer into at least two sections electrically isolated along a peripheral sidewall of the substrate is further defined as: applying a photoresist to the conductive layer; exposing a predetermined portion of the photoresist to light from a laser using an optical fiber tip supported and guided by a computerized guidance system; as well as A predetermined portion of the conductive layer between the at least two segments is etched to electrically insulate the at least two segments.

17. The method according to claim 1, characterized in that The step of separating the conductive layer into at least two sections electrically isolated along a peripheral sidewall of the substrate is further defined as: applying a photoresist to the conductive layer; exposing a predetermined portion of the photoresist to light from an optical fiber tip positioned within the slot; as well as A predetermined portion of the conductive layer between the at least two segments is developed and etched to electrically insulate the at least two segments.

18. The method according to claim 1, characterized in that The length of the slot is at least 2.85 times the width of the slot.

19. A method for manufacturing a printed circuit board, comprising the steps of: forming a first slot in a substrate having a first side and a second side and having at least three layers, the first slot having a depth extending from the first side of the substrate through at least two of the at least three layers and terminating before intersecting the second side of the substrate such that the first slot is blind, the substrate having multiple layers of traces including an inner trace and an insulator, the first slot having a length and a width, the length being greater than the width, the first slot having a perimeter sidewall, wherein at least a portion of the perimeter sidewall is linear along the length of the first slot; coating a peripheral sidewall of the substrate surrounding the first slot with a conductive layer; and separating the conductive layer into at least two electrically isolated conductive segments along the peripheral sidewall of the substrate to provide electrical connection between the inner trace and other inner or outer traces; filling the first slot with a non-conductive filling material; forming a second slot in the non-conductive fill material; and An electromagnetic shield is formed between at least two of the conductive segments by positioning a conductive material within the second slot between the at least two conductive segments.

20. The method according to claim 19, characterized in that Positioning the conductive material within the second slot is further defined as plating peripheral sidewalls forming a boundary of the second slot with the conductive material.

21. The method according to claim 20, characterized in that The method also includes filling the second slot with a non-conductive fill material.

22. The method according to claim 19, characterized in that Positioning the conductive material within the second slot is further defined as filling the second slot with the conductive material.

23. The method according to claim 22, characterized in that The conductive material is a conductive paste.

24. The method according to claim 19, characterized in that The depth of the electromagnetic shielding portion is greater than the depth of the first slot.

25. The method according to claim 19, characterized in that The depth of the electromagnetic shielding portion is smaller than the depth of the first slot.

26. The method according to claim 19, characterized in that The depth of the electromagnetic shielding portion is equal to the depth of the first slot.

27. The method according to claim 19, characterized in that The second slot is blind.

28. The method according to claim 19, characterized in that The length of the second slot extends parallel to the portion of the peripheral sidewall of the first slot that is linear along the length of the first slot.

29. The method according to claim 19, characterized in that The second slot is offset along a length of the first slot.

30. The method according to claim 19, characterized in that The at least two conductive segments include a first conductive segment, a second conductive segment, a third conductive segment and a fourth conductive segment, and forming the electromagnetic shield between at least two of the conductive segments by positioning the conductive material within the second slot between the two conductive segments includes positioning the conductive material between the first conductive segment and the second conductive segment without extending it between the third conductive segment and the fourth conductive segment.

31. The method according to claim 19, characterized in that The second slot is offset within the first slot.

32. The method according to claim 19, characterized in that The position of the electromagnetic shield is based on a desired impedance of the conductive segment.

33. The method according to claim 19, characterized in that The first slot has a floor, and the method further includes coating the floor with the conductive layer, and separating the conductive layer is further defined as removing a portion of the conductive layer on the floor of the first slot.

34. The method according to claim 19, characterized in that The method also includes covering the first slot in the substrate with one or more additional layers such that the first slot is in a buried configuration.

35. The method according to claim 19, characterized in that The substrate is a flexible film substrate.

36. A printed circuit board comprising: A substrate having a first side and a second side and having at least three layers between the first side and the second side, the substrate having a multilayer trace including a first inner trace and an insulator, the substrate having a first slot having a depth extending from the first side of the substrate through at least two of the at least three layers and terminating before intersecting the second side of the substrate such that the first slot is blind, the first slot having a length and a width, the length being greater than the width, the first slot having a peripheral sidewall, wherein at least a portion of the peripheral sidewall is linear along the length of the first slot, the peripheral sidewall having a coating of a conductive layer, the conductive layer being separated into at least two conductive segments electrically insulated along the peripheral sidewall of the substrate to provide an electrical connection between the first inner trace and other inner or outer traces, the first slot being filled with a non-conductive filling material, the substrate having a second slot formed within the conductive filling material, the second slot having a conductive layer located between the at least two conductive segments of the first slot to form an electromagnetic shield between the at least two conductive segments.

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