Semiconductor structure preparation method

Abstract

The present disclosure relates to a method for preparing a semiconductor structure. The method comprises: providing a substrate; forming an alignment mark in the substrate, wherein the alignment mark is a groove; forming a first dielectric layer and a mask layer stacked from bottom to top on the surface of the substrate and in the alignment mark, wherein the upper surface of the mask layer in the alignment mark is lower than the upper surface of the substrate; and removing the mask layer outside the alignment mark. The method can simplify the semiconductor process steps and omit the window opening process and etching process related to the mask layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure. Background Art

[0002] The photolithography process plays a vital role in the semiconductor process, and the alignment mark has a significant impact on the alignment accuracy of the photolithography process.

[0003] In the current process, after the alignment mark passes through the active area process, an additional zero-layer window lithography and etching process is required to remove the silicon dioxide above the alignment mark area, so that the subsequent process can remove the silicon nitride in the alignment mark groove. In this process, the addition of a mask layer increases the process steps and costs. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor structure preparation method that can omit the zero-layer window opening process and etching process related to the mask layer in order to solve the above technical problems.

[0005] In a first aspect, the present disclosure provides a method for preparing a semiconductor structure. The method comprises:

[0006] providing a substrate;

[0007] forming an alignment mark in the substrate, wherein the alignment mark is a groove;

[0008] Forming a first dielectric layer and a mask layer stacked sequentially from bottom to top on the surface of the substrate and in the alignment mark, wherein the upper surface of the mask layer in the alignment mark is lower than the upper surface of the substrate;

[0009] The mask layer outside the alignment mark is removed.

[0010] In one embodiment, the mask layer includes a second dielectric layer and a third dielectric layer, the second dielectric layer is located on a surface of the first dielectric layer away from the substrate, and the third dielectric layer is located on a surface of the second dielectric layer away from the substrate.

[0011] In one embodiment, the first dielectric layer includes a silicon oxide layer; the second dielectric layer includes a silicon nitride layer; and the third dielectric layer includes a silicon oxynitride layer.

[0012] In one embodiment, removing the mask layer outside the alignment mark comprises:

[0013] Etching and removing the third dielectric layer outside the alignment mark and a portion of the second dielectric layer outside the alignment mark;

[0014] The second dielectric layer outside the alignment mark is removed.

[0015] In one embodiment, the etching to remove the third dielectric layer outside the alignment mark and a portion of the second dielectric layer outside the alignment mark comprises:

[0016] Forming a patterned photoresist layer, the patterned photoresist layer is located on the surface of the third dielectric layer and fills the alignment mark; an opening is formed in the patterned photoresist layer, the opening exposes a portion of the surface of the third dielectric layer to define the shape and position of the shallow trench;

[0017] Based on the patterned photoresist layer, the third dielectric layer, the second dielectric layer, the first dielectric layer and the substrate are etched to form a shallow groove in the substrate; in the process of forming the shallow groove, the patterned photoresist layer, the third dielectric layer outside the alignment mark and a part of the second dielectric layer outside the alignment mark are etched away;

[0018] After forming the shallow trench and before etching away the second dielectric layer outside the alignment mark, the method further includes:

[0019] A fourth dielectric layer is formed, the fourth dielectric layer fills the alignment mark and the shallow groove and covers the reserved second dielectric layer; the fourth dielectric layer is a light-transmitting material layer.

[0020] In one embodiment, before etching away the second dielectric layer outside the alignment mark, the method further includes:

[0021] The fourth dielectric layer outside the alignment mark and outside the shallow trench is removed.

[0022] In one embodiment, removing the fourth dielectric layer outside the alignment mark comprises: removing the fourth dielectric layer outside the alignment mark and outside the shallow trench by using a chemical mechanical polishing process;

[0023] The removing of the second dielectric layer outside the alignment mark comprises: removing a portion of the second dielectric layer outside the alignment mark by using a chemical mechanical polishing process;

[0024] The second dielectric layer remaining outside the alignment mark is removed by a wet etching process.

[0025] In one embodiment, the thickness of the second dielectric layer remaining outside the alignment mark is less than or equal to

[0026] In one embodiment, the depth of the alignment mark is

[0027] In one embodiment, the height difference between the upper surface of the mask layer located in the alignment mark and the upper surface of the substrate is

[0028] The above-mentioned semiconductor structure preparation method controls the depth of the alignment mark so that after preparing the first dielectric layer and the mask layer, the groove above the upper surface of the mask layer in the groove serving as the alignment mark still meets the alignment requirements of the lithography process, thereby simplifying the semiconductor process steps and omitting the window opening process and etching process related to the mask layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description are used to explain the principles of the present disclosure, and do not constitute improper limitations on the present disclosure.

[0030] Figure 1 is a schematic flow chart of a method for preparing a semiconductor structure in one embodiment;

[0031] Figure 2 A schematic diagram of a cross-sectional structure of a semiconductor structure obtained in step S20 in one embodiment;

[0032] Figure 3 A schematic diagram of a cross-sectional structure of a semiconductor structure obtained in step S30 in one embodiment;

[0033] Figure 4 is a schematic diagram of a cross-sectional structure of a semiconductor structure obtained in step S30 in another embodiment;

[0034] Figure 5 is a schematic diagram of a cross-sectional structure of a semiconductor structure obtained before step S40 in another embodiment;

[0035] Figure 6 is a schematic diagram of a cross-sectional structure of a semiconductor structure obtained in step S40 in another embodiment;

[0036] Figure 7 A schematic diagram of a sub-flow chart of step S40 of a method for preparing a semiconductor structure in an embodiment;

[0037] Figure 8 is a schematic diagram of a cross-sectional structure of a semiconductor structure obtained in step S406 in another embodiment;

[0038] Fig. 9 It is a schematic diagram of a sub-flow of step S40 of the method for preparing a semiconductor structure in another embodiment;

[0039] Fig.10 is a schematic diagram of a cross-sectional structure of a semiconductor structure obtained in step S504 in another embodiment;

[0040] Fig.11 FIG. 4 is a schematic diagram of a cross-sectional structure of a semiconductor structure obtained in step S506 in another embodiment.

[0041] Description of reference numerals:

[0042] 110 - substrate, 120 - alignment mark, 130 - first dielectric layer, 140 - mask layer, 141 - second dielectric layer, 142 - third dielectric layer, 150 - photoresist layer, 160 - fourth dielectric layer. DETAILED DESCRIPTION

[0043] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0045] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0046] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0047] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0048] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0049] The present invention provides a method for preparing a semiconductor structure, such as Figure 1 As shown, the following steps are included:

[0050] S10, providing a substrate;

[0051] S20, forming an alignment mark in the substrate, wherein the alignment mark is a groove;

[0052] S30, forming a first dielectric layer and a mask layer stacked sequentially from bottom to top on the surface of the substrate and in the alignment mark, wherein the upper surface of the mask layer in the alignment mark is lower than the upper surface of the substrate;

[0053] S40, removing the mask layer outside the alignment mark.

[0054] In step S10 , a substrate 110 for preparing a semiconductor structure is provided, and the substrate is generally a silicon substrate.

[0055] In step S20, Figure 2 As shown, an alignment mark 120 is formed in the substrate 110, and the alignment mark is a groove. The number of grooves, that is, the number of alignment marks, is determined according to actual needs and is not specifically limited. Specifically, the alignment mark may include but is not limited to a zero layer mark.

[0056] In one embodiment, the depth of the alignment mark is Right now Figure 2 The depth of the alignment mark 120 satisfies the depth range In this embodiment, by controlling the depth of the alignment mark 120 , it is possible to achieve the beneficial effect of ensuring that after the alignment mark 120 is subsequently filled with the first dielectric layer and the mask layer, the remaining groove height can still meet the alignment requirements of the photolithography process.

[0057] In step S30, Figure 3As shown, a first dielectric layer 130 and a mask layer 140 are formed on the surface of the substrate 110 and in the alignment mark 120, which are stacked from bottom to top. The first dielectric layer 130 generally has an insulating function. The mask layer 140 can have a masking function. The mask layer 140 can also have a function as an anti-reflection layer. The mask layer 140 can include a single layer of material or multiple layers of material. The upper surface of the mask layer 140 located in the alignment mark 120 is lower than the upper surface of the substrate 110, that is, after the first dielectric layer 130 and the mask layer 140 are filled in the alignment mark 120, there is still an unfilled space above the mask layer 140 in the alignment mark 120. The distance between the upper surface of the mask layer 140 in the alignment mark 120 and the upper surface of the substrate 110 needs to meet the alignment requirements of the photolithography process. The photolithography process requires that the depth of the alignment mark groove reaches a certain threshold, and the specific value of the threshold is determined by the specific photolithography process equipment.

[0058] In one embodiment, the height difference between the upper surface of the mask layer 140 located in the alignment mark 120 and the upper surface of the substrate 110 satisfies the height range In this embodiment, by controlling the height difference between the upper surface of the mask layer 140 in the alignment mark 120 and the upper surface of the substrate 110 , the beneficial effect of ensuring that the height difference meets the alignment requirement of the photolithography process can be achieved.

[0059] In one embodiment, Figure 4 As shown, the mask layer 140 includes a second dielectric layer 141 and a third dielectric layer 142, the second dielectric layer 141 is located on the surface of the first dielectric layer 130 away from the substrate 110, and the third dielectric layer 142 is located on the surface of the second dielectric layer 141 away from the substrate 110. The third dielectric layer 142 can be an anti-reflection layer. In this embodiment, two dielectric layers are used as mask layers, and the third dielectric layer is an anti-reflection layer, which can achieve a beneficial effect that is more in line with the actual preparation requirements of the semiconductor structure.

[0060] In one embodiment, the first dielectric layer includes a silicon oxide layer. The second dielectric layer includes a silicon nitride layer. The third dielectric layer includes a silicon oxynitride layer. In this embodiment, by limiting the materials of the first dielectric layer, the second dielectric layer, and the third dielectric layer, the beneficial effect of better meeting the requirements for semiconductor structure preparation can be achieved.

[0061] In one embodiment, after step S30, active area photolithography is performed due to the need for device preparation. Figure 5As shown, the photoresist layer 150 will cover the entire mark, including filling the alignment mark 120 and covering the mask layer 140. The top of the photoresist layer 150 tends to be flat. After the active area is etched, the photoresist 150 will be consumed. In this embodiment, the photolithography step in the semiconductor structure preparation process is supplemented, which can achieve the beneficial effect of better meeting the semiconductor structure preparation requirements.

[0062] In step S40, the mask layer 140 outside the alignment mark 120 serving as the alignment mark is removed. The specific process used can be selected according to actual needs, for example, it can be an etching process or a chemical mechanical mask process, or multiple processes capable of removing the mask layer 140 can be used successively or simultaneously. The cross-sectional view of the semiconductor structure after removing the mask layer 140 can be as follows: Figure 6 shown.

[0063] In this embodiment, by controlling the depth of the alignment mark 120, after preparing the first dielectric layer 130 and the mask layer 140, the upper surface of the mask layer 140 in the alignment mark 120 is lower than the upper surface of the substrate 110, and the distance between the two upper surfaces meets the alignment requirements of the photolithography process, that is, the groove above the upper surface of the mask layer 140 meets the alignment requirements of the photolithography process, which can achieve the beneficial effect of simplifying the semiconductor process steps, including omitting the process of removing the mask layer in the alignment mark 120 and the zero-layer window opening process related to removing the mask layer in the alignment mark 120.

[0064] In one embodiment, the active area photolithography consumes part of the mask layer 140, that is, the mask layer 140 outside the alignment mark 120 is partially removed, so that the thickness of the mask layer 140 outside the alignment mark 120 becomes thinner. Then, by an etching process, such as a wet etching process, the remaining mask layer 140 outside the alignment mark 120 is completely removed. In this embodiment, after the active area photolithography removes part of the mask layer, the remaining mask layer is removed by etching, which can achieve the beneficial effect of ensuring that the mask layer outside the alignment mark 120 is completely removed.

[0065] In one embodiment, the mask layer 140 is removed in two steps. First, the third dielectric layer 142 outside the alignment mark 120 and a portion of the second dielectric layer 141 outside the alignment mark 120 are removed by etching. Then, the retained second dielectric layer 141 outside the alignment mark 120 is removed. Specifically, the third dielectric layer and a portion of the second dielectric layer are first removed in the active area lithography, and then the retained second dielectric layer is removed by etching. In this embodiment, by limiting the mask layer removal process when the mask layer includes the second dielectric layer and the third dielectric layer, the beneficial effect of better meeting the requirements of the mask layer removal process outside the groove can be achieved.

[0066] In one embodiment, after removing the portion of the second dielectric layer 141 outside the alignment mark 120, the thickness of the second dielectric layer 141 remaining outside the alignment mark 120 is less than or equal to In this embodiment, by limiting the thickness of the second dielectric layer retained outside the groove, the beneficial effect of better meeting the process requirements of removing the mask layer outside the groove can be achieved.

[0067] In one embodiment, Figure 7 As shown, the etching to remove the third medium outside the alignment mark and a portion of the second medium layer outside the alignment mark includes:

[0068] S402, forming a patterned photoresist layer, wherein the patterned photoresist layer is located on the surface of the third dielectric layer and fills the alignment mark; an opening is formed in the patterned photoresist layer, wherein the opening exposes a portion of the surface of the third dielectric layer to define the shape and position of the shallow trench;

[0069] S404, etching the third dielectric layer, the second dielectric layer, the first dielectric layer and the substrate based on the patterned photoresist layer to form a shallow trench in the substrate; in the process of forming the shallow trench, etching and removing the patterned photoresist layer, the third dielectric layer outside the alignment mark and a portion of the second dielectric layer outside the alignment mark;

[0070] S406, after forming the shallow trench and before etching away the second dielectric layer outside the alignment mark, further comprising:

[0071] A fourth dielectric layer is formed, the fourth dielectric layer fills the alignment mark and the shallow groove and covers the reserved second dielectric layer; the fourth dielectric layer is a light-transmitting material layer.

[0072] Specifically, the etching and removing of the third dielectric layer 142 outside the alignment mark 120 and a portion of the second dielectric layer 141 outside the alignment mark 120 includes:

[0073] The photoresist layer 150 is a patterned photoresist layer, which is located on the surface of the third dielectric layer 142 and fills the alignment mark 120 as an alignment mark. An opening is formed in the patterned photoresist layer, and the opening exposes a portion of the surface of the third dielectric layer 142 to define the shape and position of the shallow groove. Based on the patterned photoresist layer, the third dielectric layer, the second dielectric layer, the first dielectric layer and the substrate are etched to form a shallow groove in the substrate; in the process of forming the shallow groove, the patterned photoresist layer, the third dielectric layer outside the alignment mark and a portion of the second dielectric layer outside the alignment mark are etched away. The preparation of the patterned photoresist layer and the formation of the shallow groove are common preparation links of semiconductor structures in the prior art, so they are not described in detail, and the relevant links can be improved in various ways or designed in different specific ways according to actual needs, which is not limited in this case. After forming the shallow groove, before etching away the second dielectric layer 141 outside the alignment mark 120, it also includes: forming a fourth dielectric layer 160. The fourth dielectric layer 160 fills the alignment mark 120 and the shallow groove, and covers the remaining second dielectric layer 141. The fourth dielectric layer 160 is a light-transmitting material layer. Figure 8 As shown, the fourth dielectric layer 160 fills the alignment mark 120 and covers the retained second dielectric layer 141. The fourth dielectric layer 160 may include a silicon oxide layer. In this embodiment, by selecting a transparent material layer as the fourth dielectric layer when the semiconductor structure preparation process needs to cover the obtained structure with a fourth dielectric layer, the beneficial effect of not blocking the optical path above the third dielectric layer 142 inside the alignment mark 120 can be achieved.

[0074] In one embodiment, before etching and removing the second dielectric layer 141 outside the alignment mark 120, the process further includes: removing the fourth dielectric layer 160 outside the alignment mark 120 and outside the shallow trench. The specific removal method may be to use an etching or chemical mechanical polishing process. In this embodiment, by removing the fourth dielectric layer outside the alignment mark 120, the beneficial effect of better meeting the semiconductor structure preparation requirements can be achieved.

[0075] In one embodiment, Fig. 9 As shown, removing the fourth dielectric layer outside the alignment mark includes:

[0076] S502, removing the fourth dielectric layer outside the alignment mark and outside the shallow trench by using a chemical mechanical polishing process;

[0077] The removing of the second dielectric layer outside the alignment mark comprises:

[0078] S504, removing a portion of the second dielectric layer outside the alignment mark by using a chemical mechanical polishing process;

[0079] S506: Use a wet etching process to remove the second dielectric layer remaining outside the alignment mark.

[0080] Specifically, the removing of the fourth dielectric layer 160 outside the alignment mark 120 includes: removing the fourth dielectric layer 160 outside the alignment mark and outside the shallow trench by using a chemical mechanical polishing process. The removing of the second dielectric layer 141 outside the alignment mark 120 includes: firstly removing a portion of the second dielectric layer 141 outside the alignment mark 120 by using a chemical mechanical polishing process, and grinding the remaining second dielectric layer 141 and the fourth dielectric layer 160 above the alignment mark 120 flat, so as to obtain a cross-section as shown in FIG. Fig.10 The semiconductor structure shown in FIG. 1 is then removed by a wet etching process. The retained second dielectric layer 141 outside the alignment mark 120 is then removed. During this process, the fourth dielectric layer 160 above the alignment mark 120 may be partially removed. The cross-sectional view of the semiconductor structure finally obtained may be as shown in FIG. Fig.11 The upper surface of the fourth dielectric layer 160 above the alignment mark 120 may be flush with or not flush with the upper surface of the first dielectric layer 130. The fourth dielectric layer 160 inside and above the alignment mark 120 is a transparent structure and will not block the optical path used for alignment in the photolithography process.

[0081] In this embodiment, since the fourth dielectric layer 160 is a transparent material and will not block the light path when filled in the alignment mark 120, only the process steps for specifically removing the second dielectric layer (or mask layer) and the fourth dielectric layer outside the alignment mark 120 can be designed, thereby achieving the beneficial effect of omitting the removal of the fourth dielectric layer inside or above the alignment mark 120. At the same time, the process of removing the mask layer inside the alignment mark 120 and the zero-layer window opening process related to removing the mask layer inside the alignment mark 120 can also be omitted, thereby simplifying the semiconductor manufacturing process.

[0082] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0083] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0084] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises: providing a substrate; forming an alignment mark in the substrate, wherein the alignment mark is a groove; A first dielectric layer and a mask layer are formed on the surface of the substrate and in the alignment mark, and are stacked from bottom to top in sequence. The upper surface of the mask layer in the alignment mark is lower than the upper surface of the substrate, and the mask layer exposes a portion of the first dielectric layer of the sidewall of the alignment mark. The mask layer includes a second dielectric layer and a third dielectric layer. The second dielectric layer is located on the surface of the first dielectric layer away from the substrate, and the third dielectric layer is located on the surface of the second dielectric layer away from the substrate. Etching the third dielectric layer, the second dielectric layer, the first dielectric layer and the substrate to form a shallow trench in the substrate; forming a fourth dielectric layer, wherein the fourth dielectric layer fills the alignment mark and the shallow groove and covers the reserved second dielectric layer; the fourth dielectric layer is a light-transmitting material layer; The mask layer outside the alignment mark is removed.

2. The method according to claim 1, characterized in that The first dielectric layer includes a silicon oxide layer; the second dielectric layer includes a silicon nitride layer; and the third dielectric layer includes a silicon oxynitride layer.

3. The method according to claim 1, characterized in that The removing the mask layer outside the alignment mark comprises: Etching and removing the third dielectric layer outside the alignment mark and a portion of the second dielectric layer outside the alignment mark; The second dielectric layer outside the alignment mark is removed.

4. The method according to claim 3, characterized in that The etching and removing of the third dielectric layer outside the alignment mark and a portion of the second dielectric layer outside the alignment mark comprises: A patterned photoresist layer is formed, the patterned photoresist layer is located on the surface of the third dielectric layer and fills the alignment mark; an opening is formed in the patterned photoresist layer, the opening exposes a portion of the surface of the third dielectric layer to define the shape and position of the shallow trench; The third dielectric layer, the second dielectric layer, the first dielectric layer and the substrate are etched based on the patterned photoresist layer to form the shallow groove in the substrate; in the process of forming the shallow groove, the patterned photoresist layer, the third dielectric layer outside the alignment mark and a portion of the second dielectric layer outside the alignment mark are etched away.

5. The method according to claim 4, characterized in that Before etching and removing the second dielectric layer outside the alignment mark, the method further includes: The fourth dielectric layer outside the alignment mark and outside the shallow trench is removed.

6. The method according to claim 5, characterized in that The removing of the fourth dielectric layer outside the alignment mark comprises: removing the fourth dielectric layer outside the alignment mark and outside the shallow trench by using a chemical mechanical polishing process; The removing of the second dielectric layer outside the alignment mark comprises: removing a portion of the second dielectric layer outside the alignment mark by using a chemical mechanical polishing process; The second dielectric layer remaining outside the alignment mark is removed by a wet etching process.

7. The method according to claim 6, characterized in that The thickness of the second dielectric layer retained outside the alignment mark is less than or equal to 8. The method according to any one of claims 1 to 7, characterized in that The depth of the alignment mark is 9. The method according to claim 1, characterized in that: The height difference between the upper surface of the mask layer located in the alignment mark and the upper surface of the substrate is

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