GaN power chip with junction temperature monitoring and over-temperature protection capabilities and preparation method

Abstract

The present invention relates to a GaN power chip with junction temperature monitoring and over-temperature protection capabilities, comprising: a power device, a first ohmic contact structure, a second ohmic contact structure and a temperature sensor diode which are sequentially distributed laterally on a two-dimensional electron gas structure and electrically isolated from each other; the power device comprises a source, a drain and a gate; the first ohmic contact structure comprises a first ohmic contact electrode and a second ohmic contact electrode which are spaced apart; the second ohmic contact structure comprises a third ohmic contact electrode and a fourth ohmic contact electrode which are spaced apart; the temperature sensor diode comprises a cathode, an anode and a first part of a P-GaN layer; the first ohmic contact electrode is used for grounding, the second ohmic contact electrode and the third ohmic contact electrode and the gate are connected in parallel, the fourth ohmic contact electrode and the cathode are connected in series and used for outputting a voltage, and the anode is used for connecting a power supply voltage. The GaN power chip can monitor the junction temperature change of the power device in situ, and can also realize an over-temperature intelligent protection mechanism.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor intelligent power modules, and in particular relates to a GaN power chip with junction temperature monitoring and over-temperature protection capabilities and a preparation method thereof. Background Art

[0002] In recent years, GaN materials have attracted extensive attention and applications in the field of power electronics due to their advantages such as large bandgap, high breakdown electric field, fast response speed, radiation resistance and high temperature resistance. High electron mobility transistor (HEMT) devices made of them have gradually become the first choice in high-frequency and high-power applications due to their excellent switching characteristics and voltage resistance. GaN-based HEMT devices are core devices for high-frequency power conversion applications. In recent years, they have been widely used in fast chargers, electric vehicles, space radars and other fields. However, new applications have higher reliability requirements for GaN-based HEMT devices, and the reliability problems caused by device degradation cannot be ignored. The most common is the impact of long-term high operating temperature on the performance of GaN-based HEMT devices. When HEMT devices are working, frequent switching conversions will cause the heterojunction temperature to rise rapidly, and the carrier mobility of the two-dimensional electron gas (2DEG) channel will deteriorate due to the influence of temperature. Long-term operation at high temperatures may cause device degradation and reduced life, and serious safety problems.

[0003] In order to reduce or avoid device failures caused by high temperatures, in practical applications, the temperature of GaN-based power devices can be monitored and protected by designing temperature monitoring circuits and feedback protection circuits at the board level. However, this method has several disadvantages: 1. The response speed is slow, and the junction temperature of the HEMT device cannot be monitored in situ, and the shutdown response cannot be made immediately when the temperature of the HEMT rises; 2. The integration is low, the design and production costs are high, and the board-level circuit volume is large, which does not conform to the design trend of power chips; 3. It will generate additional power consumption and a series of parasitic crosstalk, which is not conducive to the efficient operation of the power module and energy conservation. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a GaN power chip with junction temperature monitoring and over-temperature protection capabilities and a preparation method. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] The embodiment of the present invention provides a GaN power chip with junction temperature monitoring and over-temperature protection capabilities, including: power devices, a first ohmic contact structure, a second ohmic contact structure, and a temperature sensor diode, which are sequentially distributed laterally on a two-dimensional electron gas structure and electrically isolated from each other, wherein:

[0006] The power device comprises a source, a drain and a gate, wherein the source, the gate and the drain are sequentially and spaced apart and distributed above the two-dimensional electron gas channel in the two-dimensional electron gas structure;

[0007] The first ohmic contact structure comprises a first ohmic contact electrode and a second ohmic contact electrode, wherein the first ohmic contact electrode and the second ohmic contact electrode are spaced apart and distributed above the two-dimensional electron gas channel;

[0008] The second ohmic contact structure comprises a third ohmic contact electrode and a fourth ohmic contact electrode, and the third ohmic contact electrode and the fourth ohmic contact electrode are spaced apart and distributed above the two-dimensional electron gas channel;

[0009] The temperature sensor diode comprises a cathode, an anode and a first portion of a P-GaN layer, wherein the first portion of the P-GaN layer is located on a surface of the two-dimensional electron gas structure, the cathode is located on one side of the first portion of the P-GaN layer and is located above the two-dimensional electron gas channel, and the anode is in contact with the other side of the first portion of the P-GaN layer and is located above the two-dimensional electron gas channel;

[0010] The first ohmic contact electrode is used for grounding, the second ohmic contact electrode and the third ohmic contact electrode are connected through a metal interconnection line, and the interconnected electrodes are connected to the gate through a metal interconnection line, the fourth ohmic contact electrode and the cathode are connected through a metal interconnection line and are used for outputting voltage, and the anode is used for connecting a power supply voltage.

[0011] In one embodiment of the present invention, the two-dimensional electron gas structure includes a substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer stacked in sequence from bottom to top, wherein the channel layer and the barrier layer form a two-dimensional electron gas channel.

[0012] In one embodiment of the present invention, the source electrode, the drain electrode, the first ohmic contact electrode, the second ohmic contact electrode, the third ohmic contact electrode, and the cathode all extend to the surface of the channel layer;

[0013] The gate and the anode are both located on the surface of the barrier layer.

[0014] In one embodiment of the present invention, the power device further comprises a second partial P-GaN layer, wherein the partial P-GaN layer is located on the surface of the two-dimensional electron gas structure between the source and the drain;

[0015] The gate is located on the surface of the second portion of the P-GaN layer.

[0016] In one embodiment of the present invention, the materials of the first portion of the P-GaN layer and the second portion of the P-GaN layer both include Mg + Ion-doped GaN, hole doping concentration is 10 17 -10 18 cm -3 , the thickness is 60-80nm.

[0017] In one embodiment of the present invention, a passivation layer is further included, wherein the passivation layer covers the surface of the two-dimensional electron gas structure, the surface of the first portion of the P-GaN layer, and the surface of the electrical isolation structure;

[0018] The anode overlaps the passivation layer.

[0019] In one embodiment of the present invention, the material of the passivation layer includes Si3N4, and the thickness is 100-150nm.

[0020] In one embodiment of the present invention, the source electrode, the drain electrode, the first ohmic contact electrode, the second ohmic contact electrode, the third ohmic contact electrode, the fourth ohmic contact electrode, and the cathode are all made of ohmic metal, including one or more of Ti, Al, Ni, and Au;

[0021] The gate and the anode are made of Schottky metal, including one or more of TiN, Ti, and Al;

[0022] The material of the metal interconnection line includes Cu.

[0023] Another embodiment of the present invention provides a method for preparing a GaN power chip with junction temperature monitoring and over-temperature protection capabilities, comprising the steps of:

[0024] S1, preparing a two-dimensional electron gas structure, preparing a P-type GaN layer in the two-dimensional electron gas structure, and etching the P-type GaN layer to form a first partial P-GaN layer;

[0025] S2, etching the two-dimensional electron gas structure to below the two-dimensional electron gas channel to form a plurality of electrical isolation structures to isolate the two-dimensional electron gas structure into a power device region, a first ohmic contact resistance region, a second ohmic contact resistance region and a temperature sensor diode region which are sequentially arranged laterally;

[0026] S3, depositing a passivation layer on the surface of the two-dimensional electron gas structure, the first part of the P-GaN layer, and the surfaces of the plurality of electrical isolation structures;

[0027] S4, preparing a metal electrode above the two-dimensional electron gas channel of the two-dimensional electron gas structure to form a source, a drain, a gate, a first ohmic contact electrode, a second ohmic contact electrode, a third ohmic contact electrode, a fourth ohmic contact electrode, a cathode and an anode, wherein the source, the gate and the drain are sequentially spaced above the two-dimensional electron gas channel in the two-dimensional electron gas structure, the first ohmic contact electrode and the second ohmic contact electrode are spaced above the two-dimensional electron gas channel, the third ohmic contact electrode and the fourth ohmic contact electrode are spaced above the two-dimensional electron gas channel, the cathode is located on one side of the first part of the P-GaN layer and above the two-dimensional electron gas channel, the anode is in contact with the other side of the first part of the P-GaN layer and is located above the two-dimensional electron gas channel; the first ohmic contact electrode is used for grounding, and the anode is used for connecting a power supply voltage;

[0028] S5. Use a metal interconnection line to connect the second ohmic contact electrode and the third ohmic contact electrode, and connect the interconnected electrodes to the gate, and use a metal interconnection line to connect the fourth ohmic contact electrode and the cathode.

[0029] In one embodiment of the present invention, step S4 includes:

[0030] S41, defining a plurality of ohmic metal electrode regions on the surface of the passivation layer, and etching the passivation layer and the two-dimensional electron gas structure in the ohmic metal electrode regions to form a plurality of ohmic metal electrode grooves;

[0031] S42, depositing ohmic metal in the plurality of ohmic metal electrode grooves and performing annealing to form the source electrode, the drain electrode, the first ohmic contact electrode, the second ohmic contact electrode, the third ohmic contact electrode, the fourth ohmic contact electrode and the cathode;

[0032] S43, defining a plurality of Schottky metal electrode regions on the surface of the passivation layer, and etching the passivation layer in the Schottky metal electrode regions to form a plurality of Schottky metal electrode grooves;

[0033] S44, depositing Schottky metal in the plurality of Schottky metal electrode grooves to form the anode and the gate.

[0034] Compared with the prior art, the present invention has the following beneficial effects:

[0035] The GaN power chip of the present invention integrates a power device, a first ohmic contact structure, a second ohmic contact structure and a temperature sensor diode on a two-dimensional electron gas structure, and the second ohmic contact electrode is interconnected with the third ohmic contact electrode and then connected in parallel with the gate, and the first ohmic contact structure and the cathode are connected in series, so that the first ohmic contact structure and the temperature sensor form an over-temperature protection circuit, and the second ohmic contact structure and the temperature sensor form a junction temperature monitoring circuit, which has the following advantages: the junction temperature change of the power device can be monitored in situ with a fast response speed; a combination design of a diode and a resistor is adopted as the temperature sensing part, with high temperature sensitivity and good linearity; an intelligent protection mechanism can be realized in which the device is shut down in time after the operating temperature exceeds the critical temperature and is restored after the operating temperature drops to the critical temperature; the integration is high, the process steps are simple, and the manufacturing cost is low; the power loss is low, and the parasitic effect is small. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram of the three-dimensional structure of a GaN power chip with junction temperature monitoring and over-temperature protection capabilities provided by an embodiment of the present invention;

[0037] Figure 2 A schematic diagram of a main view of a GaN power chip with junction temperature monitoring and over-temperature protection capabilities provided by an embodiment of the present invention;

[0038] Figure 3 A schematic flow chart of a method for preparing a GaN power chip with junction temperature monitoring and over-temperature protection capabilities provided by an embodiment of the present invention;

[0039] Figure 4a-Figure 4i A schematic diagram of a process of preparing a GaN power chip with junction temperature monitoring and over-temperature protection capabilities provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0041] Embodiment 1

[0042] See also Figure 1 and Figure 2 , Figure 1 A schematic diagram of the three-dimensional structure of a GaN power chip with junction temperature monitoring and over-temperature protection capabilities provided by an embodiment of the present invention, Figure 2 A schematic front view of a GaN power chip with junction temperature monitoring and over-temperature protection capabilities provided by an embodiment of the present invention.

[0043] The GaN power chip with junction temperature monitoring and over-temperature protection capabilities of this embodiment includes three functional parts, which are arranged from left to right as follows: 1. lateral power devices, such as GaN lateral power HEMT devices; 2. over-temperature protection intelligent circuit part, including two ohmic contact resistors and GaN lateral diode temperature sensors; 3. junction temperature monitoring intelligent circuit part, including two ohmic contact resistors and GaN lateral diode temperature sensors.

[0044] The GaN power chip specifically includes: a power device 2, a first ohmic contact structure 3, a second ohmic contact structure 4 and a temperature sensor diode 5 which are sequentially distributed laterally on a two-dimensional electron gas structure 1 and electrically isolated from each other. The power device 2 includes a source 21, a drain 22 and a gate 23, and the source 21, the gate 23 and the drain 22 are sequentially distributed above the two-dimensional electron gas channel in the two-dimensional electron gas structure 1; the first ohmic contact structure 3 includes a first ohmic contact electrode 31 and a second ohmic contact electrode 32, and the first ohmic contact electrode 31 and the second ohmic contact electrode 32 are distributed above the two-dimensional electron gas channel; the second ohmic contact structure 4 includes a third ohmic contact electrode 41 and a fourth ohmic contact electrode 42, and the third ohmic contact electrode 41 and the fourth ohmic contact electrode 42 are distributed above the two-dimensional electron gas channel; the temperature sensor diode 5 includes a cathode 51, an anode 52 and a cathode 53. 2 and a first portion of the P-GaN layer 53, the first portion of the P-GaN layer 53 is located on the surface of the two-dimensional electron gas structure 1, the cathode 51 is located on one side of the first portion of the P-GaN layer 53 and is located above the two-dimensional electron gas channel, the anode 52 is in contact with the other side of the first portion of the P-GaN layer 53 and is located above the two-dimensional electron gas channel; the first ohmic contact electrode 31 is used for grounding, the second ohmic contact electrode 32 and the third ohmic contact electrode 41 are connected through metal interconnections, and the interconnected electrodes are connected to the gate 23 through metal interconnections, the first ohmic contact structure 3 and the cathode 51 are connected through metal interconnections and are used for outputting voltage, and the anode 52 is used for connecting a power supply voltage.

[0045] Specifically, the power device 2, the first ohmic contact structure 3, the second ohmic contact structure 4 and the temperature sensor diode 5 are electrically isolated by three isolation grooves, and the bottoms of the three isolation grooves extend to the bottom of the two-dimensional electron gas channel in the two-dimensional electron gas structure 1, isolating the two-dimensional electron gas channel, so that the two-dimensional electron gas structure 1 forms an electrically isolated power device area, a first ohmic contact resistance area, a second ohmic contact resistance area and a temperature sensor diode area, and these four areas are arranged horizontally in sequence, and the power device 2, the first ohmic contact structure 3, the second ohmic contact structure 4 and the temperature sensor diode 5 are arranged in the four areas correspondingly.

[0046] Specifically, the source 21, the drain 22, the gate 23, the first ohmic contact electrode 31, the second ohmic contact electrode 32, the third ohmic contact electrode 41, the fourth ohmic contact electrode 42, the cathode 51, and the anode 52 are all located above the two-dimensional electron gas channel. It can be understood that the bottom of each electrode can be located on the surface of the two-dimensional electron gas structure 1, or can extend to the inside of the two-dimensional electron gas structure 1 and be located at any position above the two-dimensional electron gas channel. Exemplarily, the bottoms of the source 21, the drain 22, the first ohmic contact electrode 31, the second ohmic contact electrode 32, the third ohmic contact electrode 41, and the cathode 51 extend to the inside of the two-dimensional electron gas structure 1 and are located above the two-dimensional electron gas channel, and the gate 23 and the anode 52 are all located on the surface of the barrier layer 15.

[0047] Specifically, the upper surfaces of the first ohmic contact electrode 31 and the anode 52 are provided with interconnected metal wires to achieve connection with an external circuit. The second ohmic contact electrode 32 and the third ohmic contact electrode 41 are connected by metal interconnects, and the interconnected electrodes are connected to the gate 23 by metal interconnects to realize an over-temperature protection intelligent circuit. The first ohmic contact structure 3 and the cathode 51 are connected by metal interconnects to realize a junction temperature monitoring intelligent circuit.

[0048] In a specific embodiment, the two-dimensional electron gas structure 1 includes a substrate 11 , a nucleation layer 12 , a buffer layer 13 , a channel layer 14 and a barrier layer 15 stacked in sequence from bottom to top, wherein a two-dimensional electron gas channel is formed between the channel layer 14 and the barrier layer 15 .

[0049] Specifically, the substrate 11 is made of P-type (1, 1, 1) crystal orientation silicon material; the nucleation layer 12, the buffer layer 13, the channel layer 14 and the barrier layer 15 are made of AlN material, AlGaN material, GaN material and AlGaN material respectively.

[0050] Furthermore, a two-dimensional electron gas channel is formed between the GaN channel layer 14 and the AlGaN barrier layer 15. Accordingly, a plurality of isolation grooves separate the two-dimensional electron gas channel, which may extend to the interior of the GaN channel layer 14 or to the surface of the GaN buffer layer 13. The source 21, the drain 22, the first ohmic contact electrode 31, the second ohmic contact electrode 32, the third ohmic contact electrode 41, and the cathode 51 are located above the two-dimensional electron gas channel, which may extend to the interior of the AlGaN barrier layer 15 or to the surface of the GaN channel layer 14. The gate 23 and the anode 52 are located above the two-dimensional electron gas channel, which may extend to the interior of the AlGaN barrier layer 15 or to the surface of the AlGaN barrier layer 15. Exemplarily, the source 21 , the drain 22 , the first ohmic contact electrode 31 , the second ohmic contact electrode 32 , the third ohmic contact electrode 41 , and the cathode 51 all extend to the surface of the channel layer 14 ; the gate 23 and the anode 52 are both located on the surface of the barrier layer 15 .

[0051] In a specific embodiment, the power device 2 further includes a second partial P-GaN layer 24 , which is located on the surface of the two-dimensional electron gas structure 1 between the source 21 and the drain 22 ; and the gate 23 is located on the surface of the second partial P-GaN layer 24 .

[0052] Specifically, the materials of the first part P-GaN layer 53 and the second part P-GaN layer 24 both include Mg + Ion-doped GaN, hole doping concentration is 10 17 -10 18 cm -3 , the thickness is 60-80nm.

[0053] In a specific embodiment, the GaN power chip further includes a passivation layer 6 , which covers the surface of the two-dimensional electron gas structure 1 , the surface of the first part of the P-GaN layer 53 , and the surface of the electrical isolation structure; the anode 52 overlaps the passivation layer 6 .

[0054] Specifically, the passivation layer 6 covers the upper surface of the barrier layer 15, the upper surface of the first portion of the P-GaN layer 53 and the side surface close to the cathode 52, the upper surface of the second portion of the P-GaN layer 24 except the gate 23, and the bottoms and side walls of several isolation grooves.

[0055] Specifically, the material of the passivation layer 6 includes Si3N4, and the thickness is 100-150 nm.

[0056] Furthermore, the electrode structure of the above-mentioned GaN power chip can be realized through electrode grooves, including: a source groove, a drain groove, a gate groove, a first ohmic contact electrode groove, a second ohmic contact electrode groove, a third ohmic contact electrode groove, a fourth ohmic contact electrode groove, a cathode groove and an anode groove.

[0057] Specifically, the source groove and the drain groove are located on both sides of the second part of the P-GaN layer 24 in the power device region in different opposite directions, and the source groove is close to the second part of the P-GaN layer 24, and the drain groove is far away from the second part of the P-GaN layer 24. The groove depth is equal to the sum of the thickness of the passivation layer 6 and the barrier layer 15; the source 21 and the drain 22 are both made of ohmic contact metal, which fills the source groove and the drain groove and overlaps the passivation layer 6 around the groove. The gate groove is located above the second part of the P-GaN layer 24 in the power HEMT mesa region, and the groove depth is less than the thickness of the passivation layer 6; the gate 23 is a gate Schottky metal, which fills the gate groove and overlaps the passivation layer 6 around the gate groove.

[0058] The first ohmic contact electrode groove and the second ohmic contact electrode groove are located on both lateral sides of the first ohmic contact resistance area and are separated by a certain distance. The distance between the two sides is determined by the designed resistance value. The larger the designed resistance value, the larger the distance. The groove depth is equal to the sum of the thicknesses of the passivation layer 6 and the barrier layer 15. The first ohmic contact electrode 31 adopts ohmic contact metal, which fills the first ohmic contact electrode groove and overlaps the passivation layer 6 around the groove to connect to the ground terminal. The second ohmic contact electrode 32 adopts ohmic contact metal, which fills the second ohmic contact electrode groove and overlaps the passivation layer 6 around the groove, and is connected to the third ohmic contact electrode 41 through a metal interconnection line.

[0059] The third ohmic contact electrode groove and the fourth ohmic contact electrode groove are located on both lateral sides of the second ohmic contact resistance area and are separated by a certain distance. The distance between the two sides is determined by the designed resistance value. The larger the designed resistance value, the larger the distance. The groove depth is equal to the sum of the thickness of the passivation layer 6 and the barrier layer 15. The third ohmic contact electrode 41 adopts ohmic contact metal, which fills the first ohmic contact electrode groove and overlaps the passivation layer 6 around the groove, and is used to connect the ground terminal. The fourth ohmic contact electrode 42 adopts ohmic contact metal, which fills the second ohmic contact electrode groove and overlaps the passivation layer 6 around the groove, and is connected to the rectangular cathode 51 of the high-sensitivity lateral GaN temperature sensor through an interconnecting metal wire.

[0060] The anode groove is located on one side of the first part of the P-GaN layer 53 in the temperature sensor region, and the groove depth is equal to the thickness of the passivation layer 6; the anode 52 is a T-shaped anode, using an anode Schottky metal, the anode Schottky metal fills the anode groove and overlaps the passivation layer 6 around the anode groove, the top of the T-shaped anode metal covers the passivation layer 6, and the anode Schottky metal contacts the side of the first part of the P-GaN layer 53. The cathode groove is located on the other side of the temperature sensor region away from the first part of the P-GaN layer 53, and the groove depth is equal to the sum of the thickness of the passivation layer 6 and the barrier layer 15; the cathode 61 is a rectangular cathode, using a cathode ohmic metal, the cathode ohmic metal fills the cathode groove and overlaps the passivation layer 6 around the cathode groove.

[0061] In this embodiment, the electrode overlaps the passivation layer around the groove, which means that the width of the top of the electrode is greater than the width of the bottom, and the top covers the passivation layer around the groove.

[0062] Exemplarily, the materials of the source 21, the drain 22, the first ohmic contact electrode 31, the second ohmic contact electrode 32, the third ohmic contact electrode 41, the fourth ohmic contact electrode 42, and the cathode 51 are all ohmic metals, including one or more of Ti, Al, Ni, and Au; the materials of the gate 23 and the anode 52 are all Schottky metals, including one or more of TiN, Ti, and Al; and the material of the metal interconnection line includes Cu.

[0063] This embodiment does not limit the thickness of each structural layer of the GaN power chip, and the thickness can be selected according to the actual performance requirements for the T-type anode GaN Schottky temperature sensor.

[0064] A small-amplitude power supply voltage is applied to the T-type anode of the GaN power chip, and the output voltage detection is connected in parallel with the fourth ohmic contact electrode and the cathode of the temperature sensor diode, and the first ohmic contact electrode is grounded, wherein the performance of the ohmic contact electrode is measured by the ohmic contact resistance. The temperature monitoring circuit enters the working state, and the current-voltage relationship between the temperature sensor diode and the ohmic contact resistor is affected differently by temperature. The temperature sensor and the ohmic contact resistor are set in the same branch to keep the current consistent. When the HEMT junction temperature changes, the junction temperature of the sensor diode and the ohmic contact resistor also changes rapidly. The output voltage value is the power supply voltage minus the diode voltage drop, and at the same time the voltage drop on the ohmic contact resistor, which is equivalent to combining the temperature sensing capabilities of the temperature sensor diode and the resistor, significantly increasing the temperature sensitivity of the temperature monitoring circuit.

[0065] The GaN intelligent over-temperature protection circuit connects the gate of the HEMT to the second ohmic contact electrode and the third ohmic contact electrode in parallel. In the protection circuit branch, the temperature sensor diode voltage division and the ohmic contact resistance voltage division are affected differently by temperature, so that the HEMT gate voltage is consistent with the resistance voltage division of the second ohmic contact electrode. The resistance value of the second ohmic contact electrode is designed according to the required threshold voltage, so that the power HEMT can be turned on and work normally at normal temperature. Because the resistance voltage division of the second ohmic contact electrode decreases with the increase of temperature, the critical temperature value is designed according to the working conditions of the HEMT, and the proportion of the resistance of the second ohmic contact electrode in the total branch impedance is adjusted, so that after the junction temperature exceeds the critical temperature, the HEMT gate voltage decreases to below the threshold voltage, the device is turned off, and stops working; after the junction temperature cools to below the critical temperature, the HEMT gate voltage increases to above the threshold voltage, the device is turned on, and resumes working.

[0066] Therefore, the GaN power chip provided in this embodiment has the following beneficial effects:

[0067] First, the temperature monitoring circuit provided in this embodiment is integrated with the GaN power HEMT on the same epitaxial wafer, and the junction temperature change of the GaN HEMT can be measured in situ, thereby improving the response speed of the HEMT temperature monitoring. The design adopts a cascade design of a lateral GaN temperature sensor diode and an ohmic contact resistor to ensure that the temperature sensing function is completed by the sensor diode and the resistor when the voltage input remains unchanged. The temperature sensing capability is the superposition of the sensor diode and the resistor, which greatly improves the temperature sensitivity of the temperature sensing function.

[0068] Secondly, the intelligent over-temperature protection circuit provided in this embodiment is also integrated with the power HEMT and the temperature monitoring circuit on the same epitaxial wafer. By utilizing the characteristic that the temperature rise rate of the GaN temperature sensor diode is higher than the temperature rise rate of the resistor, the gate voltage of the device is adjusted to meet the normal working condition of being greater than the threshold voltage of the power HEMT when the junction temperature is low. After the junction temperature rises to the critical temperature, the resistance voltage division of the second ohmic contact electrode is also equivalent to the gate voltage of the HEMT being pulled down to a voltage less than the threshold voltage of the power HEMT, thereby turning off the device and stopping working, thereby protecting the power device. At the same time, the temperature monitoring circuit does not stop working and can still monitor the junction temperature of the device. When the junction temperature drops below the critical temperature, the gate voltage of the HEMT is pulled up to a voltage greater than the threshold voltage of the power HEMT, the power HEMT is turned on again, and the power chip resumes normal operation.

[0069] Finally, compared with traditional board-level integrated circuits, the intelligent power chip of this embodiment has the advantages of low parasitic crosstalk, small chip size, high integration, low manufacturing cost, and low power loss, and is very suitable for industrial production.

[0070] In summary, the GaN power chip of this embodiment integrates a power device, a first ohmic contact structure, a second ohmic contact structure and a temperature sensor diode on a two-dimensional electron gas structure, and interconnects the second ohmic contact electrode with the third ohmic contact electrode, the interconnected electrodes are connected to the gate, and the first ohmic contact structure and the cathode are connected in series, so that the first ohmic contact structure and the temperature sensor form an over-temperature protection circuit, and the second ohmic contact structure and the temperature sensor form a junction temperature monitoring circuit, which has the following advantages: the junction temperature change of the HEMT can be monitored in situ with a fast response speed; a combination design of a diode and a resistor is used as the temperature sensing part, with high temperature sensitivity and good linearity; an intelligent protection mechanism can be realized that is shut down in time after the operating temperature exceeds the critical temperature and resumes opening after the operating temperature drops to the critical temperature; the integration is high, the process steps are simple, and the manufacturing cost is low; the power loss is low and the parasitic effect is small.

[0071] Embodiment 2

[0072] Based on Example 1, see Figure 3 and Figure 4a-Figure 4i, Figure 3 A schematic flow chart of a method for preparing a GaN power chip with junction temperature monitoring and over-temperature protection capabilities provided by an embodiment of the present invention, Figure 4a-Figure 4i A schematic diagram of a process for preparing a GaN power chip with junction temperature monitoring and over-temperature protection capabilities provided by an embodiment of the present invention. The preparation method comprises the following steps:

[0073] S1, preparing a two-dimensional electron gas structure 1, and preparing a P-type GaN layer in the two-dimensional electron gas structure 1, etching the P-type GaN layer to form a first part of the P-GaN layer 53, such as Figure 4a and 4b shown.

[0074] Specifically, the two-dimensional electron gas structure 1 includes a substrate 11, a nucleation layer 12, a buffer layer 13, a channel layer 14 and a barrier layer 15 stacked in sequence from bottom to top, wherein a two-dimensional electron gas channel is formed between the channel layer 14 and the barrier layer 15. The substrate 11 is made of P-type (1, 1, 1) crystal orientation silicon material; the nucleation layer 12, the buffer layer 13, the channel layer 14 and the barrier layer 15 are made of AlN material, AlGaN material, GaN material and AlGaN material, respectively. Figure 4a As shown. For example, the buffer layer 13 is made of Al 0.3 Ga 0.7 N material, the barrier layer 15 is made of Al 0.2 Ga 0.8 N material.

[0075] Step S1 specifically includes:

[0076] S11. A low-temperature AlN nucleation layer is epitaxially grown on the upper surface of the Si material substrate 11 using a metal-organic chemical vapor deposition (MOCVD) technique, and then a high-temperature AlN nucleation layer is epitaxially grown on the upper surface of the low-temperature AlN nucleation layer, and the two together form a nucleation layer 12; the thickness of the low-temperature AlN nucleation layer may be 30 nm, and the thickness of the high-temperature AlN nucleation layer may be 170 nm.

[0077] S12, using trimethylaluminum as an aluminum source, trimethylgallium as a gallium source, and ammonia as an ammonia source, using MOCVD technology to deposit undoped Al on the surface of the nucleation layer 12 0.3 Ga 0.7 N buffer layer 13, the thickness of the buffer layer 13 is 5 μm.

[0078] S13, using trimethylgallium as a gallium source and ammonia as an ammonia source, an undoped GaN channel layer 14 is deposited on the upper surface of the buffer layer 13 by using MOCVD technology, and the thickness of the channel layer 14 is 200 nm.

[0079] S14, using trimethylgallium as a gallium source, trimethylaluminum as an aluminum source, and ammonia as an ammonia source, an undoped Al2O3 layer is deposited on the upper surface of the channel layer 14 by MOCVD technology. 0.2 Ga 0.8 N barrier layer 15; the thickness of the barrier layer 15 is 15 nm.

[0080] S15, epitaxially growing a Mg+ doped GaN layer on the upper surface of the barrier layer 15 by using MOCVD technology, and forming a P-type GaN layer by high temperature annealing of the epitaxially grown Mg+ doped GaN layer; the thickness of the P-type GaN layer is 60nm-80nm, and the hole doping concentration of the P-type GaN layer is 10 17 -10 18 cm -3 .

[0081] S16, first define the P-GaN region under the HEMT gate and the P-GaN region of the temperature sensor diode anode on one side of the surface of the P-GaN layer. Then, spin-coat the photoresist, expose and develop, and use plasma (ICP) to slowly etch down the P-GaN layer outside the defined area until the etching depth extends to the barrier layer 15, forming the first part of the P-GaN layer 53 and the second part of the P-GaN layer 24.

[0082] It should be noted that the P-type GaN layer can be etched downward to form only the first portion of the P-GaN layer 53 without forming the second portion of the P-GaN layer 24. The following steps are described using the example of simultaneously forming the first portion of the P-GaN layer 53 and the second portion of the P-GaN layer 24.

[0083] S2, etching the two-dimensional electron gas structure 1 to below the two-dimensional electron gas channel to form a plurality of electrical isolation structures to isolate the two-dimensional electron gas structure 1 into a power device region, a first ohmic contact resistance region, a second ohmic contact resistance region and a temperature sensor diode region which are sequentially arranged laterally, such as Figure 4c shown.

[0084] Specifically, a power device area, a first ohmic contact resistance area, a second ohmic contact resistance area and a temperature sensor diode area are defined on the surface of the current sample, and then photoresist is spin-coated and exposed and developed, and plasma (ICP) is used to etch down the AlGaN barrier layer 15 and the GaN channel layer 14 outside the defined area until the etching depth extends to the buffer layer 13, forming three isolation grooves.

[0085] S3, depositing a passivation layer 6 on the surface of the two-dimensional electron gas structure 1, the first part of the P-GaN layer 53 and the surfaces of the plurality of electrical isolation structures, such as Figure 4d shown.

[0086] Specifically, the barrier layer 15 on the surface of the current sample, i.e., the area where the P-type GaN layer is etched, the upper surface of the first part of the P-GaN layer 53, the upper surface of the second part of the P-GaN layer 24, and the bottom and side of several isolation grooves, uses silane as a silicon source and ammonia as an ammonia source to deposit the passivation layer 6 using PECVD technology, so that the thickness of the passivation layer 6 reaches 100-150nm. After the passivation layer 6 is deposited, it covers the upper surface of the P-type GaN layer. Exemplarily, the passivation layer 6 can be a Si3N4 passivation layer.

[0087] S4, preparing metal electrodes above the two-dimensional electron gas channel of the two-dimensional electron gas structure 1, forming a source 21, a drain 22, a gate 23, a first ohmic contact electrode 31, a second ohmic contact electrode 32, a third ohmic contact electrode 41, a fourth ohmic contact electrode 42, a cathode 51 and an anode 52, wherein the source 21, the gate 23 and the drain 22 are sequentially spaced above the two-dimensional electron gas channel in the two-dimensional electron gas structure 1, the first ohmic contact electrode 31 and the second ohmic contact electrode 32 are spaced above the two-dimensional electron gas channel, the third ohmic contact electrode 41 and the fourth ohmic contact electrode 42 are spaced above the two-dimensional electron gas channel, the cathode 51 is located on one side of the first part of the P-GaN layer 53 and is located above the two-dimensional electron gas channel, and the anode 52 is in contact with the other side of the first part of the P-GaN layer 53 and is located above the two-dimensional electron gas channel. Specifically comprising the steps of:

[0088] S41, defining a plurality of ohmic metal electrode regions on the surface of the passivation layer 6, and etching the passivation layer 6 and the two-dimensional electron gas structure 1 in the ohmic metal electrode regions to form a plurality of ohmic metal electrode grooves, such as Figure 4e shown.

[0089] First, on the passivation layer 6 on the surface of the current sample, the source groove region, the drain groove region, the cathode groove region, the first ohmic contact electrode groove region, the second ohmic contact electrode groove region, the third ohmic contact electrode groove region, and the fourth ohmic contact electrode groove region of the HEMT device are defined. Then, photoresist is spin-coated on the surface of the current sample and exposed and developed, and the passivation layer 6 outside the defined region is etched downward by reactive ion etching (RIE) until the etching depth extends to the channel layer 13, and finally the photoresist is removed.

[0090] S42, depositing ohmic metal in the plurality of ohmic metal electrode grooves and performing annealing to form a source 21, a drain 22, a first ohmic contact electrode 31, a second ohmic contact electrode 32, a third ohmic contact electrode 41, a fourth ohmic contact electrode 42 and a cathode 51, as shown in FIG. Figure 4f shown.

[0091] Specifically, first, on the surface of the current sample, define the source region and drain region of the HEMT device, the cathode region of the temperature sensor, the first ohmic contact electrode region, the second ohmic contact electrode region, the third ohmic contact electrode region, and the fourth ohmic contact electrode region. Then, spin-coat a double-layer photoresist and expose and develop, and use electron beam evaporation technology to deposit Ti, Al, Ni and Au from bottom to top to prepare ohmic contacts, and the thickness of each metal layer is 20nm, 140nm, 50nm and 40nm respectively. Next, the deposited ohmic metal is subjected to a rapid thermal annealing process to form an ohmic contact electrode; illustratively, the rapid thermal annealing temperature is 850°C and the time is 30 seconds. Finally, remove the photoresist on the surface of the sample to form a source 21, a drain 22, a first ohmic contact electrode 31, a second ohmic contact electrode 32, a third ohmic contact electrode 41, a fourth ohmic contact electrode 42 and a cathode 51.

[0092] S43, defining a plurality of Schottky metal electrode regions on the surface of the passivation layer 6, and etching the passivation layer 6 in the Schottky metal electrode regions to form a plurality of Schottky metal electrode grooves, such as Figure 4g shown.

[0093] Specifically, first, a gate groove region of the HEMT device and an anode groove region of the temperature sensor diode are defined on the surface of the current sample, wherein the gate groove region is located on the surface of the second portion of the P-GaN layer 24, and the anode groove region is located on the surface of the passivation layer 6 away from the cathode in the temperature sensor diode region. Then, photoresist is spin-coated and exposed and developed, and the passivation layer 6 defining the gate groove region and the anode groove region is etched downward by reactive ion etching RIE, and the etching depth extends to the surface of the second portion of the P-GaN layer 24 and the surface of the barrier layer 15, respectively. Finally, the photoresist on the sample surface is removed to form a gate groove and an anode groove.

[0094] S44, depositing Schottky metal in a plurality of Schottky metal electrode grooves to form an anode 52 and a gate 23, such as Figure 4h shown.

[0095] Specifically, first, define the gate electrode region of the HEMT device and the anode region of the temperature sensor diode. Then, spin-coat a double-layer photoresist and expose and develop it. Use magnetron sputtering technology to sputter TiN, Ti, Al and TiN metals from bottom to top to prepare the Schottky contact gate and T-type anode. The thickness of each metal layer is 30nm, 20nm, 220nm and 30nm respectively. Finally, remove the photoresist on the surface of the sample to form the gate 23 and the anode 52.

[0096] S5, using a metal interconnection line to connect the second ohmic contact electrode 32 and the third ohmic contact electrode 41, and the interconnected electrodes are connected to the gate 23, and the fourth ohmic contact electrode 42 is connected to the cathode 51, as shown in FIG. Figure 4i shown.

[0097] Specifically, through metal wire interconnection, the temperature sensor diode cathode 51 is connected in series with the fourth ohmic contact electrode 42, the second ohmic contact electrode 32 and the third ohmic contact electrode 41 are connected in series, and the HEMT gate 23 is connected in parallel with the second ohmic contact electrode 32 and the third ohmic contact electrode 41, thereby completing the preparation of a GaN smart power chip with junction temperature monitoring capability and over-temperature protection capability.

[0098] The intelligent power chip preparation method provided in this embodiment is highly consistent with the existing power HEMT preparation process, which can reduce production costs. The temperature monitoring circuit and protection circuit designed in this embodiment can be horizontally integrated with the power HEMT in the same epitaxial wafer without additional process steps. Compared with traditional board-level integrated circuits, the manufactured intelligent power chip has the advantages of low parasitic crosstalk, small chip size, high integration, low manufacturing cost, and low power loss, and is very suitable for industrial production.

[0099] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A GaN power chip with junction temperature monitoring and over-temperature protection capabilities, characterized in that: include: A power device (2), a first ohmic contact structure (3), a second ohmic contact structure (4) and a temperature sensor diode (5) are sequentially distributed laterally on a two-dimensional electron gas structure (1) and electrically isolated from each other, wherein: The power device (2) comprises a source electrode (21), a drain electrode (22) and a gate electrode (23), wherein the source electrode (21), the gate electrode (23) and the drain electrode (22) are sequentially spaced and distributed above a two-dimensional electron gas channel in the two-dimensional electron gas structure (1); The first ohmic contact structure (3) comprises a first ohmic contact electrode (31) and a second ohmic contact electrode (32), wherein the first ohmic contact electrode (31) and the second ohmic contact electrode (32) are spaced apart and distributed above the two-dimensional electron gas channel; The second ohmic contact structure (4) comprises a third ohmic contact electrode (41) and a fourth ohmic contact electrode (42), wherein the third ohmic contact electrode (41) and the fourth ohmic contact electrode (42) are spaced apart and distributed above the two-dimensional electron gas channel; The temperature sensor diode (5) comprises a cathode (51), an anode (52) and a first portion of a P-GaN layer (53), wherein the first portion of the P-GaN layer (53) is located on the surface of the two-dimensional electron gas structure (1), the cathode (51) is located on one side of the first portion of the P-GaN layer (53) and is located above the two-dimensional electron gas channel, and the anode (52) is in contact with the other side of the first portion of the P-GaN layer (53) and is located above the two-dimensional electron gas channel; The first ohmic contact electrode (31) is used for grounding, the second ohmic contact electrode (32) and the third ohmic contact electrode (41) are connected via a metal interconnection line, and the interconnected electrodes are connected to the gate (23) via a metal interconnection line, the fourth ohmic contact electrode (42) and the cathode (51) are connected via a metal interconnection line and are used for outputting a voltage, and the anode (52) is used for connecting a power supply voltage.

2. The GaN power chip with junction temperature monitoring and over-temperature protection capabilities according to claim 1, characterized in that: The two-dimensional electron gas structure (1) comprises a substrate (11), a nucleation layer (12), a buffer layer (13), a channel layer (14) and a barrier layer (15) stacked in sequence from bottom to top, wherein the channel layer (14) and the barrier layer (15) form a two-dimensional electron gas channel.

3. The GaN power chip with junction temperature monitoring and over-temperature protection capabilities according to claim 2, characterized in that: The source electrode (21), the drain electrode (22), the first ohmic contact electrode (31), the second ohmic contact electrode (32), the third ohmic contact electrode (41), and the cathode (51) all extend to the surface of the channel layer (14); The gate (23) and the anode (52) are both located on the surface of the barrier layer (15).

4. The GaN power chip with junction temperature monitoring and over-temperature protection capabilities according to claim 1, characterized in that: The power device (2) further comprises a second portion of the P-GaN layer (24), wherein the portion of the P-GaN layer (24) is located on the surface of the two-dimensional electron gas structure (1) between the source electrode (21) and the drain electrode (22); The gate (23) is located on the surface of the second portion of the P-GaN layer (24).

5. The GaN power chip with junction temperature monitoring and over-temperature protection capabilities according to claim 4, characterized in that: The materials of the first portion of the P-GaN layer (53) and the second portion of the P-GaN layer (24) both include Mg + Ion-doped GaN, hole doping concentration is 10 17 -10 18 cm -3 , the thickness is 60-80nm.

6. The GaN power chip with junction temperature monitoring and over-temperature protection capabilities according to claim 1, characterized in that: It also includes a passivation layer (6), wherein the passivation layer (6) covers the surface of the two-dimensional electron gas structure (1), the surface of the first portion of the P-GaN layer (53), and the surface of the electrical isolation structure; The anode (52) overlaps the passivation layer (6).

7. The GaN power chip with junction temperature monitoring and over-temperature protection capabilities according to claim 6, characterized in that: The material of the passivation layer (6) includes Si3N4 and has a thickness of 100-150nm.

8. The GaN power chip with junction temperature monitoring and over-temperature protection capabilities according to claim 1, characterized in that: The source electrode (21), the drain electrode (22), the first ohmic contact electrode (31), the second ohmic contact electrode (32), the third ohmic contact electrode (41), the fourth ohmic contact electrode (42), and the cathode (51) are all made of ohmic metal, including one or more of Ti, Al, Ni, and Au; The gate (23) and the anode (52) are made of Schottky metal, including one or more of TiN, Ti, and Al; The material of the metal interconnection line includes Cu.

9. A method for preparing a GaN power chip with junction temperature monitoring and over-temperature protection capabilities, characterized in that: Includes steps: S1, preparing a two-dimensional electron gas structure (1), preparing a P-type GaN layer on the two-dimensional electron gas structure (1), and etching the P-type GaN layer to form a first partial P-GaN layer (53); S2, etching the two-dimensional electron gas structure (1) to below the two-dimensional electron gas channel to form a plurality of electrical isolation structures, so as to isolate the two-dimensional electron gas structure (1) into a power device region, a first ohmic contact resistance region, a second ohmic contact resistance region and a temperature sensor diode region which are sequentially arranged laterally; S3, depositing a passivation layer (6) on the surface of the two-dimensional electron gas structure (1), the first portion of the P-GaN layer (53), and the surfaces of the plurality of electrical isolation structures; S4, preparing metal electrodes above the two-dimensional electron gas channel of the two-dimensional electron gas structure (1), forming a source electrode (21), a drain electrode (22), a gate electrode (23), a first ohmic contact electrode (31), a second ohmic contact electrode (32), a third ohmic contact electrode (41), a fourth ohmic contact electrode (42), a cathode (51) and an anode (52), wherein the source electrode (21), the gate electrode (23) and the drain electrode (22) are sequentially spaced above the two-dimensional electron gas channel in the two-dimensional electron gas structure (1), and the first ohmic contact electrode (31) and the second ohmic contact electrode (42) are spaced apart from each other. The first ohmic contact electrode (32) is spaced apart and distributed above the two-dimensional electron gas channel, the third ohmic contact electrode (41) and the fourth ohmic contact electrode (42) are spaced apart and distributed above the two-dimensional electron gas channel, the cathode (51) is located on one side of the first portion of the P-GaN layer (53) and is located above the two-dimensional electron gas channel, and the anode (52) is in contact with the other side of the first portion of the P-GaN layer (53) and is located above the two-dimensional electron gas channel; the first ohmic contact electrode (31) is used for grounding, and the anode (52) is used for connecting a power supply voltage; S5. Use a metal interconnection line to connect the second ohmic contact electrode (32) and the third ohmic contact electrode (41), and connect the interconnected electrodes to the gate (23), and use a metal interconnection line to connect the fourth ohmic contact electrode (42) and the cathode (51).

10. The method for preparing a GaN power chip with junction temperature monitoring and over-temperature protection capabilities according to claim 9, characterized in that: Step S4 includes: S41, defining a plurality of ohmic metal electrode regions on the surface of the passivation layer (6), and etching the passivation layer (6) and the two-dimensional electron gas structure (1) in the ohmic metal electrode regions to form a plurality of ohmic metal electrode grooves; S42, depositing ohmic metal in the plurality of ohmic metal electrode grooves and performing annealing to form the source electrode (21), the drain electrode (22), the first ohmic contact electrode (31), the second ohmic contact electrode (32), the third ohmic contact electrode (41), the fourth ohmic contact electrode (42) and the cathode (51); S43, defining a plurality of Schottky metal electrode regions on the surface of the passivation layer (6), and etching the passivation layer (6) in the Schottky metal electrode regions to form a plurality of Schottky metal electrode grooves; S44, depositing Schottky metal in the plurality of Schottky metal electrode grooves to form the anode (52) and the gate (23).

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