Array substrate, display panel and electronic device

Abstract

Embodiments of the present disclosure provide an array substrate, a display panel, and an electronic device. The array substrate includes: a base substrate; a first electrode, the first electrode being disposed on the base substrate; a gate line, the gate line being disposed on the base substrate and electrically insulated from the first electrode; and a second electrode, the second electrode being disposed on a side of the gate line facing away from the base substrate, wherein at least one sub-pixel unit is disposed on the base substrate, the at least one sub-pixel unit including at least one first sub-pixel unit, the at least one first sub-pixel unit including: a first connecting portion disposed on the same layer as the second electrode and a second connecting portion disposed on the same layer as the gate line, the second connecting portion being electrically connected to the first electrode, and an orthographic projection of the second connecting portion on the base substrate at least partially overlapping with an orthographic projection of the first connecting portion on the base substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and an electronic device. Background Art

[0002] With the continuous advancement of display technology, liquid crystal display products have come to dominate the display industry. In recent years, demand for larger LCD panels has increased. This has pushed the size of display panels far beyond the dimensions of the masks used in the exposure process. Consequently, when manufacturing the array substrates used in display panels, multiple masks are required for splicing and exposure. This splicing exposure requires connectors to detect offset during the splicing process. Currently, these connectors are only located around the display panel. Summary of the Invention

[0003] An embodiment of the present disclosure provides an array substrate, comprising:

[0004] substrate;

[0005] A first electrode, wherein the first electrode is disposed on the base substrate;

[0006] a gate line, the gate line being disposed on the base substrate and electrically insulated from the first electrode;

[0007] a second electrode, the second electrode being disposed on a side of the gate line away from the base substrate;

[0008] Wherein, at least one sub-pixel unit is provided on the base substrate, and the at least one sub-pixel unit includes at least one first sub-pixel unit, and the at least one first sub-pixel unit includes:

[0009] A first connection portion is arranged in the same layer as the second electrode and a second connection portion is arranged in the same layer as the gate line, the second connection portion is electrically connected to the first electrode, and the orthographic projection of the second connection portion on the base substrate at least partially overlaps with the orthographic projection of the first connection portion on the base substrate.

[0010] In some embodiments, the first connecting portion and the second connecting portion are both located on a side of the first electrode facing away from the substrate.

[0011] In some embodiments, the first connection portion is electrically connected to the second connection portion through a via.

[0012] In some embodiments, the array substrate further includes: an insulating layer located between the gate line and the second electrode, wherein the first sub-pixel unit further includes a third connecting portion, and the third connecting portion is an opening of the via hole in the insulating layer between the gate line and the second electrode.

[0013] In some embodiments, an orthographic projection of the third connection portion on the substrate at least partially overlaps with an orthographic projection of the first connection portion on the substrate.

[0014] In some embodiments, the orthographic projection of the second connecting portion on the substrate at least partially overlaps with the orthographic projection of the first electrode on the substrate, the second connecting portion has a first edge and a second edge, the first electrode has a third edge and a fourth edge located in the first sub-pixel unit, the first edge is parallel to the third edge, and the second edge is parallel to the fourth edge.

[0015] In some embodiments, the array substrate further includes:

[0016] a source-drain electrode layer, the source-drain electrode layer being located on a side of the gate line facing away from the base substrate and on a side of the second electrode facing the base substrate; and

[0017] The data line is arranged in the same layer as the source and drain electrode layer, and extends along a first direction.

[0018] In some embodiments, the first sub-pixel unit further includes a fourth connection portion disposed in the same layer as the gate line and a fifth connection portion disposed in the same layer as the source and drain electrode layer.

[0019] The orthographic projection of the fifth connecting portion on the base substrate at least partially overlaps with the orthographic projection of the fourth connecting portion on the base substrate.

[0020] In some embodiments, each of an orthographic projection of the fifth connecting portion on the base substrate and an orthographic projection of the fourth connecting portion on the base substrate does not overlap with an orthographic projection of the first connecting portion and the second connecting portion on the base substrate.

[0021] In some embodiments, the first sub-pixel unit includes a sixth connecting portion arranged in the same layer as the first electrode, and an orthographic projection of the sixth connecting portion on the base substrate falls within an orthographic projection of the gate line on the base substrate.

[0022] In some embodiments, the array substrate further includes an active layer, which is located on the side of the gate line facing away from the base substrate and on the side of the second electrode facing the base substrate, wherein the at least one sub-pixel unit further includes at least one second sub-pixel unit, and the at least one second sub-pixel unit includes a seventh connection portion arranged on the same layer as the gate line and an eighth connection portion arranged on the same layer as the active layer, and the orthographic projection of the seventh connection portion on the base substrate at least partially overlaps with the orthographic projection of the eighth connection portion on the base substrate.

[0023] In some embodiments, the first sub-pixel unit and the second sub-pixel unit are both blue sub-pixel units.

[0024] In some embodiments, the array substrate further includes a data line extending along a first direction, wherein a plurality of the first sub-pixel units and a plurality of the second sub-pixel units are arranged on the base substrate, and the plurality of the first sub-pixel units and the plurality of the second sub-pixel units are alternately distributed on the array substrate along a second direction intersecting with the first direction.

[0025] In some embodiments, the first sub-pixel unit includes a sixth connecting portion arranged in the same layer as the first electrode, and an orthographic projection of the sixth connecting portion on the base substrate falls within an orthographic projection of the gate line on the base substrate.

[0026] In some embodiments, the data line is provided with a data line widening portion, the width of the data line widening portion is greater than the width of a portion of the data line adjacent to the data line widening portion, and the repeated exposure area of ​​the source and drain layer passes through the data line widening portion.

[0027] In some embodiments, an orthographic projection of an edge of the data line widening portion on the base substrate has a shape that is concave toward the center of the data line.

[0028] In some embodiments, the array substrate further includes a gate line located in the gate line and a first electrode bridge wire arranged in the same layer as the gate line, the first electrode bridge wire and the gate line extend along a second direction, the second direction intersects with the first direction, the first electrode bridge wire is used to electrically connect the first electrodes in adjacent sub-pixels in the second direction, and the orthographic projection of the data line widening portion on the base substrate is located between the orthographic projection of the gate line on the base substrate and the orthographic projection of the first electrode bridge wire on the base substrate.

[0029] In some embodiments, the array substrate further includes: a first electrode transfer line arranged in the same layer as the second electrode, wherein the first electrode transfer line extends along a first direction and is used to electrically connect the first electrodes in adjacent sub-pixel units in the first direction, and the first electrode transfer line is provided with a transfer line widening portion, the width of the transfer line widening portion is larger than the width of a portion of the first electrode transfer line adjacent to the transfer line widening portion, and the repeated exposure area of ​​the second electrode passes through the transfer line widening portion.

[0030] In some embodiments, an orthographic projection of an edge of the widened portion of the transition line on the base substrate has a shape that is concave toward the center of the first electrode transition line.

[0031] In some embodiments, the first electrode is a common electrode, and the second electrode is a pixel electrode.

[0032] An embodiment of the present disclosure further provides a display panel, comprising:

[0033] The array substrate according to any one of the above embodiments;

[0034] an opposing substrate, located on a side of the array substrate facing away from the base substrate; and

[0035] A liquid crystal layer is located between the array substrate and the opposite substrate.

[0036] An embodiment of the present disclosure further provides an electronic device, including:

[0037] The array substrate or the display panel according to any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0039] Figure 1A A schematic diagram showing a large-size display panel manufactured using a splicing exposure method;

[0040] Figure 1B Shown with Figure 1A Schematic diagram of the corresponding mask;

[0041] Figure 2A A schematic plan view of a first sub-pixel unit on an array substrate according to an embodiment of the present disclosure is shown;

[0042] Figure 2B A schematic plan view of a second sub-pixel unit on an array substrate according to an embodiment of the present disclosure is shown;

[0043] Figure 3 Schematically shown Figure 2A Enlarged view of the middle P part;

[0044] Figure 4 Schematically shown Figure 2A Schematic diagram taken along the section line A-A';

[0045] Figure 5 Schematically shown Figure 2A Schematic diagram taken along the section line BB';

[0046] Figure 6 Schematically shown Figure 2A Schematic diagram taken along the cutting line C-C';

[0047] Figure 7 Schematically shown Figure 2A Schematic diagram taken along the section line D-D';

[0048] Figure 8 Schematically shown Figure 2A Schematic diagram taken along the section line E-E';

[0049] Figure 9 Schematically shown Figure 2B Schematic diagram taken along the section line F-F';

[0050] Figure 10 The repeated exposure area at the splicing of the exposure patterns is schematically shown;

[0051] Figure 11 Schematically illustrates the design of the repeated exposure area of ​​the array substrate according to some embodiments of the present disclosure;

[0052] Figure 12 Schematically shows an exemplary distribution of the first sub-pixel unit and the second sub-pixel unit on the array substrate; and

[0053] Figure 13 A display panel according to an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0054] To more clearly illustrate the objectives, technical solutions, and advantages of the present disclosure, embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the following description of the embodiments is intended to explain and illustrate the overall concept of the present disclosure and should not be construed as limiting the present disclosure. In the specification and drawings, the same or similar reference numerals refer to the same or similar parts or components. For the sake of clarity, the drawings are not necessarily drawn to scale, and some well-known parts and structures may be omitted in the drawings.

[0055] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and similar terms used in this disclosure do not denote any order, quantity, or importance, but are simply used to distinguish different components. The terms "a" or "an" do not exclude a plurality. Terms such as "include" or "comprise" mean that the element or object preceding the term includes the elements or objects listed after the term and their equivalents, but do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," "right," "top," or "bottom" are used only to indicate relative positional relationships; if the absolute position of the described objects changes, the relative positional relationship may also change accordingly. When an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or intervening elements may be present.

[0056] In the production of large-size display panels (especially ultra-large-size (98 inches or more) display panels), since the size of the mask plate used for exposure is usually significantly smaller than the size of the display panel, multiple mask plates need to be used for splicing exposure when producing the array substrate. Figure 1A and Figure 1B An example of splicing exposure for a large-size display panel is given. Figure 1A FIG shows a schematic plan view of a normal display area AA of a large-size display panel. Figure 1A In the display area AA, the display area is divided into three rows and four columns with twelve exposure patterns. Figure 1A The corresponding one is as follows Figure 1B The mask assembly shown in FIG. 1 includes three masks M1, M2, and M3 arranged in parallel. Taking mask M1 as an example, the mask includes three regions, namely, region A, region D, and region G. The combination of these three regions can be used to expose three patterns on the array substrate, namely, a pattern of region A + region D, a pattern of region D, and a pattern of region D + region G. These three patterns can be used to form Figure 1A Similarly, the pattern of the B region + E region, the pattern of the E region, and the pattern of the E region + H region in the mask plate M2 can be used to form Figure 1A The three patterns in the second column and the three patterns in the third column from the left in the display area AA; the pattern of the C region + F region, the pattern of the F region and the pattern of the F region + I region in the mask plate M3 can be used to form Figure 1AThe three patterns in the rightmost column of the display area AA in FIG. Thus, the above twelve exposure patterns are spliced ​​together to form a complete display area AA. Figure 1A In addition to the display area AA, three dummy areas are shown on the left and right sides. These dummy areas are used to prevent static electricity from being generated during the production process.

[0057] It should be understood that in the production process of the array substrate, it is necessary to form multiple film layers in sequence on the base substrate. In order to ensure process accuracy, it is necessary to monitor the positioning error of the pattern of each film layer, which can be achieved by setting alignment marks (or connecting parts) for the patterns of each film layer. For example, it is necessary to monitor the position of the pattern in each film layer on the base substrate to check whether there is an offset (also called absolute offset) in the pattern in the film layer relative to the base substrate (such as a glass substrate or a plastic substrate). The alignment mark used to monitor the absolute offset can be called an absolute offset alignment mark. The relative position between the patterns of different film layers must also be monitored to check whether there is a relative offset between the film layers. The alignment mark used to monitor the relative offset can also be called an overlapping alignment mark. These alignment marks can be used in pairs, that is, alignment marks that can be matched are provided at positions corresponding to the array substrate and the mask plate assembly to achieve alignment of the mask plate and the array substrate.

[0058] In the related art, the alignment marks (or connection parts) on the mask assembly can only be set at the positions around the mask, otherwise these alignment marks will fall into the display area AA, thereby affecting the normal display of the product. Figure 1A When manufacturing a large-size panel that needs to be spliced ​​and exposed in two directions (such as the x direction and the y direction), it is found that the exposure pattern (such as Figure 1A The exposure pattern (marked with an E) between the second and third columns from the left of display area AA falls within display area AA on all sides, failing to meet the requirement for providing alignment marks around the display area. However, if alignment marks were provided for these exposure patterns on the array substrate, it would be impossible to monitor the offset of the exposure pattern stitching. Such offset or misalignment could lead to defects such as dark or bright lines (e.g., due to resistance variations in the gate lines) and display anomalies (e.g., due to short or open data lines) in the final display panel.

[0059] In the embodiment of the present disclosure, the alignment mark is designed in the sub-pixel unit of the display area AA of the display panel, so that the portion in the display area AA can be used to align the exposure pattern. This can solve the problem that the alignment deviation of the splicing area cannot be monitored during the splicing exposure of the above-mentioned partial exposure pattern. It should be noted that although the present disclosure aims to monitor the alignment of the splicing exposure by setting the alignment mark in the sub-pixel unit, it does not mean that in the embodiment of the present disclosure, the alignment mark must not be set around the display area AA. If necessary, the alignment mark can still be set around the display area AA, and of course, the alignment mark can also be not set around the display area AA.

[0060] An embodiment of the present disclosure provides an array substrate, which includes a base substrate 10 and a plurality of sub-pixel units disposed on the base substrate 10. As mentioned above, alignment marks are embedded in the sub-pixel units. Figure 2A An example of a sub-pixel unit including an alignment mark is given, and the sub-pixel unit is hereinafter referred to as a first sub-pixel unit PX1. Figure 3 for Figure 2A Magnified view of part P in . Figures 4 to 8 From Figure 2A Cross-sectional views taken along lines AA', BB', CC', DD' and EE'.

[0061] As an example, the array substrate includes: a first electrode (e.g., a common electrode) 20, a gate line 30, and a second electrode (e.g., a pixel electrode) 40. The first electrode 20 is disposed on a base substrate 10. The gate line 30 is disposed on the base substrate 10 and is electrically insulated from the first electrode 20. The second electrode 40 is disposed on a side of the gate line 30 that faces away from the base substrate 10. At least one (e.g., a plurality) sub-pixel units on the base substrate includes a first sub-pixel unit PX1. The first sub-pixel unit PX1 includes: a first connecting portion 51 and a second connecting portion 52. The first connecting portion 51 is arranged on the same layer as the second electrode 40, and the second connecting portion 52 is arranged on the same layer as the gate line 30. The orthographic projection of the second connecting portion 52 on the base substrate 10 at least partially overlaps with the orthographic projection of the first connecting portion 51 on the base substrate 10. For example, the orthographic projection of the second connecting portion 52 on the base substrate 10 falls within the orthographic projection of the first connecting portion 51 on the base substrate 10, or the orthographic projection of the first connecting portion 51 on the base substrate 10 falls within the orthographic projection of the second connecting portion 52 on the base substrate 10. The first connecting portion 51 and the second connecting portion 52 are used to align the pattern in the second electrode 40 with the pattern in the gate line 30. Here, the first connecting portion 51 and the second connecting portion 52 can be considered as overlapping alignment marks for the pattern in the second electrode 40 and the pattern in the gate line 30, used to detect relative positioning errors between the pattern in the second electrode 40 and the pattern in the gate line 30. As an example, the first connecting portion 51 can also serve as an absolute offset alignment mark for the pattern in the second electrode 40, used to detect deviation of the pattern in the second electrode 40 relative to the base substrate 10. Likewise, the second connection portion 52 can also serve as an absolute offset alignment mark of the pattern in the gate line 30, for detecting deviation of the pattern in the gate line 30 relative to the base substrate 10. In some embodiments, one or more first sub-pixel units PX1 can be provided on the array substrate.

[0062] In some embodiments, the first connecting portion 51 and the second connecting portion 52 are both located on a side of the first electrode 20 facing away from the base substrate 10 .

[0063] In some embodiments, the second connection portion 52 is electrically connected to the first electrode 20. As an example, a via 41 electrically connected from the first electrode 20 through the second connection portion 52 to the first connection portion 51 can also be provided on the array substrate, and the second connection portion 52 is electrically connected to both the first electrode 20 and the first connection portion 51. It should be noted that in this embodiment, the first connection portion 51 and the second connection portion 52 are not provided separately, but are embedded in the functional structure of the first sub-pixel unit PX1. Figure 2AAs can be seen in FIG, in order to maintain the stability of the common electrode signal, the portion of the first electrode 20 in the first sub-pixel unit PX1 and the portion of the first electrode 20 in another adjacent sub-pixel unit PX1' are bridged together through the first electrode connecting line 21 arranged in the same layer as the second electrode 40. The first electrode connecting line 21 needs to be electrically connected to the first electrode 20 through the via 41. Figure 2A and Figure 4 As shown, the first connection portion 51 and the second connection portion 52 are integrated with the via 41. The first connection portion 51 can also be considered as part of the first electrode connection line 21. This design can prevent the first connection portion 51 and the second connection portion 52 from occupying the area of ​​the array substrate separately, thereby saving the area of ​​the array substrate.

[0064] In some embodiments, the array substrate further includes an insulating layer 50 located between the gate line 30 and the second electrode 40. The first sub-pixel unit PX1 further includes a third connecting portion 53. The third connecting portion 53 may be an opening in the insulating layer 50 between the gate line 30 and the second electrode 40, which is formed by the via 41 and is used to align a pattern in the insulating layer 50 with a pattern in the gate line 30 relative to the second connecting portion 52. As an example, the orthographic projection of the third connecting portion 53 on the base substrate 10 at least partially overlaps with the orthographic projection of the first connecting portion 51 on the base substrate 10. For example, the orthographic projection of the third connecting portion 53 on the base substrate 10 falls within the orthographic projection of the first connecting portion 51 on the base substrate 10. Here, the first connecting portion 51, the second connecting portion 52, and the third connecting portion 53 are integrated and reused with the via 41 to save wiring space.

[0065] In some embodiments, the first connecting portion 51, the second connecting portion 52 and the third connecting portion 53 are rectangular with a common geometric center. In this way, the patterns of the second electrode 40, the gate line 30 and the insulating layer 50 can be aligned with each other by aligning the centers of the three connecting portions. Figure 3 As shown, the distance d2 between the adjacent edges of the first connecting portion 51 and the second connecting portion 52 is approximately 3.5 microns, and the distance d3 between the adjacent edges of the second connecting portion 52 and the third connecting portion 53 is approximately 3.5 microns. However, the specific forms of the first connecting portion 51, the second connecting portion 52, and the third connecting portion 53 are not limited thereto. For example, they can also be designed into various desired shapes such as circular, hexagonal, etc.

[0066] In some embodiments, the orthographic projection of the second connecting portion 52 on the base substrate 10 at least partially overlaps with the orthographic projection of the first electrode 20 on the base substrate 10. The second connecting portion 52 has a first edge 521 and a second edge 522. The first electrode 20 has a third edge 523 and a fourth edge 524 located in the first sub-pixel unit PX1. The first edge 521 and the third edge 523 are parallel to each other and are used to align the pattern in the gate line 30 with the pattern in the first electrode 20 in the first direction (e.g., Figure 2A The second edge 522 and the fourth edge 524 are parallel to each other, and are used to align the pattern in the gate line 30 relative to the pattern in the first electrode 20 in a second direction (e.g., Figure 2A For example, the first direction and the second direction are perpendicular to each other. Here, the first edge 521 and the third edge 523 and the second edge 522 and the fourth edge 524 are used to align the pattern in the gate line 30 with the pattern in the first electrode 20 in the first direction and the second direction respectively, and can be regarded as overlapping alignment marks of the first electrode 20 and the gate line 30. For example, Figure 2A As shown, the error in the distance dx between the first edge 521 and the third edge 523 can be used to indicate the alignment error between the pattern in the gate line 30 and the pattern in the first electrode 20 in the first direction, while the error in the distance dy between the second edge 522 and the fourth edge 524 can be used to indicate the alignment error between the pattern in the gate line 30 and the pattern in the first electrode 20 in the second direction. It can be seen that the overlapping alignment marks of the first electrode 20 and the gate line 30 can also be integrated with the aforementioned via structure 41 to avoid occupying additional wiring space. As an example, the spacing between the first edge 521 and the third edge 523 can be approximately 2.5 microns; the spacing between the second edge 522 and the fourth edge 524 can also be approximately 2.5 microns.

[0067] In some embodiments, the array substrate may further include a source-drain electrode layer 60. The source-drain electrode layer 60 is located on a side of the gate line 30 facing away from the substrate 10 and on a side of the second electrode 40 facing the substrate 10. The first sub-pixel unit PX1 further includes a fourth connecting portion 54 disposed in the same layer as the gate line 30 and a fifth connecting portion 55 disposed in the same layer as the source-drain electrode layer 60. The fourth connecting portion 54 and the fifth connecting portion 55 are used to align a pattern in the source-drain electrode layer 60 with a pattern in the gate line 30. The orthographic projection of the fifth connecting portion 55 on the substrate 10 at least partially overlaps with the orthographic projection of the fourth connecting portion 54 on the substrate 10. For example, the orthographic projection of the fifth connecting portion 55 on the substrate 10 falls within the orthographic projection of the fourth connecting portion 54 on the substrate 10. Here, the fourth connection portion 54 and the fifth connection portion 55 can be regarded as overlapping alignment marks of the pattern in the source / drain layer 60 and the pattern in the gate line 30, and are used to detect the relative positioning error between the pattern in the source / drain layer 60 and the pattern in the gate line 30. As an example, the fifth connection portion 55 can also be used as an absolute offset alignment mark of the pattern in the source / drain layer 60, and is used to detect the deviation of the pattern in the source / drain layer 60 relative to the base substrate 10.

[0068] In some embodiments, each of the orthographic projection of the fifth connection portion 55 and the orthographic projection of the fourth connection portion 54 on the base substrate 10 does not overlap with the orthographic projection of the first connection portion 51 and the second connection portion 52 on the base substrate 10 .

[0069] As an example, the fourth connecting portion 54 and the fifth connecting portion 55 are rectangular with a common geometric center. In this way, the patterns of the source and drain electrode layer 60 and the gate line 30 can be aligned with each other by aligning the centers of the two connecting portions. Figure 3 As shown, the length and width of the fifth connecting portion 55 can both be approximately 8 microns, and the distance d3 between the adjacent edges of the fourth connecting portion 54 and the fifth connecting portion 55 is approximately 3.5 microns. However, the specific forms of the fourth connecting portion 54 and the fifth connecting portion 55 are not limited thereto. For example, they can also be designed into various desired shapes such as circular, hexagonal, etc.

[0070] In some embodiments, the first sub-pixel unit PX1 includes a sixth connecting portion 56 disposed in the same layer as the first electrode 20. The sixth connecting portion 56 is used to align the pattern in the first electrode 20 with the base substrate 10. The orthographic projection of the sixth connecting portion 56 on the base substrate 10 falls within the orthographic projection of the gate line 30 on the base substrate 10. Here, the sixth connecting portion 56 serves as an absolute deviation alignment mark for the first electrode 20 and is used to detect the absolute deviation of the pattern of the first electrode 20 relative to the base substrate 10.

[0071] In some embodiments, the array substrate may further include an active layer 70, which is located on a side of the gate line 30 facing away from the base substrate 10 and on a side of the second electrode 40 facing the base substrate 10. For example, the active layer 70 may be located on a side of the source / drain electrode layer 60 facing the base substrate 10. In some embodiments, the orthographic projection of the sixth connecting portion 56 on the base substrate 10 may not overlap with either the orthographic projection of the source / drain electrode layer 60 on the base substrate 10 or the orthographic projection of the active layer 70 on the base substrate 10.

[0072] The plurality of sub-pixel units may further include a second sub-pixel unit PX2. Figure 2B and Figure 9 As shown, the second sub-pixel unit PX2 may include a seventh connection portion 57 arranged in the same layer as the gate line 30 and an eighth connection portion 58 arranged in the same layer as the active layer 70. The seventh and eighth connection portions 57 and 58 are used to align the pattern in the active layer 70 with the pattern in the gate line 30. The orthographic projection of the seventh connection portion 57 on the substrate 10 at least partially overlaps with the orthographic projection of the eighth connection portion 58 on the substrate 10. For example, the orthographic projection of the eighth connection portion 58 on the substrate 10 falls within the orthographic projection of the seventh connection portion 57 on the substrate 10. Here, the seventh and eighth connection portions 57 and 58 can be considered as overlap alignment marks between the pattern in the active layer 70 and the pattern in the gate line 30, used to detect relative positioning errors between the patterns in the active layer 70 and the gate line 30. As an example, the eighth connection portion 58 can also serve as an absolute offset alignment mark for the pattern in the active layer 70, used to detect deviation of the pattern in the active layer 70 relative to the substrate 10.

[0073] It should be understood by those skilled in the art that although Figure 3 In the example shown in FIG, the fifth connection portion 55 overlaps with the first electrode 20 (or the orthographic projection of the fifth connection portion 55 on the base substrate 10 overlaps with the orthographic projection of the first electrode 20 on the base substrate 10), but the embodiments of the present disclosure are not limited to this. The fifth connection portion 55 may also be set at other positions. For example, the fifth connection portion 55 may also be set to overlap or intersect with the gate line 30 (or the orthographic projection of the fifth connection portion 55 on the base substrate 10 at least partially overlaps with the orthographic projection of the gate line 30 on the base substrate 10).

[0074] Similarly, although Figure 2BIn the example shown in FIG, the eighth connection portion 58 overlaps with the first electrode 20 (or the orthographic projection of the eighth connection portion 58 on the base substrate 10 overlaps with the orthographic projection of the first electrode 20 on the base substrate 10), but the embodiments of the present disclosure are not limited to this. The eighth connection portion 58 may also be set at other positions. For example, the eighth connection portion 58 may also be set to overlap or intersect with the gate line 30 (or the orthographic projection of the eighth connection portion 58 on the base substrate 10 at least partially overlaps with the orthographic projection of the gate line 30 on the base substrate 10).

[0075] The main difference between the second sub-pixel unit PX2 and the first sub-pixel unit PX1 is that the overlapping alignment mark between the pattern in the source / drain layer 60 and the pattern in the gate line 30 in the first sub-pixel unit PX1 is replaced with the overlapping alignment mark between the pattern in the active layer 70 and the pattern in the gate line 30 in the second sub-pixel unit PX2. The other structures of the second sub-pixel unit PX2 can be set to be the same as or similar to those of the first sub-pixel unit PX1, and the details are not repeated here.

[0076] By placing the overlapping alignment marks between the pattern in the source / drain layer 60 and the pattern in the gate line 30, and the overlapping alignment marks between the pattern in the active layer 70 and the pattern in the gate line 30, respectively, in different sub-pixel units, it is possible to avoid having too many alignment marks (or connecting portions) in a single sub-pixel unit and to make the alignment marks more evenly distributed across the sub-pixel units. This prevents the aperture ratio of the sub-pixel units from being significantly reduced due to the placement of the alignment marks and also facilitates uniformity of the light intensity displayed by the display panel.

[0077] In some embodiments, the seventh connecting portion 57 and the eighth connecting portion 58 are rectangular with a common geometric center. Thus, by aligning the centers of the two connecting portions, the patterns of the active layer 70 and the gate line 20 can be aligned. However, the specific forms of the seventh connecting portion 57 and the eighth connecting portion 58 are not limited thereto; for example, they can also be designed in various desired shapes, such as circular and hexagonal.

[0078] from Figures 4 to 9 It can be seen that a gate insulating layer GI may be further provided on the array substrate, and the gate insulating layer GI is located between the active layer (semiconductor layer) 70 and the gate line 30 . Figure 6 Schematic structure of a transistor in sub-pixel unit PX1 is shown, wherein a source electrode 601 and a drain electrode 602 are disposed in a source-drain electrode layer 60. An active layer 70 is disposed on the side of the source electrode 601 and the drain electrode 602 facing the base substrate 10 and on the side of the gate line 30 facing away from the base substrate 10. A gate insulating layer GI is further disposed between the active layer 70 and the gate line 30. Figure 5The figure shows the electrical connection between the drain electrode 602 of the transistor and the second electrode (pixel electrode) 40. In the above embodiment, the source electrode 601 and the drain electrode 602 are interchangeable.

[0079] For example, when the display panel is large, the relative offset between the array substrate and the opposing substrate (e.g., a color filter substrate) is relatively large. To prevent light leakage from the display panel, the black matrix area covering the edges of the sub-pixels is typically wide. Therefore, in the embodiments of the present invention, the connection portion is placed within the sub-pixel unit, which has a minimal impact on the aperture ratio of the sub-pixel unit.

[0080] Furthermore, when a display panel uses red (R), green (G), and blue (B) sub-pixels, the human eye is generally least sensitive to the blue sub-pixel. Therefore, placing the connector in the blue sub-pixel minimizes the impact on the display effect. In some embodiments, the first sub-pixel unit PX1 and the second sub-pixel unit PX2 can both be blue sub-pixels.

[0081] As an example, the array substrate may include a plurality of first sub-pixel units PX1 and a plurality of second sub-pixels PX2 , and the plurality of first sub-pixel units PX1 and the plurality of second sub-pixels PX2 may be alternately distributed on the array substrate. Figure 12 An exemplary embodiment of distributing the first sub-pixel unit PX1 and the plurality of second sub-pixels PX2 on the array substrate is schematically provided. Figure 12 The display area AA is shown in . A plurality of sub-pixel units may be arranged in the display area AA, which may include a plurality of the above-mentioned first sub-pixel units PX1 and a plurality of the above-mentioned second sub-pixel units PX2. As described above, in some embodiments, the first sub-pixel unit PX1 is provided with an overlapping alignment mark of the pattern in the source-drain layer 60 and the pattern in the gate line 30, and the second sub-pixel unit PX2 is provided with an overlapping alignment mark of the pattern in the active layer 70 and the pattern in the gate line 30. The plurality of first sub-pixel units PX1 and the plurality of second sub-pixels PX2 may be arranged to be alternately distributed in a certain direction, which is beneficial for taking into account the alignment of the pattern in the source-drain layer 60 with the pattern in the gate line 30 and the alignment of the pattern in the active layer 70 with the pattern in the gate line 30. In Figure 12In the example shown, the first sub-pixel unit PX1 (indicated by the left oblique hatching) and the second sub-pixel unit PX2 (indicated by the right oblique hatching) are arranged in columns. The first sub-pixel units PX1 in each column and the second sub-pixel units PX2 in each column are alternately arranged in the x-direction. The y-direction can be, for example, the direction in which the data line 61 extends, and the x-direction is a direction intersecting with the y-direction (for example, the direction in which the gate line 31 extends). The first sub-pixel units PX1 and the second sub-pixel units PX2 in each column can also be separated by other sub-pixel units PX3. The other sub-pixel units PX3 can be, for example, sub-pixel units that do not include overlapping alignment marks between the pattern in the source and drain layer 60 and the pattern in the gate line 30, nor do they include overlapping alignment marks between the pattern in the active layer 70 and the pattern in the gate line 30 (for example, conventional sub-pixel units). As for examples of the specific structures of the first sub-pixel unit PX1 and the second sub-pixel unit PX2, please refer to Figure 2A and Figure 2B It should be noted that the embodiments of the present disclosure are not limited thereto. For example, the first sub-pixel unit PX1 and the second sub-pixel unit PX2 may not be arranged in a column, or adjacent first sub-pixel units PX1 and second sub-pixel units PX2 may not be separated by other sub-pixel units PX3.

[0082] In the embodiment of the present disclosure, the first connection portion 51 may be located on a side of the fourth connection portion 54 or the seventh connection portion 57 away from the data line 61 connected to the sub-pixel unit where the first connection portion 51 is located.

[0083] It should be noted that "same-layer arrangement" in this application refers to structures within the same film layer formed from the same material through the same patterning step. Typically, structures arranged in the same layer can be exposed using the same mask during the patterning process. Considering the situation where a complete display area is formed by stitching together multiple exposure patterns, the stitching operation of the multiple exposure patterns needs to be performed for each layer of structures arranged in the same layer.

[0084] On the other hand, in the solution of splicing a plurality of exposure patterns into a complete display area of ​​a display panel, there may be misalignment between adjacent exposure patterns, which may cause a short circuit or disconnection of a signal line (such as a data line). To this end, a repeated exposure area may be provided between adjacent exposure patterns. For example, Figure 10As shown, there is an overlapping region OV between exposure pattern 11 and exposure pattern 12. Within this overlapping region OV, both exposure pattern 11 and exposure pattern 12 are exposed. Therefore, the pattern falling within this overlapping region OV is exposed twice. Therefore, this overlapping region OV can be referred to as a repeated exposure region. Because the pattern in the repeated exposure region is exposed twice, the line width of the pattern in the repeated exposure region is reduced compared to the pattern exposed once. To this end, in the embodiments of the present disclosure, a widening design is implemented for the pattern in the repeated exposure region.

[0085] Figure 11 An example of such a design is given. Figure 11 FIG1 shows a partial plan view of an array substrate. The array substrate may also include the base substrate 10, the first electrode 20, the gate line 30, the second electrode 40, and the source-drain electrode layer 60 as described above. The array substrate is further provided with a data line 61 arranged in the same layer as the source-drain electrode layer 60. The data line 61 is arranged along a first direction (e.g. Figure 11 As mentioned above, when splicing exposure is adopted, the data line 61 needs to be formed through at least two exposures. Figure 11 The source-drain layer repeated exposure area 62 is shown in FIG. The portion of the data line 61 that falls into the source-drain layer repeated exposure area 62 will be exposed twice. To this end, the data line 61 is provided with a data line widening portion 63, the width of which is greater than the width of the portion of the data line adjacent to the data line widening portion 63. The source-drain layer repeated exposure area 62 passes through the data line widening portion 63. In order to ensure that the data line widening portion 63 can cover the portion of the data line 61 that falls into the source-drain layer repeated exposure area 62, the width w2 of the data line widening portion 63 in the first direction is greater than the width w1 of the source-drain layer repeated exposure area 62 in the first direction. This can prevent the portion of the data line 61 that falls into the source-drain layer repeated exposure area 62 from becoming too narrow due to multiple exposures and being easily broken. As an example, the width w1 of the source-drain layer repeated exposure area 62 in the first direction can be between 3 microns and 20 microns, or between 3 microns and 10 microns, for example, approximately 5 microns. The width w2 of the data line widening portion 63 in the first direction may be between 8 micrometers and 15 micrometers, for example, 11.5 micrometers.

[0086] In some embodiments, as Figure 11 As shown, the orthographic projection of the edge of the data line widening portion 63 on the base substrate 10 has a shape that is concave toward the center of the data line 61. This is because the portion of the data line widening portion 63 that falls into the source-drain layer repeated exposure area 62 is narrower than the portion that is exposed once due to being exposed twice.

[0087] In some embodiments, as Figure 11As shown, the array substrate may further include a gate line 31 located in the gate line 30 and a first electrode bridge line 32 arranged in the same layer as the gate line 30, wherein the first electrode bridge line 32 and the gate line 31 extend along a second direction. Figure 11 The X direction in the figure) intersects the first direction, for example, the second direction is perpendicular to the first direction. The first electrode bridge line 32 is used to electrically connect the first electrodes 20 in adjacent sub-pixel units in the second direction, and the orthographic projection of the data line widening portion 63 on the base substrate 10 is located between the orthographic projection of the gate line 30 on the base substrate 10 and the orthographic projection of the first electrode bridge line 32 on the base substrate 10. Figure 11 As can be clearly seen above, the orthographic projection of the data line widening portion 63 on the base substrate 10 does not overlap with the orthographic projection of the gate line 30 and the orthographic projection of the first electrode bridge line 32 on the base substrate 10. This prevents the data line widening portion 63 from overlapping with structures in other metal layers (such as the gate line 30 and the first electrode bridge line 32), which would increase parasitic resistance. It also minimizes changes in the overall structure of the sub-pixel unit caused by the portion of the data line 61 associated with the source-drain layer repeated exposure region 62, thereby maintaining a good aperture ratio for the sub-pixel unit.

[0088] Similarly, similar designs can be used in other film layers of the array substrate. For example, a first electrode connection line 21 is provided on the array substrate, arranged in the same layer as the second electrode 40. The first electrode connection line 21 extends along a first direction and is used to electrically connect the first electrodes 20 in adjacent sub-pixel units in the first direction. Similar to the data line 61, when using splicing exposure, the first electrode connection line 21 also requires at least two exposures to form. Figure 11The second electrode repeated exposure area 22 is shown in the figure. The portion of the first electrode transfer line 21 that falls into the second electrode repeated exposure area 22 will be exposed twice. To this end, the first electrode transfer line 21 is provided with a transfer line widening portion 23, the width of which is greater than the width of the portion of the first electrode transfer line 21 adjacent to the transfer line widening portion 23. The second electrode repeated exposure area 22 passes through the transfer line widening portion 23. To ensure that the transfer line widening portion 23 can cover the portion of the first electrode transfer line 21 that falls into the second electrode repeated exposure area 22, the width w4 of the transfer line widening portion 23 in the first direction is greater than the width w3 of the second electrode repeated exposure area 22 in the first direction. This can prevent the portion of the first electrode transfer line 21 that falls into the second electrode repeated exposure area 22 from becoming too narrow due to multiple exposures and being easily broken. As an example, the width w3 of the second electrode repeated exposure area 22 in the first direction can be between 3 microns and 20 microns, or between 3 microns and 10 microns, for example, approximately 5 microns. The width w4 of the widened portion 23 of the connecting line in the first direction may be between 10 micrometers and 20 micrometers, for example, 14 micrometers.

[0089] Similar to the data line widening portion 63 , the edge of the transition line widening portion 23 may also have a concave shape toward the center of the first electrode transition line 21 .

[0090] In the above embodiments, the splicing of adjacent exposure patterns in the first direction is taken as an example. It should be understood that the embodiments of the present disclosure are not limited to this. If necessary, similar designs can be performed in other directions (such as the second direction) to reduce the impact of repeated exposure at the splicing.

[0091] The embodiment of the present disclosure further provides a display panel 100. Figure 13 As shown, the display panel 100 includes: an array substrate 200 as described in any of the above embodiments; an opposing substrate 300 (e.g., a color film substrate), located on the side of the array substrate 200 facing away from the base substrate 10; and a liquid crystal layer 400 located between the array substrate 200 and the opposing substrate 300.

[0092] The present disclosure also discloses an electronic device, including the array substrate 200 described in any of the above embodiments or the display panel 100 described above. For example, the electronic device may be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a smartwatch, or a tablet computer.

[0093] It should be understood in the art that the features in the above embodiments of the present disclosure can be combined with each other unless there are contradictions. Although the above embodiments use ultra-large display panels as examples, the embodiments of the present disclosure are not limited to ultra-large display panels and can also be used for small and medium-sized display panels.

[0094] Although the present disclosure is described in conjunction with the accompanying drawings, the embodiments disclosed in the drawings are intended to illustrate the embodiments of the present disclosure and are not to be construed as limiting the present disclosure. The dimensional ratios in the drawings are merely illustrative and are not to be construed as limiting the present disclosure.

[0095] The above embodiments are merely illustrative of the principles and structures of the present disclosure and are not intended to limit the present disclosure. Those skilled in the art will appreciate that any changes and improvements made to the present disclosure without departing from the overall concept of the present disclosure are within the scope of the present disclosure. The scope of protection of the present disclosure shall be determined by the scope defined in the claims of this application.

Claims

1. An array substrate, comprising: substrate; at least one first electrode, wherein the first electrode is disposed on the base substrate; a gate line, the gate line being disposed on the base substrate and electrically insulated from the first electrode; at least one second electrode, the second electrode being disposed on a side of the gate line facing away from the substrate, Wherein, at least one sub-pixel unit is provided on the base substrate, and the at least one sub-pixel unit includes at least one first sub-pixel unit, and the at least one first sub-pixel unit includes: a first connecting portion arranged in the same layer as the second electrode and a second connecting portion arranged in the same layer as the gate line, the second connecting portion being electrically connected to the first electrode, an orthographic projection of the second connecting portion on the base substrate at least partially overlapping with an orthographic projection of the first connecting portion on the base substrate; The array substrate further includes: a source-drain electrode layer, the source-drain electrode layer being located on a side of the gate line facing away from the base substrate and on a side of the second electrode facing the base substrate; and A data line arranged in the same layer as the source and drain electrode layer, the data line extending along a first direction; The first sub-pixel unit further includes a fourth connection portion arranged in the same layer as the gate line and a fifth connection portion arranged in the same layer as the source and drain electrode layer. wherein the orthographic projection of the fifth connecting portion on the base substrate at least partially overlaps with the orthographic projection of the fourth connecting portion on the base substrate; The data line is provided with a data line widening portion, wherein the width of the data line widening portion is greater than the width of a portion of the data line adjacent to the data line widening portion; The array substrate also includes a gate line located in the gate line and a first electrode bridge line arranged in the same layer as the gate line, the first electrode bridge line and the gate line extend along a second direction, the second direction intersects with the first direction, the first electrode bridge line is used to electrically connect the first electrodes in adjacent sub-pixels in the second direction, and the orthographic projection of the data line widening portion on the base substrate is located between the orthographic projection of the gate line on the base substrate and the orthographic projection of the first electrode bridge line on the base substrate.

2. The array substrate according to claim 1, wherein: The first connecting portion and the second connecting portion are both located on a side of the first electrode facing away from the base substrate.

3. The array substrate according to claim 1, wherein: The first connection portion and the second connection portion are electrically connected through a via hole.

4. The array substrate according to claim 3, further comprising: An insulating layer is located between the gate line and the second electrode, wherein the first sub-pixel unit further includes a third connecting portion, and the third connecting portion is an opening of the via hole in the insulating layer between the gate line and the second electrode.

5. The array substrate according to claim 4, wherein: An orthographic projection of the third connection portion on the base substrate at least partially overlaps with an orthographic projection of the first connection portion on the base substrate.

6. The array substrate according to claim 1, wherein: The orthographic projection of the second connecting portion on the base substrate at least partially overlaps with the orthographic projection of the first electrode on the base substrate, the second connecting portion has a first edge and a second edge, the first electrode has a third edge and a fourth edge located in the first sub-pixel unit, the first edge is parallel to the third edge, and the second edge is parallel to the fourth edge.

7. The array substrate according to claim 1, wherein: Each of an orthographic projection of the fifth connecting portion on the base substrate and an orthographic projection of the fourth connecting portion on the base substrate does not overlap with an orthographic projection of the first connecting portion and the second connecting portion on the base substrate.

8. The array substrate according to claim 1 or 7, wherein: The first sub-pixel unit includes a sixth connecting portion arranged in the same layer as the first electrode, and an orthographic projection of the sixth connecting portion on the base substrate falls within an orthographic projection of the gate line on the base substrate.

9. The array substrate according to any one of claims 1 to 6, further comprising an active layer, wherein the active layer is located on a side of the gate line facing away from the base substrate and on a side of the second electrode facing the base substrate, wherein: The at least one sub-pixel unit also includes at least one second sub-pixel unit, and the at least one second sub-pixel unit includes a seventh connection portion arranged in the same layer as the gate line and an eighth connection portion arranged in the same layer as the active layer, and the orthographic projection of the seventh connection portion on the base substrate at least partially overlaps with the orthographic projection of the eighth connection portion on the base substrate.

10. The array substrate according to claim 9, wherein: The first sub-pixel unit and the second sub-pixel unit are both blue sub-pixel units.

11. The array substrate according to claim 9, wherein: A plurality of the first sub-pixel units and a plurality of the second sub-pixel units are arranged on the base substrate, and the plurality of the first sub-pixel units and the plurality of the second sub-pixel units are alternately distributed along a second direction intersecting with the first direction on the array substrate.

12. The array substrate according to claim 9, wherein: The first sub-pixel unit includes a sixth connecting portion arranged in the same layer as the first electrode, and an orthographic projection of the sixth connecting portion on the base substrate falls within an orthographic projection of the gate line on the base substrate.

13. The array substrate according to claim 1, wherein: The orthographic projection of the edge of the data line widening portion on the base substrate has a shape that is concave toward the center of the data line.

14. The array substrate according to claim 1, further comprising: A first electrode transfer line is arranged in the same layer as the second electrode, wherein the first electrode transfer line extends along a first direction and is used to electrically connect the first electrodes in adjacent sub-pixel units in the first direction, and the first electrode transfer line is provided with a transfer line widening portion, and the width of the transfer line widening portion is greater than the width of a portion of the first electrode transfer line adjacent to the transfer line widening portion.

15. The array substrate according to claim 14, wherein: The orthographic projection of the edge of the widened portion of the transition line on the base substrate has a shape that is concave toward the center of the first electrode transition line.

16. The array substrate according to any one of claims 1 to 6, wherein: The first electrode is a common electrode, and the second electrode is a pixel electrode.

17. A display panel comprising: The array substrate according to any one of claims 1 to 16; an opposing substrate, located on a side of the array substrate facing away from the base substrate; as well as A liquid crystal layer is located between the array substrate and the opposite substrate.

18. An electronic device comprising: The array substrate according to any one of claims 1 to 16 or the display panel according to claim 17.

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