High-efficiency, compact AC-DC power controller module

Abstract

This invention relates to a high-efficiency, compact AC-DC power controller module, comprising a first package substrate, a second package substrate, a high-voltage power MOSFET transistor soldered to the first package substrate, and an AC-DC control chip soldered to the second package substrate. This invention first optimizes the size by integrating the AC-DC control chip, power MOSFET, and resistor Rcs into a single package, reducing the PCB layout area of ​​the switching power supply system to achieve high power density, and further reducing system costs by minimizing external pins and resistors. Furthermore, this invention optimizes the efficiency of the AC-DC control chip by adding a voltage-current hybrid detection control loop and multi-loop control logic, improving the control accuracy and response speed of the feedback signal while maintaining the stability of the AC-DC controller, and precisely controlling the operating mode and state of each loop, ultimately achieving higher efficiency.

Description

Technical Field

[0001] This invention relates to an AC-DC power controller module for use in power electronic systems, belonging to the field of integrated circuit technology. Background Technology

[0002] Power management chips are mainly divided into linear regulators and switching power converters. Switching power converters use switching bipolar transistors or field-effect transistors to chop the input voltage into a square wave. The square wave is adjusted by the duty cycle, and a low-pass output filter is used to obtain the DC output voltage. Compared to linear regulators, switching power converters have advantages such as high conversion efficiency and small size. Therefore, switching power supplies occupy a dominant position in today's power management market.

[0003] As the demands on power supplies for portable electronic devices continue to increase, the switching power supply market is fiercely competing on performance metrics such as low power consumption, high precision, and small size, and flyback AC-DC converters are no exception. Flyback AC-DC power supply systems require feedback of output information to the control chip, using negative feedback to adjust the duty cycle of the power switching transistors to achieve stable output. Based on the feedback method, flyback AC-DC converters can be divided into primary-side feedback (PSR) and secondary-side feedback (SSR). Secondary-side feedback technology, also known as optocoupler-isolated feedback, consists of a flyback topology circuit, an optocoupler-isolated feedback circuit, and a control chip. Primary-side feedback technology indirectly samples the output voltage by sampling the auxiliary winding voltage. Primary-side feedback technology requires fewer external components, which reduces PCB costs and improves system reliability, thus leading to its more widespread application.

[0004] A typical system block diagram of primary-side feedback technology is shown below. Figure 1 As shown. When the power transistor is on, the voltage of the auxiliary winding is proportional to the voltage of the primary winding and is negative; when the power transistor is off, the voltage of the auxiliary winding is proportional to the voltage of the secondary winding and is positive. Therefore, the voltage information of the auxiliary winding can be sampled when the secondary winding is on to indirectly obtain the voltage across the secondary winding. Ignoring the forward voltage drop of the diode, the voltage across the secondary winding when it is on is the output voltage. Therefore, primary-side feedback involves sampling the voltage across the auxiliary winding when the secondary winding is on and feeding it back to the control chip for closed-loop control by adjusting the duty cycle.

[0005] Figure 1In the switching power supply system shown, the AC-DC control chip 00, the power MOSFET, and the resistor Rcs are three separate devices. The AC-DC control chip typically uses a package with minimal area, such as SOP, while the 650V power MOSFET device M0 typically uses a relatively larger TO package. Combined with the fixed area of ​​the resistor Rcs, the overall integration density of the circuit on the PCB can be further improved. If system integration or package integration technology is used to integrate the AC-DC control chip, MOSFET device M0, and resistor Rcs into a single packaged chip, the PCB layout area of ​​the primary-side feedback switching power supply system will be further reduced, achieving a smaller AC-DC power supply system. Based on this, the present invention provides a high-efficiency, small-volume AC-DC power controller module to achieve a smaller AC-DC switching power supply system. Summary of the Invention

[0006] Based on existing technology, this invention provides a high-efficiency, small-size AC-DC controller module. Figure 2 This is a block diagram of a switching power supply system using the AC-DC power controller module technology of the present invention. The AC-DC power controller module 300 of the present invention will... Figure 1 The three components—AC-DC control chip, power MOSFET, and resistor Rcs—which were previously separate, are integrated into a single module. Compared to the original three separate packages, the overall module's package size offers two improvements: first, its smaller size allows for a further reduction in the PCB layout area of ​​the switching power supply system using this invention, enabling higher power density; second, the module has one fewer pin, resulting in one less external resistor, thereby further reducing the cost of the AC-DC power supply system.

[0007] The high-efficiency, small-size AC-DC power controller module provided by this invention includes a switch output pin SW, a power supply pin VCC, a feedback voltage signal pin FB, and a ground voltage pin VSS. The module internally includes a first packaging substrate and a second packaging substrate. A high-voltage power MOSFET transistor is soldered onto the first packaging substrate, and an AC-DC control chip is soldered onto the second packaging substrate. The drain of the high-voltage power MOSFET transistor is connected to the switch output pin SW of the module, the gate of the high-voltage power MOSFET transistor is connected to the gate drive pin VO of the AC-DC control chip, and the source of the high-voltage power MOSFET transistor is connected to the output current signal pin CS of the AC-DC control chip. The high-voltage power supply pin of the AC-DC control chip is connected to the power supply pin VCC of the module, the feedback voltage signal pin of the AC-DC control chip is connected to the feedback voltage signal pin FB of the module, and the ground voltage pin of the AC-DC control chip is connected to the ground voltage pin VSS of the module.

[0008] When the source of the high-voltage power MOSFET transistor is located on the reverse side of the chip, the source of the high-voltage power MOSFET transistor is connected to the first package substrate through solder. The first package substrate is connected to the output current signal pin CS of the AC-DC control chip through a lead. That is, the source of the high-voltage power MOSFET transistor is indirectly connected to the output current signal pin CS of the AC-DC control chip through the first package substrate with good conductivity.

[0009] The high-voltage power MOSFET transistor can be implemented as a single chip or as multiple chips connected in parallel. When the high-voltage power MOSFET transistor is implemented as multiple chips connected in parallel, a conductive substrate is required for parallel connection. The gate of each MOSFET transistor chip is connected to a common conductive substrate, and then connected to the gate drive pin VO of the AC-DC control chip through the conductive substrate. The source of each MOSFET transistor chip is connected to a common conductive substrate, and then connected to the output current signal pin CS of the AC-DC control chip through the conductive substrate. Alternatively, the source of each MOSFET transistor chip can be connected to a first packaging substrate through solder, and the first packaging substrate can be connected to the output current signal pin CS of the AC-DC control chip through leads.

[0010] Specifically, the AC-DC control chip includes: a current sensing resistor Rcs, a feedback voltage detection circuit, a primary-side peak current detection module, a feedback current detection circuit, a voltage-current hybrid detection circuit, a reference voltage generation circuit, a first voltage discrimination circuit, a second voltage discrimination circuit, a current comprehensive compensation circuit, a comprehensive comparator, an overall function control circuit, an output drive module, and a protection circuit; the current sensing resistor Rcs is connected between the switching power supply output current signal pin CS and the ground voltage pin VSS; the feedback voltage detection circuit is used to detect the feedback voltage FB output by the switching power supply and generate a detection signal Vf; the primary-side peak current detection module is used to detect the switching power supply output current signal CS and generate a detection signal LEB, which are respectively connected to... The circuit is connected to a feedback current detection circuit and a voltage-current hybrid detection circuit. The feedback current detection circuit processes the detection signal LEB and generates a detection signal Vcs2. The input of the voltage-current hybrid detection circuit is connected to the feedback voltage FB output from the switching power supply, the detection signal LEB, and the detection signal Vcs2. It processes the feedback voltage FB and the detection signal LEB and combines them with the detection signal Vcs2 to generate a detection signal Vcs1. The input of the first voltage discrimination circuit is connected to the detection signal Vcs1 and the compensation reference voltage Vrc fed back from the current comprehensive compensation circuit. It compares the detection signal Vcs1 and the compensation reference voltage Vrc to obtain the compensation signal Vc1. The input of the second voltage discrimination circuit is connected to the switching power supply. The feedback voltage FB from the source output and the compensation reference voltage Vrc from the current comprehensive compensation circuit are compared to obtain the compensation signal Vc2. The input of the current comprehensive compensation circuit is connected to the compensation signals Vc1, Vc2, and reference voltage Vadj1. Under the control of the control signal Ctr4, the compensation signals Vc1, Vc2, Vref, and Vadj1 are compensated to obtain the current compensation signal Vcom. The input of the comprehensive comparator is connected to the current compensation signal Vcom and the reference voltage Vadj2. The current compensation signal Vcom and the reference voltage Vadj2 are compared to obtain the compensation output signal Dcom. The overall function control circuit... The input terminal of the circuit is connected to the compensation output signal Dcom, the detection signal Vf, the detection signal Vcs2, the undervoltage protection signal UVLO, the overvoltage protection signal OVP, the overtemperature protection signal OTP, and the overcurrent protection signal OCP. The overall function control circuit generates control signals Ctr1~Ctr5 to control the working state of the feedback voltage detection circuit, the feedback current detection circuit, the voltage and current mixed detection circuit, the current comprehensive compensation circuit, and the comprehensive comparator, respectively. Based on the detection signal Vf, the detection signal Vcs2, the compensation output signal Dcom, the undervoltage protection signal UVLO, the overvoltage protection signal OVP, the overtemperature protection signal OTP, and the overcurrent protection signal OCP, the circuit comprehensively processes and generates a pulse drive signal Vin, which is output to the output drive module.The output drive module amplifies the pulse drive signal Vin by current and voltage, outputting a gate drive signal VO with high current drive capability. The protection circuit 13 internally includes an undervoltage protection circuit, an overvoltage protection circuit, an overtemperature protection circuit, and an overcurrent protection circuit, generating undervoltage protection signal UVLO, overvoltage protection signal OVP, overtemperature protection signal OTP, and overcurrent protection signal OCP, respectively. The input terminal of the reference voltage generation circuit is connected to an external high-voltage power supply to generate adjustable reference voltages Vadj1 and Vadj2, and also generates the on-chip low-voltage power supply and reference signal required for the operation of all the above circuits.

[0011] After the AC-DC control chip is powered on, the reference voltage generation circuit and the overall function control circuit work first. Then, the overall function control circuit outputs control signals Ctr1~Ctr5 in sequence. The order of outputting control signals Ctr1~Ctr5 is as follows: First, control signals Ctr3, Ctr4, and Ctr5 are output simultaneously to control the voltage and current mixed detection circuit, the current comprehensive compensation circuit, and the comprehensive comparator to start working, so that the feedback voltage FB and the detection signal LEB form a simple control loop, and outputs the pulse drive signal Vin to make the drive signal VO output an initial output voltage. Then, control signals Ctr1 and Ctr2 are output to control the feedback voltage detection circuit and the feedback current detection circuit to start working, respectively. At this time, all control loops of the overall AC-DC power controller are activated, and the chip forms a multi-loop control mode.

[0012] Specifically, the overall functional control circuit includes: a clock generation circuit, a first digital filter, a second digital filter, error handling logic, a counter group, a discrimination control logic, and a register group; the high-frequency clock Clk generated by the clock generation circuit is simultaneously input to the first digital filter, the second digital filter, the counter group, and the discrimination control logic; the first digital filter, under the control of the high-frequency clock Clk, filters the detection signal Vf to obtain compensation data Dc1; the second digital filter, under the control of the high-frequency clock Clk, filters the detection signal Vcs2 to obtain compensation data Dc2; the error handling logic, based on the undervoltage protection signal... Error signal Err is generated based on the conditions of UVLO, overvoltage protection signal OVP, overtemperature protection signal OTP, and overcurrent protection signal OCP. The counter group selects the count output Count based on the count selection signal Sel output by the discrimination control logic, and outputs the count output Count to the discrimination control logic. The input terminals of the discrimination control logic are respectively connected to the above-mentioned compensation data Dc1, compensation data Dc2, error signal Err, count output Count, and compensation output signal Dcom. Logical operations are performed according to the state of each signal to first generate the state control signal Set output to the register group, and then the pulse drive signal Vin is generated through comprehensive processing.

[0013] After the circuit is powered on, the clock generation circuit and error handling logic begin to work. After the clock generation circuit works normally, it outputs a high-frequency clock Clk. Then, the discrimination control logic first generates the first state control signal Set and outputs it to the register group. The register group outputs control signals Ctr3, Ctr4, and Ctr5 according to the first state control signal Set, and at the same time sets the pulse drive signal Vin to a square wave pulse of a fixed frequency. After a delay time td1, when the compensation output signal Dcom changes from the initial state to a pulse signal, the discrimination control logic will unlock the pulse drive signal Vin, so that it is controlled by the compensation output signal Dcom. Then, after a delay time td2, the discrimination control logic generates the second state control signal Set and outputs it to the register group. The register group outputs control signals Ctr1 and Ctr2 according to the second state control signal Set, and opens the remaining control loops.

[0014] The delay times td1 and td2 used by the above-mentioned discrimination control logic to change the state control signal Set are controlled by the discrimination control logic through providing different count selection signals Sel to the counter group in sequence, thereby generating different count outputs Count by the counter group.

[0015] Specifically, the current compensation circuit consists of the following functional parts: a compensation signal adjustment circuit composed of PMOS transistors M401, M402, M404, resistors R41 and R42, NMOS transistors M413, M414, M419, M420, M428, and M429, and capacitors C41 and C42; and a compensation signal adjustment circuit composed of PMOS transistors M405, M406, M409, M410, M415, and M416, resistors R43, R44, and R45, and NMOS transistors. The compensation signal amplifier circuit consists of M421, NMOS transistors M422, M426, and M427; the compensation output circuit consists of PMOS transistors M407, M408, M411, M412, M417, M418, M423, M424, M425, capacitors C43 and C44, and resistor R46; the remaining circuit forms a unity-gain buffer, including: the gate of PMOS transistor M430 connected to the reference voltage Vref; the gates of PMOS transistors M431 and M432; and PMOS transistors M427 and M428. The gate of transistor M433 is connected to bias voltage Vbc43; the gate of NMOS transistor M441 is connected to bias voltage Vbc44; the drain of PMOS transistor M430 is connected to the upper end of resistor R47 and the gate of PMOS transistor M435; the drain of PMOS transistor M431 is connected to the source of PMOS transistor M435 and the source of PMOS transistor M436; the drain of PMOS transistor M435 is connected to the drain, gate, and gate of NMOS transistors M438 and M439; the drain of PMOS transistor M436 is connected to the drain of NMOS transistor M439, gate of NMOS transistor M440, and the upper end of resistor R48, with the lower end of resistor R48 connected to the upper end of capacitor C45; the drain of PMOS transistor M432... The drain of NMOS transistor M440 is connected to the source of NMOS transistor M437; the drain of PMOS transistor M433 is connected to the gate of NMOS transistor M437, the drain of NMOS transistor M437, and the gate of NMOS transistor M434; the source of NMOS transistor M434 is connected to the drain of NMOS transistor M441 and the gate of PMOS transistor M436, and serves as the output terminal of the current compensation signal Vcom, and is also fed back to the upper end of capacitor C43 and the drain of NMOS transistor M424; the sources of PMOS transistors M430, M431, M432, and M433, and the drain of NMOS transistor M434 are all connected to the power supply voltage VCCL.The sources of NMOS transistors M438, M439, M440, and M441, the lower end of resistor R47, and the lower end of capacitor C45 are all connected to ground voltage VSS.

[0016] Specifically, the voltage-current hybrid detection circuit includes: a unity-gain amplifier, a voltage divider circuit, a variable-gain operational amplifier, and a non-inverting adder operational amplifier circuit. The unity-gain amplifier isolates and buffers the feedback voltage FB signal to output a voltage signal Vf_in, which is then connected to the non-inverting adder operational amplifier circuit. The voltage divider circuit converts the signal LEB from current to voltage, outputting a voltage Vc_det, which is then connected to the variable-gain operational amplifier. The variable-gain operational amplifier amplifies the voltage signal Vc_in, which is then connected to the non-inverting adder operational amplifier circuit. The non-inverting adder operational amplifier circuit sums the voltage signals Vf_in and Vc_in to output the final detection signal Vcs1.

[0017] Specifically, the protection circuit includes: the input terminal of the temperature detection circuit is connected to a first clamping circuit to form a temperature detection branch; the input terminal of the current detection circuit is connected to a second clamping circuit to form a current detection branch; the input terminal of the first voltage detection circuit is connected to a third clamping circuit to form an undervoltage detection branch; and the input terminal of the second voltage detection circuit is connected to a fourth clamping circuit to form an overvoltage detection branch. The output terminals of the temperature detection circuit, current detection circuit, first voltage detection circuit, and second voltage detection circuit are all connected to a detection input switch selection circuit. The output terminal of the detection input switch selection circuit is sequentially connected to a high-precision comparator, a shaping buffer circuit, and a detection output switch selection circuit. The circuit includes the following signals: over-temperature protection signal OTP, temperature lockout signal OTLock, overcurrent protection signal OCP, overcurrent lockout signal OCLock, undervoltage protection signal UVLO, undervoltage lockout signal UVLock, overvoltage protection signal OVP, and overvoltage lockout signal OVLock. The temperature lockout signal OTLock is connected to the input of the first clamping circuit, the overcurrent lockout signal OCLock is connected to the input of the second clamping circuit, the undervoltage lockout signal UVLock is connected to the input of the third clamping circuit, and the overvoltage lockout signal OVLock is connected to the input of the fourth clamping circuit.

[0018] The first clamping circuit provides a bias voltage VbT based on the state of the temperature lockout signal OTLock and outputs it to the temperature detection circuit, which obtains a temperature detection output signal VinT based on the bias voltage VbT. The second clamping circuit provides a bias voltage VbC based on the state of the overcurrent lockout signal OCLock and outputs it to the current detection circuit, which obtains a current detection output signal VinC based on the bias voltage VbC. The third clamping circuit provides a bias voltage VbL based on the state of the undervoltage lockout signal UVLock and outputs it to the first voltage detection circuit, which obtains an undervoltage detection output signal VinL based on the bias voltage VbL. The fourth clamping circuit provides a bias voltage VbH based on the state of the overvoltage lockout signal OVLock and outputs it to the second voltage detection circuit, which obtains an overvoltage detection output signal VinH based on the bias voltage VbH.

[0019] The temperature detection output signal VinT, current detection output signal VinC, undervoltage detection output signal VinL, and overvoltage detection output signal VinH simultaneously enter the detection input switch selection circuit. After selection by the switch selection control signal Selp, the detection signal Vind is output. The switch selection control signal Selp has four switching states: in state one, the temperature detection output signal VinT is selected and connected to the detection signal Vind; in state two, the current detection output signal VinC is selected and connected to the detection signal Vind; in state three, the undervoltage detection output signal VinL is selected and connected to the detection signal Vind; and in state four, the overvoltage detection output signal VinH is selected and connected to the detection signal Vind. The high-precision comparator will detect... The measured signal Vind is compared with the internal reference signal to obtain the comparison output signal Vo. The shaping buffer circuit processes the comparison output signal Vo to obtain the protection signal OP and the protection lockout signal OPL, which are connected to the input of the detection output switch selection circuit. After selection by the switch selection control signal Selp, in state one, the protection signal OP and the protection lockout signal OPL are selected and connected to the over-temperature protection signal OTP and the temperature lockout signal OTLock, respectively. In state two, they are selected and connected to the over-current protection signal OCP and the over-current lockout signal OCLock, respectively. In state three, they are selected and connected to the under-voltage protection signal UVLO and the under-voltage lockout signal UVLock, respectively. In state four, they are selected and connected to the over-voltage protection signal OVP and the over-voltage lockout signal OVLock, respectively.

[0020] Specifically, the high-precision comparator includes: a PMOS transistor M121 whose gate is connected to a bias voltage; a PMOS transistor M121 whose drain is connected to the drain of NMOS transistors M122, M122, M123, M128, and M129; an NMOS transistor M123 whose drain is connected to the drain of PMOS transistors M124, M124, and M125; and a PMOS transistor M125 whose drain is connected to a PMOS transistor M125. The source of S-MOSFET M126 and the source of PMOS transistor M127 are connected; the gate of PMOS transistor M126 is connected to the reference voltage of the high-precision comparator; the gate of PMOS transistor M127 is the comparator voltage input terminal and is connected to Vind; the drain of PMOS transistor M126 is connected to the drain of NMOS transistor M129 and the gate of NMOS transistor M1210; the drain of PMOS transistor M127 is connected to the drain of NMOS transistor M128 and the gate of NMOS transistor M1214; the drain of PMOS transistor M1211 is connected to NMOS transistor M12... 10. Drain and gate of PMOS transistor M1212; The drain of PMOS transistor M1212 is connected to the gate of PMOS transistor M1211, the drain of NMOS transistor M1214, the gate of PMOS transistor M1213, and the gate of NMOS transistor M1215; The drain of PMOS transistor M1213 is connected to the drain of NMOS transistor M1215, the upper end of resistor R121, and the upper end of capacitor C121, and serves as the signal Vo output terminal; Source of NMOS transistor M122, Source of NMOS transistor M123, and NMOS transistor M... The sources of transistors M128, M129, M1210, M1214, and M1215, the lower end of resistor R121, and the lower end of capacitor C121 are all connected to ground voltage VSS; the sources of PMOS transistors M121, M124, M125, M1211, M1212, and M1213 are all connected to power supply voltage VCCL.

[0021] The advantages of this invention are as follows: The high-efficiency, compact AC-DC power controller module provided, based on existing technologies, firstly optimizes the size by integrating the AC-DC control chip, power MOSFET, and resistor Rcs into a single package, reducing the PCB layout area of ​​the switching power supply system to achieve high power density, and further reducing external pins and resistors, thus lowering system costs. Secondly, this invention optimizes the efficiency of the AC-DC control chip by adding a voltage-current hybrid detection control loop and multi-loop control logic, improving the control accuracy and response speed of the feedback signal while maintaining the stability of the AC-DC controller. It precisely controls the operating mode and state of each loop, ultimately achieving higher efficiency. Compared with existing technologies, this invention has significant advantages in efficiency and size, and can be widely applied to various AC-DC switching power supply systems. Attached Figure Description

[0022] Figure 1 This is a block diagram of a typical primary-side feedback switching power supply system.

[0023] Figure 2 This is a block diagram of a switching power supply system using the technology of this invention.

[0024] Figure 3a This is one embodiment of the packaging structure of the present invention.

[0025] Figure 3b This is a second embodiment of the packaging structure of the present invention.

[0026] Figure 3c This is embodiment three of the packaging structure of the present invention.

[0027] Figure 3d This is embodiment four of the packaging structure of the present invention.

[0028] Figure 4 This is an internal block diagram of a typical primary-side feedback AC-DC controller.

[0029] Figure 5 This is a circuit structure block diagram of the AC-DC control chip of the present invention.

[0030] Figure 6 This is a schematic diagram of the current comprehensive compensation circuit of the present invention.

[0031] Figure 7 This is a schematic diagram of the voltage discrimination circuit of the present invention.

[0032] Figure 8 This is one embodiment of the voltage and current hybrid detection circuit of the present invention.

[0033] Figure 9 This is a circuit structure block diagram of the overall functional control circuit of the present invention.

[0034] Figure 10a This is a block diagram of one embodiment of the protection circuit of the present invention.

[0035] Figure 10b This is a structural block diagram of another embodiment of the protection circuit of the present invention.

[0036] Figure 11 This is one embodiment of the clamping circuit of the present invention.

[0037] Figure 12 This is one embodiment of the high-precision comparator of the present invention.

[0038] Figure 13 This is one embodiment of the shaping buffer circuit of the present invention. Detailed Implementation

[0039] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0040] The power controller module of this invention has the following external pins: a switch output pin SW, a power supply pin VCC, a feedback voltage signal pin FB, and a ground voltage pin VSS. In this document, the letter names of the pins refer to the names of the signals transmitted by those pins.

[0041] Figure 3a This invention provides a packaging structure. The high-efficiency, small-volume AC-DC power controller module 300 internally includes a first packaging substrate 31, a second packaging substrate 32, a high-voltage power MOSFET transistor 301 soldered to the first packaging substrate 31, and an AC-DC control chip 302 soldered to the second packaging substrate 32. The drain of the high-voltage power MOSFET transistor 301 is connected to the switch output pin SW of the high-efficiency, small-volume AC-DC power controller module 300; the gate of the high-voltage power MOSFET transistor 301 is connected to the gate drive pin VO of the AC-DC control chip 302; the source of the high-voltage power MOSFET transistor 301 is connected to the output current signal CS pin of the AC-DC control chip 302; the high-voltage power supply pin VCC of the AC-DC control chip 302 is connected to the power supply pin VCC of the AC-DC power controller module 300; the feedback voltage signal pin FB of the AC-DC control chip 302 is connected to the feedback voltage signal FB pin of the AC-DC power controller module 300; and the ground voltage pin VSS of the AC-DC control chip 302 is connected to the ground voltage pin VSS of the AC-DC power controller module 300.

[0042] Because the drain and source of a power MOSFET need to carry large currents, multiple bonding wires must be used for the two pins and external connections to meet the requirements. Figure 3a The proposed solution is suitable for power MOSFETs where the gate, drain, and source electrodes are all on the same front side. When the three electrodes of the power MOSFET are not on the same front side, the above solution needs to be modified. Figure 3b This is an alternative module structure diagram applicable to power MOSFETs where the gate, drain, and source are not on the same front side. For example, if the power MOSFET uses a VDMOS structure, the gate and drain are on the front side, while the source is on the back side of the chip. The power MOSFET chip needs to have its source soldered to the first packaging substrate 31. In this case, the first packaging substrate 31 becomes the source of the power MOSFET chip, and the first packaging substrate 31 must have excellent conductivity to meet the requirements.

[0043] In power semiconductor device applications, to increase the output current capability, multiple power devices are usually connected in parallel to increase the power output. Therefore, this invention also provides a controller module structure for the case of multiple power MOSFETs being used in parallel. Figure 3c The proposed solution is suitable for device types where the gate, drain, and source electrodes of multiple power MOSFETs are all on one front side. Figure 3d The proposed solution is suitable for device types where the gate and drain of multiple power MOSFETs are on the front side, while the source is on the back side of the chip.

[0044] Figure 3b The AC-DC power controller module 300 shown internally includes a first packaging substrate 31, a second packaging substrate 32, a high-voltage power MOSFET transistor 301 soldered on the first packaging substrate 31, solder 303 providing connection between the first packaging substrate 31 and the high-voltage power MOSFET transistor 301, and an AC-DC control chip 302 soldered on the second packaging substrate 32. The drain of the high-voltage power MOSFET transistor 301 is connected to the switch output pin SW of the AC-DC power controller module 300, and the gate of the high-voltage power MOSFET transistor 301 is connected to the gate drive pin VO of the AC-DC control chip 302. The source of the high-voltage MOSFET transistor 301 is connected to the first package substrate 31 via solder 303, and then the first package substrate 31 is connected to the output current signal CS pin of the AC-DC control chip 302 via a lead; the high-voltage power supply VCC pin of the AC-DC control chip 302 is connected to the power supply pin VCC of the AC-DC power controller module 300, the feedback voltage signal FB pin of the AC-DC control chip 302 is connected to the feedback voltage signal FB pin of the AC-DC power controller module 300, and the ground voltage pin VSS of the AC-DC control chip 302 is connected to the ground voltage pin VSS of the AC-DC power controller module 300.

[0045] Figure 3cThe structure shown includes a first packaging substrate 31, a second packaging substrate 32, a first conductive substrate 33, a second conductive substrate 34, a first high-voltage power MOSFET transistor and a second high-voltage power MOSFET transistor soldered to the first packaging substrate 31, and an AC-DC control chip soldered to the second packaging substrate 32. The drains of the first and second high-voltage power MOSFET transistors are both connected to the switch output pin SW of the AC-DC power controller module 300. The gates of the first and second high-voltage power MOSFET transistors are both connected to the first conductive substrate 33, which is also connected to the gate drive pin V of the AC-DC control chip 302. The sources of the first and second high-voltage power MOSFET transistors are both connected to the second conductive substrate 34, which is also connected to the output current signal CS pin of the AC-DC control chip 302. The high-voltage power supply VCC pin of the AC-DC control chip 302 is connected to the power supply pin VCC of the AC-DC power controller module 300. The feedback voltage signal FB pin of the AC-DC control chip 302 is connected to the feedback voltage signal FB pin of the AC-DC power controller module 300. The ground voltage pin VSS of the AC-DC control chip 302 is connected to the ground voltage pin VSS of the AC-DC power controller module 300.

[0046] Figure 3c In the proposed solution, the first conductive substrate 33 is used to connect the gates of the first and second high-voltage power MOSFET transistors and the gate drive pin VO of the AC-DC control chip 302; the second conductive substrate 34 is used to connect the sources of the first and second high-voltage power MOSFET transistors and the output current signal pin CS of the AC-DC control chip 302. This solution primarily improves upon the design in two ways: firstly, it reduces lead length while maintaining a relatively uniform lead length, thus minimizing the impact of parasitic inductance; secondly, it facilitates the parallel expansion of power MOSFETs, making parallel expansion much easier. Figure 3c The proposed solution only provides a parallel use of two power MOSFETs. Using the same strategy, it is easy to extend to the parallel use of more power MOSFETs.

[0047] Figure 3dThis is a fourth structural diagram of the high-efficiency, small-volume AC-DC power controller module of the present invention. The AC-DC power controller module 300 internally includes a first packaging substrate 31, a second packaging substrate 32, a first conductive substrate 33, a first high-voltage power MOSFET transistor and a second high-voltage power MOSFET transistor soldered to the first packaging substrate 31, a first solder 305 providing connection between the first packaging substrate 31 and the first high-voltage power MOSFET transistor, a second solder 304 providing connection between the first packaging substrate 31 and the second high-voltage power MOSFET transistor, and an AC-DC control chip 302 soldered to the second packaging substrate 32. The drains of the first and second high-voltage power MOSFET transistors are both connected to the switch output pin SW of the AC-DC power controller module 300; the gates of the first and second high-voltage power MOSFET transistors are connected to the first conductive substrate 33, and the first conductive substrate 33 is also connected to the... The gate drive pin VO of the AC-DC control chip 302; the source of the first high-voltage power MOSFET transistor is connected to the first package substrate 31 through the first solder 305, the source of the second high-voltage power MOSFET transistor is connected to the first package substrate 31 through the second solder 304, and then the first package substrate 31 is connected to the output current signal CS pin of the AC-DC control chip 302 through a lead; the high-voltage power supply VCC pin of the AC-DC control chip 302 is connected to the power supply pin VCC of the AC-DC power controller module 300, the feedback voltage signal FB pin of the AC-DC control chip 302 is connected to the feedback voltage signal FB pin of the AC-DC power controller module 300, and the ground voltage pin VSS of the AC-DC control chip 302 is connected to the ground voltage pin VSS of the AC-DC power controller module 300.

[0048] like Figure 4 The diagram shows the internal block diagram of a commonly used primary-side feedback AC-DC control chip, which includes a power supply module 40, a constant voltage control module 41, an output drive module 42, a constant current control module 43, a primary-side peak current detection module 44, a control module 45, and various auxiliary modules of the chip. Since the overall controller chip also provides a GATE output signal with high current drive capability, to ensure that the gate capacitors of the high-voltage power devices at the GATE output can charge and discharge quickly, enabling rapid saturation conduction and reliable turn-off, the output drive circuit requires low output impedance and high output current (ampere level). Therefore, a protection circuit module 46 is needed to monitor the chip's status to prevent damage to the output controlled object due to abnormal conditions. Typical protection circuits include undervoltage protection, overvoltage protection, overtemperature protection, and overcurrent protection. Figure 4In the existing solution shown, the control module 45 generates a pulse signal Vin for driving the external power transistor based on the constant voltage turn-on signal CV_ctrl, the constant current turn-on signal CC_ctrl, and the peak current detection signal LEB. This Vin is then voltage-driven and current-amplified by the output driver to obtain the output gate control signal VO. The constant voltage turn-on signal CV_ctrl and the constant current turn-on signal CC_ctrl are both digital signals, generated separately from the output voltage feedback signal FB of the switching power supply; the peak current detection signal LEB is an analog signal, generated separately from the output current feedback signal CS of the switching power supply.

[0049] In the aforementioned control system, the two analog signals, the output voltage feedback signal (corresponding to the feedback voltage signal FB of this invention) and the output current feedback signal (corresponding to the output current signal CS of this invention), are not directly related. However, in actual switching power supply systems, FB and CS are directly and closely related. If the two analog signals FB and CS can be directly correlated in the chip control loop, introducing a new control loop, the control accuracy of the AC-DC controller can be increased. However, after introducing the new control loop, the control mode becomes significantly more complex and prone to harmonic oscillations, affecting system stability. Therefore, more stringent control techniques are needed to eliminate this risk.

[0050] like Figure 5 As shown, the AC-DC control chip 302 of the present invention includes: a current detection resistor Rcs, a feedback voltage detection circuit 1, a primary-side peak current detection module 2, a feedback current detection circuit 3, a voltage-current hybrid detection circuit 4, a reference voltage generation circuit 5, a first voltage discrimination circuit 6, a second voltage discrimination circuit 7, a current comprehensive compensation circuit 9, a comprehensive comparator 10, an overall function control circuit 11, an output drive module 12, and a protection circuit 13.

[0051] The current sensing resistor Rcs is connected between the output current signal CS of the switching power supply and the ground voltage VSS; the feedback voltage detection circuit 1 is used to detect the feedback voltage FB output by the switching power supply and generate a detection signal Vf; the primary-side peak current detection module 2 is used to detect the output current signal CS of the switching power supply and generate a detection signal LEB; the feedback current detection circuit 3 is used to process the detection signal LEB and generate a detection signal Vcs2; the voltage and current hybrid detection circuit 4 is used to process the feedback voltage FB output by the switching power supply and the detection signal LEB, and combine them with the detection signal Vcs2 to generate a detection signal Vcs1.

[0052] The first voltage discrimination circuit 6 compares the detection signal Vcs1 with the compensation reference voltage Vrc fed back by the current comprehensive compensation circuit 9 to obtain the compensation signal Vc1; the second voltage discrimination circuit 7 compares the feedback voltage FB after the output of the switching power supply with the compensation reference voltage Vrc fed back by the current comprehensive compensation circuit 9 to obtain the compensation signal Vc2; under the control of the control signal Ctr4, the current comprehensive compensation circuit 9 performs compensation processing on the compensation signal Vc2, the compensation signal Vc1, the reference voltage Vref, and the reference voltage Vadj1 to obtain the current compensation signal Vcom; the comprehensive comparator 10 compares the current compensation signal Vcom with the reference voltage Vadj2 to obtain the compensation output signal Dcom.

[0053] The overall function control circuit 11 generates control signals Ctr1~Ctr5 to control the operating states of the feedback voltage detection circuit 1, feedback current detection circuit 3, voltage and current hybrid detection circuit 4, current comprehensive compensation circuit 9, and comprehensive comparator 10, respectively. Based on the detection signal Vf, detection signal Vcs2, compensation output signal Dcom, undervoltage protection signal UVLO, overvoltage protection signal OVP, overtemperature protection signal OTP, and overcurrent protection signal OCP, it comprehensively processes and generates a pulse drive signal Vin. The output drive module amplifies the pulse drive signal Vin in both current and voltage, outputting a gate drive signal VO with high current driving capability. The protection circuit 13 internally includes an undervoltage protection circuit, an overvoltage protection circuit, an overtemperature protection circuit, and an overcurrent protection circuit, generating the undervoltage protection signal UVLO, the overvoltage protection signal OVP, the overtemperature protection signal OTP, and the overcurrent protection signal OCP, respectively, and outputting all of them to the overall function control circuit 11. The reference voltage generation circuit 5 is connected to an external high-voltage power supply to generate adjustable reference voltages Vadj1 and Vadj2, as well as an on-chip low-voltage power supply and reference signal required for the operation of all the above circuits.

[0054] The first voltage discrimination circuit 6 and the second voltage discrimination circuit 7 are implemented using the same voltage discrimination circuit.

[0055] The AC-DC control chip provided by this invention offers multiple feedback control loops, improving the feedback control accuracy and efficiency of the AC-DC power controller. First, the feedback voltage FB after the switching power supply output is now processed simultaneously by three loops: the feedback voltage detection circuit 1, the voltage-current hybrid detection circuit 4, and the second voltage discrimination circuit 7. Second, the LEB signal obtained by detecting the switching power supply output current signal CS is processed simultaneously by the feedback current detection circuit 3 and the voltage-current hybrid detection circuit 4, providing output current detection functionality. Due to the added control loops, to maintain the stability of the controller, the overall functional control circuit needs to precisely control the operating mode and state of each loop.

[0056] Figure 5 In the circuit shown, the feedback voltage FB, through the feedback voltage detection circuit 1, generates a detection signal Vf, and the detection signal LEB, through the feedback current detection circuit 3, generates a detection signal Vcs2. Both are logic level signals and directly enter the overall function control circuit 11. After the overall AC-DC control chip is powered on, the reference voltage generation circuit 5 and the overall function control circuit 11 work first. Then, the overall function control circuit 11 outputs control signals Ctr1~Ctr5 in sequence, which are used to control the working state of the feedback voltage detection circuit 1, the feedback current detection circuit 3, the voltage and current hybrid detection circuit 4, the current comprehensive compensation circuit 9, and the comprehensive comparator 10 in order of priority. The overall functional control circuit 11 outputs control signals Ctr1~Ctr5 in the following order: First, it simultaneously outputs control signals Ctr3, Ctr4, and Ctr5 to control the voltage-current hybrid detection circuit 4, the current comprehensive compensation circuit 9, and the comprehensive comparator 10 to start working, so that the feedback voltage FB and the detection signal LEB form a simple control loop, and outputs a pulse drive signal Vin to make VO output an initial output voltage; Second, it outputs control signals Ctr1 and Ctr2 to control the feedback voltage detection circuit 1 and the feedback current detection circuit 3 to start working, respectively; At this time, all control loops of the overall AC-DC power controller are activated, and the chip forms a multi-loop control mode.

[0057] like Figure 6As shown, the current compensation circuit 9 is roughly divided into four functional circuits from left to right: PMOS transistors M401, M402, and M404; resistors R41 and R42; NMOS transistors M413, M414, M419, M420, M429, and M428; and capacitors C41 and C42, which constitute the compensation signal adjustment circuit; PMOS transistors M405, M406, and M409... PMOS transistors M410, M415, and M416, resistors R43, R44, and R45, NMOS transistors M421, M422, M427, M426, M429, and M428, and capacitors C41 and C42 constitute a compensation signal amplification circuit; PMOS transistors M407, M408, M411, M412, and NMOS transistors M417 and M428 constitute a compensation signal amplification circuit. The circuit consists of transistors M418, M423, M424, and M425, and capacitor C44, forming a compensation output circuit. PMOS transistors M407, M408, M411, and M412 form a common-source, common-gate mirror current source circuit. In the rightmost circuit, PMOS transistors M431, M432, M435, and M436, along with NMOS transistors M438, M439, and M440, constitute a two-stage operational amplifier. NMOS transistors M434 and M425... The 441 transistor forms a source follower. The bias signal of the NMOS transistor M434 requires a relatively high voltage, so the outputs of the two operational amplifier stages are connected to a level shifter circuit composed of M433 and M437, which then outputs to the gate of the NMOS transistor M434. The output of the source follower formed by the NMOS transistors M434 and M441 is the current compensation signal Vcom output of the current compensation circuit 9. This output is reconnected to the inputs of the two operational amplifier stages, making the overall circuit on the right a unity-gain buffer. The reference voltage Vref passes through the PMOS transistor M430 and resistor R47 to form an input bias circuit, the output of which is the gate of the M435.

[0058] The specific circuit connections are as follows.

[0059] PMOS transistors M401, M402, and M404, resistors R41 and R42, NMOS transistors M413, M414, M419, M420, M429, and M428, and capacitors C41 and C42 constitute a compensation signal adjustment circuit. The drain and gate of PMOS transistor M401 are connected and serve as the input terminal of the bias input signal IbC41, which is also connected to PMOS transistor M402. The gate of PMOS transistor M404 is connected to the lower end of capacitor C41; the drain of PMOS transistor M402 is connected to the drain and gate of NMOS transistor M419, the gate of NMOS transistor M420, and the drain of NMOS transistor M429; the drain of PMOS transistor M404 is connected to the drain of NMOS transistor M420, the source of NMOS transistor M413, the source of NMOS transistor M414, and the left end of resistor R44, which also serves as the output terminal of the compensation reference voltage Vrc; the drain of NMOS transistor M413 is connected to the lower end of resistor R41, the gate of NMOS transistor M413 is connected to the compensation signal Vc1, and the drain of NMOS transistor M414 is connected to resistor R41. The lower end of R42 and the gate of NMOS transistor M414 are connected to the compensation signal Vc2; the sources of PMOS transistors M401, M402, and M404, the upper end of capacitor C41, the upper end of resistor R41, and the upper end of resistor R42 are all connected to the power supply voltage VCCL; the sources of NMOS transistors M419, M420, M428, and M429, and the lower end of capacitor C42 are all connected to the ground voltage VSS; capacitors C41 and C42 are filter capacitors, and NMOS transistors M429 and M428 are reset transistors controlled by the reset signal S1.

[0060] PMOS transistors M405, M406, M409, M410, M415, and M416, resistors R43, R44, and R45, NMOS transistors M421, M422, M427, M426, M429, and M428, along with capacitors C41 and C42, constitute a compensation signal amplification circuit. PMOS transistors M405, M406, M409, and M416... Transistor M410 and resistor R43 constitute a self-biased cascode mirror current source circuit. The lower end of resistor R43 serves as the input terminal of the bias input signal Ibc42 and is also connected to the gates of PMOS transistors M409, M410, M411, and M412. The upper end of resistor R43 is connected to the drain of PMOS transistors M409, M405, and M406. The source of PMOS transistor M409 is connected to the drain of PMOS transistor M405, and the drain of PMOS transistor M406 is connected to the gate of PMOS transistor M406. 410 source; PMOS transistors M406 and M410 form a common-source, common-gate current source. The drain of PMOS transistor M410 is connected to the source of PMOS transistors M415 and M416. The gate of PMOS transistor M415 is connected to the right end of resistor R44 and the lower end of resistor R46. The gate of PMOS transistor M416 is connected to the left end of resistor R45. The right end of R45 is the modulation reference signal Vadj1 of the current synthesis compensation circuit 9. The drain of PMOS transistor M415 is connected to the drain and gate of NMOS transistor 521 and N... The gate of MOS transistor M423, the drain of NMOS transistor M427, and the drain of PMOS transistor M416 are connected to the drain and gate of NMOS transistor 522 and the gate of NMOS transistor M424. NMOS transistors M427 and M426 are reset transistors controlled by the reset signal S1. The sources of PMOS transistors M405 and M406 are connected to the power supply voltage VCCL. The sources of NMOS transistors M421, M422, M426, and M427 are connected to the ground voltage VSS.

[0061] PMOS transistors M407, M408, M411, and M412, NMOS transistors M417, M418, M423, M424, and M425, along with capacitors C43 and C44 and resistor R46, constitute the compensation output circuit. PMOS transistors M407, M408, M411, and M412 form a common-source mirror. In a current source circuit, the gate of PMOS transistor M407 is connected to the gate of PMOS transistor M408, the drain of PMOS transistor M411, and the drain of PMOS transistor M417. The drain of PMOS transistor M407 is connected to the source of PMOS transistor M411, and the drain of PMOS transistor M408 is connected to the source of PMOS transistor M412. The drains of PMOS transistors M411 and M412 are the output terminals of a common-source, common-gate mirrored current source. The drain of PMOS transistor M411 is connected to N... The drain of MOSFET M417 and the gate of NMOS transistor M417 are connected to the bias voltage Vbc41; the drain of PMOS transistor M412 is connected to the drain and gate of NMOS transistor M418, and serves as the output terminal of the current compensation signal Vcom. It is also connected to the upper end of capacitor C43, the drain of NMOS transistors M424 and M425, the upper end of capacitor C43, and the upper end of capacitor C44; the lower end of capacitor C43 is connected to the upper end of resistor R46; NMOS transistor... The source of M417 is connected to the drain of NMOS transistor M423 and the source of NMOS transistor M418; NMOS transistor M425 is a reset transistor controlled by the reset signal S1; capacitor C44 is a filter capacitor; the sources of PMOS transistors M407 and M408 are both connected to the power supply voltage VCCL; the sources of NMOS transistors M423, M424, and M425, as well as the lower end of capacitor C44, are all connected to the ground voltage VSS.

[0062] The gate of PMOS transistor M430 is connected to the reference voltage Vref; the gates of PMOS transistors M431, M432, and M433 are connected to the bias voltage Vbc43; the gate of NMOS transistor M441 is connected to the bias voltage Vbc44; the drain of PMOS transistor M430 is connected to both the upper end of resistor R47 and the gate of PMOS transistor M435; the drain of PMOS transistor M431 is connected to both the source of PMOS transistors M435 and M436; the drain of PMOS transistor M435 is connected to the drain of NMOS transistor M438, and also to the gates of NMOS transistors M439 and M438; the drain of PMOS transistor M436 is connected to the drain of NMOS transistor M439, and also to the gate of NMOS transistor M440, as well as the upper end of resistor R48, the lower end of which is connected to the upper end of capacitor C45; the drain of PMOS transistor M432... The drain of NMOS transistor M440 is connected to the source of NMOS transistor M437; the drain of PMOS transistor M433 is connected to the gate and drain of NMOS transistor M437, and also to the gate of NMOS transistor M434; the source of NMOS transistor M434 is connected to the drain of NMOS transistor M441, and also to the gate of PMOS transistor M436. This terminal serves as the output terminal of the current compensation signal Vcom, and is also fed back to the upper end of capacitor C43 and the drain of NMOS transistor M424; the sources of PMOS transistors M430, M431, M432, and M433 and the drain of NMOS transistor M434 are simultaneously connected to the power supply voltage VCCL; the sources of NMOS transistors M438, M439, M440, and M441, the lower end of resistor R47, and the lower end of capacitor C45 are simultaneously connected to the ground voltage VSS.

[0063] Figure 6 The current compensation circuit 9 of the present invention first converts the compensation signals Vc2 and Vc1 into a compensation reference voltage Vrc through a compensation signal adjustment circuit. The compensation reference voltage Vrc is output to the two voltage discrimination circuits mentioned earlier and input to the left input of the compensation signal amplification circuit. The right input of the compensation signal amplification circuit is the modulation reference signal Vadj1. The compensation signal amplification circuit amplifies the difference between the compensation reference voltage Vrc and the modulation reference signal Vadj1 and converts it into a current compensation signal Vcom. The current compensation signal Vcom is output and also fed back to the left input of the compensation signal amplification circuit through capacitor C43 and resistor R46, forming a buffer structure for the AC signal. The current compensation signal Vcom is finally further processed... Figure 6 The output of the unity-gain buffer on the right is buffered to obtain the current compensation signal Vcom from the current comprehensive compensation circuit 9.

[0064] Figure 7 This is one embodiment of the voltage discrimination circuit of the present invention. The circuit includes PMOS transistors M71, M72, M73, M74, M75, M76, M77, M711, M712, M715, NMOS transistors M78, M79, M710, M713, M714, and M716, resistor R71, and capacitor C71.

[0065] In this circuit, PMOS transistors M72, M73, M76, M77, M78, M79, and M710 form a two-stage comparator; PMOS transistors M711, M712, M715, M713, M714, and M716 form an output shaping circuit; resistor R71 and capacitor C71 form a low-pass filter; one input of the two-stage comparator is connected to the output signal Vrc of the current compensation circuit, and the input signal Vi to be judged is connected to the other input of the two-stage comparator after passing through the low-pass filter; the output of the two-stage comparator is connected to the output shaping circuit for signal shaping to obtain the output signal OUT of the voltage discrimination circuit; PMOS transistors M71, M74, and M75 are used to generate the hysteresis of the voltage discrimination circuit.

[0066] The gates of PMOS transistors M71, M72, M73, and M74 are connected to a bias voltage Vbc71. The sources of PMOS transistors M71, M72, M73, and M74 are connected to a power supply voltage VCCL. The drain of PMOS transistor M71 is connected to the source of PMOS transistor M74. The drain of PMOS transistor M74 is connected to the source of PMOS transistor M75. The drain of PMOS transistor M75 is connected to PM... The drain of MOSFET M76 and the drain of NMOS transistor M78 are connected together, and are also connected to the gates of NMOS transistors M79 and M78; the drain of PMOS transistor M72 is connected to the source of PMOS transistors M76 and M77; the drain of PMOS transistor M77 and the drain of NMOS transistor M79 are connected together, and are also connected to the gate of NMOS transistor M710; the gate of PMOS transistor M76 is connected to the compensation reference voltage Vrc; the gate of PMOS transistor M77 is connected to the right end of resistor R71 and the upper end of capacitor C71; The left end of resistor R71 is connected to the input signal Vi to be judged; the drain of PMOS transistor M73 is connected to the drain of NMOS transistor M710, and also to the gate of PMOS transistor M711 and the gate of NMOS transistor M713; the drain of PMOS transistor M711 is connected to the source of PMOS transistor M712; the drain of PMOS transistor M712 is connected to the drain of NMOS transistors M713 and M714, and also to the gate of PMOS transistor M715 and the gate of NMOS transistor M716, and also to the PMOS transistor... The gate of M75; the drain of PMOS transistor M715 and the drain of NMOS transistor M716 are connected and also serve as the output signal OUT of the voltage discrimination circuit; the gate of PMOS transistor M712 and the gate of NMOS transistor M714 serve as the input terminal of the reset signal S1; the source of NMOS transistor M78, the source of NMOS transistor M79, the source of NMOS transistor M710, the source of NMOS transistor M713, the source of NMOS transistor M714, the source of NMOS transistor M716 and the lower end of capacitor C51 are connected to the ground voltage VSS.

[0067] Figure 7In the voltage discrimination circuit shown, when the input signal Vi is lower than the compensation reference voltage Vrc, the two comparators output a high level, and the corresponding output signal OUT of the voltage discrimination circuit is also high. At this time, the hysteresis of PMOS transistors M71, M74, and M75 has no effect. When the input signal Vi is greater than the compensation reference voltage Vrc, the outputs of the two comparators change to a low level, and the corresponding comparator output signal OUT also changes to a low level. At this time, the hysteresis formed by PMOS transistors M71, M74, and M75 begins to take effect. M75 turns on, increasing the current and gate voltage of M78, further pulling down the outputs of the two comparators. If the input signal Vi is to change the low level of the output signal OUT back to a high level, it needs to be higher than the compensation reference voltage Vrc by a certain amount of hysteresis. The hysteresis in the above process depends on the ratio of M71 to M72; the larger the size of M71, the greater the hysteresis.

[0068] Figure 8 This is one embodiment of the voltage-current hybrid detection circuit 4 of the present invention. This circuit processes the feedback voltage signal FB and the feedback current signal LEB, ultimately forming a comprehensive compensation signal Vcs1. The voltage-current hybrid detection circuit internally includes a unity-gain amplifier 80, a voltage divider circuit 81, a variable-gain operational amplifier 82, and a non-inverting adder operational amplifier circuit 83. The unity-gain amplifier 80 isolates and buffers the FB signal to obtain a voltage signal Vf_in. The voltage divider circuit 81 performs a current-to-voltage conversion on the feedback current signal LEB to obtain a voltage Vc_det. This voltage is then converted and amplified by the variable-gain operational amplifier 82 to obtain the voltage signal Vc_in. The non-inverting adder operational amplifier circuit 83 sums the voltage signals Vf_in and Vc_in to obtain the final detection signal Vcs1. The variable-gain operational amplifier 82 can be implemented using existing mature VGA technology.

[0069] Figure 9This is an internal block diagram of the overall functional control circuit 11 of the present invention. The overall functional control circuit 11 includes a clock generation circuit 90, a first digital filter 91, a second digital filter 92, error handling logic 93, a calculator group 94, a discrimination control logic 95, and a register group 96. The high-frequency clock Clk generated by the clock generation circuit 90 is simultaneously input to the first digital filter 91, the second digital filter 92, the calculator group 94, and the discrimination control logic 95. Under the control of the high-frequency clock Clk, the first digital filter 91 filters the detection signal Vf to obtain compensation data Dc1. Under the control of the high-frequency clock Clk, the second digital filter 92 filters the detection signal Vcs2. The compensation data Dc2 is obtained; the error handling logic 93 generates an error signal Err based on the undervoltage protection signal UVLO, the overvoltage protection signal OVP, the overtemperature protection signal OTP, and the overcurrent protection signal OCP; the calculator group 94 selects the calculator group counting output Count based on the counting selection signal Sel input by the discrimination control logic 95, and outputs the counting output Count to the discrimination control logic 95; the discrimination control logic 95, based on the state of the counting output Count, the compensation data Dc1, the compensation data Dc2, the compensation output signal Dcom, and the error signal Err, first generates a state control signal Set to be output to the register group, and then performs comprehensive processing to generate a pulse drive signal Vin.

[0070] After the AC-DC control chip of the present invention is powered on, the clock generation circuit 90 and the error handling logic 93 are the first components of the overall functional control circuit 11 to start working normally. After the clock generation circuit 90 starts working normally, it outputs a high-frequency clock Clk and simultaneously inputs it to the first digital filter 91, the second digital filter 92, the calculator group 94, and the discrimination control logic 95. Then, the discrimination control logic 95 first generates a first state control signal Set and outputs it to the register group. The register group outputs control signals Ctr3, Ctr4, and Ctr5 according to the first state control signal Set, and simultaneously transmits the pulse. The drive signal Vin is set to a square wave pulse of a fixed frequency. After a delay time td1, when the compensation output signal Dcom changes from its initial state to a pulse signal, the discrimination control logic 95 will unlock the pulse drive signal Vin, so that it is controlled by the compensation output signal Dcom. Then, after a delay time td2, the discrimination control logic 95 generates a second state control signal Set and outputs it to the register group. The register group outputs control signals Ctr1 and Ctr2 according to the second state control signal Set. At this time, all control loops of the AC-DC control chip are opened.

[0071] The delay times td1 and td2 on which the state control signal Set is based by the above-mentioned discrimination control logic 95 are controlled by the discrimination control logic 95 through sequentially providing different count selection signals Sel to generate different calculator group count outputs Count.

[0072] A typical control process of the overall functional control circuit 11 of this invention is as follows: After the AC-DC control chip is powered on, the clock generation circuit 90 generates a 10MHz clock signal Clk; then, the discrimination control logic 95 first outputs the count selection signal Sel = "0000" to start the calculator group counting, and at the same time generates the first state control signal Set = "00", and outputs control signals Ctr3, Ctr4 and Ctr5 to control the voltage and current mixed detection circuit 4, the current comprehensive compensation circuit 9 and the comprehensive comparator 10 to start normal operation, respectively, and sets the pulse drive signal Vin to a 100KHz pulse signal; then, when the calculator group counts for the first time 10000 cycles (i.e. 1ms), the Count state changes, and after the compensation output signal Dcom changes from the initial state to a pulse signal, the discrimination control logic 95 will unlock the pulse drive signal Vin, making it... The control is changed to Dcom, which simultaneously resets the Count signal and outputs the count selection signal Sel="0001" to restart the counting. Then, when the counting group counts for 100,000 cycles (i.e., 10ms), the Count state changes again, and the discrimination control logic 95 will generate the second state control signal Set="01". At this time, the register group outputs control signals Ctr1 and Ctr2 to control the feedback voltage detection circuit 1 and the feedback current detection circuit 3 to start working, respectively. The discrimination control logic 95 will reset the Count signal and output the count selection signal Sel="0010" to restart the counting. At this time, all control loops of the overall AC-DC control chip are opened, and the chip forms a multi-loop control mode. The pulse drive signal Vin will be controlled simultaneously by the compensation data Dc2, compensation data Dc1, and compensation output signal Dcom.

[0073] In the overall functional control circuit 11 of this invention, the first and second digital filters are identical circuit functional modules, which can be implemented using various existing digital filtering technologies. Their function is to filter out abnormal fluctuation pulse signals in Vf and Vcs2, thereby improving the robustness of compensation data Dc2 and compensation data Dc1. The discrimination control logic 95 is the core circuit for the entire AC-DC control chip, and it is entirely composed of digital logic circuits. Its implementation methods are diverse; the most common method is state machine control. To achieve higher control precision, a DSP core or MCU can be used, although this will significantly increase hardware overhead.

[0074] Figure 9 The error handling logic 93 used in the circuit is typically composed of combinational logic gates. Its function is to synthesize the chip status monitoring signals and determine whether the circuit is functioning correctly. When the chip malfunctions, it shuts off the data output. Existing publicly available technologies can provide various solutions. Whenever the error output signal Err goes low, the entire AC-DC control chip enters a reset mode, and all circuits stop working. Only when Err returns to a high level can the various functional modules within the AC-DC control chip be started sequentially under the control of the overall function control circuit 11, restoring the chip's overall operating mode.

[0075] Figure 10a and Figure 10b These are two embodiments of the protection circuit 13 of the present invention.

[0076] Figure 10a The protection circuit 13 includes: a first clamping circuit 1011, a second clamping circuit 1021, a third clamping circuit 1031, a fourth clamping circuit 1041, a temperature detection circuit 1012, a current detection circuit 1022, a first voltage detection circuit 1032, a second voltage detection circuit 1042, a first high-precision comparator 1013, a second high-precision comparator 1023, a third high-precision comparator 1033, a fourth high-precision comparator 1043, a first shaping buffer circuit 1014, a second shaping buffer circuit 1024, a third shaping buffer circuit 1034, and a fourth shaping buffer circuit 1044.

[0077] The first clamping circuit 1011 provides a bias voltage VbT based on the state of the temperature lockout signal OTLock and outputs it to the temperature detection circuit 1012. The temperature detection circuit 1012 obtains a temperature detection output signal VinT based on the bias voltage VbT. The first high-precision comparator 1013 compares the temperature detection output signal VinT with an internal reference signal to obtain a comparison output signal VoT. The first shaping buffer circuit 1014 processes the comparison output signal VoT to obtain an over-temperature protection signal OTP and a temperature lockout signal OTLock. The over-temperature protection signal OTP is output to the error handling logic 93 in the overall function control circuit 11, and the temperature lockout signal OTLock is input to the first clamping circuit 1011 to control the magnitude of the bias voltage VbT.

[0078] The second clamping circuit 1021 provides a bias voltage VbC based on the state of the overcurrent lockout signal OCLock and outputs it to the current detection circuit 1022. The current detection circuit 1022 obtains a current detection output signal VinC based on the bias voltage VbC. The second high-precision comparator 1023 compares the current detection output signal VinC with the internal reference signal to obtain a comparison output signal VoC. The second shaping buffer circuit 1024 processes the comparison output signal VoC to obtain an overcurrent protection signal OCP and an overcurrent lockout signal OCLock. The overcurrent protection signal OCP is output to the error handling logic 93 in the overall function control circuit 11, and the overcurrent lockout signal OCLock is input to the second clamping circuit 1021 to control the magnitude of the bias voltage VbC.

[0079] The third clamping circuit 1031 provides a bias voltage VbL based on the state of the undervoltage lockout signal UVLock and outputs it to the first voltage detection circuit 1032. The first voltage detection circuit 1032 obtains an undervoltage detection output signal VinL based on the bias voltage VbL. The third high-precision comparator 1033 compares the undervoltage detection output signal VinL with an internal reference signal to obtain a comparison output signal VoL. The third shaping buffer circuit 1034 processes the comparison output signal VoL to obtain an undervoltage protection signal UVLO and an undervoltage lockout signal UVLock. The undervoltage protection signal UVLO is output to the error handling logic 93 in the overall function control circuit 11, and the undervoltage lockout signal UVLock is input to the third clamping circuit 1031 to control the magnitude of the bias voltage VbL.

[0080] The fourth clamping circuit 1041 provides a bias voltage VbH based on the state of the overvoltage lockout signal OVLock and outputs it to the second voltage detection circuit 1042. The second voltage detection circuit 1042 obtains the overvoltage detection output signal VinH based on the bias voltage VbH. The fourth high-precision comparator 1043 compares the overvoltage detection output signal VinH with the internal reference signal to obtain the comparison output signal VoH. The fourth shaping buffer circuit 1044 processes the comparison output signal VoH to obtain the overvoltage protection signal OVP and the overvoltage lockout signal OVLock. The overvoltage protection signal OVP is output to the error handling logic 93 in the overall function control circuit 11, and the overvoltage lockout signal OVLock is input to the fourth clamping circuit 1041 to control the magnitude of the bias voltage VbH.

[0081] Figure 10aThe working principle of the protection circuit 13 shown is as follows: When the temperature is normal, the temperature lockout signal OTLock is high. The high level of OTLock will control the clamping circuit 1011 to generate a higher bias voltage VbT; the temperature detection circuit 1012 will generate a temperature detection output signal VinT based on VbT. Under normal circumstances, the output signal VoT obtained by the first high-precision comparator 1013 should be high; the first shaping buffer circuit 1014 processes the comparison output signal VoT to obtain OTLock, which is also a high-level logic signal. When the chip temperature is abnormal, the temperature detection output signal VinT generated by the temperature detection circuit 1012 will change. The first high-precision comparator 1013 will change to a low-level signal based on the obtained comparison output signal VoT. The temperature lock signal OTLock obtained by the first shaping buffer circuit 1014 will also change to a low-level logic signal. The over-temperature protection signal OTP will become low. The low level of the temperature lock signal OTLock will control the first clamping circuit 1011 to generate a lower bias voltage VbT. The lower bias voltage VbT will further change the magnitude of the temperature detection output signal VinT, so that the VoT output by the first high-precision comparator 1013 will be further locked to a low-level signal.

[0082] When the current is normal, the overcurrent lockout signal OCLock is high. The high level of OCLock controls the clamping circuit 1021 to generate a higher bias voltage VbC. The current detection circuit 1022 generates a current detection output signal VinC based on VbC. Under normal circumstances, the output signal VoC obtained by the second high-precision comparator 1023 should be high. The second shaping buffer circuit 1024 processes the comparison output signal VoC to obtain a high-level logic signal for OCLock. When the chip current is abnormal, the current detection output signal VinC generated by the current detection circuit 1022 will change. The second high-precision comparator 1023 will change to a low-level signal based on the obtained comparison output signal VoC. The current lockout signal OTLock obtained by the second shaping buffer circuit 1024 will also change to a low-level logic signal. The overcurrent protection signal OCP will become low. The low level of the overcurrent lockout signal OCLock will control the second clamping circuit 1021 to generate a lower bias voltage VbC. The lower bias voltage VbC will further change the magnitude of the current detection output signal VinC, so that the VoC output by the second high-precision comparator 1023 will be further locked to a low-level signal.

[0083] When the voltage is normal, the undervoltage lockout signal UVLock is high. The high level of UVLock controls the clamping circuit 1031 to generate a higher bias voltage VbL. The first voltage detection circuit 1032 generates an undervoltage detection output signal VinL based on VbL. Under normal circumstances, the output signal VoL obtained by the third high-precision comparator 1033 should be high. The third shaping buffer circuit 1034 processes the comparison output signal VoL to obtain a high-level logic signal for UVLock. When the chip voltage is abnormally low, the undervoltage detection output signal VinL generated by the first voltage detection circuit 1032 will change. The third high-precision comparator 1033 will change the obtained comparison output signal VoL to a low level signal. The undervoltage lockout signal UVLock obtained by the third shaping buffer circuit 1034 will also change to a low level logic signal. The undervoltage protection signal UVLO will become low level. The low level of the undervoltage lockout signal UVLock will control the third clamping circuit 1031 to generate a lower bias voltage VbL. The lower bias voltage VbL will further change the magnitude of the undervoltage detection output signal VinL, so that the VoL output by the third high-precision comparator 1033 will be further locked to a low level signal.

[0084] The overvoltage protection process operates similarly to the undervoltage protection process. When the voltage is normal, the overvoltage lockout signal OVLock is high; when the voltage is too high, the overvoltage lockout signal OVLock also changes to a low logic signal, and the overvoltage protection signal OVP becomes low.

[0085] Figure 10b circuit pair Figure 10a The protection circuit 13 is integrated and includes: a first clamping circuit 1011, a second clamping circuit 1021, a third clamping circuit 1031, a fourth clamping circuit 1041, a temperature detection circuit 1012, a current detection circuit 1022, a first voltage detection circuit 1032, a second voltage detection circuit 1042, a detection input switch selection circuit 103, a high-precision comparator 104, a shaping buffer circuit 105, and a detection output switch selection circuit 106.

[0086] The first clamping circuit 1011 provides a bias voltage VbT based on the state of the temperature lockout signal OTLock and outputs it to the temperature detection circuit 1012. The temperature detection circuit 1012 obtains a temperature detection output signal VinT based on the bias voltage VbT. The second clamping circuit 1021 provides a bias voltage VbC based on the state of the overcurrent lockout signal OCLock and outputs it to the current detection circuit 1022. The current detection circuit 1022 obtains a current detection output signal VinC based on the bias voltage VbC. The third clamping circuit 1031 provides a bias voltage VbL based on the state of the undervoltage lockout signal UVLock and outputs it to the first voltage detection circuit 1032. The first voltage detection circuit 1032 obtains an undervoltage detection output signal VinL based on the bias voltage VbL. The fourth clamping circuit 1041 provides a bias voltage VbH based on the state of the overvoltage lockout signal OVLock and outputs it to the second voltage detection circuit 1042. The second voltage detection circuit 1042 obtains an overvoltage detection output signal VinH based on the bias voltage VbH. The temperature detection output signal VinT, the current detection output signal VinC, the undervoltage detection output signal VinL, and the overvoltage detection output signal VinH simultaneously enter the detection input switch selection circuit 103. After selection by the switch selection control signal Selp, the detection signal Vind is output. The switch selection control signal Selp has four switching states: in state one, the temperature detection output signal VinT is selected and connected to the detection signal Vind; in state two, the current detection output signal VinC is selected and connected to the detection signal Vind; in state three, the undervoltage detection output signal VinL is selected and connected to the detection signal Vind; and in state four, the overvoltage detection output signal VinH is selected and connected to the detection signal Vind. The high-precision comparator 104 compares the detection signal Vind with an internal reference signal to obtain a comparison output signal Vo. The shaping buffer circuit 105 processes the comparison output signal Vo to obtain a protection signal OP and a protection lockout signal OPL. The protection signal OP and the protection lockout signal OPL simultaneously enter the detection output switch selection circuit 106.

[0087] Selected by the switch selection control signal Selp, in state one, the protection signal OP and the protection lockout signal OPL are selected and connected to the over-temperature protection signal OTP and the temperature lockout signal OTLock, respectively. In state two, the protection signal OP and the protection lockout signal OPL are selected and connected to the overcurrent protection signal OCP and the overcurrent lockout signal OCLock, respectively. In state three, the protection signal OP and the protection lockout signal OPL are selected and connected to the undervoltage protection signal UVLO and the undervoltage lockout signal UVLock, respectively. In state two, the protection signal OP and the protection lockout signal OPL are selected and connected to the overvoltage protection signal OVP and the overvoltage lockout signal OVLock, respectively.

[0088] Figure 10b The proposed solution, and Figure 10a In contrast, by using two data selector circuits, the input switch selection circuit 103 and the output switch selection circuit 106, the high-precision comparator 104 and the shaping buffer circuit 105 are multiplexed, reducing hardware overhead. The input switch selection circuit 103 and the output switch selection circuit 106 can be implemented using conventional 4-to-1 data selectors.

[0089] Figure 11 This is one embodiment of the clamping circuit used in the present invention. Figure 11 The signal identifier in the circuit uses the signal from the temperature detection section. The first clamping circuit 1011, the second clamping circuit 1021, the third clamping circuit 1031, and the fourth clamping circuit 1041 of this invention all use the same signal. Figure 11 The same clamping circuit is used. This circuit consists of PMOS transistors M111, M112, M113, and M114, and resistors R111, R112, R113, and R114. The source of PMOS transistor M111, the upper end of resistor R111, and the drain of NMOS transistor M114 are all connected to the power supply voltage VCCL; the gate of PMOS transistor M111 is connected to the gate of NMOS transistor M112 and also serves as the control signal input terminal of the clamping circuit, connected to the temperature lockout signal OTLock; the drain of PMOS transistor M111 is connected to the drain of NMOS transistor M112 and simultaneously connected to the gate of NMOS transistor M113; NMOS transistor M111... The drain of transistor 3 is connected to both the upper end of resistor R113 and the lower end of resistor R112; the upper end of resistor R112 is connected to the lower end of resistor R111 and is connected to the gate of NMOS transistor M114; the source of NMOS transistor M114 is connected to the upper end of resistor R114 and serves as the bias voltage output node of the clamping circuit; the source of NMOS transistor M112, the lower end of resistor R113, the lower end of resistor R114, and the source of NMOS transistor M113 are all connected to ground voltage VSS.

[0090] In this clamping circuit, the power supply voltage VCC is detected in real time by voltage divider resistors R111, R112, and R113. The voltage value obtained by voltage division passes through a source follower consisting of NMOS transistor M114 and resistor R114 to obtain the bias voltage VbT, which then enters the subsequent temperature detection circuit 1012. The resistance value of R113 is controlled by M113, and the on / off state of M113 is controlled by the OTLock signal. When the OTLock signal is high, the gate of M113 is low, M113 is in the off state, R113 is a large resistor, and the voltage value VbT obtained by voltage division is a relatively high bias voltage. When the OTLock signal is low, the gate of M113 is high, M113 is in the on state, R113 is shorted by M113 and becomes a very small resistor, and the voltage value VbT obtained by voltage division is a relatively low bias voltage.

[0091] Figure 12 This is one embodiment of a high-precision comparator 104. The high-precision comparator includes: PMOS transistors M121, M122, M123, M124, M125, M126, M127, M128, M129, M1210, M1211, M1212, M1213, M1214, and M1215, resistor R121, and capacitor C121.

[0092] In this configuration, the gate of PMOS transistor M121 is connected to the bias voltage; the drain of PMOS transistor M121 is connected to the drain, gate, gates of NMOS transistors M122, M123, M128, and M129; the drain of NMOS transistor M123 is connected to the drain, gate, and gate of PMOS transistors M124 and M125; the drain of PMOS transistor M125 is connected to the source of PMOS transistors M126 and M127; the gate of PMOS transistor M126 is connected to the reference voltage of high-precision comparator 104; and the gate of PMOS transistor M127 is the comparison voltage input terminal, connected to Vind; PM The drain of transistor M126 is connected to the drain of NMOS transistor M129 and the gate of NMOS transistor M1210; the drain of PMOS transistor M127 is connected to the drain of NMOS transistor M128 and the gate of NMOS transistor M1214; the drain of PMOS transistor M1211 is connected to the drain of NMOS transistor M1210 and the gate of PMOS transistor M1212; the drain of PMOS transistor M1212 is connected to the gate of PMOS transistor M1211, the drain of NMOS transistor M1214, the gate of PMOS transistor M1213, and the gate of NMOS transistor M1215; the drain of PMOS transistor M1213 is connected to the drain of NMOS transistor M1215, the upper end of resistor R121, and the upper end of capacitor C121, and serves as the signal Vo output terminal.

[0093] The sources of NMOS transistors M122, M123, M128, M129, M1210, M1214, and M1215, the lower end of resistor R121, and the lower end of capacitor C121 are all connected to ground voltage VSS; the sources of PMOS transistors M121, M124, M125, M1211, M1212, and M1213 are all connected to power supply voltage VCCL.

[0094] Figure 13 This is an embodiment of a shaping buffer circuit. Figure 13 The signal identifier in the embodiment uses the signal of the shaping buffer circuit 105. The first shaping buffer circuit 1014, the second shaping buffer circuit 1024, the third shaping buffer circuit 1034, and the fourth shaping buffer circuit 1044 of the present invention are all and Figure 13The same shaping buffer circuit. This circuit includes PMOS transistors M131, M133, M135, M136, M139, M1311, NMOS transistors M132, M134, M137, M138, M1310, and M1312, resistors R131 and R132, and capacitor C131. The circuit consists of PMOS transistors M131, M133, M132, and M134, resistors R131 and R132, and capacitor C131 forming a buffer with RC filtering. PMOS transistors M135, M136, M139, M137, M138, and M1310 form a Schmitt trigger. PMOS transistors M1311 and M1312 form an output inverter. The input of the buffer with RC filtering is connected to the comparison output voltage Vo of the high-precision comparator 104. The output of the buffer with RC filtering is connected to the input of the Schmitt trigger. The output of the Schmitt trigger is connected to the input of the output inverter and the OP signal output. The output of the output inverter outputs the temperature lockout signal OPL.

[0095] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-efficiency, compact AC-DC power controller module, including a switch output pin SW, a power supply pin VCC, a feedback voltage signal pin FB, and a ground voltage pin VSS, characterized in that... The module includes a first packaging substrate (31) and a second packaging substrate (32). A high-voltage power MOSFET transistor (301) is soldered on the first packaging substrate (31), and an AC-DC control chip (302) is soldered on the second packaging substrate (32). The drain of the high-voltage power MOSFET transistor (301) is connected to the switch output pin SW of the module, the gate of the high-voltage power MOSFET transistor (301) is connected to the gate drive pin VO of the AC-DC control chip (302), and the source of the high-voltage power MOSFET transistor (301) is connected to the output current signal pin CS of the AC-DC control chip (302). The high-voltage power supply pin of the AC-DC control chip (302) is connected to the power supply pin VCC of the module, the feedback voltage signal pin of the AC-DC control chip (302) is connected to the feedback voltage signal pin FB of the module, and the ground voltage pin of the AC-DC control chip (302) is connected to the ground voltage pin VSS of the module. The AC-DC control chip (302) includes: a current detection resistor Rcs, a feedback voltage detection circuit (1), a primary peak current detection module (2), a feedback current detection circuit (3), a voltage and current hybrid detection circuit (4), a reference voltage generation circuit (5), a first voltage discrimination circuit (6), a second voltage discrimination circuit (7), a current comprehensive compensation circuit (9), a comprehensive comparator (10), an overall function control circuit (11), an output drive module (12), and a protection circuit (13). The current sensing resistor Rcs is connected between the output current signal pin CS of the switching power supply and the ground voltage pin VSS; the feedback voltage detection circuit (1) is used to detect the feedback voltage FB output by the switching power supply and generate a detection signal Vf; the primary-side peak current detection module (2) is used to detect the output current signal CS of the switching power supply and generate a detection signal LEB, which is connected to the feedback current detection circuit (3) and the voltage-current hybrid detection circuit (4) respectively; the feedback current detection circuit (3) is used to process the detection signal LEB and generate a detection signal Vcs2; the input terminal of the voltage-current hybrid detection circuit (4) is connected to the feedback voltage FB, the detection signal LEB, and the detection signal Vcs2 output by the switching power supply, and is used for The feedback voltage FB and the detection signal LEB are processed and combined with the detection signal Vcs2 to generate the detection signal Vcs1; the input terminal of the first voltage discrimination circuit (6) is connected to the detection signal Vcs1 and the compensation reference voltage Vrc fed back by the current comprehensive compensation circuit (9), and is used to compare the detection signal Vcs1 and the compensation reference voltage Vrc to obtain the compensation signal Vc1; the input terminal of the second voltage discrimination circuit (7) is connected to the feedback voltage FB output by the switching power supply and the compensation reference voltage Vrc fed back by the current comprehensive compensation circuit (9), and the feedback voltage FB and the compensation reference voltage Vrc are compared to obtain the compensation signal Vc2; the input terminal of the current comprehensive compensation circuit (9) is connected to the compensation signal Vc1 and the compensation signal Vc2. The reference voltage Vadj1, under the control of the control signal Ctr4, compensates the compensation signals Vc1, Vc2, Vref, and Vadj1 to obtain the current compensation signal Vcom; the input of the comprehensive comparator (10) is connected to the current compensation signal Vcom and the reference voltage Vadj2, and the current compensation signal Vcom and the reference voltage Vadj2 are compared to obtain the compensation output signal Dcom; the input of the overall function control circuit (11) is connected to the compensation output signal Dcom, the detection signal Vf, the detection signal Vcs2, the undervoltage protection signal UVLO, the overvoltage protection signal OVP, the overtemperature protection signal OTP, and the overcurrent protection signal OCP, and the overall function control Circuit (11) generates control signals Ctr1~Ctr5 to control the working states of feedback voltage detection circuit (1), feedback current detection circuit (3), voltage and current mixed detection circuit (4), current comprehensive compensation circuit (9) and comprehensive comparator (10), respectively. Based on the detection signal Vf, detection signal Vcs2, compensation output signal Dcom, undervoltage protection signal UVLO, overvoltage protection signal OVP, overtemperature protection signal OTP and overcurrent protection signal OCP, it comprehensively processes and generates pulse drive signal Vin, which is output to output drive module (12). The output drive module (12) is used to amplify the pulse drive signal Vin in terms of current and voltage, and output gate drive signal VO with high current drive capability.The protection circuit (13) includes an undervoltage protection circuit, an overvoltage protection circuit, an overtemperature protection circuit, and an overcurrent protection circuit, which respectively generate an undervoltage protection signal UVLO, an overvoltage protection signal OVP, an overtemperature protection signal OTP, and an overcurrent protection signal OCP; the input terminal of the reference voltage generation circuit (5) is connected to an external high-voltage power supply to generate adjustable reference voltages Vadj1 and Vadj2, and also generates the on-chip low-voltage power supply and reference signal required for the operation of all the above circuits.

2. The high-efficiency, small-size AC-DC power controller module according to claim 1, characterized in that, When the source of the high-voltage power MOSFET transistor (301) is located on the reverse side of the chip, the source of the high-voltage power MOSFET transistor (301) is connected to the first package substrate (31) through solder. The first package substrate (31) is connected to the output current signal pin CS of the AC-DC control chip (302) through a lead. That is, the source of the high-voltage power MOSFET transistor (301) is indirectly connected to the output current signal pin CS of the AC-DC control chip (302) through the first package substrate (31) with good conductivity.

3. The high-efficiency, small-size AC-DC power controller module according to claim 1, characterized in that, The high-voltage power MOSFET transistor (301) is implemented using a single chip or multiple chips connected in parallel. When the high-voltage power MOSFET transistor (301) is implemented using multiple chips connected in parallel, a conductive substrate is required for parallel connection. The gate of each MOSFET transistor chip is connected to a common conductive substrate and then connected to the gate drive pin VO of the AC-DC control chip (302) via the conductive substrate. The source of each MOSFET transistor chip is connected to a common conductive substrate and then connected to the output current signal pin CS of the AC-DC control chip (302) via the conductive substrate. Alternatively, the source of each MOSFET transistor chip can be connected to the first package substrate (31) via solder, and the first package substrate (31) can be connected to the output current signal pin CS of the AC-DC control chip (302) via a lead.

4. The high-efficiency, small-size AC-DC power controller module according to claim 1, characterized in that: After the AC-DC control chip (302) is powered on, the reference voltage generation circuit (5) and the overall function control circuit (11) work first. Then, the overall function control circuit (11) outputs control signals Ctr1~Ctr5 in sequence. The order of outputting control signals Ctr1~Ctr5 is as follows: First, control signals Ctr3, Ctr4 and Ctr5 are output simultaneously to control the voltage and current mixed detection circuit (4), current comprehensive compensation circuit (9) and comprehensive comparator (10) to start working, so that the feedback voltage FB and the detection signal LEB form a simple control loop, and output the pulse drive signal Vin to make the drive signal VO output an initial output voltage. Then, output control signals Ctr1 and Ctr2 to control the feedback voltage detection circuit (1) and feedback current detection circuit (3) to start working respectively; at this time, all control loops of the overall AC-DC power controller are opened, and the chip forms a multi-loop control mode.

5. The high-efficiency, small-size AC-DC power controller module according to claim 1, characterized in that, The overall function control circuit (11) includes: a clock generation circuit (90), a first digital filter (91), a second digital filter (92), error handling logic (93), a counter group (94), a discrimination control logic (95), and a register group (96); the high-frequency clock Clk generated by the clock generation circuit (90) is simultaneously input to the first digital filter (91), the second digital filter (92), the counter group (94), and the discrimination control logic (95); the first digital filter (91) filters the detection signal Vf under the control of the high-frequency clock Clk to obtain compensation data Dc1; the second digital filter (92) filters the detection signal Vcs2 under the control of the high-frequency clock Clk to obtain compensation data Dc2; The error handling logic (93) generates an error signal Err based on the undervoltage protection signal UVLO, the overvoltage protection signal OVP, the overtemperature protection signal OTP, and the overcurrent protection signal OCP; the counter group (94) selects the count output Count based on the count selection signal Sel output by the discrimination control logic (95), and outputs the count output Count to the discrimination control logic (95); the input terminals of the discrimination control logic (95) are respectively connected to the above-mentioned compensation data Dc1, compensation data Dc2, error signal Err, count output Count, and compensation output signal Dcom, and perform logical operations according to the status of each signal, first generating a status control signal Set output to the register group (96), and then comprehensively processing to generate a pulse drive signal Vin; After the circuit is powered on, the clock generation circuit (90) and the error handling logic (93) start working. After the clock generation circuit (90) works normally, it outputs a high-frequency clock Clk. Then, the discrimination control logic (95) first generates the first state control signal Set and outputs it to the register group (96). The register group (96) outputs control signals Ctr3, Ctr4 and Ctr5 according to the first state control signal Set, and sets the pulse drive signal Vin to a square wave pulse of a fixed frequency. Then, after a delay time td1, when the compensation output signal Dcom changes from the initial state to a pulse signal, the discrimination control logic (95) will unlock the pulse drive signal Vin and make it controlled by the compensation output signal Dcom. Then, after a delay time td2, the discrimination control logic (95) generates the second state control signal Set and outputs it to the register group (96). The register group (96) outputs control signals Ctr1 and Ctr2 according to the second state control signal Set and opens the remaining control loops. The aforementioned discrimination control logic (95) changes the delay time td1 and delay time td2 based on the state control signal Set. The discrimination control logic (95) provides different count selection signals Sel to the counter group (94) in sequence, and then the counter group (94) generates different count outputs Count for control.

6. The high-efficiency, small-size AC-DC power controller module according to claim 1, characterized in that, The current compensation circuit (9) includes: PMOS transistors M401, M402, M404, M405, M406, M407, M408, M409, M410, M411, M412, M413, M414, M415, M416, M417, M418, M419, M420, M421, M422, M423, M424, and NMOS transistors. MOSFETs M425, M426, M427, M428, and M429; resistors R41, R42, R43, R44, R45, and R46; capacitors C41, C42, C43, and C44; PMOS transistors M430, M431, M432, M433, M434, M435, M436, M437, M438, M439, M440, and M441; resistors R47 and R48; and capacitor C45. The circuit comprises PMOS transistors M401, M402, and M404, resistors R41 and R42, NMOS transistors M413, M414, M419, M420, M428, and M429, and capacitors C41 and C42, forming a compensation signal adjustment circuit. The drain of PMOS transistor M401 is connected to the gates of PMOS transistors M401, M402, and M404, and the lower end of capacitor C41, serving as the input terminal for the bias input signal IbC41. The drain of PMOS transistor M402 is connected to the drains and gates of NMOS transistors M419, M419, M420, and M429. The drain of PMOS transistor M404 is connected to the drains of NMOS transistors M420, M413, and M414. The drain of NMOS transistor M428 and the left end of resistor R44 serve as the output terminal of the compensation reference voltage Vrc; the drain of NMOS transistor M413 is connected to the lower end of resistor R41, and the gate of NMOS transistor M413 is connected to the compensation signal Vc1; the drain of NMOS transistor M414 is connected to the lower end of resistor R42, and the gate of NMOS transistor M414 is connected to the compensation signal Vc2; the sources of PMOS transistors M401, M402, and M404, the upper end of capacitor C41, the upper end of resistor R41, and the upper end of resistor R42 are all connected to the power supply voltage VCCL; the sources of NMOS transistors M419, M420, M428, and M429, and the lower end of capacitor C42 are all connected to the ground voltage VSS; capacitors C41 and C42 are filter capacitors, and NMOS transistors M429 and M428 are reset transistors controlled by the reset signal S1; PMOS transistors M405, M406, M409, M410, M415, and M416, along with resistors R43, R44, and R45, and NMOS transistors M421, M422, M426, and M427, constitute a compensation signal amplification circuit. PMOS transistors M405, M406, M409, and M410, along with resistor R43, form a self-biased cascode mirror current source circuit. The lower end of resistor R43 serves as the input terminal for the bias input signal Ibc42, and is also connected to the gates of PMOS transistors M409, M410, M411, and M412. The upper end of resistor R43 is connected to the drain of PMOS transistor M409, the gate of PMOS transistor M405, and the gate of PMOS transistor M406. The source of PMOS transistor M409 is connected to the drain of PMOS transistor M405, and the drain of PMOS transistor M406 is connected to the source of PMOS transistor M410. PMOS transistors M406 and M41... 0 forms a common-source, common-gate current source. The drain of PMOS transistor M410 is connected to the source of PMOS transistors M415 and M416. The gate of PMOS transistor M415 is connected to the right end of resistor R44 and the lower end of resistor R46. The gate of PMOS transistor M416 is connected to the left end of resistor R45. The right end of R45 is connected to the modulation reference signal Vadj1 of the current compensation circuit (9). The drain of PMOS transistor M415 is connected to the drain of NMOS transistor 421, the gate of NMOS transistor 421, the gate of NMOS transistor M423, and the drain of NMOS transistor M427. The drain of PMOS transistor M416 is connected to the drain, gate, gate, and drain of NMOS transistors M422, M424, and M426. NMOS transistors M427 and M426 are reset transistors controlled by the reset signal S1. The sources of PMOS transistors M405 and M406 are connected to the power supply voltage VCCL. The sources of NMOS transistors M421, M422, M426, and M427 are connected to the ground voltage VSS. The compensation output circuit consists of PMOS transistors M407, M408, M411, and M412, NMOS transistors M417, M418, M423, M424, and M425, capacitors C43 and C44, and resistor R46. PMOS transistors M407, M408, M411, and M412 form... In the common-source cascode current mirror circuit, the gate of PMOS transistor M407 is connected to the gate of PMOS transistor M408, the drain of PMOS transistor M411, and the drain of PMOS transistor M417. The drain of PMOS transistor M407 is connected to the source of PMOS transistor M411, and the drain of PMOS transistor M408 is connected to the source of PMOS transistor M412. The drains of PMOS transistors M411 and M412 are the output terminals of the common-source cascode current mirror circuit. The drain of transistor 11 is connected to the drain of NMOS transistor M417. The gate of NMOS transistor M417 is connected to the bias voltage Vbc41. The drain of PMOS transistor M412 is connected to the drain of NMOS transistor M418, the gate of NMOS transistor M418, the drain of NMOS transistor M424, the drain of NMOS transistor M425, the upper end of capacitor C43, and the upper end of capacitor C44, serving as the output terminal of the current compensation signal Vcom. The lower end of capacitor C43 is connected to the upper end of resistor R46. NMOS transistor... The source of M417 is connected to the drain of NMOS transistor M423 and the source of NMOS transistor M418; NMOS transistor M425 is a reset transistor controlled by reset signal S1, and capacitor C44 is a filter capacitor; the sources of PMOS transistors M407 and M408 are both connected to the power supply voltage VCCL; the sources of NMOS transistors M423, M424, and M425, as well as the lower end of capacitor C44, are all connected to the ground voltage VSS. The remaining circuitry forms a unity-gain buffer, including: the gate of PMOS transistor M430 connected to the reference voltage Vref; the gates of PMOS transistors M431, M432, and M433 connected to the bias voltage Vbc43; the gate of NMOS transistor M441 connected to the bias voltage Vbc44; the drain of PMOS transistor M430 connected to the upper end of resistor R47 and the gate of PMOS transistor M435; the drain of PMOS transistor M431 connected to the source of PMOS transistor M435 and the source of PMOS transistor M436; the drain of PMOS transistor M435 connected to the drain of NMOS transistor M438, the gate of NMOS transistor M438, and the gate of NMOS transistor M439; and PMOS transistor M436... The drain of PMOS transistor M432 is connected to the drain of NMOS transistor M439, the gate of NMOS transistor M440, and the upper end of resistor R48. The lower end of resistor R48 is connected to the upper end of capacitor C45. The drain of PMOS transistor M432 is connected to the drain of NMOS transistor M440 and to the source of NMOS transistor M437. The drain of PMOS transistor M433 is connected to the gate of NMOS transistor M437, the drain of NMOS transistor M437, and the gate of NMOS transistor M434. The source of NMOS transistor M434 is connected to the drain of NMOS transistor M441 and the gate of PMOS transistor M436, and serves as the output terminal of the current compensation signal Vcom. It is also fed back to the upper end of capacitor C43 and the drain of NMOS transistor M424. The source of PMOS transistor M430 and the drain of PMOS transistor M434 are connected to the drain of NMOS transistor M439, the gate of NMOS transistor M440, and the gate of PMOS transistor M434. The sources of transistors M431, M432, and M433, and the drain of NMOS transistor M434 are simultaneously connected to the power supply voltage VCCL; the sources of NMOS transistors M438, M439, M440, and M441, the lower end of resistor R47, and the lower end of capacitor C45 are simultaneously connected to the ground voltage VSS; among them, PMOS transistors M431, M432, M435, and M436, and NMOS transistors M438, M439, and M440 form a two-stage operational amplifier, and NMOS transistors M434 and M441 form a source follower. The bias signal of MOS transistor M434 requires a high voltage, so the output of the two-stage operational amplifier is connected to a level shift circuit composed of PMOS transistor M433 and NMOS transistor M437, and then output to the gate of NMOS transistor M434; the output of the source follower composed of NMOS transistor M434 and NMOS transistor M441 is the current compensation signal Vcom output of the current compensation circuit (9), which is reconnected to the input of the two-stage operational amplifier, so that the overall circuit constitutes a unity-gain buffer; the reference voltage Vref passes through PMOS transistor M430 and resistor R47 to form an input bias circuit, and the bias signal of the input bias circuit is output to the gate of PMOS transistor M435.

7. The high-efficiency, small-size AC-DC power controller module according to claim 1, characterized in that, The voltage and current mixed detection circuit (4) includes: a unity-gain amplifier (80), a voltage divider circuit (81), a variable-gain operational amplifier (82), and a non-inverting adder operational amplifier circuit (83). The unity-gain amplifier (80) isolates and buffers the feedback voltage FB signal to output a voltage signal Vf_in, which is connected to the non-inverting adder operational amplifier circuit (83). The voltage divider circuit (81) converts the signal LEB from current to voltage and outputs a voltage Vc_det, which is connected to the variable-gain operational amplifier (82). The variable-gain operational amplifier (82) converts and amplifies the voltage signal Vc_in, which is then connected to the non-inverting adder operational amplifier circuit (83). The non-inverting adder operational amplifier circuit (83) sums the voltage signals Vf_in and Vc_in and outputs the final detection signal Vcs1.

8. The high-efficiency, small-size AC-DC power controller module according to claim 1, characterized in that, The protection circuit (13) includes: the input terminal of the temperature detection circuit (1012) is connected to the first clamping circuit (1011) to form a temperature detection branch; the input terminal of the current detection circuit (1022) is connected to the second clamping circuit (1021) to form a current detection branch; the input terminal of the first voltage detection circuit (1032) is connected to the third clamping circuit (1031) to form an undervoltage detection branch; and the input terminal of the second voltage detection circuit (1042) is connected to the fourth clamping circuit (1041) to form an overvoltage detection branch. The output terminals of the temperature detection circuit (1012), the current detection circuit (1022), the first voltage detection circuit (1032), and the second voltage detection circuit (1042) are all connected to the detection input switch selection circuit (103). The output terminal of the detection input switch selection circuit (103) is sequentially connected to a high-precision... The circuit includes a comparator (104), a shaping buffer circuit (105), and a detection output switch selection circuit (106). The detection output switch selection circuit (106) outputs an over-temperature protection signal OTP, a temperature lockout signal OTLock, an overcurrent protection signal OCP, an overcurrent lockout signal OCLock, an undervoltage protection signal UVLO, an undervoltage lockout signal UVLock, an overvoltage protection signal OVP, and an overvoltage lockout signal OVLock. The temperature lockout signal OTLock is connected to the input of the first clamping circuit (1011), the overcurrent lockout signal OCLock is connected to the input of the second clamping circuit (1021), the undervoltage lockout signal UVLock is connected to the input of the third clamping circuit (1031), and the overvoltage lockout signal OVLock is connected to the input of the fourth clamping circuit (1041). The first clamping circuit (1011) provides a bias voltage VbT based on the state of the temperature lockout signal OTLock and outputs it to the temperature detection circuit (1012). The temperature detection circuit (1012) obtains the temperature detection output signal VinT based on the bias voltage VbT. The second clamping circuit (1021) provides a bias voltage VbC based on the state of the overcurrent lockout signal OCLock and outputs it to the current detection circuit (1022). The current detection circuit (1022) obtains the current detection output signal VinC based on the bias voltage VbC. The third... The clamping circuit (1031) provides a bias voltage VbL based on the state of the undervoltage lockout signal UVLock and outputs it to the first voltage detection circuit (1032). The first voltage detection circuit (1032) obtains the undervoltage detection output signal VinL based on the bias voltage VbL. The fourth clamping circuit (1041) provides a bias voltage VbH based on the state of the overvoltage lockout signal OVLock and outputs it to the second voltage detection circuit (1042). The second voltage detection circuit (1042) obtains the overvoltage detection output signal VinH based on the bias voltage VbH. The temperature detection output signal VinT, the current detection output signal VinC, the undervoltage detection output signal VinL, and the overvoltage detection output signal VinH simultaneously enter the detection input switch selection circuit (103), and are selected by the switch selection control signal Selp to output the detection signal Vind. The switch selection control signal Selp has four switching states: in state one, the temperature detection output signal VinT is selected and connected to the detection signal Vind; in state two, the current detection output signal VinC is selected and connected to the detection signal Vind; in state three, the undervoltage detection output signal VinL is selected and connected to the detection signal Vind; and in state four, the overvoltage detection output signal VinH is selected and connected to the detection signal Vind. The high-precision comparator (104) will detect... The measured signal Vind is compared with the internal reference signal to obtain the comparison output signal Vo; the shaping buffer circuit (105) processes the comparison output signal Vo to obtain the protection signal OP and the protection lockout signal OPL, and connects them to the input terminal of the detection output switch selection circuit (106); after selection by the switch selection control signal Selp, in state one, the protection signal OP and the protection lockout signal OPL are selected and connected to the over-temperature protection signal OTP and the temperature lockout signal OTLock respectively; in state two, they are selected and connected to the over-current protection signal OCP and the over-current lockout signal OCLock respectively; in state three, they are selected and connected to the under-voltage protection signal UVLO and the under-voltage lockout signal UVLock respectively; in state four, they are selected and connected to the over-voltage protection signal OVP and the over-voltage lockout signal OVLock respectively.

9. The high-efficiency, small-size AC-DC power controller module according to claim 8, characterized in that, The high-precision comparator (104) includes: PMOS transistors M121, M122, M123, M124, M125, M126, M127, M128, M129, M1210, M1211, M1212, M1213, M1214, and M1215, resistor R121, and capacitor C121; wherein, the gate of PMOS transistor M121 is connected to a bias voltage, and PMOS transistor M121... The drain of NMOS transistor M122 is connected to the drain and gate of NMOS transistor M122, the gate of NMOS transistor M123, the gate of NMOS transistor M128, and the gate of NMOS transistor M129; the drain of NMOS transistor M123 is connected to the drain and gate of PMOS transistor M124, the gate of PMOS transistor M124, and the gate of PMOS transistor M125; the drain of PMOS transistor M125 is connected to the source of PMOS transistor M126 and the source of PMOS transistor M127; the gate of PMOS transistor M126 is connected to the reference voltage of the high-precision comparator (104); the gate of PMOS transistor M127 is the comparison voltage input terminal and is connected to Vind; PMOS transistor M126... The drain of PMOS transistor M127 is connected to the drain of NMOS transistor M129 and the gate of NMOS transistor M1210; the drain of PMOS transistor M127 is connected to the drain of NMOS transistor M128 and the gate of NMOS transistor M1214; the drain of PMOS transistor M1211 is connected to the drain of NMOS transistor M1210 and the gate of PMOS transistor M1212; the drain of PMOS transistor M1212 is connected to the gate of PMOS transistor M1211, the drain of NMOS transistor M1214, the gate of PMOS transistor M1213, and the gate of NMOS transistor M1215; the drain of PMOS transistor M1213 is connected to the drain of NMOS transistor M1215, the upper end of resistor R121, and capacitor C12.

1. The upper end serves as the signal Vo output terminal; the sources of NMOS transistors M122, M123, M128, M129, M1210, M1214, and M1215, the lower end of resistor R121, and the lower end of capacitor C121 are all connected to ground voltage VSS; the sources of PMOS transistors M121, M124, M125, M1211, M1212, and M1213 are all connected to power supply voltage VCCL.

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