Delay circuit, module, chip and delay method suitable for low-power chip

Abstract

The present invention relates to a delay circuit, module, chip and delay method suitable for low-power chips. The delay circuit comprises: a buffer, N cascaded delay units, N leakage units and N load capacitors. The delay unit comprises a PMOS tube PM1 and an NMOS tube NM1, and the leakage unit comprises a PMOS tube PM5. The gate of PM1 is connected to the gate of NM1 and serves as the input end of the delay unit, the source of PM1 is connected to the gate of PM5, the source of NM1, the lower plate of the load capacitor and the drain of PM5 are connected, the drain of PM1, the drain of NM1, the source of PM5 and the upper plate of the load capacitor are connected as the output end of the delay unit, and the input end of the buffer is connected to the output end of the delay unit at the final stage. When the voltage source is powered on or off, the present invention adaptively discharges the excess charge in time through the leakage unit, thereby ensuring the correct delay function and delay size.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a delay circuit suitable for a low-power chip, a delay integrated module suitable for a low-power chip, a low-power delay chip, and a delay method suitable for a low-power chip. Background Art

[0002] Emerging application scenarios such as wearable devices and implantable medical devices are gradually coming into people's view. The battery capacity of these devices is often limited by their size, and replacing batteries may cause high costs or inconveniences. Therefore, strict low-power consumption requirements are placed on chips.

[0003] The limitation of low power consumption often causes the voltage regulator that provides power inside the chip to take a long time to stabilize. In order for the system to enter normal working state after the power supply stabilizes, the reset output of the power-on reset module must be given after the voltage regulator outputs a stable power supply voltage. Therefore, a longer delay module is required and the power consumption of this module is low enough.

[0004] Traditional long delay circuits are generally obtained by cascading multiple delay unit circuits, and delay units have multiple implementation forms, typical representatives of which are "active delay circuit-inverter" and "passive delay circuit-resistor and capacitor".

[0005] When a traditional long delay circuit encounters a situation where its power supply voltage is continuously powered on or off in a short period of time, the large capacitor inside it will cause the change in the power supply voltage to couple. The coupled charge cannot be cleared in time, resulting in a significant reduction in delay, or even the delay circuit losing its delay function, thus failing to meet the long delay requirements of low-power chips. Summary of the invention

[0006] Based on this, it is necessary to provide a delay circuit, module, chip and delay method suitable for low-power chips to address the problem of unstable delay function of the delay circuit.

[0007] A delay circuit suitable for a low-power chip comprises: a buffer, N cascaded delay units, N leakage units corresponding to the multiple delay units one-to-one, and N load capacitors corresponding to the multiple delay units one-to-one.

[0008] Each delay unit includes a PMOS transistor PM1 and an NMOS transistor NM1. The gate of PM1 is electrically connected to the gate of NM1 and serves as the input of the corresponding delay unit, the source of PM1 is electrically connected to the voltage source VDDH, the source of NM1 is electrically connected to the voltage source AVSS, and the drain of PM1 is electrically connected to the drain of NM1 and serves as the output of the corresponding delay unit. Since multiple delay units are cascaded, the input of the delay unit at the starting end serves as the input IN of the entire delay circuit.

[0009] Each leakage unit includes a PMOS transistor PM5. The gate of PM5 is electrically connected to the source of PM1, the drain of PM5 is electrically connected to the voltage source AVSS, and the source of PM5 is electrically connected to the drains of PM1 and NM1 and serves as the output end of the corresponding delay unit.

[0010] The upper plate of each load capacitor CAP1 is connected to the output end of the corresponding delay unit, and the lower plate is connected to the voltage source AVSS.

[0011] The input end of the buffer is connected to the output end of the delay unit at the end, the power end of the buffer is connected to the voltage source VDDH, the ground end of the buffer is electrically connected to the voltage source AVSS, and the output end of the buffer serves as the output end OUT of the entire delay circuit.

[0012] The delay circuit of the present invention adds a leakage unit controlled by a voltage source at the output node of each delay unit, and its function is to increase the discharge path of the charge on the large capacitor. When the voltage source is powered on or off, the large capacitor at the output node of the delay unit will couple the change of the voltage source, thereby inducing excess charge, and the leakage unit can adaptively and timely discharge the excess charge, thereby ensuring the correct delay function and delay size.

[0013] In one of the embodiments, the working process of the delay circuit includes: when the power supply voltage is at the power-on or power-off edge, the leakage unit starts to work and automatically clears the residual charge coupled on the capacitors of each node in the circuit; when the power supply voltage is stable, the initial state of the delay circuit is that there is no residual charge on the capacitors of the output nodes of each delay unit, ensuring the normal operation of the delay circuit and the correct delay duration.

[0014] In one embodiment, the delay unit includes an RC active device or an RC passive device. The RC active device includes an inverter.

[0015] In one embodiment, the leakage unit includes any one of a PMOS tube, an NMOS tube, a CMOS tube and a TFET tube.

[0016] In one embodiment, the leakage unit is controlled by a power supply voltage VDDH, and the leakage unit is used to form a discharge path in the delay circuit.

[0017] The present invention also provides a delay module suitable for a low-power chip, which internally adopts the circuit layout of the delay circuit suitable for a low-power chip. The delay module includes: an input interface, an output interface, a power interface and a ground interface. The input interface is electrically connected to the input terminal IN of the delay circuit. The output interface is electrically connected to the output terminal OUT of the delay circuit. The power interface is connected to the power terminal of the buffer, and the power interface is used to connect the voltage source VDDH. The ground interface is connected to the ground terminal of the buffer, and the ground interface is used to electrically connect the voltage source AVSS.

[0018] The present invention also provides a low-power delay chip. The delay chip is packaged by a delay circuit. The delay chip includes an input pin, an output pin, a power pin and a ground pin. The input pin is electrically connected to the input terminal IN of the delay circuit. The output pin is electrically connected to the output terminal OUT of the delay circuit. The power pin is connected to the power terminal of the buffer, and the power pin is used to connect the voltage source VDDH. The ground pin is connected to the ground terminal of the buffer, and the ground pin is used to electrically connect the voltage source AVSS.

[0019] The present invention also provides a delay method suitable for a low-power chip, which comprises the following steps:

[0020] Phase 1: When the voltage source VDDH is at a high level power-on edge, and the input signal received by the delay circuit is a rising signal, the leakage unit works to discharge the excess charge coupled to the node load capacitor CAP1 during the power-on process. When the voltage source VDDH is stable, the leakage unit is turned off and the delay unit starts working. The voltage of each output node is delayed by RC and accumulated, and the voltage output by the delay unit at the end is shaped by the buffer and reaches the output node OUT, which finally delays the output signal for a long time.

[0021] Phase 2: In the state of phase 1, after the circuit works for a preset cycle, the voltage source VDDH drops to a low level. At this time, the delay unit does not work, and the leakage unit starts to work. All load capacitors CAP1 in the circuit begin to discharge and clear the charge, and the speed of discharging and clearing the charge is fast and clean.

[0022] Phase 3: After the end of phase 2, when the power supply voltage is powered up again to a high level, the input signal is a rising signal. Return to phase 1. Since the load capacitor CAP1 has been cleared of charge in phase 2, the signal output by the output node OUT can still maintain a long delay time.

[0023] The technical solution provided by the present invention has the following beneficial effects:

[0024] 1. The delay circuit of the present invention adds a leakage unit controlled by a voltage source at the output node of each delay unit, and its function is to increase the discharge path for the charge on the large capacitor. When the voltage source is powered on or off, the large capacitor at the output node of the delay unit will couple the change of the voltage source, thereby inducing excess charge, and the leakage unit can adaptively and timely discharge the excess charge, thereby ensuring the correct delay function and delay size.

[0025] 2. The delay circuit of the present invention can provide a sufficiently long delay in the scenario where the voltage source is continuously powered on and off in a short period of time, ensuring that the output of the power-on reset module is given after the voltage regulator outputs a stable power supply voltage, thereby ensuring the normal operation of the low-power chip.

[0026] 3. The delay circuit of the present invention also has the advantage that the leakage unit only discharges the residual charge to the node capacitance, and does not directly increase the path of the voltage source to the ground, that is, it does not increase the extra power consumption, thus ensuring the low power consumption requirement of the low power consumption chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic diagram of a delay circuit according to Embodiment 1 of the present invention;

[0028] Figure 2 for Figure 1 The circuit diagram of the delay circuit having 4 delay units;

[0029] Figure 3 for Figure 2 The unit structure diagram of the medium delay circuit;

[0030] Figure 4 for Figure 2 Working waveform of the medium delay unit;

[0031] Figure 5 for Figure 2 Schematic diagram of the structure in which the medium delay circuit is encapsulated into a delay chip. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component at the same time. When a component is considered to be "fixed to" another component, it may be directly fixed on the other component or there may be a central component at the same time.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "or / and" used herein includes any and all combinations of one or more of the related listed items.

[0035] See also Figure 1 , Figure 1 : is a schematic diagram of the delay circuit of this embodiment. The delay circuit includes: a buffer, N cascaded delay units, N leakage units corresponding to the delay units one by one, and N load capacitors corresponding to the delay units one by one.

[0036] Each delay unit includes a PMOS tube PM1 and an NMOS tube NM1. The gate of PM1 is connected to the gate of NM1 and serves as the input of the corresponding delay unit, the source of PM1 is connected to the voltage source VDDH, the source of NM1 is connected to the voltage source AVSS, and the drain of PM1 is connected to the drain of NM1 as the output of the corresponding delay unit. Since multiple delay units are cascaded, the input of the delay unit at the starting end serves as the input IN of the entire delay circuit. The delay unit can be composed of RC active devices, such as inverters, or RC passive devices. In the present embodiment, the delay unit is composed of a combination of a PMOS tube and an NMOS tube. Of course, in other embodiments, the delay unit can also be composed of an inverter or a combination of two PMOS tubes or two NMOS tubes.

[0037] Each leakage unit includes a PMOS tube PM5. The gate of PM5 is connected to the source of PM1, the drain of PM5 is connected to the voltage source AVSS, and the source of PM5 is electrically connected to the output end of the corresponding delay unit. The leakage unit is controlled by the power supply voltage VDDH, and the leakage unit is used to form a discharge path in the delay circuit. The leakage unit can be composed of a PMOS tube, or an NMOS tube, a CMOS tube or a TFET tube, as long as it has the function of discharging charge. The components used in the leakage unit can be silicon material transistors or germanium material transistors.

[0038] The upper plate of each load capacitor CAP1 is electrically connected to the output end of the corresponding delay unit, and the lower plate is electrically connected to the source of the corresponding NMOS transistor NM1.

[0039] The input end of the buffer is electrically connected to the output end of the delay unit at the end, the power end of the buffer is electrically connected to the voltage source VDDH, the ground end of the buffer is electrically connected to the voltage source AVSS, and the output end of the buffer serves as the output end OUT of the entire delay circuit. The buffer can shape the delayed signal transmitted by the delay circuit.

[0040] Please combine Figure 2 and Figure 3 , Figure 2 for Figure 1 The structural diagram of the delay circuit with 4 delay units; Figure 3 for Figure 2 Unit structure diagram of the delay circuit. In this embodiment, the number of delay units is 4 for example, and the number of leakage units and load capacitors is also 4. Of course, in other embodiments, the number of delay units can be more or less, and the delay time of multiple delay units is superimposed. According to the delay requirements, a delay circuit composed of different numbers of delay units cascaded is selected to meet the delay requirements of different time lengths.

[0041] In the delay circuit composed of four delay units cascaded, the first-stage delay unit includes a PMOS tube PM1 and an NMOS tube NM1. The second-stage delay unit includes a PMOS tube PM2 and an NMOS tube NM2. The third-stage delay unit includes a PMOS tube PM3 and an NMOS tube NM3. The fourth-stage delay unit includes a PMOS tube PM4 and an NMOS tube NM4. The first-stage leakage unit includes a PMOS tube PM5. The second-stage leakage unit includes a PMOS tube PM6. The third-stage leakage unit includes a PMOS tube PM7. The fourth-stage leakage unit includes a PMOS tube PM8. The first-stage load capacitor is a capacitor CAP1. The second-stage load capacitor is a capacitor CAP2. The third-stage load capacitor is a capacitor CAP3. The fourth-stage load capacitor is a capacitor CAP4.

[0042] The gate of PM1 and the gate of NM1 are electrically connected and serve as the input terminal IN of the entire delay circuit. The source of PM1, the gate of PM5, the source of PM2, the gate of PM6, the source of PM3, the gate of PM7, the source of PM4, the gate of PM8 and the power supply terminal of the buffer are connected to the voltage source VDDH. The source of NM1, the drain of PM5, the lower plate of CAP1, the source of NM2, the drain of PM6, the lower plate of CAP2, the source of NM3, the drain of PM7, the lower plate of CAP3, the source of NM4, the drain of PM8, the lower plate of CAP4 and the ground terminal of the buffer are connected to the voltage source AVSS. The source of PM8 and the upper plate of CAP4 are connected to the input terminal of the buffer. The output terminal of the buffer serves as the output terminal OUT of the entire delay circuit.

[0043] The working process of the delay circuit includes the following stages:

[0044] Phase 1: When the voltage source VDDH is at a high level power-on edge, and the input signal received by the delay circuit is a rising signal, the leakage unit works to discharge the excess charge coupled to the node load capacitor CAP1 during the power-on process. When the voltage source VDDH is stable, the leakage unit is turned off and the delay unit starts working. The voltage of each output node is delayed by RC and accumulated, and the voltage output by the delay unit at the end is shaped by the buffer and reaches the output node OUT, which finally delays the output signal for a long time.

[0045] Phase 2: In the state of phase 1, after the circuit works for a preset cycle, the voltage source VDDH drops to a low level. At this time, the delay unit does not work, and the leakage unit starts to work. All load capacitors CAP1 in the circuit begin to discharge and clear the charge, and the speed of discharging and clearing the charge is fast and clean.

[0046] Phase 3: After the end of phase 2, the power supply voltage is powered up again to a high level. At this time, the input signal is a rising signal; return to phase 1. Since the load capacitor CAP1 has been cleared of charge in phase 2, the signal output by the output node OUT can still maintain a long delay time.

[0047] Please combine Figure 3 , which is Figure 2 The working waveform of the delay unit. For ease of viewing, the time interval of each stage on the waveform is relatively long, but it is actually shorter. The waveform diagram intuitively shows the working process described above for easy understanding.

[0048] During the use of the delay circuit, it is often necessary to connect multiple PMOS tubes, multiple NMOS tubes, and multiple load capacitors in a corresponding manner. For consumers, the connection process is relatively complicated, the assembly process is cumbersome, and it is difficult to use directly. In order to facilitate consumers to directly use the delay circuit, this embodiment also provides a delay module suitable for low-power chips. The delay module includes: an input interface, an output interface, a power interface, and a ground interface. The input interface is electrically connected to the input terminal IN of the delay circuit. The output interface is electrically connected to the output terminal OUT of the delay circuit. The power interface is connected to the power terminal of the buffer, and the power interface is used to connect the voltage source VDDH. The ground interface is connected to the ground terminal of the buffer, and the ground interface is used to electrically connect the voltage source AVSS.

[0049] The delay module can be used on larger electrical appliances, such as being installed in the housing of the electrical appliance, to delay part of the input signal of the electrical appliance. However, for smaller electrical appliances or chips, the delay integrated module obviously cannot be used directly. Therefore, in order to reduce the volume and weight of the delay circuit in practical applications, the present embodiment also provides a low-power delay chip. The corresponding delay chip is encapsulated using a delay circuit. The delay chip includes an input pin, an output pin, a power pin and a ground pin. The input pin is electrically connected to the input terminal IN of the delay circuit. The output pin is electrically connected to the output terminal OUT of the delay circuit. The power pin is connected to the power terminal of the buffer, and the power pin is used to connect the voltage source VDDH. The ground pin is connected to the ground terminal of the buffer, and the ground pin is used to electrically connect the voltage source AVSS.

[0050] This embodiment also provides a delay method suitable for a low-power chip. The delay method includes the following steps:

[0051] Phase 1: When the voltage source VDDH is at a high level power-on edge, and the input signal received by the delay circuit is a rising signal, the leakage unit works, thereby discharging the excess charge coupled to the node load capacitor CAP1 during the power-on process. When the voltage source VDDH is stable, the leakage unit is turned off, and the delay unit starts working. After the voltage source VDDH is stable, the delay unit starts working. The voltage of each output node is delayed by RC and accumulated, and the voltage output by the delay unit at the end is shaped by the buffer and reaches the output node OUT, which eventually delays the output signal for a long time.

[0052] Phase 2: In the state of phase 1, after the circuit works for a preset cycle, the voltage source VDDH drops to a low level. At this time, the delay unit does not work, and the leakage unit starts to work. All load capacitors CAP1 in the circuit begin to discharge and clear the charge, and the speed of discharging and clearing the charge is fast and clean.

[0053] Phase 3: After the end of phase 2, the power supply voltage is powered up again to a high level. At this time, the input signal is a rising signal. Return to phase 1. Since the load capacitor CAP1 has been cleared of charge in phase 2, the signal output by the output node OUT can still maintain a long delay time.

[0054] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0055] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A delay circuit suitable for a low-power chip, characterized in that: It includes: N delay units are cascaded, each delay unit includes a PMOS tube PM1 and an NMOS tube NM1; the gate of PM1 is connected to the gate of NM1 and serves as the input end of the corresponding delay unit, the source of PM1 is connected to the voltage source VDDH, the source of NM1 is connected to the voltage source AVSS, and the drain of PM1 is connected to the drain of NM1 as the output end of the corresponding delay unit; among the multiple delay units in the cascade, the input end of the delay unit at the first stage serves as the input end IN of the entire delay circuit; N leakage units corresponding to the delay units one by one, each leakage unit including a PMOS tube PM5; the gate of PM5 is connected to the source of PM1 in the corresponding delay unit, the drain of PM5 is connected to the voltage source AVSS, and the source of PM5 in each leakage unit is connected to the output end of the corresponding delay unit; N load capacitors CAP1 corresponding to the delay units one by one, the upper plate of each CAP1 being connected to the output end of the corresponding delay unit, and the lower plate being connected to the corresponding ground voltage source AVSS; as well as The buffer has an input end connected to the output end of the delay unit at the final stage, a power supply end of the buffer connected to a voltage source VDDH, a ground end of the buffer connected to a voltage source AVSS, and an output end of the buffer serving as an output end OUT of the entire delay circuit.

2. The delay circuit suitable for a low-power chip according to claim 1, characterized in that: The working process of the delay circuit includes: when the power supply voltage is at the power-on or power-off edge, the leakage unit starts to work and automatically clears the residual charge coupled on the capacitors of each node in the circuit; when the power supply voltage is stable, the initial state of the delay circuit is that the capacitors of the output nodes of each delay unit have no residual charge, ensuring the normal operation of the delay circuit and the correct delay duration.

3. The delay circuit suitable for a low-power chip according to claim 1, characterized in that: The delay unit includes an RC active device or an RC passive device; the RC active device includes an inverter.

4. The delay circuit suitable for a low-power chip according to claim 1, characterized in that: The leakage unit includes any one of a PMOS tube, an NMOS tube, a CMOS tube and a TFET tube. 5 . The delay circuit suitable for a low-power chip according to claim 1 , wherein the leakage unit is controlled by a power supply voltage VDDH, and the leakage unit is used to form a discharge path in the delay circuit.

6. A delay module suitable for low-power chips, characterized in that: The delay module internally adopts the circuit layout of the delay circuit applicable to the low-power chip as claimed in any one of claims 1 to 5, and the delay module comprises: An input interface, electrically connected to an input terminal IN of the delay circuit; An output interface, electrically connected to an output terminal OUT of the delay circuit; A power interface, which is electrically connected to a power supply terminal of the buffer of the delay circuit, and the power interface is used to connect to a voltage source VDDH; A ground interface is electrically connected to a ground terminal of a buffer of the delay circuit, and the ground interface is used to electrically connect to a voltage source AVSS.

7. A low power consumption delay chip, characterized in that: The delay chip is internally packaged with the delay circuit applicable to the low-power chip as claimed in any one of claims 1 to 5, and the delay chip externally comprises: An input pin, electrically connected to an input terminal IN of the delay circuit; An output pin, electrically connected to an output terminal OUT of the delay circuit; A power pin electrically connected to a power supply terminal of a buffer of the delay circuit, the power pin being used to connect to a voltage source VDDH; A ground pin is electrically connected to a ground terminal of a buffer of the delay circuit, and the ground pin is used to electrically connect to a voltage source AVSS.

8. A delay method suitable for low-power chips, characterized in that: It is applied in a delay circuit suitable for a low-power chip as described in any one of claims 1 to 5, and the delay method includes stage one: when the voltage source VDDH is at a high-level power-up edge and the input signal received by the delay circuit is a rising signal, the leakage unit works; when the voltage source VDDH is stable, the leakage unit is turned off and the delay unit starts working.

9. The delay method applicable to low-power chips according to claim 8, characterized in that: The delay method includes a second stage: in the state of the first stage, after the circuit works for a preset cycle, the voltage source VDDH drops to a low level, at which time the delay unit does not work and the leakage unit starts to work.

10. The delay method applicable to low power consumption chips according to claim 9, characterized in that: The delay method includes a third stage: after the second stage is finished, the power supply voltage is powered on again to a high level, at which time the input signal is a rising signal; and the method returns to the first stage.

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