A dual-control soft-start circuit and a switching power supply system

Abstract

The present invention relates to a novel dual-control soft-start circuit and a novel switching power supply system, belonging to the technical field of switching power supplies. The novel dual-control soft-start circuit includes: a reference voltage source, a first inverter, a second inverter, an AND gate, a frequency divider, a first soft-start pulse width generator, and a second soft-start pulse width generator. The novel switching power supply system includes: a transformer, a novel switching power supply controller, a power switch tube, and a feedback device; the novel switching power supply controller includes: a power-on / off enabling circuit, a pulse width modulator, a driving circuit, and the novel dual-control soft-start circuit. Through the VDD port and the VCS port, dual-control soft-start operation of dual-channel signals is performed on the novel switching power supply system containing the novel dual-control soft-start circuit, enabling it to complete soft start during power-on and better protect the power tube when the CS pin is short-circuited to the ground. Therefore, it can maximize the safety of user electrical equipment and has good market application prospects.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, and particularly to a novel dual-control soft-start circuit and a novel switching power supply system. Background Art

[0002] As a power supply device for all electronic products, the power supply needs to meet more stringent safety standards. Since the voltage at the secondary output terminal of the system transformer has not been established when the switching power supply system starts up, and it is almost zero voltage, at this time, the magnetic energy stored in the primary side of the transformer cannot be released when the power tube conducts and continuously accumulates, which is extremely likely to cause the current I of the primary side coil of the transformer to be too high and damage the power tube from the first cycle during startup. P Therefore, traditional single-control soft-start technology is generally adopted in traditional switching power supply systems to avoid the above problems. Now, consider another special case of a switching power supply system using traditional single-control soft-start technology, that is, when the current detection pin CS of the primary side coil is short-circuited to the ground. Although each switching power supply controller contains protection for the CS pin short-circuited to the ground, when the short circuit occurs, the power tube needs to output a pulse to detect whether the CS pin is short-circuited to the ground. At this time, the voltage of the CS pin is zero, resulting in the failure of the overcurrent protection and soft start inside the switching power supply controller. As a result, the power tube needs to output an extremely large pulse width to turn off, and this extremely large pulse width will cause the peak value of the current I of the primary side coil of the transformer to soar beyond the rated maximum current value of the power tube and cause damage. P to exceed the rated maximum current value of the power tube and cause damage.

[0003] As shown in the traditional switching power supply system Figure 1 as follows, Figure 1 shows a traditional switching power supply system 10, and its working waveforms are as shown in Figure 6 and Figure 8 . By sampling the secondary output voltage Vo of the transformer TR to the FB pin port of the switching power supply controller 11 through the feedback device 12 and sampling the current Ip in the primary side coil of the transformer through the power tube M1 and the current-limiting resistor Rcs to the CS pin port of the power converter 11, a square wave signal Vsw with variable pulse width is generated to control the on and off of the power tube M1, thereby completing the energy transfer of the transformer TR. The traditional switching power supply system 10 adopts traditional single-control soft-start technology. The startup process waveform of the traditional switching power supply system 10 when it is working properly is as shown in Figure 6 . Each time it starts up, a ramp voltage V that slowly changes from low level to high level is generated inside the switching power supply controller 11 SS , V SS acts as a current-limiting threshold to cut the peak value of the voltage V of the CS pin CS . As a result, the peak value of V CS slowly rises from low level cycle by cycle with the ramp voltage V SS , and V CS = I PR CS (R CS is the resistor of the CS pin to the ground), so the current I in the primary coil of the transformer TR P slowly rises from low to high peak by peak in each cycle, and as a result, the soft start technology protects the power transistor M1 during startup. Refer to Figure 8 , Figure 8 is the waveform when the CS pin of the traditional switching power supply system 10 is short-circuited to the ground. It can be seen from the waveform that when the CS pin of the traditional switching power supply system 10 is short-circuited to the ground, V CS = 0, and the soft start output signal V SST each pulse has the maximum pulse width, which is the same as the maximum pulse width of CLK. As a result, the gate signal V of the driving power transistor M1 SW appears with the maximum pulse width, and the I P peak soars beyond the maximum rated current value of the power transistor M1, which is extremely easy to damage the power transistor. Therefore, it is necessary to take measures to avoid the above problems, so as to achieve the purpose of protecting the safety of user equipment. Summary of the Invention

[0004] The purpose of the present invention is to provide a new type of dual-control soft start circuit and a new type of switching power supply system to ensure the safe and stable operation of the switching power supply applying the new type of dual-control soft start circuit, thereby improving the safety of user electrical equipment.

[0005] To achieve the above purpose, the present invention provides the following solutions:

[0006] A new type of dual-control soft start circuit, comprising: a reference voltage source, a first inverter, a second inverter, an AND gate, a frequency divider, a first soft start pulse width generator, and a second soft start pulse width generator;

[0007] The input end of the reference voltage source is connected to the power supply port VDD, and the output end of the reference voltage source generates a reference voltage vref;

[0008] The input end of the first inverter is connected to the enable signal EN output by the power-on and power-off enable circuit, and the output end of the first inverter generates the inverted signal EN_N of the enable signal EN;

[0009] The input end of the second inverter is connected to the tenth output end of the frequency divider, and the output end of the second inverter is connected to the first input end of the AND gate; the second input end of the AND gate is connected to the clock signal CLK output by the pulse width modulator; the output end of the AND gate is connected to the first input end of the frequency divider; the second input end of the frequency divider is connected to the enable signal EN; the first to tenth output ends of the frequency divider respectively generate first to tenth digital frequency division signals Q1 to Q10;

[0010] The first input terminal of the first soft start pulse width generator is connected to the reference voltage vref, the second input terminal of the first soft start pulse width generator is connected to the clock signal CLK, and the third input terminal of the first soft start pulse width generator is connected to the soft start voltage V SS ; The output terminal of the first soft start pulse width generator generates a first pulse width signal V SST_TON ;

[0011] The first input terminal of the second soft start pulse width generator is connected to the reference voltage vref, the second input terminal of the second soft start pulse width generator is connected to the clock signal CLK, and the third input terminal of the second soft start pulse width generator is connected to the current limiting voltage V of the CS port CS ; The fourth to seventh input terminals of the second soft start pulse width generator are respectively connected to the seventh to tenth digital frequency division signals Q7 to Q10 output by the frequency divider; the first output terminal of the second soft start pulse width generator generates a soft start voltage V SS ; The second output terminal of the second soft start pulse width generator generates a second pulse width signal V SST .

[0012] Optionally, the frequency divider includes: the first to tenth flip-flops connected in electrical series;

[0013] Each flip-flop includes a clock terminal CLK2, a clear terminal CLR, and an output terminal Q; the clock terminal CLK2 of the first flip-flop is the first input terminal of the frequency divider, and the clear terminal CLR of the first flip-flop is the second input terminal of the frequency divider; the output terminals Q of the first to tenth flip-flops are respectively the first to tenth output terminals of the frequency divider; the clear terminals CLR of the first to tenth flip-flops are all connected to the enable signal EN; the output terminals Q of the first to ninth flip-flops are respectively connected to the clock terminals CLK2 of the second to tenth flip-flops.

[0014] Optionally, the first soft start pulse width generator includes: a voltage period triangular wave generator, a first comparator, an OR gate, and a NAND gate;

[0015] The first input terminal of the voltage period triangular wave generator is the first input terminal of the first soft start pulse width generator, the second input terminal of the voltage period triangular wave generator is the second input terminal of the first soft start pulse width generator, and the output terminal of the voltage period triangular wave generator generates a voltage period triangular wave signal V with the same frequency as the clock signal CLK SAW ; The positive input terminal of the first comparator is connected to the voltage period triangular wave signal V SAW, the inverting input terminal of the first comparator is the third input terminal of the first soft-start pulse width generator; the voltage input terminal of the first comparator is connected to the reference voltage vref; the output terminal of the first comparator is connected to the first input terminal of the OR gate; the second input terminal of the OR gate is connected to the inverted signal CLK_N of the clock signal CLK; the output terminal of the OR gate is connected to the first input terminal of the NAND gate; the second input terminal of the NAND gate is connected to the output terminal of the second inverter; the output terminal of the NAND gate is the output terminal of the first soft-start pulse width generator.

[0016] Optionally, the voltage-period triangular wave generator includes: a first current mirror, a second current mirror, a first switch, a second switch, a third inverter, an N-type switch transistor, and a first capacitor;

[0017] The input terminal of the first current mirror is the first input terminal of the voltage-period triangular wave generator; the output terminal of the first current mirror is connected to the first connection terminal of the first switch; the second connection terminal of the first switch is respectively connected to the first connection terminal of the second switch, the drain of the N-type switch transistor, and one end of the first capacitor; the gate of the N-type switch transistor is connected to the inverted signal EN_N of the enable signal EN; the second connection terminal of the second switch is connected to the input terminal of the second current mirror; the output terminal of the second current mirror, the source of the N-type switch transistor, and the other end of the first capacitor are all grounded; the input terminal of the third inverter is the second input terminal of the voltage-period triangular wave generator; the input terminal of the third inverter is connected to the control terminal of the first switch; the output terminal of the third inverter is connected to the control terminal of the second switch; the drain of the N-type switch transistor is the output terminal of the voltage-period triangular wave generator.

[0018] Optionally, the second soft-start pulse width generator includes a digital-to-analog converter, a second comparator, a fourth inverter, and an eleventh flip-flop;

[0019] The first to fourth input terminals of the digital-to-analog converter are respectively the fourth to seventh input terminals of the second soft-start pulse width generator; the voltage input terminal of the digital-to-analog converter is the first input terminal of the second soft-start pulse width generator; the output terminal of the digital-to-analog converter is the first output terminal of the second soft-start pulse width generator; the non-inverting input terminal of the second comparator is connected to the soft-start voltage V SS; The inverting input terminal of the second comparator is the third input terminal of the second soft-start pulse width generator; the voltage input terminal of the second comparator is connected to the reference voltage vref; the output terminal of the second comparator is connected to the clear terminal CLR of the eleventh flip-flop; the input terminal of the fourth inverter is the second input terminal of the second soft-start pulse width generator; the output terminal of the fourth inverter is connected to the clock terminal CLK3 of the eleventh flip-flop; the input digital signal terminal D of the eleventh flip-flop is connected to the reference voltage vref; the output terminal Q of the eleventh flip-flop is the second output terminal of the second soft-start pulse width generator.

[0020] A novel switching power supply system includes: a transformer, a novel switching power supply controller, a power switch tube, and a feedback device; the novel switching power supply controller includes: a power-on and power-off enabling circuit, a pulse width modulator, and a driving circuit.

[0021] The novel switching power supply controller further includes: the novel dual-control soft-start circuit as described above; the first input terminal of the driving circuit is connected to the first pulse width signal V SST_TON ; the second input terminal of the driving circuit is connected to the second pulse width signal V SST ; the output terminal of the driving circuit is connected to the gate of the power switch tube.

[0022] According to the specific embodiments provided by the present invention, the following technical effects of the present invention are disclosed:

[0023] The present invention provides a novel dual-control soft-start circuit and a novel switching power supply system. The novel dual-control soft-start circuit includes: a reference voltage source, a first inverter, a second inverter, an AND gate, a frequency divider, a first soft-start pulse width generator, and a second soft-start pulse width generator; the input terminal of the reference voltage source is connected to the power supply port VDD, and the output terminal of the reference voltage source generates a reference voltage vref; the input terminal of the first inverter is connected to the enabling signal EN output by the power-on and power-off enabling circuit, and the output terminal of the first inverter generates an inverted signal EN_N of the enabling signal EN; the input terminal of the second inverter is connected to the tenth output terminal of the frequency divider, and the output terminal of the second inverter is connected to the first input terminal of the AND gate; the second input terminal of the AND gate is connected to the clock signal CLK output by the pulse width modulator; the output terminal of the AND gate is connected to the first input terminal of the frequency divider; the second input terminal of the frequency divider is connected to the enabling signal EN; the first to tenth output terminals of the frequency divider respectively generate first to tenth digital frequency division signals Q1 to Q10; the first input terminal of the first soft-start pulse width generator is connected to the reference voltage vref, the second input terminal of the first soft-start pulse width generator is connected to the clock signal CLK, and the third input terminal of the first soft-start pulse width generator is connected to the soft-start voltage V SS; The output terminal of the first soft start pulse width generator generates a first pulse width signal V SST_TON ; The first input terminal of the second soft start pulse width generator is connected to the reference voltage vref, the second input terminal of the second soft start pulse width generator is connected to the clock signal CLK, and the third input terminal of the second soft start pulse width generator is connected to the current limiting voltage V of the CS port CS ; The fourth to seventh input terminals of the second soft start pulse width generator are respectively connected to the seventh to tenth digital frequency division signals Q7 to Q10 output by the frequency divider; the first output terminal of the second soft start pulse width generator generates a soft start voltage V SS ; The second output terminal of the second soft start pulse width generator generates a second pulse width signal V SST . The present invention can perform dual-control soft start operation on the new switch power supply system containing the new dual-control soft start circuit through the VDD port and the VCS port, enabling it to complete soft start during power-on and better protect the power tube when the CS pin port is short-circuited to the ground. Therefore, it can maximize the safety of user electrical equipment and has good market application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0025] Figure 1 It is a schematic diagram of a traditional switch power supply system;

[0026] Figure 2 It is a schematic diagram of the new switch power supply system provided by the present invention;

[0027] Figure 3 It is a connection schematic diagram of the new dual-control soft start circuit provided by the present invention;

[0028] Figure 4 It is a partial timing waveform diagram of the internal signals of the new dual-control soft start circuit provided by the present invention;

[0029] Figure 5 It is another partial timing waveform diagram of the internal signals of the new dual-control soft start circuit provided by the present invention;

[0030] Figure 6 It is a normal working timing waveform diagram of a traditional switch power supply system;

[0031] Figure 7 It is a normal working timing waveform diagram of the new switch power supply system provided by the present invention;

[0032] Figure 8 It is the timing waveform diagram of the CS terminal of the traditional switching power supply system short - circuited to the ground;

[0033] Figure 9 It is the timing waveform diagram of the CS terminal of the new - type switching power supply system provided by the present invention short - circuited to the ground;

[0034] Figures 6 to 9 where V SS Each voltage step time contains about 128 switching waveforms. If all are drawn in the figure, due to the paper size, they cannot be clearly displayed, which will not help to explain the waveform working principle. Therefore, in the figure, it is simplified to 2 CLK - cycle waveforms to clearly explain the circuit working principle;

[0035] The symbols shown in the figure are explained as follows:

[0036] 10: Traditional switching power supply system

[0037] 10A: New - type switching power supply system provided by the present invention

[0038] 11: Traditional switching power supply controller

[0039] 11A: New - type switching power supply controller provided by the present invention

[0040] 12: Feedback device, i.e., FeedBack

[0041] 20: Power - on / off enable circuit, i.e., UVLO

[0042] 30: Pulse - width modulator, i.e., PWM

[0043] 40: Driver circuit, i.e., DRIVER

[0044] 50: Soft - start circuit inside the traditional switching power supply controller 11, i.e., SST

[0045] 50A: New - type dual - control soft - start circuit inside the new - type switching power supply controller 11A, i.e., DSST

[0046] 60A: Timing waveform diagram of signals EN, CLK, CLK1, Q1, Q2, Q3, Q4, Q5, Q6, Q7 inside the new - type dual - control soft - start circuit 50A

[0047] 60B: Timing waveform diagram of signals CLK, CLK1, Q7, Q8, Q9, Q10, NQ10, V SS inside the new - type dual - control soft - start circuit 50A

[0048] 70A: Normal working timing waveform diagram of the traditional switching power supply system

[0049] 70B: Timing waveform diagram of the normal operation of the novel switching power supply system provided by the present invention

[0050] 80A: Timing waveform diagram of the CS terminal of the traditional switching power supply system being shorted to the ground

[0051] 80B: Timing waveform diagram of the CS terminal of the novel switching power supply system provided by the present invention being shorted to the ground

[0052] In 70A, 70B, 80A, and 80B, V SS Each voltage step time contains approximately 128 switching waveforms. If all are drawn in the figure, it will not be clearly shown due to the paper size, and the working waveform cannot be demonstrated clearly. Therefore, the figure is simplified to 2 CLK cycle waveforms to clearly illustrate the circuit working principle;

[0053] M1: External power switch transistor, having a drain, a gate, and a source

[0054] M50: N-type switch transistor, having a drain, a gate, and a source

[0055] TR: Transformer

[0056] Lp: Primary coil of the transformer TR

[0057] Ls: Secondary coil of the transformer TR

[0058] La: Auxiliary coil of the transformer TR, responsible for supplying power to the capacitor C at the VDD port VDD Power supply

[0059] D1: Full-wave rectifier diode for AC input

[0060] D2, D3: Diodes, having a cathode and an anode

[0061] Rst: Starting resistor

[0062] R1, Rx, Rcs: Resistors

[0063] C1, Cx, C VDD 、C2、C SST : Capacitors

[0064] 51: Reference voltage transformer, i.e., VREF, whose input is the voltage signal V DD , and the output is the reference voltage vref. vref is also the power supply for the internal low-voltage circuit

[0065] 52: Two-input AND gate, i.e., AND2, whose input and output are both logic signals, and the output is the AND operation of the input signals

[0066] 53 to 59, 61 to 63: Flip-flops, whose inputs and outputs are all logic signals, used for frequency division of the input clock

[0067] 64, 66, 74: Inverters, namely INV, whose inputs and outputs are all logic signals, used for inverting the input signal

[0068] 65, 67: Current mirrors, where 65 is I CH_OSC is a charging current mirror with a value equal to I1 (I1 is a set constant value), and 67 is I DIS_OSC is a charging current mirror with a value equal to 2I1

[0069] 68, 72: Comparators, having a positive input terminal, a negative input terminal, a voltage input terminal, and an output terminal. When the voltage at the positive input terminal is higher than the voltage at the negative input terminal, the output is logic high; otherwise, the output is logic low

[0070] 69: Two-input OR gate, namely OR2, whose inputs and outputs are all logic signals, and the output is the OR operation of the input signals

[0071] 71: Flip-flop, whose inputs and outputs are all logic signals, used for pulse width modulation of the input signal

[0072] 73: Three-bit digital-to-analog converter, namely DAC, whose input is digital logic, and the DAC is used for digital-to-analog conversion of the input signal

[0073] 75: Two-input NAND gate, namely NAND2, whose inputs and outputs are all logic signals, and the output is the NAND operation of the input signals

[0074] 76: Frequency divider, used for frequency division of the CLK signal to generate digital frequency division signals Q1 to Q10

[0075] 77: First soft start pulse width generator, according to V SS and V SAW generates a first pulse width signal V with a gradually increasing pulse width from 0 SST_TON

[0076] 79: Periodic triangular wave generator SAW inside the first soft start pulse width generator 77, used for generating a periodic triangular wave signal V with the same frequency as CLK SAW

[0077] 78: Second soft start pulse width generator, according to V SS and V CS generates a second pulse width signal V with a gradually increasing pulse width from 0 SST

[0078] 81: Inverter, namely INV, whose inputs and outputs are all logic signals, used for inverting the input signal

[0079] K51, K52: Switches

[0080] VDD: Power supply port

[0081] FB: Feedback port

[0082] CS: Current monitoring port

[0083] DRV: Drive output port

[0084] GND: Ground port

[0085] VAC: AC input voltage

[0086] Vo: Secondary side DC output voltage of transformer TR

[0087] I P : Current in primary coil L of transformer TR P in

[0088] I P_MIN : Minimum current of L controlled by V in soft start SST in P soft start

[0089] I P_MAX : Maximum current of L controlled by V in soft start SST in P soft start

[0090] I P_MIN1 : Minimum current of L controlled by V in soft start when CS pin is shorted to ground SST_TON in P soft start

[0091] I P_MAX1 : Maximum current of L controlled by V in soft start when CS pin is shorted to ground SST_TON in P soft start

[0092] I P_SCP : Current in L when CS pin is shorted to ground P in

[0093] Vsw: Switching signal, i.e., pulse width voltage signal for driving the gate of power transistor M1

[0094] V FB : Feedback voltage

[0095] V CS : Current limiting voltage of CS port, source voltage of M1, equal to the product of current I in Lp and R, with the same frequency as CLK P and CS R

[0096] V DD : Voltage of power supply port

[0097] V PWM : PWM output signal, used to modulate the pulse width of Vsw

[0098] EN: Enable signal output by UVLO

[0099] V SST : Second pulse width signal, used to control the pulse width of Vsw

[0100] V SST_TON : First pulse width signal, used to control the pulse width of Vsw

[0101] CLK: Output clock signal of PWM

[0102] CLK_N: Inverse of CLK

[0103] CLK1: Input clock signal of frequency divider 76, generated by the AND operation of NQ10 and CLK

[0104] CLK2: Input clock control terminal of the flip-flop inside frequency divider 76

[0105] CLK3: Input clock control terminal of flip-flop 71

[0106] D: Input digital signal terminal of flip-flop 71

[0107] Q: Output terminal of the flip-flop

[0108] CLR: Input initialization enable signal of the flip-flop. When it is at a low level, the output terminal Q is initialized to a low level

[0109] vref: Reference voltage output by VREF51

[0110] I O : Secondary side output current of transformer TR

[0111] NQ10: Output of the second inverter 74, which is the signal obtained by inverting the input Q10 of the second inverter 74

[0112] VDD OFF : Power-down threshold of VDD voltage

[0113] VDD ON : Power-up threshold of VDD voltage

[0114] Q1~Q10: Outputs of flip-flops 53~59, 61~63 respectively

[0115] V SS : Soft start voltage, used to generate the first pulse width signal V after cutting Vcs SST , participating in controlling the gate of power switch M1

[0116] V SS_MAX 、V SS_MIN : Respectively V SS The maximum and minimum values

[0117] V SAW : A triangular wave voltage with the same period as CLK, used for V SS Cut V SAW After that, a second pulse width signal V is generated SST_TON , and it also participates in controlling the gate of the power switch tube M1

[0118] V FB_OPEN : The open-circuit voltage of the FB port

[0119] "1": Logic high, corresponding to the voltage vref

[0120] "0": Logic low, corresponding to the voltage 0

[0121] EN SST : The output signal of the second comparator 72

[0122] EN SST_TON : The output signal of the first comparator 68

[0123] V SST_TON1 : The output signal of the OR gate 69

[0124] T Q1 ~T Q10 : Respectively the periods of the first to tenth digital frequency division signals Q1~Q10

[0125] V CSTH : The overcurrent threshold voltage of the CS pin, used to define the maximum peak current I of the TR primary coil, that is, the power switch tube M1 PK , where I PK =V CSTH / Rcs

[0126] Vstep: The digital-to-analog conversion step voltage of the digital-to-analog converter 73, and its step period is half of the period of Q7, that is, the period T of Q6 Q6

[0127] V LP : The voltage on L P The voltage on

[0128] T SW : The period of CLK

[0129] D M : The duty cycle of CLK

[0130] T SST : V SST The positive pulse width time

[0131] T SST_TON : V SST_TON Positive pulse width time

[0132] T SST_TON_MIN : V SST_TON Minimum positive pulse width time of

[0133] β: Equal to L P / V LP L P is the inductance of the primary coil of the transformer TR, and V LP is the voltage across L P . Detailed implementation manners

[0134] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0135] The purpose of the present invention is to provide a novel dual-control soft start circuit and a novel switching power supply system to ensure the safe and stable operation of the switching power supply applying the novel dual-control soft start circuit, thereby improving the safety of user electrical equipment.

[0136] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0137] The present invention provides a novel dual-control soft start circuit and a novel switching power supply system. As Figure 2 shown, the novel dual-control soft start circuit DSST provided by the present invention can be applied to Figure 1 the traditional switching power supply system shown in, and work instead of the soft start circuit SST in its traditional switching power supply controller. Figure 3 is the connection schematic diagram of the novel dual-control soft start circuit provided by the present invention. Refer to Figure 3 , the novel dual-control soft start circuit provided by the present invention includes: a reference voltage source 51, a first inverter 64, a second inverter 74, an AND gate 52, a frequency divider 76, a first soft start pulse width generator 77, and a second soft start pulse width generator 78.

[0138] Among them, the input end of the reference voltage source 51 is connected to the power supply port VDD (i.e., connected to the voltage signal V DD ), and the output end of the reference voltage source generates a reference reference voltage vref.

[0139] The input terminal of the first inverter 64 is connected to the enable signal EN output by the power-on and power-off enabling circuit, and the output terminal of the first inverter 64 generates an inverted signal EN_N of the enable signal EN.

[0140] The input terminal of the second inverter 74 is connected to the tenth output terminal of the frequency divider 76 (i.e., connected to the tenth digital frequency division signal Q10), and the output terminal of the second inverter 74 (generating an inverted signal NQ10 of Q10) is connected to the first input terminal of the AND gate 52. The second input terminal of the AND gate 52 is connected to the clock signal CLK output by the pulse width modulator 30. The output terminal of the AND gate 52 (generating the clock signal CLK1) is connected to the first input terminal of the frequency divider 76 (i.e., the clock terminal CLK2 of the first flip-flop 53). The second input terminal of the frequency divider 76 (i.e., the common connection terminal of the clear terminals CLR of the first to tenth flip-flops) is connected to the enable signal EN. The first to tenth output terminals of the frequency divider 76 (i.e., the output terminals Q of the first to tenth flip-flops) respectively generate the first to tenth digital frequency division signals Q1 to Q10.

[0141] The first input terminal of the first soft start pulse width generator 77 (i.e., the input terminal of the first current mirror 65) is connected to the reference voltage vref, the second input terminal of the first soft start pulse width generator (i.e., the input terminal of the third inverter 66) is connected to the clock signal CLK, and the third input terminal of the first soft start pulse width generator 77 (i.e., the inverting input terminal of the first comparator 68) is connected to the soft start voltage V SS ; the output terminal of the first soft start pulse width generator 77 (i.e., the output terminal of the NAND gate 75) generates the first pulse width signal V SST_TON .

[0142] The first input terminal of the second soft start pulse width generator 78 (i.e., the voltage input terminal of the digital-to-analog converter 73) is connected to the reference voltage vref, the second input terminal of the second soft start pulse width generator 78 (i.e., the input terminal of the fourth inverter 81) is connected to the clock signal CLK, and the third input terminal of the second soft start pulse width generator 78 (i.e., the inverting input terminal of the second comparator 72) is connected to the current limiting voltage V of the CS port CS ; the fourth to seventh input terminals of the second soft start pulse width generator 78 (i.e., the first to fourth input terminals of the digital-to-analog converter 73) are respectively connected to the seventh to tenth digital frequency division signals Q7 to Q10 output by the frequency divider 76; the first output terminal of the second soft start pulse width generator 78 (i.e., the output terminal of the digital-to-analog converter 73) generates the soft start voltage V SS ; the second output terminal of the second soft start pulse width generator 78 (i.e., the output terminal Q of the eleventh flip-flop 71) generates the second pulse width signal V SST .

[0143] Specifically, the frequency divider 76 includes: first to tenth flip-flops 53 to 59, 61 to 63 connected in electrical series; each of the flip-flops includes a clock terminal CLK2, a clear terminal CLR, and an output terminal Q. The clock terminal CLK2 of the first flip-flop 53 is the first input terminal of the frequency divider 76, and the clear terminal CLR of the first flip-flop 53 is the second input terminal of the frequency divider 76. The output terminals Q of the first to tenth flip-flops 53 to 59, 61 to 63 are the first to tenth output terminals of the frequency divider 76 respectively, generating first to tenth digital frequency division signals Q1 to Q10. The clear terminals CLR of the first to tenth flip-flops 53 to 59, 61 to 63 are all connected to the enable signal EN. The output terminals Q of the first to ninth flip-flops 53 to 59, 61 to 62 are respectively connected to the clock terminals CLK2 of the second to tenth flip-flops 54 to 59, 61 to 63.

[0144] The frequency divider 76 is composed of ten identical flip-flops 53 to 59, 61 to 63 connected in electrical series; the output terminal Q of the flip-flops 53 to 59, 61 to 62 is connected to the clock terminal CLK2 of the next flip-flop in series with it. The frequency divider 76 initializes all output terminals to zero in response to the logic low of the enable signal EN, and it generates frequency division digital logic signals Q1 to Q10 of the clock signal CLK1 at the first to tenth output terminals in response to the clock signal CLK1, and the period of Q1 is twice that of CLK1, the period of Q2 is twice that of Q1, the period of Q3 is twice that of Q2, and then Q4 to Q10 follow in sequence.

[0145] Specifically, the first soft start pulse width generator 77 includes: a voltage period triangular wave generator 79, a first comparator 68, an OR gate 69, and a NAND gate 75. The first input terminal of the voltage period triangular wave generator 79 is the first input terminal of the first soft start pulse width generator 77 (connected to the reference voltage vref), and the second input terminal of the voltage period triangular wave generator 79 is the second input terminal of the first soft start pulse width generator 77 (connected to the clock signal CLK). The output terminal of the voltage period triangular wave generator 79 generates a voltage period triangular wave signal V with the same frequency as the clock signal CLK SAW . The positive input terminal of the first comparator 68 is connected to the voltage period triangular wave signal V SAW , and the negative input terminal of the first comparator 68 is the third input terminal of the first soft start pulse width generator 77 (connected to the soft start voltage V SS ). The voltage input terminal of the first comparator 68 is connected to the reference voltage vref. The output terminal of the first comparator 68 (generating the signal EN SST_TON) is connected to the first input terminal of the OR gate 69; the second input terminal of the OR gate 69 is connected to the inverted signal CLK_N of the clock signal CLK; the output terminal of the OR gate 69 (generating signal V SST_TON1 ) is connected to the first input terminal of the NAND gate 75; the second input terminal of the NAND gate 75 is connected to the output terminal of the second inverter 74 (i.e., connected to signal NQ10); the output terminal of the NAND gate 75 is the output terminal of the first soft start pulse width generator 77 (generating the first pulse width signal V SST_TON ).

[0146] Specifically, the voltage period triangular wave generator 79 includes: a first current mirror 65, a second current mirror 67, a first switch K52, a second switch K51, a third inverter 66, an N-type switch tube M50, and a first capacitor C SST . The input terminal of the first current mirror 65 is the first input terminal of the voltage period triangular wave generator 79 (connected to the reference voltage vref); the output terminal of the first current mirror 65 is connected to the first connection terminal of the first switch K52; the second connection terminal of the first switch K52 is respectively connected to the first connection terminal of the second switch K51, the drain of the N-type switch tube M50, and one end of the first capacitor C SST . The gate of the N-type switch tube M50 is connected to the inverted signal EN_N of the enable signal EN. The second connection terminal of the second switch K51 is connected to the input terminal of the second current mirror 67; the output terminal of the second current mirror 67, the source of the N-type switch tube M50, and the other end of the first capacitor C SST are all grounded. The input terminal of the third inverter 66 is the second input terminal of the voltage period triangular wave generator 79 (connected to the clock signal CLK); the input terminal of the third inverter 66 is connected to the control terminal of the first switch K52 (i.e., connected to the clock signal CLK); the output terminal of the third inverter 66 (generating the inverted signal CLK_N of the clock signal CLK) is connected to the control terminal of the second switch K51; the drain of the N-type switch tube M50 is the output terminal of the voltage period triangular wave generator 79 (i.e., generating the voltage period triangular wave signal V SAW ).

[0147] The soft start pulse width generator 77 described above initializes the voltage period triangular wave V SAW to zero potential in response to the high level of the inverted signal EN_N of the enable signal EN, generates a voltage period triangular wave V SAW with the same frequency in response to the clock signal CLK, generates a soft start voltage pulse width control signal V SS at its output terminal in response to the soft start voltage V SST_TON , and generates a high level of V SST_TON at its output terminal in response to the low level of the signal NQ10.

[0148] Specifically, the second soft start pulse width generator 78 includes a digital-to-analog converter 73, a second comparator 72, a fourth inverter 81, and an eleventh flip-flop 71. The first to fourth input terminals D1, D2, D3, and EN2 of the digital-to-analog converter 73 are respectively the fourth to seventh input terminals of the second soft start pulse width generator 78 (connected to the seventh to tenth digital frequency division signals Q7 to Q10); the voltage input terminal of the digital-to-analog converter 73 is the first input terminal of the second soft start pulse width generator 78 (connected to the reference voltage vref); the output terminal of the digital-to-analog converter 73 (generating a soft start voltage V SS ) is the first output terminal of the second soft start pulse width generator 78. The positive input terminal of the second comparator 72 is connected to the soft start voltage V SS ; the negative input terminal of the second comparator 72 is the third input terminal of the second soft start pulse width generator 78 (connected to the current limiting voltage V CS ) of the CS port; the voltage input terminal of the second comparator 72 is connected to the reference voltage vref; the output terminal of the second comparator 72 (generating a signal EN SST ) is connected to the clear terminal CLR of the eleventh flip-flop 71. The input terminal of the fourth inverter 81 is the second input terminal of the second soft start pulse width generator 78 (connected to the clock signal CLK); the output terminal of the fourth inverter 81 (generating an inverted signal CLK_N1 of the clock signal CLK) is connected to the clock terminal CLK3 of the eleventh flip-flop 71; the input digital signal terminal D of the eleventh flip-flop 71 is connected to the reference voltage vref; the output terminal Q of the eleventh flip-flop 71 is the second output terminal of the second soft start pulse width generator 78 (generating a second pulse width signal V SST ).

[0149] The second soft start pulse width generator 78 generates a soft start voltage V SS in response to the seventh to tenth digital frequency division signals Q7 to Q10, and in response to the current limiting voltage V CS of the CS port, the clock signal CLK, and the soft start voltage V SS , generates a soft start voltage pulse width control signal V SST at its output terminal.

[0150] In practical applications, for the novel dual-control soft start circuit of the present invention, the internal frequency divider 76 thereof may not be limited to ten flip-flops and ten-digit digital outputs, and the internal digital-to-analog converter 73 may also not be limited to four-digit digital signal inputs. Any person skilled in this field can make some modifications and replacements without departing from the spirit and scope of the present invention to implement the functions of the circuit of the present invention.

[0151] The novel dual-control soft-start circuit provided by the present invention is electrically coupled together by a reference voltage source 51, a frequency divider 76, soft-start pulse width generators 77 and 78, inverters 74 and 64, and an AND gate 52. According to signals V DD 、CLK、EN、V CS two dual-control soft-start control enable signals V SST_TON 、V SST are generated. Signals V SST_TON 、V SST can not only complete the soft-start function of the system during the start-up phase of the novel switch power supply system 10A, but also avoid the risk of damage to the power transistor when the CS pin is shorted to the ground. Therefore, the novel dual-control soft-start circuit provided by the present invention can be applied to devices such as switch power supplies. For example, it is applied to a flyback switch power supply on the secondary side of a transformer. By controlling the novel dual-control soft-start circuit through ports VDD and CS, the switch power supply system containing the novel dual-control soft-start circuit operates more safely.

[0152] Therefore, based on a novel dual-control soft-start circuit provided by the present invention, the present invention also provides a novel switch power supply system. Refer to Figure 2 , the novel switch power supply system 10A includes: a transformer TR, a novel switch power supply controller 11A, a power switch transistor M1, and a feedback device 12; the novel switch power supply controller 11A includes: a power-on and power-off enable circuit 20, a pulse width modulator 30, a drive circuit 40, and the novel dual-control soft-start circuit 50A provided by the present invention.

[0153] The novel switch power supply controller 11A is composed of four circuit modules, namely a novel dual-control soft-start circuit DSST50A, a power-on and power-off enable circuit UVLO20, a pulse width modulator PWM30, and a drive circuit DRIVER40, which are electrically connected. The first input terminal CS of the PWM30 is connected to one end of a sampling resistor Rcs and the source electrode of a power transistor (power switch transistor) M1. The second input terminal FB of the PWM30 is connected to the output terminal of the feedback device 12. The second output terminal V PWM of the PWM30 is connected to the fourth input terminal of the drive circuit DRIVER40; the other end of the sampling resistor Rcs is grounded. The input terminal of the UVLO20 is connected to the power VDD port of the novel switch power supply controller 11A, the first input terminal of the DSST, the third input terminal of the PWM30, and the third input terminal of the DRIVER40; the output terminal DRV of the DRIVER40 is externally connected to the gate of the power transistor M1; the drain of the power transistor M1 is connected to the primary coil L P of the transformer TR. The novel switch power supply controller 11A is a switch power supply controller in a flyback manner on the secondary side of the transformer.

[0154] The described new dual-control soft-start circuit 50A is embedded in the new switch-mode power supply controller 11A. The VDD terminal of the new dual-control soft-start circuit 50A is connected to the power supply VDD of the switch-mode power supply controller 11A; the EN terminal of the new dual-control soft-start circuit 50A is connected to the UVLO output terminal EN of the switch-mode power supply controller 11A; the V CS terminal of the new dual-control soft-start circuit 50A is connected to the input terminal CS of the switch-mode power supply controller 11A; the CLK terminal of the new dual-control soft-start circuit 50A is connected to the output signal CLK of the PWM of the switch-mode power supply controller 11A; the V SST terminal of the new dual-control soft-start circuit 50A is connected to the second input terminal of the DRIVER of the switch-mode power supply controller 11A; the V SST_TON terminal of the new dual-control soft-start circuit 50A is connected to the first input terminal of the DRIVER of the switch-mode power supply controller 11A.

[0155] The new switch-mode power supply controller 11A is coupled to a feedback device 12 provided at the output terminal of the transformer TR to generate a switching signal V SW , and the power switch M1 is controlled by the switching signal V SW to adjust the pulse width of the transformer TR, thereby regulating the energy transmission of the switch-mode power supply 10A containing the new dual-control soft-start circuit 50A. The new switch-mode power supply controller 11A is composed of the new dual-control soft-start circuit 50A, a power-on / off enabling circuit 20, a pulse width modulator 30, and a driving circuit 40 coupled together.

[0156] The difference in the circuit connection relationship between the new switch-mode power supply controller 11A provided by the present invention and Figure 1 the traditional switch-mode power supply controller 11 shown is that the new dual-control soft-start circuit 50A is used to replace the traditional soft-start circuit 50. As a result, in addition to the original V PWM , V CS_SCP , V SST , V DD , the input signal of the driving circuit 40 also includes an additional first pulse width signal V SST_TON . Specifically, the first input terminal of the driving circuit 40 is connected to the first pulse width signal V SST_TON ; the second input terminal of the driving circuit 40 is connected to the second pulse width signal V SST ; the third, fourth, and fifth input terminals of the driving circuit are respectively connected to the signals V DD , V PWM , V CS_SCP ; the output terminal of the driving circuit 40 is connected to the gate of the power switch tube M1. The connection methods of other components in the new switch-mode power supply system are the same as those in the traditional switch-mode power supply system, and will not be elaborated here.

[0157] The working principle of a novel switching power supply system 10A provided by the present invention is as follows:

[0158] On the one hand, the novel dual-control soft-start circuit 50A responds to the enable signal EN to initialize and set the internal circuit; responds to the clock signal CLK to generate a soft-start voltage V SS ; responds to the soft-start voltage V SS , the current-limiting voltage V at the CS port CS to generate a soft-start voltage pulse-width control signal (i.e., the second pulse-width signal) V at the second output end SST ; on the other hand, the novel dual-control soft-start circuit responds to the soft-start voltage V SS to generate a soft-start voltage pulse-width control signal (i.e., the first pulse-width signal) V at its first output end SST_TON .

[0159] The control signals V SST , V SST_TON generated by the novel dual-control soft-start circuit 50A cause the peak value of V CS to gradually rise from close to zero during the soft-start time in the normal start-up and power-on process of the novel switching power supply system 10A. As a result, the current I P in the power transistor M1 slowly climbs from close to zero in the start-up timing of the switching power supply system. This process is called soft start. The soft-start function greatly reduces the drain voltage of the power transistor M1, thus avoiding the risk of breakdown and damage caused by too high a drain voltage of the power transistor due to the absence of the soft-start function.

[0160] In addition, although most switching power supply controller integrated circuits have a function of protecting against short circuit between the CS pin and the ground, when a short circuit occurs between the CS pin and the ground (i.e., V CS is equal to zero), V SST is the maximum pulse width. Due to only one-way V SST control during soft start in the traditional switching power supply controller 11 integrated circuit, at least one pulse with the maximum duty cycle is generated by the power transistor M1, resulting in the peak current in the power transistor M1 exceeding the maximum rated current value of the power transistor M1 per cycle and damaging the power transistor. However, the present invention adopts a dual-control technology of soft-start dual signals V SST , V SST_TON . When a short circuit occurs between the CS pin and the ground, V SST_ON controls the time widths of the first dozens of pulses of the power transistor M1 to be close to zero, and the current in the power transistor M1 is limited to be far lower than its maximum rated current value, ensuring the safety of the power transistor M1. Therefore, the circuit of the present invention can not only complete the soft-start function when the switching power supply system is powered on, but also avoid the risk of damaging the power transistor M1 when a short circuit occurs between the CS pin and the ground.

[0161] The novel dual-control soft-start circuit 50A provided by the present invention is composed of a reference voltage source 51, a frequency divider 76, soft-start pulse width generators 77 and 78, inverters 74 and 64, and an AND gate 52 connected electrically. Based on the working principles of the novel dual-control soft-start circuit 50A and the novel switching power supply system 10A provided by the present invention, a user can perform a dual-control soft-start operation on the novel switching power supply system 10A including the novel dual-control soft-start circuit 50A through the VDD port and the CS port, enabling it to complete soft start during power-on and better protect the power transistor when the CS pin port is short-circuited to the ground, thereby maximizing the safety of the user's electrical equipment.

[0162] The novel switching power supply controller 11A described in the present invention can be applied to transformer secondary-side feedback isolation type and transformer primary-side feedback isolation type switching power supply systems. The switching power supply controller 11A is composed of the novel dual-control soft-start circuit 50A, a power-on / off enabling circuit 20, a pulse width modulator 30, and a driving circuit 40 embedded in an integrated circuit to save external components.

[0163] The following provides the specific working process of a novel dual-control soft-start circuit 50A of the present invention.

[0164] During the process of VDD powering on from 0, when V DD < VDD ON (where VDD ON is the power-on threshold), EN is logic "0". After being inverted by the first inverter 64, EN_N is logic "1". EN initializes the outputs Q1 to Q10 of all flip-flops 53 to 59 and 61 to 63 in the frequency divider 76 to logic "0", and EN_N initializes the capacitor C SST in the periodic voltage triangular wave generator 79 to 0 voltage. When V DD > VDD ON later, EN is "1" and EN_N is "0", and EN and EN_N no longer function, and the circuit enters normal operation.

[0165] The voltage V DD at the VDD port is input to the reference voltage transformer 55 and then outputs a reference voltage vref to supply power to the internal functional blocks. NQ10 is the inversion of the output Q10 of the last flip-flop 63 in the frequency divider 76. Since the initial logic of Q10 is "0", the initial logic of NQ10 is "1", and CLK1 has the same clock signal as CLK. The frequency divider 76 performs frequency division on CLK. Among them, the period T Q1 of Q1 is twice that of CLK, the period T Q2 of Q2 is twice that of Q1, the period T Q3 of Q3 is twice that of Q2, and so on. By analogy, the period T Q10It is twice that of Q9. Let the period of CLK be T SW , then we have:

[0166] T Q1 = 2T SW (1)

[0167] T Q2 = 4T SW (2)

[0168] T Q3 = 8T SW (3)

[0169] T Q4 = 16T SW (4)

[0170] T Q5 = 32T SW (5)

[0171] T Q6 = 64T SW (6)

[0172] T Q7 = 128T SW (7)

[0173] T Q8 = 256T SW (8)

[0174] T Q9 = 512T SW (9)

[0175] T Q10 = 1024T SW (10)

[0176] When Q10 flips to logic "1", NQ10 flips to logic "0" to lock the AND gate 52, and CLK1 logic is constantly "0", no longer changing with the logic of CLK. Q10 is constantly "1", and Q1 - Q9 are constantly "0". The waveforms of Q1 - Q10 are as shown in Figure 4 and Figure 5 shown, and the timing relationships of EN, CLK, CLK1, Q1 - Q10, NQ10, V SS can also be seen from the figure.

[0177] Look at Figure 3 again. In the second soft start pulse width generator circuit 78, the input digital signals for the digital - to - analog converter 73 for digital - to - analog conversion are Q7 - Q9, Q10 is its enable input signal, and the reference voltage input is vref. The specific working principle is that when Q10 is logic "0", the digital - to - analog converter 73 works normally, and its output voltage V SSAs Q7 to Q9 increase incrementally by binary for each CLK cycle, V SS The minimum value is close to the zero level, V SS The maximum value is the overcurrent threshold of the CS pin V CSTH ; when Q10 is logic "1", V SS is vref. V SS The waveform of V Figure 5 is shown in SS , where T

[0178] V SS = Vstep(1 + Q7 + 2Q8 + 4Q9) (11)

[0179] V SS_MAX = V CSTH = Vstep(1 + 1 + 2 + 4) = 8Vstep(12)

[0180] V SS_MIN = V CSTH / 8 = Vstep(1 + 0 + 0 + 0) = Vstep(13)

[0181] For equation (11), if Q7, Q8, Q9, NQ10 are logic "1", substitute the value 1, if they are logic "0", substitute the value 0. For equations (11) and (12), V SS_MAX , V SS_MIN are the maximum and minimum values of V SS respectively.

[0182] V SS is converted into a triangular wave V CS by the second comparator 72. When the peak value of V CS touches V SS , the output of the eleventh flip - flop 71 is set to "0", and the eleventh flip - flop 71 transfers the signal vref at the D terminal to the output V SST and sets it to "1" at the falling edge of the clock signal CLK_N1. Therefore, the period of V SST is the same as that of CLK_N1, and the starting point of the positive pulse width of V SST is the falling edge of CLK_N1. Here, CLK_N1 is the inverted signal of CLK through the fourth inverter 81. Therefore, the period of V SST is the same as that of CLK, and the starting point of the positive pulse width is the rising edge of CLK, and the ending point of the positive pulse width is the peak point of V SST . Let the positive pulse width time of V SST be T CS . Then there is: SST The positive pulse width time of V SST is T

[0183] T SST = βVSS / R CS = βVstep(1 + Q7 + 2Q8 + 4Q9) / R CS (14)

[0184] where β = L P / V LP ,L P is the inductance of the primary coil of transformer TR, and V LP is the voltage across L P . Then, the output voltage pulse width control signal V SW within each CLK clock cycle T SST is:

[0185] V SST = vref, 0 ≤ t ≤ T SST (15)

[0186] V SST = 0, T SST < t ≤ T SW (16)

[0187] Since V SS is clipped by the triangular wave V CS by the second comparator 72, so V SS is the envelope voltage of the peak value of V CS . V SS starts from near zero potential and slowly ramps up to V SS within the soft start time T CSTH , so V SS well limits the peak value of V CS , completes the soft start function of the primary coil current I P of the transformer, and protects the power transistor M1 safely. Therefore, the following equation holds:

[0188] I P = V CS / R CS = Vstep(1 + Q7 + 2Q8 + 4Q9) / R CS (17)

[0189] I P_MIN = V CSL / R CS = Vstep(1 + 0 + 0 + 0) / R CS (18)

[0190] I P_MAX = V CSTH / R CS = Vstep(1 + 1 + 2 + 4) / R CS (19)

[0191] Here I P_MIN 、I P_MAX is the minimum and maximum peak current limited by V SS during the soft start when CS is not shorted to the ground within T SST ; V P is the minimum value of V CSL during the soft start within T SS ; V CS is the current limiting voltage threshold of the switching power supply system. As CSTH shown in Figure 6 、 Figure 7 , both the traditional switching power supply system 10 and the novel switching power supply system 10A can complete the soft start, and the V CS peak value increases slowly from small to large for each cycle, that is, I P = V CS / R CS peak value increases slowly from small to large for each cycle, thus protecting the safety of the power transistor. Figures 6 to 9 In SS , due to the paper size limitation, in order to clearly demonstrate all the periodic signal waveforms, here, each V SS step voltage is simplified, and only 2-cycle waveforms are given for the principle demonstration. The actual situation is that each V CS step voltage contains approximately 128 cycles of V SW waveforms, V SST , CLK, V SST_TON .

[0192] Next, see Figure 3 again. In the first soft start pulse width generator circuit 77 in the figure, the periodic voltage triangular wave generator 79 inside, the charge and discharge capacitor C SST , when the soft start is initialized, the enable signal EN_N initializes it to zero voltage, and then it starts to charge and discharge according to the square wave of the CLK clock signal, generating a periodic voltage triangular wave signal V SAW . Its charge and discharge process is as follows:

[0193] When CLK is logic "1", the first switch K52 is closed, CLK_N is logic "0", the second switch K51 is open, and the first current source 65 charges C CH_OSC with I SST = I1, and V SAW rises from zero with a constant slope; when CLK flips to logic "0", the first switch K52 is open, CLK_N is logic "1", the second switch K51 is closed, and the second current source 67 discharges C DIS_OSC with I SST = 2I1, and V SAW starts to decline with a constant slope. Therefore, V SAWIn each CLK clock cycle T SW The expressions within are as follows:

[0194] V SAW = I CH_OSC × t / C SST = I1t / C SST , 0 ≤ t < D M T SW (20)

[0195] V SAW = I1 × t / C SST = I1D M T SW / C SST = V CSTH , t = D M T SW (21)

[0196] V SAW = I1D M T SW / C SST - I DIS_OSC × t / C SST

[0197] = V CSTH - I1t / C SST , D M T SW < t ≤ T SW (22)

[0198] Here, D M is the duty cycle of CLK, T SW is the CLK period, V SAW The maximum value is V CSTH .

[0199] Looking again Figure 3 , V SAW After being generated, it is compared with V SS through the first comparator 68 to generate a square wave signal EN SST_TON , EN SST_TON is OR - operated with the square wave CLK_N through the OR gate 69 to generate V SST_TON1 , because NQ10 is at logic "1" during the soft - start period T SS and has no effect on the NAND gate 75, so V SST_TON1 is inverted through the NAND gate 75 to obtain the voltage pulse - width signal V SST_TON . Let the positive pulse - width time of V SST_TON be T SST_TON , then within each CLK cycle T SW the T SST_TON , V SST_TON expressions are:

[0200] V SS = Vstep(1 + Q7 + 2Q8 + 4Q9)

[0201] = V SAW = I1T SST_TON / C SST , 0 ≤ T SST_TON < D M T SW (23)

[0202] T SST_TON = V SS C SST / I1 = C SST Vstep(1 + Q7 + 2Q8 + 4Q9) / I1 (24)

[0203] T SST_TON_MIN = C SST Vstep(1 + 0 + 0 + 0) / I1 = C SST Vstep / I1 (25)

[0204] V SST_TON = vref, 0 ≤ t ≤ T SST_TON (26)

[0205] V SST_TON = 0, T SST_TON < t ≤ T SW (27)

[0206] I P = T SST_TON / β = C SST Vstep(1 + Q7 + 2Q8 + 4Q9) / (βI1) (28)

[0207] I P_MIN1 = C SST Vstep(1 + 0 + 0 + 0) / (βI1) = C SST Vstep / (βI1) (29)

[0208] I P_MAX1 = C SST Vstep(1 + 1 + 2 + 4) / (βI1) = 8C SST Vstep / (βI1) (30)

[0209] Here I P_MIN1 、I P_MAX1 are the currents in L controlled by V during the soft start period T when CS is short - circuited to the ground SS within SST_TON L PThe minimum and maximum peak currents, which are independent of the CS pin signal V CS and exist independently. Equation (29) shows the initial V of soft start SS In the first step voltage step of P I P_MIN1 = I P After that, it increases step by step with time. The maximum value of I SS appears on the last V P step voltage step, which is 8Vstep. At this time, I P_MAX1 = I SST_TON_MIN In addition, T SST_TON is the minimum positive pulse width time of V SST_TON For the working waveform of V Figure 7 see SST_TON When V SW is 0, it can turn off the DRIVER output drive signal V SW That is, V Figure 9 = 0, and then turn off the power transistor M1. When the CS pin is shorted to the ground, the waveform of the new switching power supply system of the present invention is as shown in SST_TON Due to the existence of V P the peak value of I

[0210] When the time of T SS arrives, the soft start process ends. NQ10 is logic "0", and V SST_TON and V SST are always logic high.

[0211] V SST_TON = vref, 0 < t ≤ T SW (31)

[0212] V SS = vref >> V CSTH 0 < t ≤ T SW (32)

[0213] Since the PWM contains an overcurrent protector inside, and its overcurrent threshold is V CSTH During normal operation, it will limit V CS to V CSTH Therefore, when V SS = vref >> V CSTH the output EN SST of comparator 72 is always high, and V SST becomes always high, that is:

[0214] V SST = vref, 0 < t ≤ T SW (33)

[0215] Since VSST , V SST_TON The drive signal V can be turned off only when it is logic low SW and then the power transistor M1 is turned off. Therefore, after the soft-start process ends, V SST , V SST_TON no longer acts on the switching power supply system, and the power transistor M1 is controlled by the signal V at the pin FB FB .

[0216] The above is a complete soft-start working process of a new type of dual-control soft-start circuit 50A of the present invention under normal conditions. The timing waveform is shown in Figure 4 , Figure 5 , Figure 7 . The new type of switching power supply system 10A containing the new type of dual-control soft-start circuit 50A realizes the soft-start function

[0217] . The comparison of the working waveforms between the new type of switching power supply system 10A with the new type of dual-control soft-start circuit 50A and the traditional switching power supply system 10 when the CS pin is short-circuited to the ground is as shown in Figure 9 and Figure 8 . The comparison of the working waveforms under normal conditions is as shown in Figure 7 and Figure 6 .

[0218] From Figure 8 's waveform, it can be seen that when the CS pin of the traditional switching power supply system 10 is short-circuited to the ground, although it also has a short-circuit protection function, since the short-circuit protection requires the power transistor to be turned on for one cycle to detect whether the CS pin is short-circuited to the ground, as a result, the traditional switching power supply system 10 appears a V SW waveform with the maximum pulse width, which causes the current I P of the primary coil L P of the transformer TR to exceed the maximum rated current of the power transistor M1, damaging the power transistor M1. The current I P of the primary coil L P of the transformer TR when the CS pin of the traditional switching power supply system 10 is short-circuited to the ground is as follows

[0219] I P = I P_SCP = (V L / L P ) D M T SW = D M T SW / β (34)

[0220] Substituting equation (21) into (34) gives

[0221] I P = I P_SCP = D M T SW / β = CSST V CSTH / (βI1) (35)

[0222] From Figure 9 the waveform, it can be seen that when the CS pin of the switching power supply system of the present invention is short - circuited to the ground, a cycle of V waveform is also turned on. However, the positive pulse width of V SW is limited to the minimum value T SW by the positive pulse width time T SST_TON of the first cycle. As a result: SST_TON SST_TON_MIN SST_TON_MIN SST_TON_MIN

[0223] I P = I P_SCP = I P_MIN1 = C SST Vstep / (βI1) = C SST V CSTH / (8βI1) (36)

[0224] Therefore, the current I P in the primary coil L P of the transformer TR is 1 / 8 of that of the traditional switching power supply system, which is much smaller than the maximum rated current of the power transistor M1, protecting the safety of the power transistor M1 and also ensuring the safety of the user's electrical appliances.

[0225] Although the present invention is disclosed above with preferred embodiments, it should not limit the present invention. Any person skilled in this field, without departing from the spirit and scope of the present invention, can make some modifications and substitutions. For example, the present invention can be applied to the secondary - coil feedback switching power supply system with resistor start or high - voltage switch start, and also applicable to the primary - coil feedback switching power supply system with resistor start or high - voltage switch start. The safety of the switching power supply system applying this new double - control soft - start circuit is significantly better than other switching power supply systems, which can bring more safety guarantees to the user's switching power supply system. Therefore, the protection scope of the present invention shall be subject to that defined by the appended patent scope.

[0226] In this specification, each embodiment is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0227] In this article, specific examples are used to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the control method and its core idea of the present invention. At the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A dual-control soft-start circuit, characterized in that, Comprising: A reference voltage source, a first inverter, a second inverter, an AND gate, a frequency divider, a first soft-start pulse-width generator, and a second soft-start pulse-width generator; The input end of the reference voltage source is connected to the power supply port VDD, and the output end of the reference voltage source generates a reference voltage vref; The input end of the first inverter is connected to the enable signal EN output by the power-on and power-off enabling circuit, and the output end of the first inverter generates an inverted signal EN_N of the enable signal EN; The input end of the second inverter is connected to the tenth output end of the frequency divider, and the output end of the second inverter is connected to the first input end of the AND gate; the second input end of the AND gate is connected to the clock signal CLK output by the pulse-width modulator; the output end of the AND gate is connected to the first input end of the frequency divider; the second input end of the frequency divider is connected to the enable signal EN; the first to tenth output ends of the frequency divider respectively generate first to tenth digital frequency division signals Q1 to Q10; The first input terminal of the first soft start pulse width generator is connected to the reference voltage vref, the second input terminal of the first soft start pulse width generator is connected to the clock signal CLK, and the third input terminal of the first soft start pulse width generator is connected to the soft start voltage V SS ; the output terminal of the first soft start pulse width generator generates a first pulse width signal V SST_TON ; The first input terminal of the second soft start pulse width generator is connected to the reference voltage vref, the second input terminal of the second soft start pulse width generator is connected to the clock signal CLK, and the third input terminal of the second soft start pulse width generator is connected to the current limiting voltage V of the CS port CS ; the fourth to seventh input terminals of the second soft start pulse width generator are respectively connected to the seventh to tenth digital frequency division signals Q7 to Q10 output by the frequency divider; the first output terminal of the second soft start pulse width generator generates a soft start voltage V SS ; the second output terminal of the second soft start pulse width generator generates a second pulse width signal V SST .

2. The dual-control soft start circuit according to claim 1, characterized in that, The frequency divider includes: first to tenth flip-flops connected in electrical series; Each flip-flop includes a clock terminal CLK2, a clear terminal CLR, and an output terminal Q; the clock terminal CLK2 of the first flip-flop is the first input end of the frequency divider, and the clear terminal CLR of the first flip-flop is the second input end of the frequency divider; the output terminals Q of the first to tenth flip-flops are respectively the first to tenth output ends of the frequency divider; the clear terminals CLR of the first to tenth flip-flops are all connected to the enable signal EN; the output terminals Q of the first to ninth flip-flops are respectively connected to the clock terminals CLK2 of the second to tenth flip-flops.

3. The dual-control soft start circuit according to claim 1, wherein The first soft-start pulse-width generator includes: a voltage-period triangular wave generator, a first comparator, an OR gate, and a NAND gate; The first input terminal of the voltage-period triangular wave generator is the first input terminal of the first soft-start pulse width generator, the second input terminal of the voltage-period triangular wave generator is the second input terminal of the first soft-start pulse width generator, and the output terminal of the voltage-period triangular wave generator generates a voltage-period triangular wave signal V with the same frequency as the clock signal CLK. SAW The positive input terminal of the first comparator is connected to the voltage-period triangular wave signal V SAW , and the negative input terminal of the first comparator is the third input terminal of the first soft-start pulse width generator; the voltage input terminal of the first comparator is connected to the reference voltage vref; the output terminal of the first comparator is connected to the first input terminal of the OR gate; the second input terminal of the OR gate is connected to the inverted signal CLK_N of the clock signal CLK; the output terminal of the OR gate is connected to the first input terminal of the NAND gate; the second input terminal of the NAND gate is connected to the output terminal of the second inverter; the output terminal of the NAND gate is the output terminal of the first soft-start pulse width generator.

4. The dual-control soft start circuit according to claim 3, wherein The voltage-period triangular wave generator includes: a first current mirror, a second current mirror, a first switch, a second switch, a third inverter, an N-type switch transistor, and a first capacitor; The input end of the first current mirror is the first input end of the voltage-period triangular wave generator; the output end of the first current mirror is connected to the first connection end of the first switch; the second connection end of the first switch is respectively connected to the first connection end of the second switch, the drain of the N-type switch transistor, and one end of the first capacitor; the gate of the N-type switch transistor is connected to the inverted signal EN_N of the enable signal EN; the second connection end of the second switch is connected to the input end of the second current mirror; the output end of the second current mirror, the source of the N-type switch transistor, and the other end of the first capacitor are all grounded; the input end of the third inverter is the second input end of the voltage-period triangular wave generator; the input end of the third inverter is connected to the control end of the first switch; the output end of the third inverter is connected to the control end of the second switch; the drain of the N-type switch transistor is the output end of the voltage-period triangular wave generator.

5. The dual-control soft start circuit according to claim 1, characterized in that, The second soft-start pulse-width generator includes a digital-to-analog converter, a second comparator, a fourth inverter, and an eleventh flip-flop; The first to fourth input terminals of the digital-to-analog converter are respectively the fourth to seventh input terminals of the second soft-start pulse width generator; the voltage input terminal of the digital-to-analog converter is the first input terminal of the second soft-start pulse width generator; the output terminal of the digital-to-analog converter is the first output terminal of the second soft-start pulse width generator; the positive input terminal of the second comparator is connected to the soft-start voltage V SS ; the negative input terminal of the second comparator is the third input terminal of the second soft-start pulse width generator; the voltage input terminal of the second comparator is connected to the reference voltage vref; the output terminal of the second comparator is connected to the clear terminal CLR of the eleventh flip-flop; the input terminal of the fourth inverter is the second input terminal of the second soft-start pulse width generator; the output terminal of the fourth inverter is connected to the clock terminal CLK3 of the eleventh flip-flop; the input digital signal terminal D of the eleventh flip-flop is connected to the reference voltage vref; the output terminal Q of the eleventh flip-flop is the second output terminal of the second soft-start pulse width generator.

6. A switching power supply system, comprising: A transformer, a switch-mode power supply controller, a power switch transistor, and a feedback device; The switch-mode power supply controller includes: a power-on and power-off enabling circuit, a pulse-width modulator, and a drive circuit; Characterized in that the switching power supply controller further includes: a dual-control soft-start circuit as described in any one of claims 1-5; a first input terminal of the drive circuit is connected to the first pulse width signal V SST_TON ; a second input terminal of the drive circuit is connected to the second pulse width signal V SST ; an output terminal of the drive circuit is connected to a gate of the power switch transistor.

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