A method, system, device and medium for improving BRAM initialization speed in FPGA

Abstract

The embodiment of the present invention provides a method, system, device and medium for improving the initialization speed of BRAM in FPGA, using an additional bit CE_INV signal with a delayed pulse to perform an XOR logic operation with a first chip select enable signal with a wide pulse to obtain a second chip select enable signal with a narrow pulse, and the second chip select enable signal with a narrow pulse is used to automatically turn off the BRAM chip select signal during the initialization process in the BRAM, without the need to send an additional operation of turning off the BRAM chip select enable signal before the next write operation after each BRAM write operation is completed. The width of the narrow pulse is the time required to write data to a CFG bit in the configuration memory, which is much shorter than the cycle required to rewrite the chip select enable signal to 0 to ensure that the BRAM will not act before the next write operation, thus saving the initialization time of the BRAM and meeting the application requirements that require fast response.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of computer application technology, and in particular to a method, system, device and medium for improving the initialization speed of BRAM in FPGA. Background Art

[0002] In FPGA (Field-Programmable Gate Array), BRAM (Block Random Access Memory) generally needs to be initialized after power-on, and fixed data is input, so that it can be used as ROM. The more common initialization method is to send the required address, data, read / write enable, and chip select signal to BRAM in each cycle through the configuration memory. Since BRAM can only write one row of data each time, the chip select signal needs to be turned off before the next address and data are prepared. Wait until the next address and data are ready, then turn on the chip select signal. To achieve the above operation by configuring the memory, the process becomes to first send the address, data, read / write enable, and chip select enable (on) required for the first write to BRAM; then send the chip select enable (off) to BRAM; then send the address, data, read / write enable, and chip select enable (on) required for the second write to BRAM. Cycle in sequence, and finally send the closed chip select enable to BRAM after all data is written. When the FPGA capacity becomes larger and larger, it will take more time for the configuration memory to send a single chip select enable to turn off between two write operations. For applications that require fast response, initialization time becomes more important. Summary of the invention

[0003] To this end, the embodiments of the present invention provide a method, system, device and medium for improving the initialization speed of BRAM in FPGA, so as to solve the technical problem that the initialization time of BRAM in the existing FPGA is long and cannot meet the application requirements that require fast response.

[0004] In order to achieve the above purpose, the embodiment of the present invention provides the following technical solutions:

[0005] According to a first aspect of an embodiment of the present invention, an embodiment of the present application provides a method for improving the initialization speed of a BRAM in an FPGA, the method comprising:

[0006] For the first chip select enable signal with a wide pulse, an additional bit CE_INV signal with a delayed pulse is configured;

[0007] Performing an XOR logic operation on the first chip select enable signal and the additional bit CE_INV signal to obtain a second chip select enable signal with a narrow pulse;

[0008] According to the second chip selection enable signal, the initialization data is controlled to be written into the BRAM in sequence according to the address sequence number.

[0009] Furthermore, for the first chip select enable signal with a wide pulse, an additional bit CE_INV signal with a delayed pulse is configured, including:

[0010] Writing the first chip select enable signal into a first storage address in a configuration memory;

[0011] After a preset time, a signal having the same pulse width as the first chip select enable signal is obtained and written into a second storage address in the configuration memory to form the additional bit CE_INV signal;

[0012] The address sequence number of the second storage address is higher than the address sequence number of the first storage address.

[0013] Further, performing an XOR logic operation on the first chip select enable signal and the additional bit CE_INV signal to obtain a second chip select enable signal with a narrow pulse includes:

[0014] When the first wide pulse of the first chip select enable signal starts, the first chip select enable signal becomes high. Since the address number of the second storage address is higher than the address number of the first storage address, the additional bit CE_INV signal is low. At this time, the two perform an exclusive OR logic operation, and the second chip select enable signal becomes high, and the first narrow pulse high signal begins to be generated;

[0015] After the preset time, the first wide pulse of the additional bit CE_INV signal starts, and the additional bit CE_INV signal also becomes high. At this time, the two perform an XOR logic operation, the second chip select enable signal becomes low, and the generated first narrow pulse ends;

[0016] When the first wide pulse of the first chip select enable signal ends, the first chip select enable signal becomes low, and since the address number of the second storage address is higher than the address number of the first storage address, the additional bit CE_INV signal is high, and at this time, the two perform an exclusive OR logic operation, and the second chip select enable signal becomes high, and the next narrow pulse high signal begins to be generated;

[0017] After the preset time, the first wide pulse of the additional bit CE_INV signal ends, and the

[0018] The additional bit CE_INV signal also becomes low, and the two perform an XOR logic operation, the second chip select enable signal becomes low, and the next narrow pulse generated ends;

[0019] The first chip select enable signal repeatedly generates wide pulses, the additional bit CE_INV signal repeatedly generates delayed wide pulses, the two are subjected to an exclusive OR logic operation, and the second chip select enable signal repeatedly generates narrow pulses;

[0020] Until the first chip select enable signal and the additional bit CE_INV signal simultaneously maintain low signals or high signals, at which time the two perform an exclusive OR logic operation, and the second chip select enable signal maintains a low signal.

[0021] Further, according to the second chip select enable signal, controlling the initialization data to be written into the BRAM in sequence according to the address sequence number, including:

[0022] When the second chip select enable signal becomes high and starts to generate a first narrow pulse high signal, start writing the initialization data into the first address in the BRAM through the data input terminal;

[0023] When the second chip select enable signal becomes low and the first narrow pulse generated ends, the initialization data is written into the first address in the BRAM through the data input terminal, and the initialization data is temporarily prohibited from being written into the BRAM through the data input terminal;

[0024] When the second chip select enable signal becomes high and starts to generate a high signal of the next narrow pulse, start writing the initialization data into the next address in the BRAM through the data input terminal;

[0025] When the second chip select enable signal becomes low and the next narrow pulse generated ends, the initialization data is written into the next address in the BRAM through the data input terminal, and the initialization data is temporarily prohibited from being written into the BRAM through the data input terminal;

[0026] As the second chip select enable signal repeatedly generates narrow pulses, the initialization data is controlled to be written into the BRAM in sequence according to the address sequence number;

[0027] Until the second chip select enable signal maintains a low signal, the initialization write operation of BARM is completed.

[0028] Further, according to the second chip select enable signal, controlling the initialization data to be written into the BRAM in sequence according to the address sequence number, further comprising:

[0029] When the second chip select enable signal becomes high each time and starts to generate a high signal of a narrow pulse, it is determined whether the memory address signal received via the ADDR input terminal jumps;

[0030] If the memory address signal jumps, the initialization data is written into the corresponding address in the BRAM through the data input terminal according to the memory address signal after the jump;

[0031] If the memory address signal does not jump, it is prohibited to write the initialization data into the BRAM through the data input terminal.

[0032] Further, according to the second chip select enable signal, controlling the initialization data to be written into the BRAM in sequence according to the address sequence number, further comprising:

[0033] When the second chip select enable signal becomes high each time and starts to generate a high signal of a narrow pulse, it is determined whether the write enable signal received through the WE signal input terminal is high;

[0034] If the write enable signal is high, the initialization data is written into the corresponding address in the BRAM through the data input terminal;

[0035] If the write enable signal is not high, the initialization data is prohibited from being written into the BRAM through the data input terminal.

[0036] According to a second aspect of an embodiment of the present invention, an embodiment of the present application provides a system for improving the initialization speed of BRAM in an FPGA, the system comprising:

[0037] A configuration module, used for configuring an additional bit CE_INV signal with a delayed pulse for a first chip select enable signal with a wide pulse;

[0038] An operation module, used for performing an XOR logic operation on the first chip select enable signal and the additional bit CE_INV signal to obtain a second chip select enable signal with a narrow pulse;

[0039] The control module is used to control the initialization data to be written into the BRAM in sequence according to the address sequence number according to the second chip selection enable signal.

[0040] Furthermore, for the first chip select enable signal with a wide pulse, an additional bit CE_INV signal with a delayed pulse is configured, including:

[0041] Writing the first chip select enable signal into a first storage address in a configuration memory;

[0042] After a preset time, a signal having the same pulse width as the first chip select enable signal is obtained and written into a second storage address in the configuration memory to form the additional bit CE_INV signal;

[0043] The address sequence number of the second storage address is higher than the address sequence number of the first storage address.

[0044] Further, performing an XOR logic operation on the first chip select enable signal and the additional bit CE_INV signal to obtain a second chip select enable signal with a narrow pulse includes:

[0045] When the first wide pulse of the first chip select enable signal starts, the first chip select enable signal becomes high. Since the address number of the second storage address is higher than the address number of the first storage address, the additional bit CE_INV signal is low. At this time, the two perform an exclusive OR logic operation, and the second chip select enable signal becomes high, and the first narrow pulse high signal begins to be generated;

[0046] After the preset time, the first wide pulse of the additional bit CE_INV signal starts, and the additional bit CE_INV signal also becomes high. At this time, the two perform an XOR logic operation, the second chip select enable signal becomes low, and the generated first narrow pulse ends;

[0047] When the first wide pulse of the first chip select enable signal ends, the first chip select enable signal becomes low, and since the address number of the second storage address is higher than the address number of the first storage address, the additional bit CE_INV signal is high, and at this time, the two perform an exclusive OR logic operation, and the second chip select enable signal becomes high, and the next narrow pulse high signal begins to be generated;

[0048] After the preset time, the first wide pulse of the additional bit CE_INV signal ends, and the additional bit CE_INV signal also becomes low. At this time, the two perform an XOR logic operation, the second chip select enable signal becomes low, and the next narrow pulse generated ends;

[0049] The first chip select enable signal repeatedly generates wide pulses, the additional bit CE_INV signal repeatedly generates delayed wide pulses, the two are subjected to an exclusive OR logic operation, and the second chip select enable signal repeatedly generates narrow pulses;

[0050] Until the first chip select enable signal and the additional bit CE_INV signal simultaneously maintain low signals or high signals, at which time the two perform an exclusive OR logic operation, and the second chip select enable signal maintains a low signal.

[0051] Further, according to the second chip select enable signal, controlling the initialization data to be written into the BRAM in sequence according to the address sequence number, including:

[0052] When the second chip select enable signal becomes high and starts to generate a first narrow pulse high signal, start writing the initialization data into the first address in the BRAM through the data input terminal;

[0053] When the second chip select enable signal becomes low and the first narrow pulse generated ends, the initialization data is written into the first address in the BRAM through the data input terminal, and the initialization data is temporarily prohibited from being written into the BRAM through the data input terminal;

[0054] When the second chip select enable signal becomes high and starts to generate a high signal of the next narrow pulse, start writing the initialization data into the next address in the BRAM through the data input terminal;

[0055] When the second chip select enable signal becomes low and the next narrow pulse generated ends, the initialization data is written into the next address in the BRAM through the data input terminal, and the initialization data is temporarily prohibited from being written into the BRAM through the data input terminal;

[0056] As the second chip select enable signal repeatedly generates narrow pulses, the initialization data is controlled to be written into the BRAM in sequence according to the address sequence number;

[0057] Until the second chip select enable signal maintains a low signal, the initialization write operation of BARM is completed.

[0058] Furthermore, the control module is also used for:

[0059] When the second chip select enable signal becomes high each time and starts to generate a high signal with a narrow pulse, it is determined whether the memory address signal received through the ADDR input terminal jumps; if the memory address signal jumps, the initialization data is written into the corresponding address in the BRAM through the data input terminal according to the memory address signal after the jump; if the memory address signal does not jump, it is prohibited to write the initialization data into the BRAM through the data input terminal; and / or

[0060] Each time the second chip select enable signal becomes high and starts to generate a high signal with a narrow pulse, it is determined whether the write enable signal received through the WE signal input terminal is high; if the write enable signal is high, the initialization data is written to the corresponding address in the BRAM through the data input terminal; if the write enable signal is not high, it is prohibited to write the initialization data into the BRAM through the data input terminal.

[0061] According to a third aspect of an embodiment of the present invention, there is provided a device for improving the initialization speed of BRAM in an FPGA, the device comprising: a processor and a memory;

[0062] The memory is used to store one or more program instructions;

[0063] The processor is used to run one or more program instructions to execute the steps of a method for improving the initialization speed of BRAM in FPGA as described in any one of the above items.

[0064] According to a third aspect of an embodiment of the present invention, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of a method for improving the initialization speed of BRAM in an FPGA as described in any one of the above items are implemented.

[0065] Compared with the prior art, the embodiment of the present application provides a method, system, device and medium for improving the initialization speed of BRAM in FPGA, using an additional bit CE_INV signal with a delayed pulse to perform an XOR logic operation with a first chip select enable signal of a wide pulse to obtain a second chip select enable signal of a narrow pulse, and the second chip select enable signal of a narrow pulse is used to automatically turn off the BRAM chip select signal during the initialization process in the BRAM, without the need to send an additional operation of turning off the BRAM chip select enable signal before the next write operation after each BRAM write operation is completed. The width of the narrow pulse is the time required to write data to a CFG bit in the configuration memory, which is much shorter than the cycle required to rewrite the chip select enable signal to 0 to ensure that the BRAM will not act before the next write operation, thus saving the initialization time of the BRAM and meeting the application requirements that require fast response. At the same time, since the frequency of the narrow pulse is much lower than the frequency of writing data in the BRAM, the time for writing data once to the CFG bit in the configuration memory is sufficient to ensure a write operation in the BRAM. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] In order to more clearly illustrate the implementation methods of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the implementation methods or the description of the prior art. Obviously, the drawings in the following description are only exemplary, and for ordinary technicians in this field, other implementation drawings can be derived from the provided drawings without creative work.

[0067] The structures, proportions, sizes, etc. illustrated in this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with the technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantial technical significance. Any structural modification, change in proportion or adjustment of size shall still fall within the scope of the technical contents disclosed in the present invention without affecting the effects and purposes that can be achieved by the present invention.

[0068] Figure 1 A schematic diagram of the logical structure of a system for improving the initialization speed of BRAM in FPGA provided by an embodiment of the present invention;

[0069] Figure 2 A schematic diagram of the corresponding relationship between the configuration memory and the BRAM provided in an embodiment of the present invention;

[0070] Figure 3 A flow chart of a method for improving the initialization speed of BRAM in FPGA provided by an embodiment of the present invention;

[0071] Figure 4 A schematic diagram of the corresponding relationship among the first chip select enable signal, the additional bit CE_INV signal, and the second chip select enable signal provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0072] The following is a description of the implementation of the present invention by specific embodiments. People familiar with the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0073] When BRAM is initialized, after each write operation is completed, the chip enable signal (CE, chip enable) corresponding to CFGBIT (Control Flow Guard, configuration memory) in the configuration memory needs to be written back to 0 to turn off the write operation of BRAM, which wastes a lot of configuration time.

[0074] The purpose of this application is to provide a method, system, device and medium for improving the initialization speed of BRAM in FPGA, and automatically turn off CE by using CE additional bit (additional bit CE_INV signal) in the circuit. The initialization time of BRAM in FPGA can be shortened, which can greatly improve the response speed.

[0075] In order to solve the above technical problems, Figure 1 As shown, an embodiment of the present application provides a system for improving the initialization speed of BRAM in FPGA, which specifically includes: a configuration module 1, a calculation module 2, and a control module 3.

[0076] Furthermore, the configuration module 1 is used to configure an additional bit CE_INV signal with a delayed pulse for the first chip select enable signal with a wide pulse; the operation module 2 is used to perform an XOR logic operation on the first chip select enable signal and the additional bit CE_INV signal to obtain a second chip select enable signal with a narrow pulse; the control module 3 is used to control the initialization data to be written into the BRAM in sequence according to the address sequence number according to the second chip select enable signal.

[0077] Furthermore, the control module 3 is also used to: determine whether the memory address signal received through the ADDR input terminal jumps each time the second chip select enable signal becomes high and starts to generate a high signal with a narrow pulse; if the memory address signal jumps, write the initialization data to the corresponding address in the BRAM through the data input terminal according to the memory address signal after the jump; if the memory address signal does not jump, it is prohibited to write the initialization data into the BRAM through the data input terminal.

[0078] Furthermore, the control module 3 is also used to: when the second chip select enable signal becomes high each time and starts to generate a high signal with a narrow pulse, determine whether the write enable signal received through the WE signal input terminal is high; if the write enable signal is high, write the initialization data to the corresponding address in the BRAM through the data input terminal; if the write enable signal is not high, prohibit the initialization data from being written into the BRAM through the data input terminal.

[0079] Compared with the prior art, the embodiment of the present application provides a system for improving the initialization speed of BRAM in FPGA, using an additional bit CE_INV signal with a delayed pulse to perform an XOR logic operation with a first chip select enable signal of a wide pulse to obtain a second chip select enable signal of a narrow pulse, and the second chip select enable signal of a narrow pulse is used to automatically turn off the BRAM chip select signal during the initialization process in the BRAM, without the need to send an additional operation of turning off the BRAM chip select enable signal before the next write operation after each BRAM write operation is completed. The width of the narrow pulse is the time required to write data to a CFG bit in the configuration memory, which is much shorter than the cycle required to rewrite the chip select enable signal to 0 to ensure that the BRAM will not act before the next write operation, thus saving the initialization time of the BRAM and meeting the application requirements that require fast response. At the same time, since the frequency of the narrow pulse is much lower than the frequency of writing data in the BRAM, the time for writing data to the CFG bit in the configuration memory is sufficient to ensure a write operation in the BRAM.

[0080] Corresponding to the above-disclosed system for improving the initialization speed of BRAM in FPGA, an embodiment of the present invention further discloses a method for improving the initialization speed of BRAM in FPGA. The following describes in detail a method for improving the initialization speed of BRAM in FPGA disclosed in an embodiment of the present invention in combination with the above-described system for improving the initialization speed of BRAM in FPGA.

[0081] In one embodiment of the present invention, Figure 3 As shown, the specific steps of a method for improving the BRAM initialization speed in FPGA provided by an embodiment of the present application are described in detail below.

[0082] Step S11: the configuration module 1 is used to configure an additional bit CE_INV signal with a delayed pulse for the first chip select enable signal with a wide pulse.

[0083] refer to Figure 2 Specifically, the above step S11 specifically includes: writing the first chip select enable signal into the first storage address in the configuration memory 4; after a preset time, taking a signal with the same pulse width as the first chip select enable signal, and writing it into the second storage address in the configuration memory 4 to form an additional bit CE_INV signal; the address number of the second storage address is higher than the address number of the first storage address.

[0084] Step S12: the operation module 2 is used to perform an XOR logic operation on the first chip select enable signal and the additional bit CE_INV signal to obtain a second chip select enable signal with a narrow pulse.

[0085] Specifically, refer to Figure 2 , the second chip select enable signal is sent from the CE_out signal output terminal of the configuration memory 4 to the BRAM 5 via the CE signal input terminal. Figure 4 The above step S12 specifically includes: when the first wide pulse of the first chip select enable signal starts, the first chip select enable signal becomes high. Since the address number of the second storage address is higher than the address number of the first storage address, the additional bit CE_INV signal is low. At this time, the two perform an exclusive OR logic operation, the second chip select enable signal becomes high, and the first narrow pulse high signal begins to be generated; after a preset time, the first wide pulse of the additional bit CE_INV signal starts, and the additional bit CE_INV signal also becomes high. At this time, the two perform an exclusive OR logic operation, the second chip select enable signal becomes low, and the generated first narrow pulse ends.

[0086] refer to Figure 4 Furthermore, when the first wide pulse of the first chip select enable signal ends, the first chip select enable signal becomes low. Since the address number of the second storage address is higher than the address number of the first storage address, the additional bit CE_INV signal is high. At this time, the two perform an exclusive OR logic operation, and the second chip select enable signal becomes high, and the next narrow pulse high signal begins to be generated; after a preset time, the first wide pulse of the additional bit CE_INV signal ends, and the additional bit CE_INV signal also becomes low. At this time, the two perform an exclusive OR logic operation, and the second chip select enable signal becomes low, and the next narrow pulse generated ends.

[0087] As described above, the first chip select enable signal repeatedly generates wide pulses, the additional bit CE_INV signal repeatedly generates delayed wide pulses, the two perform an XOR logic operation, and the second chip select enable signal repeatedly generates narrow pulses; until the first chip select enable signal and the additional bit CE_INV signal simultaneously maintain low signals or high signals, at which time the two perform an XOR logic operation and the second chip select enable signal maintains a low signal.

[0088] Step S13: the control module 3 is used to control the initialization data to be written into the BRAM in sequence according to the address sequence number according to the second chip selection enable signal.

[0089] refer to Figure 2 Specifically, the above step S13 specifically includes: when the second chip select enable signal becomes high and starts to generate a high signal of the first narrow pulse, start writing the initialization data into the first address in the BRAM 5 through the data input terminal (DI); when the second chip select enable signal becomes low and the generated first narrow pulse ends, complete writing the initialization data into the first address in the BRAM 5 through the data input terminal (DI, deta input), and temporarily prohibit writing the initialization data into the BRAM 5 through the data input terminal.

[0090] Furthermore, when the second chip select enable signal becomes high and starts to generate the next narrow pulse of high signal, the initialization data is started to be written to the next address in BRAM 5 through the data input terminal (DI); when the second chip select enable signal becomes low and the next narrow pulse generated ends, the initialization data is completed to be written to the next address in BRAM 5 through the data input terminal, and the initialization data is temporarily prohibited from being written to BRAM 5 through the data input terminal (DI).

[0091] As described above, as the second chip select enable signal repeatedly generates narrow pulses, the initialization data is controlled to be written into the BRAM 5 in sequence according to the address sequence number; until the second chip select enable signal maintains a low signal, the initialization write operation of the BRAM 5 is terminated.

[0092] Further, refer to Figure 2 The above step S13 specifically also includes: when the second chip select enable signal becomes high each time and starts to generate a high signal with a narrow pulse, it is determined whether the memory address signal received through the ADDR input terminal has a jump; if the memory address signal has a jump, the initialization data is written into the corresponding address in the BRAM 5 through the data input terminal according to the memory address signal after the jump; if the memory address signal has not jumped, it is prohibited to write the initialization data into the BRAM5 through the data input terminal (DI).

[0093] Further, refer to Figure 2The above step S13 specifically also includes: when the second chip select enable signal becomes high each time and starts to generate a high signal with a narrow pulse, it is determined whether the write enable signal received through the WE signal input terminal is high; if the write enable signal is high, the initialization data is written to the corresponding address in the BRAM 5 through the data input terminal; if the write enable signal is not high, it is prohibited to write the initialization data into the BRAM 5 through the data input terminal.

[0094] Compared with the prior art, the embodiment of the present application provides a method for improving the initialization speed of BRAM in FPGA, using an additional bit CE_INV signal with a delayed pulse to perform an XOR logic operation with a first chip select enable signal of a wide pulse to obtain a second chip select enable signal of a narrow pulse, and the second chip select enable signal of a narrow pulse is used to automatically turn off the BRAM chip select signal during the initialization process in the BRAM, without the need to send an additional operation of turning off the BRAM chip select enable signal before the next write operation after each BRAM write operation is completed. The width of the narrow pulse is the time required to write data to a CFG bit in the configuration memory, which is much shorter than the cycle required to rewrite the chip select enable signal to 0 to ensure that the BRAM will not act before the next write operation, thus saving the initialization time of the BRAM and meeting the application requirements that require fast response. At the same time, since the frequency of the narrow pulse is much lower than the frequency of writing data in the BRAM, the time for writing data once to the CFG bit in the configuration memory is sufficient to ensure a write operation in the BRAM.

[0095] In addition, an embodiment of the present invention also provides a device for improving the initialization speed of BRAM in FPGA, the device comprising: a processor and a memory; the memory is used to store one or more program instructions; the processor is used to run one or more program instructions to execute the steps of a method for improving the initialization speed of BRAM in FPGA as described in any of the above items.

[0096] In addition, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of a method for improving the initialization speed of BRAM in an FPGA as described in any of the above items are implemented.

[0097] In the embodiment of the present invention, the processor may be an integrated circuit chip having the signal processing capability. The processor may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0098] The methods, steps and logic block diagrams disclosed in the embodiments of the present invention can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiments of the present invention can be directly embodied as a hardware decoding processor for execution, or can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The processor reads the information in the storage medium and completes the steps of the above method in combination with its hardware.

[0099] The storage medium may be a memory, which may be, for example, a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memory.

[0100] Among them, the non-volatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory.

[0101] The volatile memory may be a random access memory (RAM) which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDRSDRAM), enhanced synchronous DRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus DRAM (DRRAM).

[0102] The storage media described in the embodiments of the present invention are intended to include, but are not limited to, these and any other suitable types of memory.

[0103] Those skilled in the art will appreciate that in one or more of the above examples, the functions described in the present invention can be implemented using a combination of hardware and software. When software is used, the corresponding functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of computer programs from one place to another. Storage media can be any available media that can be accessed by general or special-purpose computers.

[0104] Although the present invention has been described in detail above by general description and specific embodiments, it is obvious to those skilled in the art that some modifications or improvements can be made to the present invention. Therefore, these modifications or improvements made without departing from the spirit of the present invention all belong to the scope of protection claimed by the present invention.

Claims

1. A method for improving the initialization speed of BRAM in FPGA, characterized in that: The method comprises: For the first chip select enable signal with a wide pulse, an additional bit CE_INV signal with a delayed pulse is configured; Performing an XOR logic operation on the first chip select enable signal and the additional bit CE_INV signal to obtain a second chip select enable signal with a narrow pulse; According to the second chip select enable signal, controlling the initialization data to be written into the BRAM in sequence according to the address sequence number; For the first chip select enable signal with a wide pulse, an additional bit CE_INV signal with a delayed pulse is configured, including: Writing the first chip select enable signal into a first storage address in a configuration memory; After a preset time, a signal having the same pulse width as the first chip select enable signal is obtained and written into a second storage address in the configuration memory to form the additional bit CE_INV signal; The address sequence number of the second storage address is higher than the address sequence number of the first storage address; Performing an XOR logic operation on the first chip select enable signal and the additional bit CE_INV signal to obtain a second chip select enable signal with a narrow pulse includes: When the first wide pulse of the first chip select enable signal starts, the first chip select enable signal becomes high. Since the address number of the second storage address is higher than the address number of the first storage address, the additional bit CE_INV signal is low. At this time, the two perform an exclusive OR logic operation, and the second chip select enable signal becomes high, and the first narrow pulse high signal begins to be generated; After the preset time, the first wide pulse of the additional bit CE_INV signal starts, and the additional bit CE_INV signal also becomes high. At this time, the two perform an XOR logic operation, the second chip select enable signal becomes low, and the generated first narrow pulse ends; When the first wide pulse of the first chip select enable signal ends, the first chip select enable signal becomes low, and since the address number of the second storage address is higher than the address number of the first storage address, the additional bit CE_INV signal is high, and at this time, the two perform an exclusive OR logic operation, and the second chip select enable signal becomes high, and the next narrow pulse high signal begins to be generated; After the preset time, the first wide pulse of the additional bit CE_INV signal ends, and the additional bit CE_INV signal also becomes low. At this time, the two perform an XOR logic operation, the second chip select enable signal becomes low, and the next narrow pulse generated ends; The first chip select enable signal repeatedly generates wide pulses, the additional bit CE_INV signal repeatedly generates delayed wide pulses, the two are subjected to an exclusive OR logic operation, and the second chip select enable signal repeatedly generates narrow pulses; Until the first chip select enable signal and the additional bit CE_INV signal both maintain low signals or high signals, at which time the two perform an exclusive OR logic operation, and the second chip select enable signal maintains a low signal; According to the second chip select enable signal, controlling the initialization data to be written into the BRAM in sequence according to the address sequence number, including: When the second chip select enable signal becomes high and starts to generate a first narrow pulse high signal, start writing the initialization data into the first address in the BRAM through the data input terminal; When the second chip select enable signal becomes low and the first narrow pulse generated ends, the initialization data is written into the first address in the BRAM through the data input terminal, and the initialization data is temporarily prohibited from being written into the BRAM through the data input terminal; When the second chip select enable signal becomes high and starts to generate a high signal of the next narrow pulse, start writing the initialization data into the next address in the BRAM through the data input terminal; When the second chip select enable signal becomes low and the next narrow pulse generated ends, the initialization data is written into the next address in the BRAM through the data input terminal, and the initialization data is temporarily prohibited from being written into the BRAM through the data input terminal; As the second chip select enable signal repeatedly generates narrow pulses, the initialization data is controlled to be written into the BRAM in sequence according to the address sequence number; Until the second chip select enable signal maintains a low signal, the initialization write operation of BARM is completed.

2. A method for improving the initialization speed of BRAM in FPGA as claimed in claim 1, characterized in that: According to the second chip select enable signal, controlling the initialization data to be written into the BRAM in sequence according to the address sequence number, further comprising: When the second chip select enable signal becomes high each time and starts to generate a high signal of a narrow pulse, it is determined whether the memory address signal received via the ADDR input terminal jumps; If the memory address signal jumps, the initialization data is written into the corresponding address in the BRAM through the data input terminal according to the memory address signal after the jump; If the memory address signal does not jump, it is prohibited to write the initialization data into the BRAM through the data input terminal.

3. A method for improving the initialization speed of BRAM in FPGA as claimed in claim 1 or 2, characterized in that: According to the second chip select enable signal, controlling the initialization data to be written into the BRAM in sequence according to the address sequence number, further comprising: When the second chip select enable signal becomes high each time and starts to generate a high signal of a narrow pulse, it is determined whether the write enable signal received through the WE signal input terminal is high; If the write enable signal is high, the initialization data is written into the corresponding address in the BRAM through the data input terminal; If the write enable signal is not high, the initialization data is prohibited from being written into the BRAM through the data input terminal.

4. A system for improving the initialization speed of BRAM in FPGA, characterized in that: The system comprises: A configuration module, used for configuring an additional bit CE_INV signal with a delayed pulse for a first chip select enable signal with a wide pulse; An operation module, used for performing an XOR logic operation on the first chip select enable signal and the additional bit CE_INV signal to obtain a second chip select enable signal with a narrow pulse; A control module, configured to control the initialization data to be written into the BRAM in sequence according to the address sequence number according to the second chip selection enable signal; For the first chip select enable signal with a wide pulse, an additional bit CE_INV signal with a delayed pulse is configured, including: Writing the first chip select enable signal into a first storage address in a configuration memory; After a preset time, a signal having the same pulse width as the first chip select enable signal is obtained and written into a second storage address in the configuration memory to form the additional bit CE_INV signal; The address sequence number of the second storage address is higher than the address sequence number of the first storage address; Performing an XOR logic operation on the first chip select enable signal and the additional bit CE_INV signal to obtain a second chip select enable signal with a narrow pulse includes: When the first wide pulse of the first chip select enable signal starts, the first chip select enable signal becomes high. Since the address number of the second storage address is higher than the address number of the first storage address, the additional bit CE_INV signal is low. At this time, the two perform an exclusive OR logic operation, and the second chip select enable signal becomes high, and the first narrow pulse high signal begins to be generated; After the preset time, the first wide pulse of the additional bit CE_INV signal starts, and the additional bit CE_INV signal also becomes high. At this time, the two perform an XOR logic operation, the second chip select enable signal becomes low, and the generated first narrow pulse ends; When the first wide pulse of the first chip select enable signal ends, the first chip select enable signal becomes low, and since the address number of the second storage address is higher than the address number of the first storage address, the additional bit CE_INV signal is high, and at this time, the two perform an exclusive OR logic operation, and the second chip select enable signal becomes high, and the next narrow pulse high signal begins to be generated; After the preset time, the first wide pulse of the additional bit CE_INV signal ends, and the additional bit CE_INV signal also becomes low. At this time, the two perform an XOR logic operation, the second chip select enable signal becomes low, and the next narrow pulse generated ends; The first chip select enable signal repeatedly generates wide pulses, the additional bit CE_INV signal repeatedly generates delayed wide pulses, the two are subjected to an exclusive OR logic operation, and the second chip select enable signal repeatedly generates narrow pulses; Until the first chip select enable signal and the additional bit CE_INV signal both maintain low signals or high signals, at which time the two perform an exclusive OR logic operation, and the second chip select enable signal maintains a low signal; According to the second chip select enable signal, controlling the initialization data to be written into the BRAM in sequence according to the address sequence number, including: When the second chip select enable signal becomes high and starts to generate a first narrow pulse high signal, start writing the initialization data into the first address in the BRAM through the data input terminal; When the second chip select enable signal becomes low and the first narrow pulse generated ends, the initialization data is written into the first address in the BRAM through the data input terminal, and the initialization data is temporarily prohibited from being written into the BRAM through the data input terminal; When the second chip select enable signal becomes high and starts to generate a high signal of the next narrow pulse, start writing the initialization data into the next address in the BRAM through the data input terminal; When the second chip select enable signal becomes low and the next narrow pulse generated ends, the initialization data is written into the next address in the BRAM through the data input terminal, and the initialization data is temporarily prohibited from being written into the BRAM through the data input terminal; As the second chip select enable signal repeatedly generates narrow pulses, the initialization data is controlled to be written into the BRAM in sequence according to the address sequence number; Until the second chip select enable signal maintains a low signal, the initialization write operation of BARM is completed.

5. A system for improving the initialization speed of BRAM in FPGA as claimed in claim 4, characterized in that: The control module is also used for: When the second chip select enable signal becomes high each time and starts to generate a high signal of a narrow pulse, it is determined whether the memory address signal received via the ADDR input terminal jumps; If the memory address signal jumps, the initialization data is written into the corresponding address in the BRAM through the data input terminal according to the memory address signal after the jump; If the memory address signal does not jump, it is prohibited to write the initialization data into the BRAM through the data input terminal; and / or When the second chip select enable signal becomes high each time and starts to generate a high signal of a narrow pulse, it is determined whether the write enable signal received through the WE signal input terminal is high; If the write enable signal is high, the initialization data is written into the corresponding address in the BRAM through the data input terminal; If the write enable signal is not high, the initialization data is prohibited from being written into the BRAM through the data input terminal.

6. A device for improving the initialization speed of BRAM in FPGA, characterized in that: The device comprises: a processor and a memory; The memory is used to store one or more program instructions; The processor is used to run one or more program instructions to execute the steps of a method for improving the initialization speed of BRAM in FPGA as described in any one of claims 1 to 3.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of a method for improving the initialization speed of BRAM in an FPGA as claimed in any one of claims 1 to 3 are implemented.

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