Chip structure and manufacturing method, and electronic device
By introducing a highly thermally conductive thermal diffusion buffer layer and buffer zone into the chip structure, the chip expansion and explosion problems caused by excessive temperature during laser cutting are solved, and the stability and heat resistance of the chip are improved.
Patent Information
- Application Number
- CN202210735433.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-06-27
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2042-06-27
AI Technical Summary
During the chip production process, the chip expands or explodes due to excessive temperature and heat during laser cutting, causing abnormal phenomena.
A chip structure is designed, including a thermal diffusion buffer structure, including a high thermal conductivity thermal diffusion buffer layer and a thermal diffusion buffer zone, the buffer layer surrounds the edge of the second conductive layer, isolates other layers, and provides heat with voids below it. Diffusion buffer to absorb expansion deformation and relieve stress.
It effectively alleviates the problem of excessive local temperature during laser cutting, improves the stability of the chip, and prevents the risk of thermal rupture.
Smart Images
Figure CN115101485B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip manufacturing, and in particular to a chip structure and manufacturing method, and electronic equipment. Background Art
[0002] During the chip manufacturing process, the chips are not independent, but many chips are connected together as a whole. Only after most of the manufacturing process is completed, laser cutting is carried out to obtain independent chips. Figure 1 As shown. During the laser cutting process, very high temperature and heat will be generated in the local position of the cutting path. When the temperature and heat are too concentrated, the chip will expand or even explode during the cutting process, causing chip abnormality. Summary of the invention
[0003] In order to solve one of the above technical problems, the present invention provides a chip structure and a manufacturing method, and an electronic device.
[0004] A first aspect of an embodiment of the present invention provides a chip structure, including:
[0005] a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer,
[0006] a first conductive layer electrically connected to the first semiconductor layer, a reflective layer electrically connected to the first conductive layer, a second conductive layer electrically connected to the reflective layer, and an electrode electrically connected to the second conductive layer, wherein the first conductive layer, the reflective layer, the second conductive layer and the electrode constitute a first electrically connected layer,
[0007] A recess that penetrates the first semiconductor layer and the active layer and extends to the inside of the second semiconductor layer, wherein a gap is formed in the recess,
[0008] a first insulating layer covering the sidewall of the recess and one side of the first electrical connection layer, a third conductive layer partially contacting the insulating layer and partially electrically connected to the second semiconductor layer through the recess,
[0009] a substrate in contact with the third conductive layer,
[0010] The chip structure also includes a heat diffusion buffer structure, which includes a heat diffusion buffer layer and a heat diffusion buffer zone. The heat diffusion buffer layer is arranged around the edge of the second conductive layer and is isolated from the first electrical connection layer, the first semiconductor layer, the second semiconductor layer, the active layer and the third conductive layer. The heat diffusion buffer zone is located directly below the heat diffusion buffer layer, and the heat diffusion buffer zone includes a third conductive layer with gaps.
[0011] Optionally, the chip structure further includes a second insulating layer which is partially located between the first semiconductor layer and the second conductive layer, adjacent to the side surfaces of the first conductive layer and the reflective layer, and partially exposed outside the first semiconductor layer.
[0012] Optionally, the heat diffusion buffer layer and the second conductive layer are made of the same material.
[0013] Optionally, the thermal conductivity of the heat diffusion buffer layer is greater than 10 W / (m·K).
[0014] Optionally, the gap in the heat diffusion buffer zone has an opening, and the opening is located toward the outside of the chip structure.
[0015] Optionally, the gap in the heat diffusion buffer zone has an opening, and the opening is located toward the outside of the chip structure.
[0016] Optionally, the reflective layer, the second conductive layer, the third conductive layer and the electrode are all multi-layer metal layers.
[0017] Optionally, when the substrate is a non-conductive material, the third conductive layer is a second electrical connection layer; when the substrate is conductive, the third conductive layer and the substrate form a second electrical connection layer.
[0018] A second aspect of an embodiment of the present invention provides a method for manufacturing a chip structure, the method comprising:
[0019] A second semiconductor layer, an active layer and a first semiconductor layer are sequentially grown on an epitaxial growth substrate, and at least two recesses are formed which penetrate through the first semiconductor layer and the active layer and extend into the second semiconductor layer, wherein at least one recess is located at an edge of the chip and surrounds most of the edge of the chip, and at least one recess is located inside the chip;
[0020] A first conductive layer and a reflective layer are sequentially formed on a portion of the surface of the first semiconductor layer, a second conductive layer is formed on a portion of the surface of the first semiconductor layer, the side surfaces of the first conductive layer and the reflective layer, and the surface of the reflective layer, and a heat diffusion buffer layer is formed on the remaining portion of the surface of the first semiconductor layer and the side surface of the chip edge recess, and a gap is left between the heat diffusion buffer layer and the adjacent side surface of the second conductive layer;
[0021] A first insulating layer is formed on the surface of the second conductive layer, the surface of the heat diffusion buffer layer and the side of the recess inside the chip, and the first insulating layer is filled in the gap between the heat diffusion buffer layer and the adjacent side of the second conductive layer;
[0022] A third conductive layer is formed on the surface of the first insulating layer and the surface of the substrate respectively, and the third conductive layer on the surface of the first insulating layer is electrically connected to the second semiconductor layer through a recess inside the chip. When the third conductive layer on the surface of the first insulating layer and the third conductive layer on the surface of the substrate are connected as one, gaps are formed inside the third conductive layer at all recessed positions, wherein the third conductive layer located at the edge of the chip and having gaps inside forms a heat diffusion buffer zone;
[0023] The epitaxial growth substrate is removed, the redundant second semiconductor layer, the active layer and the first semiconductor layer are removed, and electrodes electrically connected to the second conductive layer are fabricated to obtain a chip board composed of multiple chip structures;
[0024] Cutting is performed at the location of the heat diffusion buffer layer to obtain an independent chip structure.
[0025] Optionally, the method further comprises:
[0026] Form a second insulating layer on the remaining surface of the first semiconductor layer, and arrange the second insulating layer around the first conductive layer and the reflective layer;
[0027] A second conductive layer is fabricated on the surface of the first conductive layer and part of the surface of the second insulating layer, and a heat diffusion buffer layer is fabricated on the remaining surface of the second insulating layer and the recessed side of the chip edge, with a gap left between the heat diffusion buffer layer and the adjacent side of the second conductive layer.
[0028] A third aspect of the embodiments of the present invention provides an electronic device, wherein the electronic device includes the chip structure described in the first aspect of the embodiments of the present invention.
[0029] The beneficial effects of the present invention are as follows: the chip structure and manufacturing method proposed in the present invention set a heat diffusion buffer layer at the edge of the conventional chip structure, the heat diffusion buffer layer has a high thermal conductivity, and can diffuse a large amount of heat generated during the laser cutting of the chip to the adjacent area, effectively alleviating the problem of excessively high local temperature during the cutting process, and improving the stability of the chip. At the same time, a heat diffusion buffer zone is set below the heat diffusion buffer layer, and there is a gap in the heat diffusion buffer zone, which can effectively absorb the expansion deformation generated by the chip structure when heated during the laser cutting process, and alleviate the structural damage caused by stress accumulation. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0031] Figure 1 It is a schematic diagram of the chip board cutting process;
[0032] Figure 2 It is a structural schematic diagram of an existing chip structure;
[0033] Figure 3 This is a schematic structural diagram of a chip structure according to Embodiment 1 of the present invention;
[0034] Figure 4 This is a schematic diagram of the principle of the heat diffusion buffer layer and the heat diffusion buffer zone described in Example 1 of the present invention;
[0035] Figure 5 This is a schematic diagram of another chip structure according to Embodiment 1 of the present invention;
[0036] Figure 6 This is a flow chart of a chip structure manufacturing method according to Embodiment 2 of the present invention;
[0037] Figures 7 to 13 A schematic diagram of a manufacturing process of a chip structure according to Embodiment 2 of the present invention;
[0038] Fig.14 This is a flow chart of another chip structure manufacturing method according to Embodiment 2 of the present invention;
[0039] Figures 15 to 19 This is a schematic diagram of the manufacturing process of another chip structure described in Example 2 of the present invention.
[0040] Reference numerals:
[0041] 1. First semiconductor layer, 2. Second semiconductor layer, 3. Active layer, 4. First conductive layer, 5. Reflective layer, 6. Second conductive layer, 7. Electrode, 8. Recess, 9. First insulating layer, 10. Second insulating layer, 11. Third conductive layer, 12. Substrate, 13. Gap, 14. Thermal diffusion buffer layer, 15. Thermal diffusion buffer zone, 16. Epitaxial growth substrate. DETAILED DESCRIPTION
[0042] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.
[0043] Example 1
[0044] like Figure 2 The figure shows a chip structure, which specifically includes:
[0045] a first semiconductor layer 1, a second semiconductor layer 2, and an active layer 3 located between the first semiconductor layer 1 and the second semiconductor layer 2,
[0046] a first conductive layer 4 electrically connected to the first semiconductor layer 1, a reflective layer 5 electrically connected to the first conductive layer 4, a second conductive layer 6 electrically connected to the reflective layer 5, and an electrode 7 electrically connected to the second conductive layer 6; the first conductive layer 4, the reflective layer 5, the second conductive layer 6 and the electrode 7 constitute a first electrical connection layer;
[0047] A recess 8 penetrates through the first semiconductor layer 1 and the active layer 3 and extends to the inside of the second semiconductor layer 2, wherein a gap 13 is formed inside the recess 8.
[0048] a first insulating layer 9 covering the sidewall of the recess 8 and one side of the first electrical connection layer, a third conductive layer 11 partially contacting the first insulating layer 9 and partially electrically connected to the second semiconductor layer 2 through the recess 8,
[0049] A substrate 12 is in contact with the third conductive layer 11 .
[0050] Among them, the reflective layer 5, the second conductive layer 6, the third conductive layer 11 and the electrode 7 are all multi-layer metal layers. When the substrate 12 is a non-conductive material, the third conductive layer 11 is a second electrical connection layer; when the substrate 12 is conductive, the third conductive layer 11 and the substrate 12 form a second electrical connection layer. It should be noted that steps will appear at different positions between the third conductive layer 11 and the first insulating layer 9. In the actual production process, the height of the step is much smaller than the height of the depression, and no obvious gap will be formed at the step.
[0051] The above chip structure is a conventional structure of the existing chip structure. In the conventional structure of the chip structure, high heat is generated on the cutting path surface due to laser irradiation during the laser cutting process. This embodiment sets a heat diffusion buffer structure based on the above conventional chip structure. The heat diffusion buffer structure includes a heat diffusion buffer layer 14 and a heat diffusion buffer zone 15, such as Figure 3 As shown. The heat diffusion buffer layer 14 is located on the outside of the second conductive layer 6, that is, at the edge of the overall structure of the chip structure. The heat diffusion buffer layer 14 is also located on the route that the cutting path must pass when laser cutting the chip. The heat diffusion buffer layer 14 is made of a material with high thermal conductivity, such as a metal material, and the thermal conductivity is greater than 10W / (m·K). In this way, when laser cutting the chip, the heat diffusion buffer layer 14 can quickly diffuse a large amount of heat generated on the surface of the cutting path due to laser irradiation to adjacent areas, effectively alleviating the problem of local excessive temperature. In order to save the production cost of the heat diffusion buffer layer 14 and simplify the production process, the heat diffusion buffer layer 14 can use the same material and structure as the second conductive layer 6.
[0052] In addition, in this embodiment, since the heat diffusion buffer layer 14 only plays a role of heat conduction, in order not to affect the performance of the chip, when the heat diffusion buffer layer 14 is a conductive material, such as a metal material, the heat diffusion buffer layer 14 needs to be insulated from other structures to avoid electrical connection between the heat diffusion buffer layer 14 and other structures and affect the normal use of the chip. Specifically, this embodiment uses the existing first insulating layer 9 in the conventional chip structure to insulate the heat diffusion buffer layer 14 from the first electrical connection layer, the first semiconductor layer 1, the second semiconductor layer 2, the active layer 3 and the third conductive layer 11, and only the size of the first insulating layer 9 needs to be fine-tuned, and no complicated process will be generated.
[0053] Furthermore, the edge of the third conductive layer 11 is raised away from the substrate 12 to form a heat diffusion buffer zone 15 . The heat diffusion buffer zone 15 is insulated from the heat diffusion buffer layer 14 by the first insulating layer 9 , and a gap 13 is formed inside the heat diffusion buffer zone 15 .
[0054] Specifically, in the present embodiment, a heat diffusion buffer zone 15 is also provided at the edge of the chip structure and on the line of the laser cutting path. The heat diffusion buffer zone 15 is essentially produced by the same principle as the recess 8, and the present embodiment uses different naming methods to facilitate functional distinction between the two. A gap 13 is also formed inside the heat diffusion buffer zone 15. The gap 13 is caused by the excessive height difference between the recess 8 and the heat diffusion buffer zone 15 during the combination of the third conductive layer 11 under the heating and pressurizing process during the manufacturing process of the chip structure. Since this is a common phenomenon, this embodiment will not describe it in detail. The gap in the heat diffusion buffer zone 15 is a side-opening structure, and the opening faces the outside of the chip structure. The gap 13 inside the heat diffusion buffer zone 15 can achieve an excellent coordination effect with the heat diffusion buffer layer 14. As shown in FIG. Figure 4 As shown, when the heat during laser cutting causes the cutting path material to expand, the gap 13 inside the heat diffusion buffer layer 14 can effectively absorb part of the expanded volume, thereby buffering the material extrusion generated during the expansion process and effectively avoiding the risk of thermal cracking.
[0055] Furthermore, Figure 5 As shown, the chip structure of this embodiment also includes a second insulating layer that is partially located between the first semiconductor layer and the second conductive layer, adjacent to the sides of the first conductive layer and the reflective layer, and partially exposed to the outside of the first semiconductor layer. The second insulating layer can ensure a better insulation effect during the chip structure manufacturing process.
[0056] Example 2
[0057] This embodiment proposes a method for manufacturing a chip structure. The chip structure can refer to the content described in Example 1, and this embodiment will not repeat it. The method proposed in this embodiment first manufactures a chip board, and the chip board array is arranged with multiple independent chip structures. After the chip board is manufactured, laser cutting is performed to obtain independent chip structures. Figure 6 As shown, the method proposed in this embodiment includes the following steps:
[0058] S101. A second semiconductor layer 2, an active layer 3 and a first semiconductor layer 1 are grown in sequence on an epitaxial growth substrate 16, and at least two recesses 8 are made which penetrate the first semiconductor layer 1 and the active layer 3 and extend into the second semiconductor layer 2, wherein at least one recess is located at the edge of the chip and surrounds most of the edge of the chip.
[0059] First, the second semiconductor layer 2, the active layer 3 and the first semiconductor layer 1 are sequentially grown on the basis of the epitaxial growth substrate 16. Figure 7 Then, a UV mask patterning and chemical etching method is used to obtain a recess 8 that penetrates the first semiconductor layer 1 and the active layer 3 and extends to the inside of the second semiconductor layer 2, as shown. Figure 8 As shown, the recesses 8 are distributed in the middle region and edge region of the second semiconductor layer 2 .
[0060] S102. A first conductive layer 4 and a reflective layer 5 are sequentially fabricated on a portion of the surface of the first semiconductor layer 1; a second conductive layer 6 is fabricated on a portion of the surface of the first semiconductor layer 1, on the sides of the first conductive layer 4 and the reflective layer 5, and on the surface of the reflective layer 5; a heat diffusion buffer layer 14 is fabricated on the remaining portion of the surface of the first semiconductor layer 1 and on the recessed sides of the chip edge, with a gap being left between the heat diffusion buffer layer 14 and adjacent sides of the second conductive layer 6.
[0061] The first conductive layer 4 and the reflective layer 5 are sequentially formed on a portion of the surface of the first semiconductor layer 1 by using a UV mask imaging and physical evaporation method. Fig. 9 As shown. The second conductive layer 6 is formed on the partial surface of the first semiconductor layer 1, the side of the first conductive layer 4 and the reflective layer 5, and the surface of the reflective layer 5 by using the method of ultraviolet mask patterning and physical evaporation, and the heat diffusion buffer layer 14 is formed on the remaining surface of the first semiconductor layer 1 and the side of the chip edge recess, and a gap is left between the heat diffusion buffer layer 14 and the adjacent side of the second conductive layer 6, as shown in FIG. Fig.10 It should be noted that if the second conductive layer 6 and the heat diffusion buffer layer 14 have the same material and structure, they only need to be patterned by UV mask and physically evaporated once. If the second conductive layer 6 and the heat diffusion buffer layer 14 have different materials and structures, they need to be patterned by UV mask and physically evaporated twice at least.
[0062] S103 , a first insulating layer 9 is formed on the surface of the second conductive layer 6 , the surface of the heat diffusion buffer layer 14 and the side of the recess inside the chip, and the first insulating layer 9 is filled in the gap between the heat diffusion buffer layer 14 and the adjacent side of the second conductive layer 6 .
[0063] By vapor deposition, UV mask patterning and chemical etching, a first insulating layer 9 is formed on the surface of the second conductive layer 6, the surface of the heat diffusion buffer layer 14 and the side of the recess 8 inside the chip. Fig.11 And the first insulating layer 9 is filled in the gap between the heat diffusion buffer layer 14 and the adjacent side surfaces of the second conductive layer 6 to ensure that there is no electrical connection between the heat diffusion buffer layer 14 and the second conductive layer 6 .
[0064] S104. A third conductive layer 11 is respectively formed on the surface of the first insulating layer 9 and the surface of the substrate 12, and the third conductive layer 11 on the surface of the first insulating layer 9 is electrically connected to the second semiconductor layer 2 through the recess 8 inside the chip. When the third conductive layer 11 on the surface of the first insulating layer 9 and the third conductive layer 11 on the surface of the substrate 12 are connected as a whole, gaps 13 are formed inside the third conductive layer 11 at the positions of all the recesses 8, wherein the third conductive layer 11 located at the edge of the chip and having gaps inside forms a thermal diffusion buffer zone 15.
[0065] By physical evaporation, the third conductive layer 11 is formed on the surface of the first insulating layer 9 and the surface of the substrate 12, respectively, and the third conductive layer 11 on the surface of the first insulating layer 9 is electrically connected to the second semiconductor layer 2 through the recess 8 inside the chip. Fig.12 Then, under the conditions of heating and pressurization, the third conductive layer 11 on the surface of the first insulating layer 9 and the third conductive layer 11 on the surface of the substrate 12 are connected as a whole. In this process, due to the large height difference inside the recess 8, an obvious gap 13 will be left, as shown in FIG. Fig.13 As shown, the third conductive layer located at the edge of the chip and having a gap inside forms a heat diffusion buffer zone.
[0066] S105, removing the epitaxial growth substrate 16, removing the redundant second semiconductor layer 2, active layer 3 and first semiconductor layer 1, and making electrodes 7 electrically connected to the second conductive layer 6, to obtain a chip board consisting of multiple chip structures.
[0067] The epitaxial growth substrate 16 is removed, and the unnecessary second semiconductor layer 2, active layer 3 and first semiconductor layer 1 are removed by UV mask patterning and chemical etching. Then, the electrode 7 electrically connected to the second conductive layer 6 is obtained by physical evaporation, such as Figure 3 At this point, a chip board consisting of multiple chip structure arrays can be obtained.
[0068] S106 , cutting is performed at the position of the heat diffusion buffer layer 14 to obtain an independent chip structure.
[0069] Finally, an independent chip structure can be obtained by laser cutting only at the location of the heat diffusion buffer layer 14 .
[0070] Furthermore, the method proposed in this embodiment further comprises forming a second insulating layer before forming the first insulating layer. Fig.14 As shown, the specific process is:
[0071] A second insulating layer 10 is formed on the remaining surface of the first semiconductor layer 1, and the second insulating layer 10 is disposed around the first conductive layer 4 and the reflective layer 5;
[0072] A second conductive layer 6 is fabricated on the surface of the first conductive layer 4 and part of the surface of the second insulating layer 10, and a heat diffusion buffer layer 14 is fabricated on the remaining surface of the second insulating layer 10 and the recessed side of the chip edge, with a gap left between the heat diffusion buffer layer 14 and the adjacent side of the second conductive layer 6.
[0073] The first conductive layer 4 and the reflective layer 5 are sequentially formed on a portion of the surface of the first semiconductor layer 1 by using a UV mask imaging and physical evaporation method. Fig. 9 Then, the second insulating layer 10 is obtained by vapor deposition, UV mask patterning and chemical etching. Fig.15 As shown. The side of the second insulating layer 10 is in contact with the side of the first conductive layer 4 and the reflective layer 5. The second conductive layer 6 is formed on the surface of the first conductive layer 4 and part of the surface of the second insulating layer 10 by using UV mask patterning and physical evaporation methods, and the heat diffusion buffer layer 14 is formed on the remaining surface of the second insulating layer 10, and a gap is left between the heat diffusion buffer layer 14 and the adjacent side of the second conductive layer 6, as shown in FIG. Fig.16 shown.
[0074] The second insulating layer 10 can ensure a better insulation effect during the chip structure manufacturing process. Except for the difference in the process of manufacturing the second insulating layer 10, the other manufacturing processes are the same as the process of the chip structure without the second insulating layer 10, and will not be described in detail in this embodiment. The specific manufacturing process is as follows Figures 17 to 19 shown.
[0075] Example 3
[0076] This embodiment provides an electronic device, which includes the chip structure described in Embodiment 1, and will not be described in detail here.
[0077] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
Claims
1. A chip structure, comprising: a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer, a first conductive layer electrically connected to the first semiconductor layer, a reflective layer electrically connected to the first conductive layer, a second conductive layer electrically connected to the reflective layer, and an electrode electrically connected to the second conductive layer, wherein the first conductive layer, the reflective layer, the second conductive layer and the electrode constitute a first electrically connected layer, A recess that penetrates the first semiconductor layer and the active layer and extends to the inside of the second semiconductor layer, wherein a gap is formed in the recess, a first insulating layer covering the sidewall of the recess and one side of the first electrical connection layer, a third conductive layer partially contacting the insulating layer and partially electrically connected to the second semiconductor layer through the recess, a substrate in contact with the third conductive layer, It is characterized in that the chip structure also includes a heat diffusion buffer structure, which includes a heat diffusion buffer layer and a heat diffusion buffer zone, the heat diffusion buffer layer is arranged around the edge of the second conductive layer and is isolated from the first electrical connection layer, the first semiconductor layer, the second semiconductor layer, the active layer and the third conductive layer, the heat diffusion buffer zone is located directly below the heat diffusion buffer layer, and the heat diffusion buffer zone includes a third conductive layer with gaps.
2. The chip structure according to claim 1, characterized in that: The chip structure further includes a second insulating layer which is partially located between the first semiconductor layer and the second conductive layer, adjacent to the side surfaces of the first conductive layer and the reflective layer, and partially exposed outside the first semiconductor layer.
3. The chip structure according to claim 1, characterized in that: The heat diffusion buffer layer and the second conductive layer are made of the same material.
4. The chip structure according to claim 1, characterized in that: The thermal conductivity of the heat diffusion buffer layer is greater than 10 W / (m·K). 5 . The chip structure according to claim 1 , wherein the gap in the heat diffusion buffer zone has an opening, and the opening is located toward the outside of the chip structure.
6. The chip structure according to claim 1, characterized in that: The reflective layer, the second conductive layer, the third conductive layer and the electrode are all multi-layer metal layers.
7. The chip structure according to claim 1, characterized in that: When the substrate is made of a non-conductive material, the third conductive layer is a second electrical connection layer; when the substrate is conductive, the third conductive layer and the substrate form a second electrical connection layer.
8. A method for manufacturing a chip structure, characterized in that: The method comprises: A second semiconductor layer, an active layer and a first semiconductor layer are sequentially grown on an epitaxial growth substrate, and at least two recesses are formed which penetrate through the first semiconductor layer and the active layer and extend into the second semiconductor layer, wherein at least one recess is located at an edge of the chip and surrounds most of the edge of the chip, and at least one recess is located inside the chip; A first conductive layer and a reflective layer are sequentially formed on a portion of the surface of the first semiconductor layer, a second conductive layer is formed on a portion of the surface of the first semiconductor layer, the side surfaces of the first conductive layer and the reflective layer, and the surface of the reflective layer, and a heat diffusion buffer layer is formed on the remaining portion of the surface of the first semiconductor layer and the side surface of the chip edge recess, and a gap is left between the heat diffusion buffer layer and the adjacent side surface of the second conductive layer; A first insulating layer is formed on the surface of the second conductive layer, the surface of the heat diffusion buffer layer and the side of the recess inside the chip, and the first insulating layer is filled in the gap between the heat diffusion buffer layer and the adjacent side of the second conductive layer; A third conductive layer is formed on the surface of the first insulating layer and the surface of the substrate respectively, and the third conductive layer on the surface of the first insulating layer is electrically connected to the second semiconductor layer through a recess inside the chip. When the third conductive layer on the surface of the first insulating layer and the third conductive layer on the surface of the substrate are connected as one, gaps are formed inside the third conductive layer at all recessed positions, wherein the third conductive layer located at the edge of the chip and having gaps inside forms a heat diffusion buffer zone; The epitaxial growth substrate is removed, the redundant second semiconductor layer, the active layer and the first semiconductor layer are removed, and electrodes electrically connected to the second conductive layer are fabricated to obtain a chip board composed of multiple chip structures; Cutting is performed at the location of the heat diffusion buffer layer to obtain an independent chip structure.
9. The method according to claim 8, characterized in that The method further comprises: Form a second insulating layer on the remaining surface of the first semiconductor layer, and arrange the second insulating layer around the first conductive layer and the reflective layer; A second conductive layer is fabricated on the surface of the first conductive layer and part of the surface of the second insulating layer, and a heat diffusion buffer layer is fabricated on the remaining surface of the second insulating layer and the recessed side of the chip edge, with a gap left between the heat diffusion buffer layer and the adjacent side of the second conductive layer.
10. An electronic device, characterized in that: The electronic device comprises the chip structure according to any one of claims 1 to 7.