Display substrate and manufacturing method thereof, and display device

Abstract

The present disclosure provides a display substrate, a preparation method thereof, and a display device. The display substrate of the present disclosure includes a display area and a binding area located on one side of the display area, the binding area includes a lead area, a first transition area, a bending area, a second transition area, and a binding pin area sequentially arranged in a direction away from the display area; on a plane perpendicular to the display substrate, the lead area and the binding pin area include a composite insulating layer arranged on a substrate and a metal wire arranged on a side of the composite insulating layer away from the substrate, the first transition area and the second transition area include a composite insulating layer arranged on a substrate, an inorganic insulating layer arranged on a side of the composite insulating layer away from the substrate, and a metal wire arranged on a side of the inorganic insulating layer away from the substrate; the binding area is also provided with a structural hole for maintaining the thickness of the photoresist in the first transition area and the second transition area. The present disclosure reduces the risk of metal wire breakage in the existing display device through the provided structural holes.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a method for preparing the same, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field.

[0003] The inventor of the present application has found through research that the existing OLED display device has the problem of metal disconnection. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by the present disclosure is to provide a display substrate and a preparation method thereof and a display device, so as to overcome the problem of metal disconnection in the existing OLED display device.

[0006] On the one hand, the present disclosure provides a display substrate, including a display area and a binding area located on one side of the display area, the binding area including a lead area, a first transition area, a bending area, a second transition area and a binding pin area arranged in sequence along a direction away from the display area; on a plane perpendicular to the display substrate, the lead area and the binding pin area include a composite insulating layer arranged on a substrate and a metal wire arranged on a side of the composite insulating layer away from the substrate, the first transition area and the second transition area include a composite insulating layer arranged on the substrate, an inorganic insulating layer arranged on a side of the composite insulating layer away from the substrate, and a metal wire arranged on a side of the inorganic insulating layer away from the substrate; the binding area is also provided with structural holes for maintaining the thickness of the photoresist in the first transition area and the second transition area.

[0007] In an exemplary embodiment, at least one structural hole is disposed in at least one or more of the lead region, the first transition region, the second transition region, and the binding pin region, and the structural hole is disposed on the metal wire.

[0008] In an exemplary embodiment, the structural hole includes a first structural hole, and the first structural hole is disposed at any one or more of the following positions: the lead area and the first transition area.

[0009] In an exemplary embodiment, the first structural hole of the lead region is disposed in a region of the lead region close to the first transition region, and the first structural hole of the first transition region is disposed in a region of the first transition region close to the lead region.

[0010] In an exemplary embodiment, the first transition zone includes a first climbing zone and a first flat zone, the first climbing zone is located on a side of the first transition zone close to the lead zone, the first flat zone is located on a side of the first climbing zone away from the lead zone, and the first structural hole is arranged on a metal line of the first flat zone.

[0011] In an exemplary embodiment, the structural hole includes a second structural hole, and the second structural hole is arranged at any one or more of the following positions: the binding pin area and the second transition area.

[0012] In an exemplary embodiment, the second structural hole of the binding pin area is disposed in a region of the binding pin area close to the second transition area, and the second structural hole of the second transition area is disposed in a region of the second transition area close to the binding pin area.

[0013] In an exemplary embodiment, the second transition zone includes a second climbing zone and a second flat zone, the second climbing zone is located on a side of the second transition zone close to the binding pin zone, the second flat zone is located on a side of the second climbing zone away from the binding pin zone, and the second structural hole is arranged on the metal line of the second flat zone.

[0014] In an exemplary embodiment, at least one structural hole is disposed in at least one or more of the first transition region and the second transition region, and the structural hole is disposed on the inorganic insulating layer.

[0015] In an exemplary embodiment, the structural holes include a third structural hole and a fourth structural hole, the third structural hole is disposed in the first transition region, and the fourth structural hole is disposed in the second transition region.

[0016] In an exemplary embodiment, the third structural hole is disposed in a region of the first transition region close to the lead region, and the fourth structural hole is disposed in a region of the second transition region close to the binding pin region.

[0017] In an exemplary embodiment, the metal wire covers the hole wall and the hole bottom of the third structure hole, and the metal wire covers the hole wall and the hole bottom of the fourth structure hole.

[0018] In an exemplary embodiment, the shape of the structural hole includes any one or more of the following: triangle, rectangle, pentagon, hexagon, circle and ellipse.

[0019] In an exemplary embodiment, the shape of the structural hole is circular, the diameter of the structural hole is greater than or equal to 1 / 4 of the width of the metal wire, the diameter of the structural hole is less than or equal to 2 / 3 of the width of the metal wire, and the width of the metal wire is the dimension perpendicular to the extension direction of the metal wire.

[0020] In an exemplary embodiment, the areas of the plurality of structural holes are the same.

[0021] In an exemplary embodiment, the areas of the plurality of structural holes gradually increase along a direction away from the display area, or, along a direction approaching the display area, the areas of the plurality of structural holes gradually increase.

[0022] In an exemplary embodiment, the areas of the multiple structural holes in the lead area gradually increase along the direction away from the first transition area; the areas of the multiple structural holes in the first transition area gradually increase along the direction away from the lead area; the areas of the multiple structural holes in the second transition area gradually increase along the direction away from the binding pin area; and the areas of the multiple structural holes in the binding pin area gradually increase along the direction away from the second transition area.

[0023] On the other hand, the present disclosure further provides a display device, comprising the aforementioned display substrate.

[0024] In another aspect, the present disclosure further provides a method for preparing a display substrate, the display substrate comprising a display area and a binding area located on one side of the display area, the binding area comprising a lead area, a first transition area, a bending area, a second transition area, and a binding pin area sequentially arranged in a direction away from the display area; the preparation method comprises:

[0025] A composite insulating layer arranged on the substrate and a metal wire arranged on the side of the composite insulating layer away from the substrate are formed in the lead area and the binding pin area, and a composite insulating layer arranged on the substrate, an inorganic insulating layer arranged on the side of the composite insulating layer away from the substrate and a metal wire arranged on the side of the inorganic insulating layer away from the substrate are formed in the first transition area and the second transition area; the binding area is also formed with structural holes that maintain the thickness of the photoresist in the first transition area and the second transition area.

[0026] The present disclosure provides a display substrate, a preparation method thereof and a display device, which reduces the flow of photoresist caused by the step structure in metal patterning by setting structural holes in the binding area, maintains the photoresist thickness in the first transition area and the second transition area, and reduces the risk of metal disconnection.

[0027] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0029] Figure 1 is a structural schematic diagram of a display device;

[0030] Figure 2 It is a schematic diagram of a planar structure of a display substrate;

[0031] Figure 3 for Figure 2 A side view of the substrate is shown in FIG.

[0032] Figure 4 A schematic diagram of a planar structure of a display area;

[0033] Figure 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0034] Figure 6 is a working timing diagram of a pixel driving circuit;

[0035] Figure 7 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0036] Figure 8 is a schematic cross-sectional structure diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0037] Fig. 9 is a schematic diagram of forming a bending zone pattern according to an exemplary embodiment of the present disclosure;

[0038] Fig.10 is a schematic diagram of forming a third conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0039] Fig.11 is a schematic structural diagram of a first structural hole of an exemplary embodiment of the present disclosure;

[0040] Fig.12 is a schematic structural diagram of a second structural hole of an exemplary embodiment of the present disclosure;

[0041] Fig.13 is a schematic diagram of a planar structure of a first structural hole of an exemplary embodiment of the present disclosure;

[0042] FIG. 14A to FIG. 14E is a schematic diagram of a preparation process of a metal wire according to an exemplary embodiment of the present disclosure;

[0043] Fig.15 is a schematic structural diagram of another first structural hole according to an exemplary embodiment of the present disclosure;

[0044] Fig.16 is a structural schematic diagram of another first structural hole according to an exemplary embodiment of the present disclosure;

[0045] Fig.17 is a schematic diagram of a planar structure of another first structural hole according to an exemplary embodiment of the present disclosure;

[0046] Fig.18 is a schematic plan view of another first structural hole according to an exemplary embodiment of the present disclosure;

[0047] Fig.19 is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0048] Fig. 20 is a schematic structural diagram of a third structural hole of an exemplary embodiment of the present disclosure;

[0049] Fig.21 It is a schematic structural diagram of a fourth structural hole of an exemplary embodiment of the present disclosure.

[0050] Description of reference numerals:

[0051] 1-display substrate; 2-glass substrate; 10-base;

[0052] 11-first insulating layer; 12-second insulating layer; 13-third insulating layer;

[0053] 14-inorganic insulating layer; 15-metal wire; 20-photoresist;

[0054] 30-mask; 40-ultraviolet light; 50-first structure hole;

[0055] 51-second structural hole; 60-third structural hole; 61-fourth structural hole;

[0056] 100-display area; 101A-transistor; 101B-storage capacitor;

[0057] 200-binding area; 210-lead area; 220-first transition area;

[0058] 221-first climbing area; 222-first flat area; 230-bending area;

[0059] 231-bending groove; 240-second transition zone; 241-second climbing zone;

[0060] 242 - second flat area; 250 - binding pin area; 251 - binding pin;

[0061] 260-integrated circuit; 270-flexible circuit board; 300-border area. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0063] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0064] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0065] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0066] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0067] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0068] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0069] In this specification, triangles, squares, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, squares, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0070] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0071] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit may include at least one scan signal line, at least one data signal line, at least one light emitting signal line and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, may provide a clock signal suitable for the specifications of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specifications of the light emitting driver, an emission stop signal, etc. to the light emitting driver. The data driver may generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data driver may sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan driver may generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide a scan signal with a conduction level pulse to the scan signal lines S1 to Sm. For example, the scan driver may be constructed in the form of a shift register, and may sequentially transmit the scan start signal provided in the form of a conduction level pulse to the next level circuit under the control of the clock signal to generate a scan signal, where m may be a natural number. The light emitting driver may generate an emission signal to be provided to the light emitting signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be constructed in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number.

[0072] Figure 2 A schematic diagram of the planar structure of a display substrate, showing the unfolded state of the binding area before bending. Figure 3 for Figure 2 The side view of the substrate is shown in FIG. , which illustrates the bent state of the binding area after bending. Figure 2 and Figure 3 As shown, on a plane parallel to the display substrate 1, the display substrate 1 may include a display area 100 and an edge area located around the display area 100, and the edge area may include a binding area 200 located on one side of the display area 100 and a frame area 300 located on the other side of the display area 100. For example, the binding area 200 may be located on one side of the first direction D1 (the direction away from the display area) of the display area 100, and the frame area 300 may be located on both sides of the second direction D2 of the display area 100 and on one side of the display area 100 in the opposite direction of the first direction D1, and the first direction D1 and the second direction D2 intersect.

[0073] In an exemplary embodiment, the display area 100 may include a plurality of sub-pixels Pxij constituting a pixel array, the plurality of sub-pixels Pxij being configured to display an image, and the display area 100 may be deformable, such as curling, bending, folding or rolling up. The binding area 200 may include at least an isolation dam and a binding circuit, the binding circuit being configured to connect the signal line of the display area 100 to an external driving device. The border area 300 may include at least an isolation dam, a gate driving circuit, and a power line for transmitting a voltage signal to a plurality of sub-pixels, and the isolation dams of the binding area 200 and the border area 300 may be an integral structure, and may be prepared synchronously by the same patterning process to form a ring structure surrounding the display area 100.

[0074] In an exemplary embodiment, the binding area 200 may be bent and attached to the back surface of the display area 100 , and the binding area 200 may overlap with the display area 100 in a direction perpendicular to the plane of the display area.

[0075] In an exemplary embodiment, the binding area 200 may include a lead area 210 , a bending area 230 , and a binding pin area 250 which are sequentially disposed along a first direction D1 (a direction away from the display area).

[0076] In an exemplary embodiment, the lead area 210 may be provided with a plurality of lead wires. The bending area 230 may include a composite insulating layer provided with grooves, and the bending area 230 may be bent with a curvature in the third direction D3 (thickness direction), and the surface of the binding pin area 250 may be reversed, that is, the surface of the binding pin area 250 facing upward may be turned over to face downward by bending the bending area 230, and the third direction D3 intersects with the first direction D1. In an exemplary embodiment, when the bending area 230 is bent, the binding pin area 250 may overlap with the display area 100 in the third direction D3.

[0077] In an exemplary embodiment, the binding pin area 250 may include at least a driving chip and a plurality of binding pins (Bonding PIN), the driving chip may be an integrated circuit (IC) 260, the integrated circuit 260 may be connected to a plurality of signal leads, and an external flexible printed circuit (FPC) 270 may be bonded and connected to the plurality of binding pins. In an exemplary embodiment, the integrated circuit 260 may generate a driving signal required for driving a sub-pixel, and may provide the driving signal to the sub-pixel in the display area 100. For example, the driving signal may be a data signal for driving the brightness of the sub-pixel. In an exemplary embodiment, the integrated circuit 260 may be bonded and connected to the driving chip area by an anisotropic conductive film or other means, and the width of the integrated circuit 260 in the second direction D2 may be smaller than the width of the binding pin area 250 in the second direction D2.

[0078] Figure 4 FIG. 1 is a schematic diagram of a planar structure of a display area. Figure 4 As shown, the display area may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light, and the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 may each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the sub-pixels are respectively connected to the scanning signal lines, the data signal lines, and the light-emitting signal lines, and the pixel driving circuits are configured to receive the data voltage transmitted by the data signal lines under the control of the scanning signal lines and the light-emitting signal lines, and output the corresponding current to the light-emitting devices. The light-emitting devices in the sub-pixels are respectively connected to the pixel driving circuits of the sub-pixels in which they are located, and the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixels in which they are located.

[0079] In an exemplary embodiment, the first sub-pixel P1 may be a red (R) sub-pixel, the second sub-pixel P2 may be a green (G) sub-pixel, and the third sub-pixel P3 may be a blue (B) sub-pixel. In an exemplary embodiment, the shape of the sub-pixels in the pixel unit may be rectangular, rhombus, pentagonal or hexagonal, and the three sub-pixels may be arranged horizontally, vertically or in a herringbone manner. In some possible exemplary embodiments, the pixel unit may include four sub-pixels, and the four sub-pixels may be arranged horizontally, vertically, in a square or diamond shape, etc., which is not limited in the present disclosure.

[0080] Figure 5FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure. Figure 5 As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C, and the pixel driving circuit may be connected to 7 signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, initial signal line INIT, first power line VDD and second power line VSS).

[0081] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, the second node N2 is respectively connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the control electrode of the third transistor T3, and the second end of the storage capacitor C, and the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6.

[0082] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0083] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3, so that the charge amount of the control electrode of the third transistor T3 is initialized.

[0084] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.

[0085] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS according to the potential difference between its control electrode and the first electrode.

[0086] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, a scan transistor, etc. When the on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 enables the data voltage of the data signal line D to be input to the pixel driving circuit.

[0087] The control electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. The fifth transistor T5 and the sixth transistor T6 can be called light emitting transistors. When the on-level light emitting signal is applied to the light emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power line VDD and the second power line VSS to make the light emitting device emit light.

[0088] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. When the on-level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the initialization voltage to the first electrode of the light emitting device to initialize or release the charge accumulated in the first electrode of the light emitting device.

[0089] In an exemplary embodiment, the second electrode of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously provided high level signal. The first scanning signal line S1 is a scanning signal line in the pixel driving circuit of the current display row, and the second scanning signal line S2 is a scanning signal line in the pixel driving circuit of the previous display row, that is, for the nth display row, the first scanning signal line S1 is S(n), and the second scanning signal line S2 is S(n-1), and the second scanning signal line S2 of the current display row is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display row, which can reduce the signal lines of the display panel and realize the narrow frame of the display panel.

[0090] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.

[0091] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the emission signal line E and the initial signal line INIT extend in a horizontal direction, and the second power line VSS, the first power line VDD and the data signal line D extend in a vertical direction.

[0092] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0093] Figure 6 This is a working timing diagram of a pixel driving circuit. Figure 6 The operation process of the pixel driving circuit of the example is described in detail. Figure 6 The pixel driving circuit in the embodiment includes 7 transistors (a first transistor T1 to a sixth transistor T7) and a storage capacitor C, and all the 7 transistors are P-type transistors.

[0094] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0095] The first stage A1 is called the reset stage. The signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals. The signal of the second scanning signal line S2 is a low-level signal, which turns on the first transistor T1. The signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor. The signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, which turns off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7. In this stage, the OLED does not emit light.

[0096] The second stage A2 is called the data writing stage or the threshold compensation stage. The signal of the first scanning signal line S1 is a low level signal, the signals of the second scanning signal line S2 and the light emitting signal line E are high level signals, and the data signal line D outputs the data voltage. In this stage, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The signal of the first scanning signal line S1 is a low level signal, which turns on the second transistor T2, the fourth transistor T4 and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage of the second end (the second node N2) of the storage capacitor C is Vd-|Vth|, Vd is the data voltage output by the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is provided to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and the OLED is ensured not to emit light. The signal of the second scanning signal line S2 is a high-level signal, which turns off the first transistor T1. The signal of the light-emitting signal line E is a high-level signal, which turns off the fifth transistor T5 and the sixth transistor T6.

[0097] The third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals. The signal of the light-emitting signal line E is a low-level signal, which turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the OLED to emit light.

[0098] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0099] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0100] Among them, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0101] In order to meet the needs of high pixel density (PPI) in existing OLED display products, the signal transmission line is increased from the original one layer of metal to two or more layers, which requires more inorganic insulating layers to block different metal layers. The inventors of this application have found that since some positions need to retain the inorganic insulating layer, and some positions need to remove the inorganic insulating layer, a step structure with a certain height difference will be generated, and the step difference can usually reach about 2μm. When applying photoresist during metal patterning, due to the presence of the step structure, the photoresist at the inorganic insulating layer retention area, i.e., the high position, will be thinner due to its flow to the inorganic insulating layer removal area, i.e., the low position, so that when etching the metal, the metal at the position where the photoresist is thin will be cut off, resulting in the situation of metal disconnection, resulting in the product being unable to display normally or displaying unevenly. Although the disconnection problem can be overcome to a certain extent by increasing the photoresist coating thickness, increasing the photoresist coating thickness will cause the photoresist in the low position area to be too thick, reducing the uniformity of metal routing etching, resulting in uneven display problems.

[0102] An exemplary embodiment of the present disclosure provides a display substrate, comprising a display area and a binding area located on one side of the display area, wherein the binding area comprises a lead area, a first transition area, a bending area, a second transition area and a binding pin area which are sequentially arranged in a direction away from the display area; on a plane perpendicular to the display substrate, the lead area and the binding pin area comprise a composite insulating layer arranged on a substrate and a metal wire arranged on a side of the composite insulating layer away from the substrate, the first transition area and the second transition area comprise a composite insulating layer arranged on the substrate, an inorganic insulating layer arranged on a side of the composite insulating layer away from the substrate and a metal wire arranged on a side of the inorganic insulating layer away from the substrate; the binding area is also provided with structural holes for maintaining the thickness of the photoresist in the first transition area and the second transition area.

[0103] In an exemplary embodiment, at least one structural hole is disposed in at least one or more of the lead region, the first transition region, the second transition region, and the binding pin region, and the structural hole is disposed on the metal wire.

[0104] In an exemplary embodiment, at least one structural hole is disposed in at least one or more of the first transition region and the second transition region, and the structural hole is disposed on the inorganic insulating layer.

[0105] In an exemplary embodiment, the shape of the structural hole includes any one or more of the following: triangle, rectangle, pentagon, hexagon, circle and ellipse.

[0106] In an exemplary embodiment, the shape of the structural hole is circular, the diameter of the structural hole is greater than or equal to 1 / 4 of the width of the metal wire, the diameter of the structural hole is less than or equal to 2 / 3 of the width of the metal wire, and the width of the metal wire is the dimension perpendicular to the extension direction of the metal wire.

[0107] In an exemplary embodiment, the areas of the plurality of structural holes are the same.

[0108] In an exemplary embodiment, the areas of the plurality of structural holes gradually increase along a direction away from the display area, or, along a direction approaching the display area, the areas of the plurality of structural holes gradually increase.

[0109] In an exemplary embodiment, the areas of the multiple structural holes in the lead area gradually increase along the direction away from the first transition area; the areas of the multiple structural holes in the first transition area gradually increase along the direction away from the lead area; the areas of the multiple structural holes in the second transition area gradually increase along the direction away from the binding pin area; and the areas of the multiple structural holes in the binding pin area gradually increase along the direction away from the second transition area.

[0110] Figure 7 FIG. 1 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. Figure 7 As shown, in a plane parallel to the display substrate, the display substrate 1 may include a display area 100 and a binding area 200 located on one side of the display area, and the binding area 200 may include a lead area 210, a first transition area 220, a bending area 230, a second transition area 240, and a binding pin area 250 sequentially arranged along a first direction D1 (a direction away from the display area). The lead area 210 may be connected to the display area 100, the first transition area 220 may be connected to the lead area 210, the bending area 230 may be connected to the first transition area 220, the second transition area 240 may be connected to the bending area 230, and the binding pin area 250 may be connected to the second transition area 240.

[0111] In an exemplary embodiment, the lead area 210 can be provided with multiple signal leads, a first power line, and a second power line, the data leads among the multiple signal leads are configured to be connected to the data lines of the display area 100 in a fan-out routing manner, the touch leads among the multiple signal leads are configured to be connected to the touch electrodes of the display area 100, the first power line is configured to be connected to the high voltage power line (VDD) of the display area 100, and the second power line is configured to be connected to the low voltage power line (VSS) of the border area.

[0112] In an exemplary embodiment, the bending region 230 may include a composite insulating layer provided with a groove, and the binding pin region 250 may be bent and attached to the back side of the display region 100 by utilizing the groove of the bending region 220 .

[0113] In an exemplary embodiment, the binding pin area 250 may include at least a plurality of binding pins 251 and a plurality of signal connection lines, wherein the plurality of binding pins are configured to be bound and connected to an external flexible printed circuit (FPC), and the plurality of signal connection lines are configured to be connected to the plurality of binding pins 251 accordingly.

[0114] In an exemplary embodiment, the first direction D1 may be an extension direction of a data signal line in the display area (column direction), the second direction D2 may be an extension direction of a scanning signal line in the display area (row direction), the third direction D3 may be a direction perpendicular to the plane of the display substrate (thickness direction), the first direction D1 and the second direction D2 may be perpendicular to each other, and the first direction D1 and the third direction D3 may be perpendicular to each other.

[0115] The inventors of the present application have found that since the inorganic insulating layer 14 is retained in the first transition region 220 and the second transition region 240, and the first transition region 220 is close to the side of the display region 100 (such as Figure 7 The inorganic insulating layer is removed from the lead area 210 shown in FIG. 1 , so a high-low step structure (such as Figure 7 ), the second transition region 240 is away from the side of the display area 100 (as shown in the upper dotted box in FIG. Figure 7 The inorganic insulating layer is removed from the area of ​​the binding pin area 250 shown in FIG. 1 , so that a high-low step difference structure (such as FIG. 1 ) appears on the side of the second transition area 240 away from the display area 100. Figure 7 ). When the metal wire 15 is prepared by a patterning process, the boundary area between the first transition area 220 and the lead area 210 on the side of the first transition area 220 close to the display area 100 and the boundary area between the second transition area 240 and the binding pin area 250 on the side of the second transition area 240 far from the display area 100 are areas where the metal wire is prone to breakage. The present disclosure reduces the risk of metal wire breakage by providing a structural hole for maintaining the photoresist thickness of the first transition area and the second transition area in the binding area, such as by providing a structural hole for maintaining the photoresist thickness of the first transition area and the second transition area in at least one or more areas of the lead area, the first transition area, the second transition area, and the binding pin area.

[0116] In an exemplary embodiment, at least one first structural hole 50 is disposed in a boundary region between the first transition region 220 and the lead region 210 on a side of the first transition region 220 close to the display region 100 .

[0117] In an exemplary embodiment, at least one second structural hole 51 is disposed in a boundary region between the second transition region 240 and the binding pin region 250 on a side of the second transition region 240 away from the display region 100 .

[0118] Figure 8Schematic diagram of a cross-sectional structure of a display substrate of an exemplary embodiment of the present disclosure. In a plane parallel to the display substrate, the binding area 200 may include a lead area 210, a first transition area 220, a bending area 230, a second transition area 240, and a binding pin area 250 arranged in sequence along a first direction D1 (a direction away from the display area). The lead area 210 may be connected to the display area 100, the first transition area 220 may be connected to the lead area 210, the bending area 230 may be connected to the first transition area 220, the second transition area 240 may be connected to the bending area 230, and the binding pin area 250 may be connected to the second transition area 240.

[0119] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display area 100 may include: a substrate, a driving structure layer arranged on the substrate, a light-emitting structure layer arranged on a side of the driving structure layer away from the substrate, an encapsulation structure layer arranged on a side of the light-emitting structure layer away from the substrate, and a touch structure layer arranged on a side of the encapsulation structure layer away from the substrate.

[0120] In an exemplary embodiment, the driving structure layer of the display area 100 may include: a first insulating layer 11 disposed on the substrate 10, a semiconductor layer disposed on the side of the first insulating layer 11 away from the substrate, a second insulating layer 12 disposed on the side of the semiconductor layer away from the substrate, a first conductive layer disposed on the side of the second insulating layer 12 away from the substrate, a third insulating layer 13 disposed on the side of the first conductive layer away from the substrate, a second conductive layer disposed on the side of the third insulating layer 13 away from the substrate, a fourth insulating layer 14 disposed on the side of the second conductive layer away from the substrate, and a third conductive layer disposed on the side of the fourth insulating layer 14 away from the substrate. In an exemplary embodiment, the semiconductor layer may include at least an active layer of a plurality of transistors, the first conductive layer may include at least gate electrodes of a plurality of transistors and a first plate of a storage capacitor, the second conductive layer may include at least a second plate of a storage capacitor, the third conductive layer may include at least a first electrode and a second electrode of a plurality of transistors, Figure 8 In the figure, only one transistor 101A and a storage capacitor 101B in the display area 100 are taken as an example for illustration.

[0121] In an exemplary embodiment, on a plane perpendicular to the display substrate, the lead area 210 and the binding pin area 250 include a composite insulating layer (including a first insulating layer 11, a second insulating layer 12 and a third insulating layer 13) disposed on the substrate 10 and a metal wire 15 disposed on a side of the composite insulating layer away from the substrate 10, the first transition area 220 and the second transition area 240 include a composite insulating layer (including a first insulating layer 11, a second insulating layer 12 and a third insulating layer 13) disposed on the substrate 10, an inorganic insulating layer 14 disposed on a side of the composite insulating layer away from the substrate 10 and a metal wire 15 disposed on a side of the inorganic insulating layer 14 away from the substrate 10; the binding area 200 also includes a first structural hole 50 and a second structural hole 51 for maintaining the photoresist thickness of the first transition area 220 and the second transition area 240.

[0122] In an exemplary embodiment, the first transition region 220 includes a first structural hole 50 . The first structural hole 50 of the first transition region 220 is disposed in a region of the first transition region 220 close to the lead region 210 , and the first structural hole 50 may be disposed on the metal line 15 .

[0123] In an exemplary embodiment, the second transition region 240 includes a second structural hole 51 . The second structural hole 51 of the second transition region 240 is disposed in a region of the second transition region 240 close to the bonding pin region 250 , and the second structural hole 51 may be disposed on the metal line 15 .

[0124] The following is an exemplary description of the preparation process of the display substrate, taking the display area 100 and the binding area 200 as examples. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating, and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0125] The preparation of the display substrate of the exemplary embodiment of the present disclosure may include the following steps:

[0126] (1) Forming a bending zone pattern. In an exemplary embodiment, forming a bending zone pattern may include:

[0127] A. First, a base 10 is prepared on a glass substrate 2, and then a first insulating film and a semiconductor film are sequentially deposited on the base 10, and the semiconductor film is patterned by a patterning process to form a first insulating layer 11 covering the entire base 10, and a semiconductor layer pattern disposed on the first insulating layer 11, wherein the semiconductor layer pattern at least includes an active layer located in the display area 100. After this patterning process, the binding area 200 may include the first insulating layer 11 disposed on the base 10.

[0128] B. Subsequently, a second insulating film and a first conductive film are sequentially deposited, and the first conductive film is patterned by a patterning process to form a second insulating layer 12 covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer 12, wherein the first conductive layer pattern at least includes a gate electrode and a first electrode plate located in the display area 100. After this patterning process, the binding area 200 may include a first insulating layer 11 and a second insulating layer 12 stacked on the substrate 10. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0129] C. Subsequently, a third insulating film and a second conductive film are sequentially deposited, and the second conductive film is patterned by a patterning process to form a third insulating layer 13 covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer 13, wherein the second conductive layer pattern at least includes a second electrode located in the display area 100, and the orthographic projection of the second electrode on the substrate overlaps at least partially with the orthographic projection of the first electrode on the substrate. After this patterning process, the lead area 210 and the bending area 230 of the binding area 200 may include a first insulating layer 11, a second insulating layer 12, and a third insulating layer 13 stacked on the substrate 10. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0130] D. Subsequently, a fourth insulating film is deposited and patterned by a patterning process to form a pattern of the inorganic insulating layer 14 and a bending groove 231 . The bending groove 231 is disposed in the bending region 230 in the binding region 200 .

[0131] In an exemplary embodiment, two masks (Etch Bending A MASK, EBAMASK for short and Etch Bending B MASK, EBB MASK for short) can be used to form a groove structure consisting of a first groove and a second groove through two patterning processes. The first groove and the second groove together constitute a bending groove 231. The inorganic insulating layer 14, the third insulating layer 13, the second insulating layer 12 and the first insulating layer 11 in the bending groove 231 are removed to expose the surface of the substrate 10.

[0132] In an exemplary embodiment, in the patterning process using a mask (EBA MASK), the inorganic insulating layer 14 in the lead area 210 and the binding pin area 250 can also be removed, and only the inorganic insulating layer 14 in the first transition area 220 and the second transition area 230 is retained in the binding area 200.

[0133] In an exemplary embodiment, two via holes K1 and K2 are also formed in the display area 100 in the patterning process using a mask.

[0134] In an exemplary embodiment, the EBA MASK and EBB MASK processes are patterning processes for trenching the bending region of the display substrate, which can reduce the thickness of the bending region. In an exemplary embodiment, in the EBB MASK process, part of the thickness of the substrate in the bending groove 231 can be etched away, for example, the second barrier layer of the substrate is etched away, and the present disclosure is not limited thereto.

[0135] At this point, the preparation of the bending area pattern is completed, such as Fig. 9 shown.

[0136] After this patterning process, the display area 100 may include a substrate 10 disposed on the glass substrate 2, and a first insulating layer 11, a semiconductor layer, a second insulating layer 12, a first conductive layer, a third insulating layer 13, a second conductive layer, and an inorganic insulating layer 14 stacked on the substrate 10. The lead area 210 and the binding pin area 250 of the binding area 200 may include the substrate 10 and the first insulating layer 11, the second insulating layer 12, and the third insulating layer 13 stacked on the substrate 10. The bending area 230 may include the substrate 10 and a bending groove disposed on the substrate 10. The first transition area 220 and the second transition area 240 of the binding area 200 may include the substrate 10 and the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, and the inorganic insulating layer 14 stacked on the substrate 10.

[0137] In an exemplary embodiment, the first insulating layer 11 , the second insulating layer 12 , and the third insulating layer 13 may be referred to as a composite insulating layer.

[0138] In an exemplary embodiment, the substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass substrate. The first and second flexible material layers may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc. The first and second inorganic material layers may be made of silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate. The first and second inorganic material layers may be called barrier layers, and the semiconductor layer may be made of amorphous silicon (a-Si). Taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: first coating a layer of polyimide on a glass substrate, and forming a first flexible (PI1) layer after solidification; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible (PI2) layer after solidification; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.

[0139] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer and the inorganic insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. The first insulating layer may be referred to as a buffer layer, and the second insulating layer and the third insulating layer may be referred to as a (GI) layer. The first conductive layer, the second conductive layer and the third conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multilayer composite structure, such as Ti / Al / Ti, etc.

[0140] (2) Forming a third conductive layer. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern, patterning the third conductive film through a patterning process to form a third conductive layer pattern, wherein the third conductive layer at least includes a plurality of metal wires 15 extending from the display area 100 to the binding pin area 250, such as Fig.10 In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0141] In an exemplary embodiment, the first transition zone 220 and the second transition zone 240 retain an inorganic insulating layer, and the first transition zone 220 and the second transition zone 240 can be referred to as an inorganic insulating layer retention area. The inorganic insulating layer of the first transition zone 220 close to the display area 100, such as the lead area 210, is removed, and the inorganic insulating layer of the second transition zone 240 away from the display area 100, such as the binding pin area 250, is removed, and the lead area 210 and the binding pin area 250 can be referred to as an inorganic insulating layer removal area. The inventor of the present application has found through research that the boundary area between the first transition zone 220 and the lead area 210 and the boundary area between the second transition zone 240 and the binding pin area 250 both present a high-low step difference structure and are areas where metal wire breakage is prone to occur. The present disclosure can reduce the risk of metal wire breakage by setting structural holes in the first transition zone 220 and the second transition zone 240.

[0142] In an exemplary embodiment, the first transition region 220 may include a first structural hole 50, and the first structural hole 50 of the first transition region 220 may be disposed on the metal line 15. The depth of the first structural hole 50 may be equal to the thickness of the metal line 15, that is, the first structural hole 50 may be a through hole penetrating the metal line.

[0143] In an exemplary embodiment, the second transition region 240 may include a second structural hole 51, and the second structural hole 51 of the second transition region 240 may be disposed on the metal line 15. The depth of the second structural hole 51 may be equal to the thickness of the metal line 15, that is, the second structural hole 51 may be a through hole penetrating the metal line.

[0144] Fig.11 is a schematic structural diagram of a first structural hole of an exemplary embodiment of the present disclosure, Fig.10 A local enlarged schematic diagram of the middle point. Fig.11 As shown, there is a first junction position Q1 between the first transition region 220 and the lead region 210. Relative to the first junction position Q1, the plurality of first structural holes 50 of the first transition region 220 may be arranged in a region of the first transition region 220 close to the first junction position Q1.

[0145] In an exemplary embodiment, the first transition region 220 may include a first climbing region 221 and a first flat region 222. The first climbing region 221 may be located on a side of the first junction position Q1 away from the lead region 210, and the first flat region 222 may be located on a side of the first climbing region 221 away from the first junction position Q1.

[0146] In an exemplary embodiment, a plurality of first structure holes 50 may be disposed on the metal line 15 of the first planar region 222 .

[0147] In an exemplary embodiment, on a plane parallel to the substrate, the shape of the first structure hole 50 may include any one or more of the following: triangle, rectangle, pentagon, hexagon, circle, and ellipse.

[0148] Fig.12 is a schematic structural diagram of a second structural hole of an exemplary embodiment of the present disclosure, Fig.10 A partial enlarged schematic diagram of point B in the figure. Fig.12 As shown, there is a second junction position Q2 between the second transition region 240 and the binding pin region 250. Relative to the second junction position Q2, the plurality of second structural holes 51 of the second transition region 240 may be disposed in a region of the second transition region 240 close to the second junction position Q2.

[0149] In an exemplary embodiment, the metal wire 15 of the second transition zone 240 may include a second climbing zone 241 and a second flat zone 242, the second climbing zone 241 may be located on a side of the second junction position Q2 away from the binding pin zone 250, and the second flat zone 242 may be located on a side of the second climbing zone 241 away from the second junction position Q2.

[0150] In an exemplary embodiment, a plurality of second structure holes 51 may be disposed on the metal wire 15 of the second planar region 242 .

[0151] In an exemplary embodiment, on a plane parallel to the substrate, the shape of the second structure hole 51 may include any one or more of the following: triangle, rectangle, pentagon, hexagon, circle, and ellipse.

[0152] Fig.13 FIG. 1 is a schematic diagram of a planar structure of a first structural hole of an exemplary embodiment of the present disclosure, taking a circular structural hole as an example. Fig.13 As shown, the metal line 15 is in the shape of a line extending along the first direction D1. In the second direction D2, the metal line 15 has a width W. The width W of the metal line can be a dimension perpendicular to the extension direction of the metal line (the second direction D2). On a plane parallel to the substrate, the shape of the first structural hole 50 can be circular and have a diameter D.

[0153] In an exemplary embodiment, along the first direction D1 , the plurality of first structure holes 50 may have the same diameter, that is, the plurality of first structure holes 50 may have the same area.

[0154] In an exemplary embodiment, along the first direction D1 , the plurality of second structure holes 51 may have the same diameter, that is, the plurality of second structure holes 51 may have the same area.

[0155] In an exemplary embodiment, a diameter D of the first structure hole or the second structure hole may be greater than or equal to ¼ of a width W of the metal line.

[0156] In an exemplary embodiment, a diameter D of the first structure hole or the second structure hole may be less than or equal to 2 / 3 of a width W of the metal line.

[0157] FIG. 14A to FIG. 14E Schematic diagram of the preparation process of the metal wire of the exemplary embodiment of the present disclosure. A metal film 15 is deposited on the inorganic insulating layer 14 of the first transition region 220, and then a layer of photoresist 20 (such as Fig.14A As shown, the photoresist in this embodiment is a negative photoresist); then the mask 30 is exposed by ultraviolet light 40, and the light passes through the completely transparent area to make the area a completely exposed area (such as Fig. 14B After development, the photoresist in the fully exposed area is completely retained because it is insoluble in the developer, becoming the photoresist completely retained area, and the unexposed part is dissolved in the developer, becoming the photoresist completely removed area (as shown in FIG. Fig. 14C ); then the metal film in the area outside the photoresist pattern is removed by etching process (as shown in Fig.14D Finally, the remaining photoresist is stripped off to form a metal line 15 having a pattern of structural holes 50 (as shown in FIG. Fig.14E shown).

[0158] In an exemplary embodiment, a positive photoresist may also be coated on the metal film to perform subsequent exposure, development and other processes.

[0159] In an exemplary embodiment, a similar patterning method can be used to coat and pattern a film layer on the substrate of the aforementioned pattern to form additional layers, including but not limited to a first planar layer, a fourth conductive layer (a second source-drain metal (SD2) layer), a second planar layer, and an anode conductive (AND) layer.

[0160] The present invention provides at least one structural hole in the metal wire in the area where the inorganic insulating layer is retained (such as the first transition area or the second transition area), thereby reducing the amount of photoresist flowing from a high position (such as the first transition area or the second transition area) to a low position (such as the lead area or the binding pin area) due to the step structure between two adjacent areas (such as between the first transition area and the lead area, or between the second transition area and the binding pin area) during the coating of the photoresist during patterning, and even completely preventing the photoresist at a high position from flowing to a low position, thereby avoiding the photoresist at a high position being too thin, resulting in the metal at the high position being exposed and etched, and reducing the risk of metal wire breakage.

[0161] Fig.15 is a schematic structural diagram of another first structural hole of an exemplary embodiment of the present disclosure, Fig.10 A local enlarged schematic diagram of the middle point. Fig.15 As shown, the main structure of the display substrate of this embodiment is basically the same as the above-mentioned embodiment, except that the first structure hole 50 can be arranged in the lead area 210, and multiple first structure holes 50 can be arranged in the area of ​​the lead area 210 close to the first junction position Q1.

[0162] In an exemplary embodiment, the first structural hole 50 of the lead region 210 may be disposed in a region of the lead region 210 close to the first transition region 220 , and the first structural hole 50 may be disposed on the metal line 15 .

[0163] In an exemplary embodiment, the second structural hole 51 of the bonding pin region 250 may be disposed in a region of the bonding pin region 250 close to the second transition region 240 , and the second structural hole 51 may be disposed on the metal line 15 .

[0164] The present invention provides at least one structural hole in a metal wire in an area where the inorganic insulating layer is not retained (such as a lead area adjacent to a first transition area or a binding pin area adjacent to a second transition area) that is adjacent to an area where the inorganic insulating layer is retained, so that the thickness of the photoresist at high and low positions tends to be the same, thereby preventing the photoresist at a high position from being too thin, causing the metal at the high position to be exposed and etched, and reducing the risk of metal wire breakage.

[0165] Fig.16 is a schematic structural diagram of another first structural hole of an exemplary embodiment of the present disclosure, Fig.10 A local enlarged schematic diagram of the middle point. Fig.16 As shown, the main structure of the display substrate of this embodiment is basically the same as that of the aforementioned embodiment, except that the first structural hole 50 can be arranged in two positions, the lead area 210 and the first transition area 220, and a plurality of first structural holes 50 can be arranged in an area of ​​the lead area 210 close to the first junction position Q1 and an area of ​​the first transition area 220 close to the first junction position Q1.

[0166] In an exemplary embodiment, the first structural hole 50 of the lead area 210 can be disposed in a region of the lead area 210 close to the first transition area 220, and the first structural hole 50 can be disposed on the metal line 15. The first structural hole 50 of the first transition area 220 can be disposed in a region of the first transition area 220 close to the lead area 210, and the first structural hole 50 can be disposed on the metal line 15.

[0167] In an exemplary embodiment, the second structural hole 51 can be set in two locations of the second transition area 240 and the binding pin area 250. The second structural hole 51 of the binding pin area 250 can be set in the area of ​​the binding pin area 250 close to the second transition area 240, and the second structural hole 51 can be set on the metal line 15. The second structural hole 51 of the second transition area 240 can be set in the area of ​​the second transition area 240 close to the binding pin area 250, and the second structural hole 51 can be set on the metal line 15.

[0168] The present invention provides a plurality of structural holes in the metal wires in two regions, namely, a region where an inorganic insulating layer is retained (such as the first transition region or the second transition region) and an adjacent region where the inorganic insulating layer is not retained (such as a lead region adjacent to the first transition region or a binding pin region adjacent to the second transition region), thereby slowing down the flow of photoresist at a high position to a low position, which is beneficial for making the photoresist thickness at high and low positions tend to be the same, and maximally avoiding the risk of metal wire breakage when etching a high position where the photoresist thickness is thin due to excessive difference in photoresist thickness.

[0169] Fig.17 FIG. 2 is a schematic diagram of a planar structure of another first structural hole of an exemplary embodiment of the present disclosure, taking a circular structural hole as an example. Fig.17 As shown, the plurality of first structural holes 50 may adopt a structure with gradually varying areas.

[0170] In an exemplary embodiment, the areas of the plurality of first structure holes 50 gradually increase along a direction away from the display area 100 , or the areas of the plurality of first structure holes 50 gradually increase along a direction approaching the display area 100 .

[0171] In an exemplary embodiment, along a direction away from the first transition region 220 , the areas of the plurality of first structure holes 50 in the lead region 210 gradually increase.

[0172] In an exemplary embodiment, along a direction away from the lead region 210 , the areas of the plurality of first structure holes 50 in the first transition region 220 gradually increase.

[0173] In an exemplary embodiment, the plurality of second structure holes 51 may have a structure with gradually changing areas.

[0174] In an exemplary embodiment, along a direction away from the binding pin area 250 , the areas of the plurality of second structure holes 51 in the second transition area 240 gradually increase.

[0175] In an exemplary embodiment, along a direction away from the second transition region 240 , the areas of the plurality of second structure holes 51 in the binding pin region 250 gradually increase.

[0176] Fig.18 FIG. 2 is a schematic diagram of a planar structure of another first structural hole of an exemplary embodiment of the present disclosure, taking an elliptical structural hole as an example. Fig.18 As shown, the metal line 15 is in the shape of a line extending along the first direction D1. In the second direction D2, the metal line 15 has a width W, that is, the width of the metal line is a dimension perpendicular to the extension direction of the metal line. On a plane parallel to the substrate, the shape of the first structure hole 50 can be elliptical, with a long axis L1 extending along the second direction D2 and a short axis L2 extending along the first direction D1. The multiple first structure holes 50 can adopt an elliptical area gradient structure.

[0177] In an exemplary embodiment, along a direction away from the first transition region 220 , the areas of the plurality of first structure holes 50 in the lead region 210 gradually increase.

[0178] In an exemplary embodiment, along a direction away from the lead region 210 , the areas of the plurality of first structure holes 50 in the first transition region 220 gradually increase.

[0179] On a plane parallel to the substrate, the second structure hole 51 may be elliptical in shape, having a major axis L1 extending along the second direction D2 and a minor axis L2 extending along the first direction D1. The plurality of second structure holes 50 may have an elliptical structure with a gradually varying area.

[0180] In an exemplary embodiment, along a direction away from the binding pin area 250 , the areas of the plurality of second structure holes 51 in the second transition area 240 gradually increase.

[0181] In an exemplary embodiment, along a direction away from the second transition region 240 , the areas of the plurality of second structure holes 51 in the binding pin region 250 gradually increase.

[0182] In an exemplary embodiment, the major axis L1 of the first structure hole or the second structure hole may be less than or equal to 2 / 3 of the width W of the metal line.

[0183] In an exemplary embodiment, the short axis L2 of the first structure hole or the second structure hole may be greater than or equal to ¼ of the width W of the metal line.

[0184] The first structural holes or the second structures may also have other shapes, sizes or arrangements, which will not be described in detail here.

[0185] The present invention can further reduce or slow down the flow of photoresist at high positions to low positions by setting at least one structural hole in at least one of a region where an inorganic insulating layer is retained (such as a first transition region or a second transition region) and an adjacent region where an inorganic insulating layer is not retained (such as a lead region adjacent to the first transition region or a binding pin region adjacent to the second transition region) and by changing parameters such as the number, shape, and size of the structural holes, so that the thickness of the photoresist at high and low positions tends to be the same, thereby avoiding the risk of metal disconnection when etching a high position where the photoresist thickness is too thin due to excessive difference in photoresist thickness.

[0186] Fig.19 FIG. 1 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure. Fig.19 As shown, the first transition zone 220 and the second transition zone 240 retain an inorganic insulating layer, and the first transition zone 220 and the second transition zone 240 can be referred to as an inorganic insulating layer retention area. The inorganic insulating layer on the side of the first transition zone 220 close to the display area 100 is removed, and the inorganic insulating layer on the side of the second transition zone 240 away from the display area 100 is removed, and the lead area 210 and the binding pin area 250 can be referred to as inorganic insulating layer removal areas. The inventors of the present application have found through research that the boundary area between the first transition zone 220 and the lead area 210 and the boundary area between the second transition zone 240 and the binding pin area 250 both present a high-low step difference structure and are areas where metal wire breakage is prone to occur. The present disclosure can reduce the risk of metal wire breakage by setting structural holes in the first transition zone 220 and the second transition zone 240.

[0187] In an exemplary embodiment, the first transition region 220 may include a third structural hole 60, and the third structural hole 60 of the first transition region 220 may be disposed on the inorganic insulating layer 14. The depth of the third structural hole 60 may be equal to the thickness of the inorganic insulating layer 14, that is, the third structural hole 60 may be a through hole penetrating the inorganic insulating layer.

[0188] In an exemplary embodiment, the second transition region 240 may include a fourth structure hole 61, and the fourth structure hole 61 of the second transition region 240 may be disposed on the inorganic insulating layer 14. The depth of the fourth structure hole 61 may be equal to the thickness of the inorganic insulating layer 14, that is, the fourth structure hole 61 may be a through hole penetrating a metal line.

[0189] Fig. 20 is a schematic structural diagram of a third structural hole of an exemplary embodiment of the present disclosure, Fig.19 A local enlarged schematic diagram of the middle point. Fig. 20As shown, there is a first junction position Q1 between the first transition region 220 and the lead region 210. Relative to the first junction position Q1, the plurality of third structural holes 60 of the first transition region 220 may be disposed in a region of the first transition region 220 close to the first junction position Q1.

[0190] In an exemplary embodiment, the third structure hole 60 of the first transition region 220 may be disposed in a region of the first transition region 220 close to the lead region 210 , and the third structure hole 60 may be disposed on the inorganic insulating layer 14 .

[0191] In an exemplary embodiment, the metal wire 15 covers the hole wall and the hole bottom of the third structure hole 60 .

[0192] In an exemplary embodiment, on a plane parallel to the substrate, the shape of the third structure hole 60 may include any one or more of the following: triangle, rectangle, pentagon, hexagon, circle, and ellipse.

[0193] Fig.21 is a schematic structural diagram of a fourth structural hole of an exemplary embodiment of the present disclosure, Fig.19 A partial enlarged schematic diagram of point B in the figure. Fig.21 As shown, there is a second junction position Q2 between the second transition region 240 and the binding pin region 250. Relative to the second junction position Q2, the plurality of fourth structural holes 61 of the second transition region 240 may be disposed in an area of ​​the second transition region 240 close to the second junction position Q2.

[0194] In an exemplary embodiment, the fourth structure hole 61 of the second transition region 240 may be disposed in a region of the second transition region 240 close to the binding pin region 250 , and the fourth structure hole 61 may be disposed on the inorganic insulating layer 14 .

[0195] In an exemplary embodiment, the metal wire 15 covers the hole wall and the hole bottom of the fourth structure hole 61 .

[0196] In an exemplary embodiment, on a plane parallel to the substrate, the shape of the fourth structure hole 61 may include any one or more of the following: triangle, rectangle, pentagon, hexagon, circle, and ellipse.

[0197] In an exemplary embodiment, the third structure hole or the fourth structure hole may be circular and have a diameter D.

[0198] In an exemplary embodiment, along the first direction D1 , the third structure holes or the fourth structure holes may have the same diameter, that is, the third structure holes or the fourth structure holes may have the same area.

[0199] In an exemplary embodiment, the third structure hole or the fourth structure hole may have a structure with a gradually changing area.

[0200] In an exemplary embodiment, a diameter D of the third structure hole or the fourth structure hole may be greater than or equal to 1 / 4 and less than or equal to 2 / 3 of the width W of the metal line.

[0201] In an exemplary embodiment, the third structure hole or the fourth structure hole is elliptical and has a major axis L1 extending along the second direction D2 and a minor axis L2 extending along the first direction D1.

[0202] In an exemplary embodiment, the third structure hole or the fourth structure hole may adopt an elliptical structure with a gradually changing area.

[0203] In an exemplary embodiment, the major axis L1 of the third structure hole or the fourth structure hole may be less than or equal to 2 / 3 of the width W of the metal line and the minor axis L2 may be greater than or equal to 1 / 4 of the width W of the metal line.

[0204] In an exemplary embodiment, similar to Fig. 9 and Fig.10 The method shown in the figure forms an inorganic insulating layer on the substrate, and Figures 14A to 14E A plurality of structural holes are formed on the inorganic insulating layer by a method.

[0205] The present invention provides at least one structural hole in the inorganic insulating layer within the region where the inorganic insulating layer is retained (such as the first transition region or the second transition region), so that when the patterning process forms the metal line, the metal will be deposited in the structural hole of the inorganic insulating layer to form a metal pit. When the photoresist is coated, the photoresist will fill a plurality of metal pits, thereby increasing the friction between the photoresist and the metal layer, thereby also reducing or slowing down the flow of the photoresist at a high position to a low position, thereby preventing the photoresist at a high position from being too thin, resulting in the metal at the high position being exposed and etched.

[0206] The structure and preparation process of the substrate shown in the exemplary embodiment of the present disclosure are merely exemplary. In the exemplary implementation, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0207] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0208] The present disclosure also provides a method for preparing a display substrate, wherein the display substrate comprises a display area and a binding area located on one side of the display area, wherein the binding area comprises a lead area, a first transition area, a bending area, a second transition area, and a binding pin area sequentially arranged in a direction away from the display area; the preparation method comprises:

[0209] A composite insulating layer disposed on the substrate and a metal wire disposed on the side of the composite insulating layer away from the substrate are formed in the lead area and the binding pin area; a composite insulating layer disposed on the substrate, an inorganic insulating layer disposed on the side of the composite insulating layer away from the substrate and a metal wire disposed on the side of the inorganic insulating layer away from the substrate are formed in the first transition area and the second transition area; a structural hole is also formed in the binding area to maintain the thickness of the photoresist in the first transition area and the second transition area.

[0210] The present disclosure also provides a display device, including the display substrate of the above embodiment. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator.

[0211] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of the present disclosure shall still be subject to the scope defined in the attached claims.

Claims

1. A display substrate, characterized in that: It includes a display area and a binding area located on one side of the display area, wherein the binding area includes a lead area, a first transition area, a bending area, a second transition area and a binding pin area which are sequentially arranged in a direction away from the display area; on a plane perpendicular to the display substrate, the lead area and the binding pin area include a composite insulating layer arranged on a substrate and a metal wire arranged on a side of the composite insulating layer away from the substrate, the first transition area and the second transition area include a composite insulating layer arranged on the substrate, an inorganic insulating layer arranged on a side of the composite insulating layer away from the substrate and a metal wire arranged on a side of the inorganic insulating layer away from the substrate; the binding area is also provided with structural holes for maintaining the thickness of the photoresist in the first transition area and the second transition area.

2. The display substrate according to claim 1, characterized in that: At least one structural hole is provided in at least one or more of the lead area, the first transition area, the second transition area, and the binding pin area, and the structural hole is provided on the metal wire.

3. The display substrate according to claim 2, characterized in that: The structural holes include a first structural hole, and the first structural hole is arranged at any one or more of the following positions: the lead area and the first transition area.

4. The display substrate according to claim 3, characterized in that: The first structural hole of the lead area is arranged in a region of the lead area close to the first transition area, and the first structural hole of the first transition area is arranged in a region of the first transition area close to the lead area.

5. The display substrate according to claim 4, characterized in that: The first transition zone includes a first climbing zone and a first flat zone. The first climbing zone is located on a side of the first transition zone close to the lead zone, the first flat zone is located on a side of the first climbing zone away from the lead zone, and the first structural hole is arranged on a metal line in the first flat zone.

6. The display substrate according to claim 2, characterized in that: The structural holes include second structural holes, and the second structural holes are arranged at any one or more of the following positions: the binding pin area and the second transition area.

7. The display substrate according to claim 6, characterized in that: The second structural hole of the binding pin area is arranged in a region of the binding pin area close to the second transition area, and the second structural hole of the second transition area is arranged in a region of the second transition area close to the binding pin area.

8. The display substrate according to claim 7, characterized in that: The second transition zone includes a second climbing zone and a second flat zone. The second climbing zone is located on a side of the second transition zone close to the binding pin zone, the second flat zone is located on a side of the second climbing zone away from the binding pin zone, and the second structural hole is arranged on the metal line of the second flat zone.

9. The display substrate according to claim 1, characterized in that: At least one structural hole is disposed in at least one or more of the first transition region and the second transition region, and the structural hole is disposed on the inorganic insulating layer.

10. The display substrate according to claim 9, characterized in that: The structural holes include a third structural hole and a fourth structural hole, the third structural hole is arranged in the first transition area, and the fourth structural hole is arranged in the second transition area.

11. The display substrate according to claim 10, characterized in that: The third structural hole is disposed in a region of the first transition region close to the lead region, and the fourth structural hole is disposed in a region of the second transition region close to the binding pin region.

12. The display substrate according to claim 11, characterized in that: The metal wire covers the hole wall and the hole bottom of the third structure hole, and the metal wire covers the hole wall and the hole bottom of the fourth structure hole.

13. The display substrate according to any one of claims 1 to 12, characterized in that: The shape of the structural hole includes any one or more of the following: triangle, rectangle, pentagon, hexagon, circle and ellipse.

14. The display substrate according to claim 13, characterized in that: The shape of the structural hole is circular, the diameter of the structural hole is greater than or equal to 1 / 4 of the width of the metal wire, the diameter of the structural hole is less than or equal to 2 / 3 of the width of the metal wire, and the width of the metal wire is the dimension perpendicular to the extension direction of the metal wire.

15. The display substrate according to claim 13, characterized in that: The areas of the plurality of structural holes are the same.

16. The display substrate according to claim 13, characterized in that: Along the direction away from the display area, the areas of the plurality of structural holes gradually increase, or along the direction approaching the display area, the areas of the plurality of structural holes gradually increase.

17. The display substrate according to claim 16, characterized in that: Along the direction away from the first transition zone, the area of ​​the multiple structural holes in the lead zone gradually increases; along the direction away from the lead zone, the area of ​​the multiple structural holes in the first transition zone gradually increases; along the direction away from the binding pin zone, the area of ​​the multiple structural holes in the second transition zone gradually increases; along the direction away from the second transition zone, the area of ​​the multiple structural holes in the binding pin zone gradually increases.

18. A display device, characterized in that: The invention comprises the display substrate as claimed in any one of claims 1 to 17.

19. A method for preparing a display substrate, characterized in that: The display substrate comprises a display area and a binding area located on one side of the display area, wherein the binding area comprises a lead area, a first transition area, a bending area, a second transition area and a binding pin area which are sequentially arranged in a direction away from the display area; the preparation method comprises: A composite insulating layer arranged on the substrate and a metal wire arranged on the side of the composite insulating layer away from the substrate are formed in the lead area and the binding pin area, and a composite insulating layer arranged on the substrate, an inorganic insulating layer arranged on the side of the composite insulating layer away from the substrate and a metal wire arranged on the side of the inorganic insulating layer away from the substrate are formed in the first transition area and the second transition area; the binding area is also formed with structural holes that maintain the thickness of the photoresist in the first transition area and the second transition area.

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