Thin film transistor and manufacturing method thereof, display panel, and display device

Abstract

The present application discloses a thin film transistor and a manufacturing method thereof, a display panel, and a display device, which belong to the field of display technology. In this method, a protective electrode layer and an active layer are formed by a single patterning process, and the protective electrode layer and the source and drain electrode layer are formed by different patterning processes. In this way, without increasing the difficulty of the process, the formed protective electrode layer can cover the source and drain electrode layer, reducing the probability of the source and drain electrode layer being oxidized, improving the conductivity of the source and drain electrode layer, and thus improving the performance of the thin film transistor.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a thin film transistor and a manufacturing method thereof, a display panel, and a display device. Background Art

[0002] A thin film transistor (TFT) generally includes a gate, a gate insulating layer, an active layer, a source-drain electrode layer, and a protective electrode layer which are sequentially arranged on a substrate. The source-drain electrode layer includes a source electrode and a drain electrode respectively connected to the active layer, and the protective electrode layer includes a first protective electrode covering the source electrode and a second protective electrode covering the drain electrode, and the protective electrode layer and the source-drain electrode layer are obtained by a single patterning process.

[0003] However, during the etching process, the protective electrode layer is prone to over-etching, resulting in part of the source and drain layer not being covered by the protective electrode layer. The part of the source and drain layer not covered by the protective electrode layer is easily oxidized, thereby affecting the conductivity of the source and drain layer, resulting in poor performance of the thin film transistor. Summary of the invention

[0004] The embodiments of the present application provide a thin film transistor and a manufacturing method thereof, a display panel, and a display device. The problem of poor performance of thin film transistors in the prior art can be solved. The technical solution is as follows:

[0005] In a first aspect, a method for manufacturing a thin film transistor is provided, the method comprising:

[0006] Forming a semiconductor thin film covering the entire substrate on the substrate, wherein the semiconductor thin film is at least used to form an active layer of the thin film transistor after subsequent patterning;

[0007] Forming a patterned source-drain electrode layer on the substrate on which the semiconductor thin film is formed, wherein the source-drain electrode layer at least includes a source electrode and a drain electrode of the thin film transistor;

[0008] Forming a conductive film covering the entire substrate on the substrate having the source and drain electrode layers formed thereon, wherein the conductive film is at least used for forming a protective electrode layer covering the source and drain electrodes through subsequent patterning;

[0009] The semiconductor film and the conductive film are patterned simultaneously to obtain the active layer formed by the semiconductor film and the protective electrode layer formed by the conductive film, and the protective electrode layer is processed so that at least part of the protective electrode layer between the source and the drain is disconnected or insulated.

[0010] Optionally, the semiconductor film and the conductive film are patterned simultaneously to obtain the active layer formed by the semiconductor film and the protective electrode layer formed by the conductive film, and the protective electrode layer is processed so that at least a portion of the protective electrode layer between the source electrode and the drain electrode is disconnected, comprising:

[0011] forming a photoresist layer on the conductive film, performing exposure and development processing on the photoresist layer to retain a first photoresist region located above the source electrode and the drain electrode, and a second photoresist region located between the source electrode and the drain electrode, and removing the photoresist in the photoresist completely removed region, wherein the photoresist thickness in the first photoresist region is greater than the photoresist thickness in the second photoresist region;

[0012] Simultaneously wet-etching the semiconductor film and the conductive film to remove the semiconductor film and the conductive film corresponding to the photoresist completely removed area to form the active layer and the protective electrode layer;

[0013] The photoresist in the second photoresist area is removed by dry etching, and the protective electrode layer corresponding to the second photoresist area is removed to form a first protective electrode located on the source and a second protective electrode located above the drain, and the first protective electrode and the second protective electrode are disconnected.

[0014] Optionally, a first orthographic projection of the source electrode on the substrate is located within a second orthographic projection of a first photoresist region on the source electrode on the substrate, and a distance between an outer boundary of the first orthographic projection and an outer boundary of the second orthographic projection is greater than a preset distance threshold;

[0015] The third orthographic projection of the drain on the substrate is located within the fourth orthographic projection of the first photoresist region on the drain on the substrate, and the distance between the outer boundary of the third orthographic projection and the outer boundary of the fourth orthographic projection is greater than a preset distance threshold;

[0016] After the protective electrode layer is formed, the protective electrode layer wraps around the side surfaces of the source electrode and the drain electrode.

[0017] Optionally, the first photoresist region located above the source electrode has two side surfaces, and the two side surfaces are respectively flush with the two side surfaces of the source electrode, and the first photoresist region located above the drain electrode has two side surfaces, and the two side surfaces are respectively flush with the two side surfaces of the drain electrode, so that the first photoresist region covers the source electrode and the drain electrode, and is flush with the side surfaces of the source electrode and the drain electrode;

[0018] After the protective electrode layer is formed, the side of the source electrode away from the drain electrode is flush with the side of the protective electrode layer, and the side of the drain electrode away from the source electrode is flush with the side of the protective electrode layer. Optionally, the protective electrode layer has a first portion and a second portion, the first portion contacts the source electrode and faces the drain electrode, the second portion contacts the drain electrode and faces the source electrode, and the second photoresist region is located between the first portion and the second portion;

[0019] The method comprises: removing the photoresist in the second photoresist area by dry etching, and removing the protective electrode layer corresponding to the second photoresist area to form a first protective electrode on the source electrode and a second protective electrode on the drain electrode, wherein the first protective electrode and the second protective electrode are disconnected, comprising:

[0020] Using dry etching to remove the photoresist between the first portion and the second portion, and thinning the photoresist in the first photoresist area;

[0021] The portion of the protective electrode layer located between the first portion and the second portion is removed by dry etching to allow the active layer to leak out, thereby forming the first protective electrode and the second protective electrode.

[0022] Optionally, after removing the portion of the protective electrode layer between the first portion and the second portion by dry etching to allow the active layer to leak out, the method further includes:

[0023] The active layer is surface treated using plasma including at least one of oxygen gas and nitrous oxide gas to adjust the concentration of oxygen vacancies in the active layer.

[0024] Optionally, before forming the semiconductor thin film on the substrate, the method further comprises:

[0025] A gate and a gate insulating layer are sequentially formed on the base substrate, wherein the orthographic projection of the active layer on the base substrate is located within the orthographic projection of the gate on the base substrate.

[0026] In a second aspect, a thin film transistor is provided, the thin film transistor comprising:

[0027] an active layer located on one side of the substrate base;

[0028] A source-drain electrode layer located on a side of the active layer away from the substrate, the source-drain electrode layer at least comprising a source electrode and a drain electrode;

[0029] And, a protective electrode layer located on a side of the source and drain layer away from the substrate, wherein the protective electrode layer covers the source and the drain, and at least a portion of the protective electrode layer between the source and the drain is disconnected or insulated.

[0030] Optionally, the protection electrode layer includes a first protection electrode located on the source electrode and a second protection electrode located on the drain electrode, and the first protection electrode and the second protection electrode are disconnected.

[0031] Optionally, the first protective electrode wraps around a side surface of the source electrode, and the second protective electrode wraps around a side surface of the drain electrode.

[0032] Optionally, the side surface of the first protection electrode is flush with the side surface of the source electrode, and the side surface of the second protection electrode is flush with the side surface of the drain electrode.

[0033] Optionally, a side of the first protection electrode away from the second protection electrode is flush with a side of the active layer, and a side of the second protection electrode away from the first protection electrode is flush with a side of the active layer.

[0034] Optionally, the orthographic projections of the source and the drain on the substrate are located within the orthographic projection of the active layer on the substrate.

[0035] Optionally, the thin film transistor further includes: a third protection electrode located between the active layer and the source electrode, and a fourth protection electrode located between the active layer and the drain electrode.

[0036] Optionally, the material of the source and drain electrode layers includes: metallic copper, and the material of the protective electrode layer includes: molybdenum-niobium alloy.

[0037] In a third aspect, a display panel is provided, the display panel comprising:

[0038] A base substrate, and a plurality of the above-mentioned thin film transistors located on the base substrate.

[0039] In a fourth aspect, a display device is provided, the display device comprising:

[0040] Power supply components and the above-mentioned display panel;

[0041] The power supply component is used to supply power to the display panel.

[0042] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least:

[0043] A method for manufacturing a thin film transistor is provided. In the method, a protective electrode layer and an active layer are formed by a single patterning process, and the protective electrode layer and the source and drain electrode layer are formed by different patterning processes. In this way, without increasing the difficulty of the process, the formed protective electrode layer can cover the source and drain electrode layer, thereby reducing the probability of the source and drain electrode layer being oxidized, improving the conductivity of the source and drain electrode layer, and thus improving the performance of the thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 This is a schematic diagram of the film layer structure of a common thin film transistor;

[0046] Figure 2 is a flow chart of a method for manufacturing a thin film transistor shown in an embodiment of the present application;

[0047] Figure 3 is a flow chart of another method for manufacturing a thin film transistor provided in an embodiment of the present application;

[0048] Figure 4 yes Figure 3 A schematic structural diagram of a substrate in the method shown;

[0049] Figure 5 yes Figure 3 Another structural schematic diagram of the substrate in the method shown;

[0050] Figure 6 yes Figure 3 Another structural schematic diagram of the substrate in the method shown;

[0051] Figure 7 yes Figure 3 A schematic diagram of another structure of the substrate in the method shown;

[0052] Figure 8 It is a flow chart of patterning a semiconductor film and a conductive film provided in an embodiment of the present application;

[0053] Fig. 9 yes Figure 8 A schematic structural diagram of a substrate in the method shown;

[0054] Fig.10 It is a structural schematic diagram of a grayscale mask provided in an embodiment of the present application;

[0055] Fig.11 yes Figure 8 A schematic structural diagram of a substrate in the method shown;

[0056] Fig.12 yes Figure 8 Another structural schematic diagram of the substrate in the method shown;

[0057] Fig.13 yes Figure 8 Another structural schematic diagram of the substrate in the method shown;

[0058] Fig.14 yes Figure 8 A schematic diagram of another structure of the substrate in the method shown;

[0059] Fig.15 yes Figure 8 Another structural schematic diagram of the substrate in the method shown;

[0060] Fig.16 yes Figure 8 Another structural schematic diagram of the substrate in the method shown;

[0061] Fig.17 yes Figure 8 Another structural schematic diagram of the substrate in the method shown;

[0062] Fig.18 yes Figure 3 Another structural schematic diagram of the substrate in the method shown;

[0063] Fig.19 is a flow chart of another method for manufacturing a thin film transistor provided in an embodiment of the present application;

[0064] Fig. 20 yes Fig.19 A schematic structural diagram of a substrate in the method shown;

[0065] Fig.21 yes Fig.19 Another structural schematic diagram of the substrate in the method shown;

[0066] Fig. 22 yes Fig.19 Another structural schematic diagram of the substrate in the method shown;

[0067] Fig.23 yes Fig.19 A schematic diagram of another structure of the substrate in the method shown;

[0068] Fig.24 yes Fig.19 Another structural schematic diagram of the substrate in the method shown;

[0069] Fig.25 yes Fig.19 Another structural schematic diagram of the substrate in the method shown;

[0070] Fig.26 is a schematic diagram of a film layer structure of a thin film transistor provided in an embodiment of the present application;

[0071] Fig. 27 It is a schematic diagram of the film layer structure of another thin film transistor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0072] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0073] Please refer to Figure 1 , Figure 1 The thin film transistor 00 may include: an active layer 01 located on one side of a substrate 10, a source-drain electrode layer 02 located on the side of the active layer 01 away from the substrate 10, and a protective electrode layer 03 located on the side of the source-drain electrode layer 02 away from the substrate 10.

[0074] The source-drain electrode layer 02 includes a source electrode 021 and a drain electrode 022 respectively connected to the active layer 01. The protective electrode layer 03 includes a first protective electrode 031 covering the source electrode 021 and a second protective electrode 031 covering the drain electrode 022. The protective electrode layer 03 and the source-drain electrode layer 02 are obtained by a single patterning process. The single patterning process generally includes: photoresist coating, exposure, development, etching, and photoresist stripping.

[0075] During the etching process in a patterning process, the lateral etching rate of the protective electrode layer 03 is greater than the lateral etching rate of the source and drain electrode layer 02. Therefore, during the etching process, the protective electrode layer 03 is prone to over-etching, resulting in part of the source and drain electrode layer 02 not being covered by the protective electrode layer 03. The part of the source and drain electrode layer 02 not covered by the protective electrode layer 03 is easily oxidized, thereby affecting the conductivity of the source and drain electrode layer 02, resulting in poor performance of the thin film transistor 00.

[0076] Please refer to Figure 2 , Figure 2 is a flow chart of a method for manufacturing a thin film transistor shown in an embodiment of the present application. The method may include:

[0077] Step 201: forming a semiconductor thin film covering the entire substrate on a substrate.

[0078] The semiconductor film is at least used for forming an active layer of a thin film transistor through subsequent patterning.

[0079] Step 202 : forming a patterned source and drain layer on the base substrate on which the semiconductor thin film is formed.

[0080] The source-drain electrode layer at least includes a source electrode and a drain electrode of the thin film transistor.

[0081] Step 203: forming a conductive film covering the entire substrate on the substrate having the source and drain electrode layers formed thereon.

[0082] The conductive film is at least used for forming a protective electrode layer covering the source electrode and the drain electrode through subsequent patterning.

[0083] Step 204: pattern the semiconductor film and the conductive film simultaneously to obtain an active layer formed by the semiconductor film and a protective electrode layer formed by the conductive film, and process the protective electrode layer so that at least part of the protective electrode layer between the source and the drain is disconnected or insulated.

[0084] In summary, the embodiment of the present application provides a method for manufacturing a thin film transistor. In this method, a protective electrode layer and an active layer are formed by a single patterning process, and the protective electrode layer and the source and drain electrode layer are formed by different patterning processes. In this way, without increasing the difficulty of the process, the formed protective electrode layer can cover the source and drain electrode layer, reducing the probability of the source and drain electrode layer being oxidized, improving the conductivity of the source and drain electrode layer, and thus improving the performance of the thin film transistor.

[0085] Figure 3 is a flow chart of another method for manufacturing a thin film transistor provided in an embodiment of the present application, the method may include:

[0086] Step 301: Obtain a substrate.

[0087] The material of the substrate may include glass or polyimide.

[0088] Step 302: forming a gate and a gate insulating layer in sequence on the substrate.

[0089] The gate may be a structure in a thin film transistor. When forming the gate, a gate metal layer may be first formed on a substrate substrate (the gate metal layer may be formed by deposition, sputtering, etc.), and then the gate metal layer may be processed by a patterning process to obtain a gate. It should be noted that a gate pattern including a plurality of gates may be obtained by a patterning process, and some or all of the gates in the gate pattern may refer to the gates involved in the embodiments of the present application. In the embodiments of the present application, the patterning processes involved may include photoresist coating, exposure, development, etching, and photoresist stripping.

[0090] When forming the gate insulating layer, the gate insulating layer may be formed by deposition, and the gate insulating layer may be used to prevent the gate from being short-circuited with other structures in the thin film transistor.

[0091] For example, Figure 4 As shown, Figure 4 3 is a schematic diagram of a structure of a substrate when step 302 is completed, wherein a gate 112 is formed on a substrate 111, and a gate insulating layer 113 is formed on the substrate 111 having the gate 112. The material of the gate 112 may include a metal material such as aluminum, copper or alloy. The material of the gate insulating layer 113 may include silicon dioxide, silicon nitride or a mixed material of silicon dioxide and silicon nitride.

[0092] Step 303: forming a semiconductor film covering the entire substrate on the gate insulating layer.

[0093] The semiconductor film may be formed by deposition. The material of the semiconductor film may include: oxide semiconductor material. For example, the material of the semiconductor film may be: indium gallium zinc oxide (IGZO). The semiconductor film is at least used to form an active layer of a thin film transistor through subsequent patterning.

[0094] For example, Figure 5 As shown, Figure 5 FIG. 1 is another schematic diagram of the structure of the substrate when step 303 is completed, in which a semiconductor thin film 114 is formed on the substrate 111 on which the gate insulating layer 113 is formed.

[0095] Step 304 : forming a patterned source and drain layer on the base substrate on which the semiconductor film is formed.

[0096] Forming a patterned source-drain electrode layer on a substrate substrate having a semiconductor thin film formed thereon may include: forming a source-drain electrode metal layer on a substrate substrate having a semiconductor thin film formed thereon, and then processing the source-drain electrode metal layer through a patterning process to obtain a source-drain electrode layer. The source-drain electrode layer includes at least a source electrode and a drain electrode of a thin film transistor. In the embodiment of the present application, the patterning process involved may include photoresist coating, exposure, development, etching, and photoresist stripping.

[0097] For example, Figure 6 As shown, Figure 6 This is another structural schematic diagram of the substrate substrate at the end of step 304, where a source-drain metal layer is formed on the substrate substrate 111 formed with the semiconductor thin film 114, and then a patterning process is performed on the source-drain metal layer to form a source-drain electrode layer 115. The source-drain electrode layer 115 at least includes a source electrode 115a and a drain electrode 115b of the thin film transistor. The material of the source-drain electrode layer 115 may include metal materials such as metal aluminum, metal silver, metal copper or alloys.

[0098] In the currently common thin film transistors, the source-drain electrode layer and the protective electrode layer are formed by a single patterning process. First, a source-drain electrode metal layer and a protective electrode metal layer are sequentially formed on the active layer, then a photoresist film is formed on the protective electrode metal, and the photoresist film is exposed and developed, then the source-drain electrode metal layer and the protective electrode metal layer are etched to form a source-drain electrode layer and a protective electrode layer, and finally the photoresist is stripped. The material of the protective electrode layer may include metal materials such as titanium, molybdenum-titanium alloy or molybdenum-niobium alloy.

[0099] However, when the material of the protective electrode layer is a molybdenum-niobium alloy, the adhesion of the molybdenum-niobium alloy to the photoresist is poor. Therefore, during the patterning process, the photoresist on the protective electrode metal layer is prone to fall off, resulting in over-etching of the source and drain metal layers, thereby affecting the yield of the thin film transistor.

[0100] In the present application, the source and drain electrode layers are formed through the above step 304, that is, the source and drain electrode layers are formed through a single patterning process. In this way, the phenomenon of over-etching of the source and drain electrode metal layers due to photoresist peeling off during the patterning process can be avoided, thereby improving the yield of the thin film transistor.

[0101] In another optional implementation, forming a patterned source and drain layer on a substrate substrate having a semiconductor film formed thereon may also include: forming a conductive metal layer and a source and drain metal layer in sequence on a substrate substrate having a semiconductor film formed thereon, and then processing the conductive metal layer and the source and drain metal layer through a patterning process to obtain a third protective electrode, a fourth protective electrode, a source and a drain, wherein the third protective electrode is located between the semiconductor film and the source, and the fourth protective electrode is located between the semiconductor film and the drain. The third protective electrode and the fourth protective electrode are used to protect the source and the drain to prevent the metal ions in the source and the drain from diffusing into the semiconductor film. In the embodiment of the present application, the patterning process involved may include photoresist coating, exposure, development, etching, and photoresist stripping.

[0102] Step 305 : forming a conductive film covering the entire substrate on the substrate having the source and drain electrode layers formed thereon.

[0103] The conductive film may be formed by deposition, and the conductive film is at least used for subsequent patterning to form a protective electrode layer covering the source and drain. The material of the conductive film may include: conductive materials such as metal molybdenum, metal titanium, molybdenum-titanium alloy or molybdenum-niobium alloy. For example, the material of the conductive film may be: metal molybdenum.

[0104] For example, Figure 7 As shown, Figure 7 FIG. 1 is another structural diagram of the base substrate when step 305 is completed, where a conductive film 116 is formed on the base substrate 111 on which the source-drain electrode layer 115 is formed.

[0105] Step 306: pattern the semiconductor film and the conductive film simultaneously to obtain an active layer formed by the semiconductor film and a protective electrode layer formed by the conductive film, and process the protective electrode layer so that at least a portion of the protective electrode layer between the source and the drain is disconnected.

[0106] like Figure 8 As shown, Figure 8 This is a flow chart of simultaneously patterning a semiconductor film and a conductive film provided by an embodiment of the present application. Step 306 may include the following four sub-steps:

[0107] Sub-step 3061: forming a photoresist layer on the conductive film.

[0108] For example, Fig. 9 As shown, Fig. 9 It is a schematic structural diagram of a substrate when step 3061 is completed, and a photoresist layer 117 is formed on the conductive film 116.

[0109] Step 3062: Expose and develop the photoresist layer to retain the first photoresist region above the source and the drain, and the second photoresist region between the source and the drain, and remove the photoresist in the photoresist completely removed region.

[0110] The formation process may include: using a grayscale mask to expose and develop the photoresist layer to retain the first photoresist area above the source and drain, and the second photoresist area between the source and drain, and removing the photoresist in the photoresist complete removal area. Among them, the photoresist, also known as photoresist, is the carrier medium of photolithography imaging. Its function is to use the principle of photochemical reaction to convert the light information after diffraction and filtering in the photolithography system into chemical energy, thereby completing the replication of the mask pattern.

[0111] like Fig.10 As shown, Fig.10 : is a schematic diagram of the structure of a grayscale mask provided in an embodiment of the present application. The grayscale mask 20 may include: a non-light-transmitting area 21, a semi-light-transmitting area 22 and a light-transmitting area 23, wherein the light transmittance of the non-light-transmitting area 21 is less than the light transmittance of the semi-light-transmitting area 22, and the light transmittance of the semi-light-transmitting area 22 is less than the light transmittance of the light-transmitting area 23. Taking the material of the photoresist layer as a positive photoresist as an example, after the photoresist layer is exposed and developed, the first photoresist area located above the source and the drain, and the second photoresist area located between the source and the drain can be retained, and the photoresist in the photoresist completely removed area is removed, and the photoresist thickness in the first photoresist area is greater than the photoresist thickness in the second photoresist area. The first photoresist area corresponds to the non-light-transmitting area 21 in the grayscale mask 20 , the second photoresist area corresponds to the semi-light-transmitting area 22 in the grayscale mask 20 , and the photoresist completely removed area corresponds to the light-transmitting area 23 in the grayscale mask 20 .

[0112] It should be noted that the embodiment of the present invention is schematically illustrated by taking the material of the photoresist film as positive photoresist as an example. In other optional implementations, the material of the photoresist film may also be negative photoresist, which is not limited in the embodiment of the present invention.

[0113] For example, Fig.11 As shown, Fig.11 It is a structural schematic diagram of the substrate when step 3062 is completed. The photoresist layer 117 is exposed and developed using a grayscale mask 20 to retain the first photoresist area 117a located above the source 115a and the drain 115b, and the second photoresist area 117b located between the source 115a and the drain 115b, and the photoresist in the photoresist complete removal area 117c is removed, and the photoresist thickness in the first photoresist area 117a is greater than the photoresist thickness in the second photoresist area 117b.

[0114] Sub-step 3063: wet-etching the semiconductor film and the conductive film simultaneously to remove the semiconductor film and the conductive film corresponding to the photoresist completely removed area to form an active layer and a protective electrode layer.

[0115] The semiconductor film and the conductive film corresponding to the photoresist completely removed area can be wet-etched simultaneously to remove the semiconductor film and the conductive film corresponding to the photoresist completely removed area to form an active layer and a protective electrode layer. The orthographic projection of the active layer on the substrate is located within the orthographic projection of the gate on the substrate.

[0116] Among them, wet etching processing refers to using an etchant to etch the semiconductor film and the conductive film.

[0117] In the embodiment of the present application, there are multiple possible implementations of the positional relationship between the first photoresist region and the source and drain, and there are multiple possible implementations of the shape of the formed protective electrode layer. The embodiment of the present application is schematically described by taking the following two possible implementations as examples:

[0118] In the first possible implementation, Fig.11 As shown, the first orthographic projection of the source 115a on the substrate 111, the first photoresist region 117a on the source 115a is within the second orthographic projection on the substrate 111, and the distance between the outer boundary of the first orthographic projection and the outer boundary of the second orthographic projection is greater than the preset distance threshold; the third orthographic projection of the drain 115b on the substrate 111, the first photoresist region 117a on the drain 115b is within the fourth orthographic projection on the substrate 111, and the distance between the outer boundary of the third orthographic projection and the outer boundary of the fourth orthographic projection is greater than the preset distance threshold. In this case, as Fig.12 As shown, Fig.12 This is another structural schematic diagram of the substrate substrate at the end of step 3063, where the semiconductor film 114 and the conductive film 116 corresponding to the photoresist completely removed area 117c are wet-etched simultaneously to remove the semiconductor film 114 and the conductive film 116 corresponding to the photoresist completely removed area 117c, so as to form an active layer 118 and a protective electrode layer 119. The orthographic projection of the active layer 118 on the substrate substrate 111 is located within the orthographic projection of the gate electrode 112 on the substrate substrate 111, and the protective electrode layer 119 can wrap the side surfaces of the source electrode 115a and the drain electrode 115b.

[0119] In the second possible implementation, Fig.13 As shown, Fig.133 is another structural diagram of the substrate when step 3062 is completed. The first photoresist region 117a located above the source 115a has two side surfaces, and the two side surfaces are respectively flush with the two side surfaces of the source 115a. The first photoresist region 117a located above the drain 115b also has two side surfaces, and the two side surfaces are respectively flush with the two side surfaces of the drain 115b. That is, the first photoresist region 117a can cover the source 115a and the drain 115b, and the first photoresist region 117a is flush with the side surfaces of the source 115a and the drain 115b. In this case, as Fig.14 As shown, Fig.14 3 is another structural schematic diagram of the substrate when step 3063 is completed, the semiconductor film 114 and the conductive film 116 corresponding to the photoresist completely removed area 117c are wet-etched simultaneously to remove the semiconductor film 114 and the conductive film 116 corresponding to the photoresist completely removed area 117c to form an active layer 118 and a protective electrode layer 119. The orthographic projection of the active layer 118 on the substrate 111 is located within the orthographic projection of the gate 112 on the substrate 111, the side of the source 115a away from the drain 115b is flush with the side of the protective electrode layer 119, and the side of the drain 115b away from the source 115a is flush with the side of the protective electrode layer 119.

[0120] It should be noted that the following embodiments of the present application are schematically described by taking the first possible implementation method as an example.

[0121] Sub-step 3064, using dry etching to remove the photoresist in the second photoresist area, and remove the protective electrode layer corresponding to the second photoresist area to form a first protective electrode located on the source and a second protective electrode located above the drain, and the first protective electrode and the second protective electrode are disconnected.

[0122] like Fig.12 As shown, the protective electrode layer 119 has a first portion 119c and a second portion 119d, wherein the first portion 119c contacts the source 115a and faces the drain 115b, and the second portion 119d contacts the drain 115b and faces the source 115a. The second photoresist region 117b is located between the first portion 119c and the second portion 119d.

[0123] The sub-step 3064 may include the following steps:

[0124] Step A1: remove the photoresist between the first portion and the second portion by dry etching, and thin the photoresist in the first photoresist area.

[0125] The substrate substrate formed with the protective electrode layer can be placed in a dry etching chamber, and an ashing gas is introduced, so that the ashing gas removes the photoresist between the first part and the second part, and thins the photoresist in the first photoresist area. The ashing gas is used to react with the photoresist to eliminate the photoresist on the substrate substrate. For example, the ashing gas may include a mixed gas of oxygen and sulfur hexafluoride.

[0126] For example, Fig.15 As shown, Fig.15 This is another structural schematic diagram of the substrate when step A1 is completed. The photoresist between the first portion 119c and the second portion 119d is removed by dry etching, and the photoresist in the first photoresist region 117a is thinned.

[0127] Step A2: using dry etching to remove the portion of the protective electrode layer between the first portion and the second portion, so that the active layer leaks out, thereby forming a first protective electrode and a second protective electrode.

[0128] Dry etching can be used to remove the portion of the protective electrode layer between the first portion and the second portion, so that the active layer leaks out to form the first protective electrode and the second protective electrode. In this way, the first protective electrode formed can completely wrap the side of the source electrode, and the second protective electrode can completely wrap the side of the drain electrode. In the subsequent process of depositing film layers on the first protective electrode and the second protective electrode, plasma bombardment of the side of the source electrode and the drain electrode can be avoided, and the metal ions in the source electrode and the drain electrode can be avoided from diffusing to the channel of the active layer, further ensuring the characteristics of the thin film transistor.

[0129] Among them, dry etching treatment refers to etching the conductive film using plasma in a dry etching chamber. The dry etching treatment can better control the etching rate of the conductive film, thereby reducing the probability of over-etching of the conductive film, thereby ensuring that the protective electrode layer can cover the source and drain layer, avoiding oxidation of the source and drain layer, and improving the conductivity of the source and drain layer. Optionally, the plasma can be: a mixed gas of oxygen and sulfur hexafluoride.

[0130] For example, Fig.16 As shown, Fig.16 This is another structural schematic diagram of the substrate when step A2 is completed. Dry etching is used to remove the portion of the protective electrode layer 119 between the first portion 119c and the second portion 119d, so that the active layer 118 leaks out to form a first protective electrode 119a and a second protective electrode 119b.

[0131] Step A3: using a plasma containing at least one of oxygen gas and nitrous oxide gas to perform surface treatment on the active layer.

[0132] The active layer may be surface treated by plasma to increase the oxygen vacancy concentration in the active layer, reduce the ohmic contact resistance between the active layer and the source and drain electrode layers, and thus improve the characteristics of the thin film transistor.

[0133] It should be noted that the above steps A1 to A3 can be performed in the same dry etching chamber.

[0134] Sub-step 3065 , removing the photoresist in the first photoresist area.

[0135] The photoresist in the first photoresist region may be removed by stripping.

[0136] For example, Fig.17 As shown, Fig.17 This is another schematic diagram of the structure of the substrate when step 3065 is completed, and the photoresist in the first photoresist area 117c is removed by stripping.

[0137] Step 307 : forming a passivation layer on the first protection electrode and the second protection electrode.

[0138] The passivation layer can be formed by chemical vapor deposition using plasma, which can protect the thin film transistor from being polluted by water vapor and impurities, and can also be used to prevent the thin film transistor from short-circuiting with the pixel electrode in the display panel formed later.

[0139] Optionally, the plasma may be a mixture of nitrous oxide gas and silane gas.

[0140] For example, Fig.18 As shown, Fig.18 This is another structural schematic diagram of the substrate when step 307 is completed. A passivation layer 1110 is formed on the first protection electrode 119a and the second protection electrode 119b. The material of the passivation layer 1110 may include silicon dioxide, silicon nitride, or a mixed material of silicon dioxide and silicon nitride.

[0141] It should be noted that a bottom-gate thin film transistor can be formed through the above steps 301 to 307 .

[0142] In summary, the embodiment of the present application provides a method for manufacturing a thin film transistor. In this method, a protective electrode layer and an active layer are formed by a single patterning process, and the protective electrode layer and the source and drain electrode layer are formed by different patterning processes. In this way, without increasing the difficulty of the process, the formed protective electrode layer can cover the source and drain electrode layer, reducing the probability of the source and drain electrode layer being oxidized, improving the conductivity of the source and drain electrode layer, and thus improving the performance of the thin film transistor.

[0143] Fig.19is a flow chart of another method for manufacturing a thin film transistor provided in an embodiment of the present application, the method may include:

[0144] Step 401: Obtain a substrate.

[0145] This step may refer to the above step 301 and will not be described in detail here.

[0146] Step 402: forming a semiconductor thin film on the substrate to cover the entire substrate.

[0147] The step 402 may refer to the above Figure 3 Step 303 in the illustrated embodiment will not be described in detail in the embodiment of the present application.

[0148] For example, Fig. 20 As shown, Fig. 20 It is a schematic diagram of the structure of a substrate when step 402 is completed, and a semiconductor film 114 is formed on the substrate 111 .

[0149] Step 403: forming a gate insulating layer, a gate and an intermediate dielectric layer in sequence on the semiconductor film.

[0150] When forming the gate insulating layer, a gate insulating film can first be formed on a semiconductor film by deposition, and then the gate insulating film is processed by a composition process to obtain a gate insulating layer, which can be used to prevent the gate from short-circuiting with other structures in the thin film transistor.

[0151] The gate may be a structure in a thin film transistor. When forming the gate, a gate metal layer may be first formed on a substrate substrate (the gate metal layer may be formed by deposition, sputtering, etc.), and then the gate metal layer may be processed by a patterning process to obtain a gate. It should be noted that a gate pattern including a plurality of gates may be obtained by a patterning process, and some or all of the gates in the gate pattern may refer to the gates involved in the embodiments of the present application. In the embodiments of the present application, the patterning processes involved may include photoresist coating, exposure, development, etching, and photoresist stripping.

[0152] When forming the intermediate dielectric layer, firstly, an intermediate dielectric film may be formed on the base substrate on which the gate is formed, and then a patterning process is performed on the intermediate dielectric film to form the intermediate dielectric layer.

[0153] For example, Fig.21 As shown, Fig.214 is another structural schematic diagram of the substrate when step 403 is completed, wherein a gate insulating layer 113, a gate electrode 112 and an intermediate dielectric layer 1111 are sequentially formed on the semiconductor film 114. The material of the gate electrode 112 may include metal. The materials of the gate insulating layer 113 and the intermediate dielectric layer 1111 may include silicon dioxide, silicon nitride or a mixed material of silicon dioxide and silicon nitride.

[0154] Step 404 : forming a patterned source and drain layer on the base substrate on which the semiconductor film is formed.

[0155] The step 404 may refer to the above Figure 3 Step 304 in the illustrated embodiment will not be described in detail in the embodiment of the present application.

[0156] For example, Fig. 22 As shown, Fig. 22 This is another structural schematic diagram of the substrate when step 404 is completed. A source-drain metal layer is formed on the substrate 111 formed with the intermediate dielectric layer 1111 , and then a patterning process is performed on the source-drain metal layer to form a source-drain electrode layer 115 .

[0157] Step 405 : forming a conductive film covering the entire substrate on the substrate having the source and drain electrode layers formed thereon.

[0158] The step 405 may refer to the above Figure 3 Step 305 in the illustrated embodiment will not be described in detail in the embodiment of the present application.

[0159] For example, Fig.23 As shown, Fig.23 4 is another structural schematic diagram of the base substrate when step 405 is completed. A conductive film 116 covering the entire base substrate 111 is formed on the base substrate 111 on which the source-drain electrode layer 115 is formed.

[0160] Step 406: pattern the semiconductor film and the conductive film simultaneously to obtain an active layer formed by the semiconductor film and a protective electrode layer formed by the conductive film, and process the protective electrode layer so that at least a portion of the protective electrode layer between the source and the drain is disconnected.

[0161] The step 406 may refer to the above Figure 3 Sub-steps 3061 to 3065 in the illustrated embodiment will not be described in detail in the embodiment of the present application.

[0162] For example, Fig.24 As shown, Fig.24This is another schematic diagram of the structure of the substrate when step 406 is completed. The semiconductor film 114 and the conductive film 116 are patterned simultaneously to obtain an active layer 118 formed by the semiconductor film 114 and a protective electrode layer 119 formed by the conductive film 116 .

[0163] Step 407 : forming a passivation layer on the first protection electrode and the second protection electrode.

[0164] The step 407 may refer to the above Figure 3 Step 307 in the illustrated embodiment will not be described in detail in the embodiment of the present application.

[0165] For example, Fig.25 As shown, Fig.25 FIG. 4 is another schematic diagram of the structure of the substrate when step 407 is completed, and a passivation layer 1110 is formed on the first protection electrode 119 a and the second protection electrode 119 b .

[0166] It should be noted that a top-gate thin film transistor can be formed through the above steps 401 to 407 .

[0167] In summary, the embodiment of the present application provides a method for manufacturing a thin film transistor. In this method, a protective electrode layer and an active layer are formed by a single patterning process, and the protective electrode layer and the source and drain electrode layer are formed by different patterning processes. In this way, without increasing the difficulty of the process, the formed protective electrode layer can cover the source and drain electrode layer, reducing the probability of the source and drain electrode layer being oxidized, improving the conductivity of the source and drain electrode layer, and thus improving the performance of the thin film transistor.

[0168] The present application also provides a thin film transistor, which can be manufactured by the thin film transistor manufacturing method in the above embodiment. Fig.26 or Fig. 27 , Fig.26 is a schematic diagram of a film layer structure of a thin film transistor provided in an embodiment of the present application, Fig. 27 Schematic diagram of the film layer structure of another thin film transistor provided in an embodiment of the present application. The thin film transistor may include:

[0169] The active layer 118 is located on one side of the base substrate 111 .

[0170] The source-drain electrode layer 115 is located on a side of the active layer 118 away from the base substrate 111 , and the source-drain electrode layer 115 at least includes a source electrode 115 a and a drain electrode 115 b .

[0171] And, a protective electrode layer 119 is located on the side of the source and drain layer 115 away from the substrate. The protective electrode layer 119 covers the source 115a and the drain 115b, and at least a portion of the protective electrode layer 119 between the source 115a and the drain 115b is disconnected or insulated.

[0172] In the embodiments of the present application, Fig.26 and Fig. 27 As shown, the protective electrode layer in the thin film transistor may include: a first protective electrode 119a located on the source electrode 115a and a second protective electrode 119b located on the drain electrode 115b, and the first protective electrode 119a and the second protective electrode 119b are disconnected. The side of the first protective electrode 119a away from the second protective electrode 119b is flush with the side of the active layer 118, and the side of the second protective electrode 119b away from the first protective electrode 119a is flush with the side of the active layer 118.

[0173] In the present application, there are many possible implementations of the shapes of the first protection electrode 119a and the second protection electrode 119b. The present application embodiment uses the following two possible implementations as examples for schematic illustration:

[0174] In the first possible implementation, Fig.26 As shown, the first protection electrode 119a wraps the side of the source electrode 115a, and the second protection electrode 119b wraps the side of the drain electrode 115b. In this way, the first protection electrode 119a can completely wrap the side of the source electrode 115a, and the second protection electrode 119b can completely wrap the side of the drain electrode 115b. In the subsequent process of depositing a film layer on the first protection electrode 119a and the second protection electrode 119b, plasma bombardment of the side of the source electrode 115a and the drain electrode 115b can be avoided, and the metal ions in the source electrode 115a and the drain electrode 115b can be avoided from diffusing to the channel of the active layer 118, further ensuring the characteristics of the thin film transistor.

[0175] In the second possible implementation, Fig. 27 As shown, the side of the first protection electrode 119a is flush with the side of the source electrode 115a, and the side of the second protection electrode 119b is flush with the side of the drain electrode 115b. In this way, the first protection electrode 119a can cover the source electrode 115a, and the second protection electrode 119b can cover the drain electrode 115b, which reduces the probability of the source electrode 115a and the drain electrode 115b being oxidized, improves the conductivity of the source electrode 115a and the drain electrode 115b, and thus improves the performance of the thin film transistor.

[0176] In this application, if Fig.17 and Fig.24As shown, the orthographic projections of the source electrode 115a and the drain electrode 115b on the base substrate 111 are located within the orthographic projection of the active layer 118 on the base substrate 111. In this way, the source electrode 115a and the drain electrode 115b do not need to climb on the active layer 118, thereby avoiding the phenomenon that the source electrode 115a and the drain electrode 115b are broken due to the step difference, and further ensuring the characteristics of the thin film transistor.

[0177] In the embodiments of the present application, Fig.26 and Fig. 27 As shown, the thin film transistor may further include: a third protection electrode A located between the active layer 118 and the source electrode 115a, and a fourth protection electrode B located between the active layer 118 and the drain electrode 115b. The third protection electrode A and the fourth protection electrode B may be used to protect the source electrode 115a and the drain electrode 115b, and prevent metal ions in the source electrode 115a and the drain electrode 115b from diffusing into the semiconductor film.

[0178] In this application, if Fig.26 and Fig. 27 As shown, the thin film transistor may further include: a gate electrode 112 and a gate insulating layer 113 located on the base substrate 111. The orthographic projection of the active layer 118 in the thin film transistor on the base substrate 111 is located within the orthographic projection of the gate electrode 112 on the base substrate 111, and the active layer 118 and the gate electrode 112 are insulated by the gate insulating layer 113.

[0179] Optionally, the material of the source and drain electrode layer 115 may include metal copper, and the material of the protective electrode layer 119 may include molybdenum-niobium alloy.

[0180] Optionally, the thin film transistor may further include a passivation layer 1110 located on a side of the protection electrode 119 away from the base substrate 111 .

[0181] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the principles of the various components in the display panel described above can refer to the corresponding contents in the embodiment of the aforementioned method for manufacturing the display panel, and will not be repeated here.

[0182] In summary, the embodiment of the present application provides a thin film transistor. In the thin film transistor, the protective electrode layer can cover the source and drain electrode layer, reducing the probability of the source and drain electrode layer being oxidized, improving the conductivity of the source and drain electrode layer, and thus improving the performance of the thin film transistor. At the same time, since the source and drain electrode layer is completely covered by the protective electrode layer, during the subsequent deposition of the film layer on the protective electrode layer, it is possible to avoid plasma bombardment of the side of the source and drain electrode layer, thereby preventing the metal ions in the source and drain electrode layer from diffusing to the channel of the active layer, further ensuring the characteristics of the thin film transistor.

[0183] The present application also provides a display panel, which may include: a substrate, and a plurality of Fig.26 or Fig. 27 The thin film transistor shown. The display panel may be a liquid crystal display panel and an organic light-emitting diode (OLED) display panel. When the display panel is a liquid crystal display panel, the thin film transistor may be integrated in an array substrate in the liquid crystal display panel.

[0184] The embodiment of the present application also provides a display device, which may include a power supply component and the above-mentioned display panel, and the power supply component is used to supply power to the display panel. The display device may be: a liquid crystal panel, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0185] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0186] In the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "plurality" refers to two or more than two, unless otherwise clearly defined.

[0187] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for manufacturing a thin film transistor, characterized in that: The method comprises: Forming a semiconductor thin film covering the entire substrate on the substrate, wherein the semiconductor thin film is at least used to form an active layer of the thin film transistor after subsequent patterning; Forming a patterned source-drain electrode layer on the substrate on which the semiconductor thin film is formed, wherein the source-drain electrode layer at least includes a source electrode and a drain electrode of the thin film transistor; Forming a conductive film covering the entire substrate on the substrate having the source and drain electrode layers formed thereon, wherein the conductive film is at least used for forming a protective electrode layer covering the source and drain electrodes through subsequent patterning; The semiconductor film and the conductive film are patterned simultaneously to obtain the active layer formed by the semiconductor film and the protective electrode layer formed by the conductive film, and the protective electrode layer is processed so that at least part of the protective electrode layer between the source and the drain is disconnected or insulated.

2. The method according to claim 1, characterized in that The semiconductor film and the conductive film are patterned simultaneously to obtain the active layer formed by the semiconductor film and the protective electrode layer formed by the conductive film, and the protective electrode layer is processed so that at least a portion of the protective electrode layer between the source electrode and the drain electrode is disconnected, comprising: Forming a photoresist layer on the conductive film, performing exposure and development processing on the photoresist layer to retain a first photoresist region located above the source electrode and the drain electrode, and a second photoresist region located between the source electrode and the drain electrode, and removing the photoresist in the photoresist completely removed region, wherein the photoresist thickness in the first photoresist region is greater than the photoresist thickness in the second photoresist region; Simultaneously wet-etching the semiconductor film and the conductive film to remove the semiconductor film and the conductive film corresponding to the photoresist completely removed area to form the active layer and the protective electrode layer; The photoresist in the second photoresist area is removed by dry etching, and the protective electrode layer corresponding to the second photoresist area is removed to form a first protective electrode located on the source and a second protective electrode located above the drain, and the first protective electrode and the second protective electrode are disconnected.

3. The method according to claim 2, characterized in that A first orthographic projection of the source electrode on the substrate is located within a second orthographic projection of a first photoresist region on the source electrode on the substrate, and a distance between an outer boundary of the first orthographic projection and an outer boundary of the second orthographic projection is greater than a preset distance threshold; The third orthographic projection of the drain on the substrate is located within the fourth orthographic projection of the first photoresist region on the drain on the substrate, and the distance between the outer boundary of the third orthographic projection and the outer boundary of the fourth orthographic projection is greater than a preset distance threshold; After the protective electrode layer is formed, the protective electrode layer wraps the side surfaces of the source electrode and the drain electrode.

4. The method according to claim 2, characterized in that: The first photoresist region located above the source electrode has two side surfaces, and the two side surfaces are respectively flush with the two side surfaces of the source electrode; the first photoresist region located above the drain electrode has two side surfaces, and the two side surfaces are respectively flush with the two side surfaces of the drain electrode, so that the first photoresist region covers the source electrode and the drain electrode, and is flush with the side surfaces of the source electrode and the drain electrode; After the protective electrode layer is formed, the side of the source electrode away from the drain electrode is flush with the side of the protective electrode layer, and the side of the drain electrode away from the source electrode is flush with the side of the protective electrode layer.

5. The method according to claim 3, characterized in that: The protective electrode layer has a first portion and a second portion, the first portion is in contact with the source electrode and faces the drain electrode, the second portion is in contact with the drain electrode and faces the source electrode, and the second photoresist region is located between the first portion and the second portion; The method comprises: removing the photoresist in the second photoresist area by dry etching, and removing the protective electrode layer corresponding to the second photoresist area to form a first protective electrode on the source electrode and a second protective electrode on the drain electrode, wherein the first protective electrode and the second protective electrode are disconnected, comprising: Using dry etching to remove the photoresist between the first portion and the second portion, and thinning the photoresist in the first photoresist area; The portion of the protective electrode layer located between the first portion and the second portion is removed by dry etching to allow the active layer to leak out, thereby forming the first protective electrode and the second protective electrode.

6. The method according to claim 5, characterized in that After removing the portion of the protective electrode layer between the first portion and the second portion by dry etching to allow the active layer to leak out, the method further includes: The active layer is surface treated using plasma including at least one of oxygen gas and nitrous oxide gas to adjust the concentration of oxygen vacancies in the active layer.

7. The method according to any one of claims 1 to 6, characterized in that: Before forming the semiconductor thin film on the substrate, the method further comprises: A gate and a gate insulating layer are sequentially formed on the base substrate, wherein the orthographic projection of the active layer on the base substrate is located within the orthographic projection of the gate on the base substrate.

8. A thin film transistor, characterized in that: The thin film transistor is manufactured by the method according to any one of claims 1 to 7; the thin film transistor comprises: an active layer located on one side of the substrate base; A source-drain electrode layer located on a side of the active layer away from the substrate, the source-drain electrode layer at least comprising a source electrode and a drain electrode; And, a protective electrode layer is located on the side of the source and drain layer away from the base substrate, the orthographic projection of the protective electrode layer on the base substrate completely covers the orthographic projection of the source on the base substrate, and the orthographic projection of the protective electrode layer on the base substrate completely covers the orthographic projection of the drain on the base substrate, and at least part of the protective electrode layer between the source and the drain is disconnected or insulated.

9. The thin film transistor according to claim 8, characterized in that: The protection electrode layer includes a first protection electrode located on the source electrode and a second protection electrode located on the drain electrode, and the first protection electrode and the second protection electrode are disconnected.

10. The thin film transistor according to claim 9, characterized in that: The first protection electrode wraps around a side surface of the source electrode, and the second protection electrode wraps around a side surface of the drain electrode.

11. The thin film transistor according to claim 9, characterized in that: The side surface of the first protection electrode is flush with the side surface of the source electrode, and the side surface of the second protection electrode is flush with the side surface of the drain electrode.

12. The thin film transistor according to claim 10 or 11, characterized in that: A side surface of the first protection electrode away from the second protection electrode is flush with a side surface of the active layer, and a side surface of the second protection electrode away from the first protection electrode is flush with a side surface of the active layer.

13. The thin film transistor according to claim 12, characterized in that: The orthographic projections of the source electrode and the drain electrode on the base substrate are located within the orthographic projection of the active layer on the base substrate.

14. The thin film transistor according to any one of claims 8 to 11, characterized in that: The thin film transistor further includes: a third protection electrode located between the active layer and the source electrode, and a fourth protection electrode located between the active layer and the drain electrode.

15. The thin film transistor according to claim 14, characterized in that: The material of the source and drain electrode layers includes: metallic copper, and the material of the protective electrode layer includes: molybdenum-niobium alloy.

16. A display panel, characterized in that: The display panel comprises: a base substrate, and a plurality of thin film transistors according to any one of claims 8 to 15 located on the base substrate.

17. A display device, characterized in that: The display device comprises: a power supply component and a display panel as claimed in claim 16; The power supply component is used to supply power to the display panel.

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