Slew rate acceleration circuit and buffer circuit including the same

Abstract

The present disclosure discloses a slew rate acceleration circuit and a buffer circuit including the same. The slew rate acceleration circuit in a buffer circuit is configured to: detect a current flowing through a load stage of the buffer circuit; compare the value of the detected current with a reference value; and, based on the comparison result, provide a regulated driving voltage to an output stage of the buffer circuit to increase the slew rate of the buffer circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0036348, filed on March 22, 2021, which is hereby incorporated by reference in its entirety for all purposes. Technical Field

[0003] The following description relates to a slew rate acceleration circuit and a buffer circuit including the slew rate acceleration circuit. Background Art

[0004] Buffer circuits can be used to buffer signals and can be applied to various technical fields, such as source drivers and gate drivers of display devices. In the case of display devices, slew rate is becoming an important issue due to an increase in load capacitance and a decrease in horizontal period caused by an increase in size.

[0005] The display device includes a source driver for driving a display panel, and the source driver provides source driving signals corresponding to image data to data lines of the display panel.

[0006] The source driver includes a buffer circuit that buffers a source driving signal and outputs it to prevent the source driving signal from being distorted by load components such as resistance of a data line and a capacitor. An operational amplifier may be used as the buffer circuit.

[0007] Recently, as display devices have become larger and have higher resolutions, the time required to drive one horizontal line has decreased. As a result, the required margin for pull-up or pull-down in the buffer circuit cannot be ensured, and the source drive signal cannot reach the target voltage within a predetermined period of time, resulting in a problem of deteriorating image quality.

[0008] To solve the above problem, a method of increasing the slew rate of the buffer circuit by increasing the bias current of the buffer circuit can be considered. However, this requires increased power consumption.

[0009] Therefore, a buffer circuit is needed for achieving a stable high conversion rate without increasing power consumption. Summary of the Invention

[0010] This Summary is provided to introduce a series of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0011] In one general aspect, a slew rate acceleration circuit in a buffer circuit is configured to: detect a current flowing through a load stage of the buffer circuit; compare a value of the detected current with a reference value; and, based on a result of the comparison, provide a regulated driving voltage to an output stage of the buffer circuit to increase a slew rate of the buffer circuit.

[0012] The load stage of the buffer circuit may include at least one current mirror circuit, and the slew rate acceleration circuit may be further configured to detect a current flowing through the load stage based on a gate voltage of a transistor in the current mirror circuit.

[0013] The slew rate acceleration circuit may include a current detection circuit configured to form a current mirror with a current mirror circuit of the load stage.

[0014] The current detection circuit may include a current sensing transistor configured to perform a current mirror operation on the current flowing through the load stage, and a gate electrode of the current sensing transistor may be connected to a gate electrode of a transistor constituting the current mirror circuit of the load stage.

[0015] The slew rate acceleration circuit may further include at least one bias transistor, and the reference value may be controlled based on a gate voltage of the bias transistor.

[0016] The output stage may include at least one driving transistor, and the slew rate acceleration circuit may further include a control circuit configured to provide a regulated driving voltage to a gate electrode of the driving transistor.

[0017] The control circuit may include at least one accelerating transistor, and a source electrode of the accelerating transistor may be connected to a gate electrode of the driving transistor.

[0018] The current mirror operation may be configured to transmit a control signal to a gate electrode of the acceleration transistor, and the acceleration transistor may be configured to be turned on / off based on the control signal.

[0019] At least one driving transistor may include a first driving transistor and a second driving transistor, at least one accelerating transistor may include a first accelerating transistor and a second accelerating transistor, the source electrode of the first driving transistor and the drain electrode of the second accelerating transistor may be connected to a first power supply voltage, and the source electrode of the second driving transistor and the drain electrode of the first accelerating transistor may be connected to a second power supply voltage.

[0020] The source electrode of the first acceleration transistor and the gate electrode of the first driving transistor may be commonly connected to the first output terminal of the current mirror circuit, and the source electrode of the second acceleration transistor and the gate electrode of the second driving transistor may be commonly connected to the second output terminal of the current mirror circuit.

[0021] The first driving transistor and the first accelerating transistor may be PMOS transistors, and the second driving transistor and the second accelerating transistor may be NMOS transistors.

[0022] In another general aspect, a buffer circuit includes an operational amplifier configured to amplify an input voltage and output an output voltage through an output node; a current detection circuit configured to detect a current flowing through a load stage of the operational amplifier; and a control circuit configured to provide a regulated drive voltage to the output stage of the operational amplifier based on a control signal to increase a slew rate of the operational amplifier.

[0023] The load stage may include at least one current mirror circuit, the output stage may include at least one driver transistor, and the control circuit may be configured to provide a regulated drive voltage to a gate electrode of the driver transistor.

[0024] The current detection circuit may include a current sensing transistor configured to perform a current mirror operation on the current flowing through the load stage, and a gate electrode of the current sensing transistor may be connected to a gate electrode of a transistor constituting the current mirror circuit of the load stage.

[0025] The control circuit may include at least one accelerating transistor, and a source electrode of the accelerating transistor may be connected to a gate electrode of the driving transistor.

[0026] The current mirror operation may be configured to transmit a control signal to a gate electrode of the acceleration transistor, and the acceleration transistor may be configured to be turned on / off based on the control signal.

[0027] At least one driving transistor may include a first driving transistor and a second driving transistor, at least one accelerating transistor may include a first accelerating transistor and a second accelerating transistor, the source electrode of the first driving transistor and the drain electrode of the second accelerating transistor may be connected to a first power supply voltage, and the source electrode of the second driving transistor and the drain electrode of the first accelerating transistor may be connected to a second power supply voltage.

[0028] The source electrode of the first acceleration transistor and the gate electrode of the first driving transistor may be commonly connected to the first output terminal of the current mirror circuit, and the source electrode of the second acceleration transistor and the gate electrode of the second driving transistor may be commonly connected to the second output terminal of the current mirror circuit.

[0029] The first driving transistor and the first accelerating transistor may be PMOS transistors, and the second driving transistor and the second accelerating transistor may be NMOS transistors.

[0030] Other features and aspects will be apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a block diagram of an example of a buffer circuit according to one or more embodiments of the present disclosure.

[0032] Figure 2 According to one or more embodiments of the present disclosure Figure 1 A more detailed block diagram of an example of a buffer circuit.

[0033] Figure 3 is a more detailed description of one or more embodiments according to the present disclosure. Figure 2 The circuit diagram of the block diagram of the buffer circuit.

[0034] Figure 4 and Figure 5 Exemplary waveforms of the input signal voltage, gate voltage, and output signal voltage of the acceleration transistor are shown.

[0035] Figure 6 An example of a display device including a buffer circuit according to one or more embodiments of the present disclosure is conceptually illustrated.

[0036] Throughout the drawings and detailed description, like reference numerals refer to like elements. The drawings may not be drawn to scale, and the relative sizes, proportions, and depictions of elements in the drawings may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0037] The following detailed description is provided to help the reader obtain a comprehensive understanding of the methods, devices and / or systems described herein. However, after understanding the disclosure of the application, various changes, modifications and equivalents of the methods, devices and / or systems described herein will be apparent. For example, except for operations that must occur in a specific order, the order of operations described herein is merely an example and is not limited to the order set forth herein, but may be changed as apparent after understanding the disclosure of the application. In addition, for increased clarity and brevity, descriptions of features known in the art may be omitted.

[0038] The features described herein may be embodied in different forms and should not be construed as limited to the examples described herein. Moreover, the examples described herein are provided merely to illustrate some of the many possible ways to implement the methods, devices, and / or systems described herein that will become apparent upon understanding the disclosure of this application.

[0039] Throughout the specification, when an element such as a layer, a region, or a substrate is described as being “on,” “connected to,” or “coupled to” another element, the element may be directly “on,” “connected to,” or “coupled to” the other element, or one or more other elements may be interposed between the element and the other element. In contrast, when an element is described as being “directly on,” “directly connected to,” or “directly coupled to” another element, no other elements may be interposed.

[0040] As used herein, the term "and / or" includes any one of the associated listed items and any combination of any two or more.

[0041] Although terms such as "first," "second," and "third" may be used herein to describe various members, components, regions, layers, or portions, these members, components, regions, layers, or portions are not limited by these terms. Moreover, these terms are only used to distinguish one member, component, region, layer, or portion from another member, component, region, layer, or portion. Thus, in the examples described herein, a first member, a first component, a first region, a first layer, or a first portion may also be referred to as a second member, a second component, a second region, a second layer, or a second portion without departing from the teachings of the examples.

[0042] For ease of description, spatially relative terms such as "above," "up," "below," and "below" may be used herein to describe the relationship of one element to another element as shown in the figures. In addition to the orientations depicted in the figures, such spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is turned over, an element described as being "above" or "up" relative to another element will be "below" or "down" relative to the other element. Therefore, depending on the spatial orientation of the device, the term "above" covers both the "above" and "below" orientations. The device may also be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative terms used herein will be interpreted accordingly.

[0043] The terms used herein are intended only to describe various examples and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the articles "a," "an," and "the" are also intended to include plural forms. The terms "comprise," "include," and "have" specify the presence of the stated features, numbers, operations, components, elements, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, components, elements, and / or combinations thereof.

[0044] Due to manufacturing techniques and / or tolerances, variations in the shapes shown in the drawings may occur. Therefore, the examples described herein are not limited to the specific shapes shown in the drawings but also include variations in shapes produced during manufacturing.

[0045] As will be apparent after understanding the disclosure of the present application, the features of the examples described herein can be combined in various ways. In addition, as will be apparent after understanding the disclosure of the present application, although the examples described herein have multiple configurations, other configurations are possible.

[0046] Figure 1 is a block diagram of a buffer circuit according to one or more embodiments of the present disclosure.

[0047] Reference Figure 1 The buffer circuit 100 may receive an input voltage VIN and output an output voltage VOUT based on the input voltage VIN. According to one or more embodiments, the buffer circuit 100 may buffer the input voltage VIN and output it as an output voltage VOUT. For example, the output voltage VOUT may be generated by amplifying the input voltage VIN.

[0048] In this specification, when a random voltage is received, a line through which the random voltage is supplied is electrically connected to a corresponding configuration.

[0049] The buffer circuit 100 may include an operational amplifier 110 and a slew rate acceleration circuit 120. In addition, according to one or more embodiments, each buffer circuit 100 may include an operational amplifier and a slew rate acceleration circuit.

[0050] Operational amplifier 110 can amplify input voltage VIN and output it as output voltage VOUT. Ideally, operational amplifier 110 can output output voltage VOUT immediately in response to application of input voltage VIN. However, in practice, the transition between input voltage VIN and output voltage VOUT may take time (i.e., transition time). This transition time can be expressed as a slew rate.

[0051] The slew rate acceleration circuit 120 can control the slew rate of the operational amplifier 110. According to one or more embodiments, the slew rate acceleration circuit 120 can receive the value of the operating current flowing within the operational amplifier 110 and can adjust the transition time between the input voltage VIN and the output voltage VOUT based on the value of the operating current. For example, when the value of the operating current flowing within the operational amplifier 110 exceeds a reference value, the slew rate acceleration circuit 120 can be turned on, and the transition time between the input voltage VIN and the output voltage VOUT can be reduced.

[0052] Figure 2 According to one or more embodiments of the present disclosure Figure 1 A more detailed block diagram of the buffer circuit.

[0053] Reference Figure 1 and Figure 2 , the operational amplifier 110 may include an input stage 111 , a load stage 113 , and an output stage 115 .

[0054] The input stage 111 may receive an input voltage VIN and an output voltage VOUT and may determine a magnitude of a difference between the input voltage VIN and the output voltage VOUT. In addition, the input stage 111 may be electrically connected to a load stage 113.

[0055] The load stage 113 may determine a gain of the operational amplifier 110. According to one or more embodiments, the load stage 113 may amplify the input voltage VIN according to the gain and transmit the amplified input voltage to the output stage 115.

[0056] The load stage 113 may transmit a driving signal DS for controlling the output stage 115 to the output stage 115. For example, the driving signal DS may be a pull-up or pull-down voltage used in the operational amplifier 110.

[0057] The output stage 115 may output the output voltage VOUT in response to the driving signal DS. According to one or more embodiments, the output stage 115 may be turned on by the driving signal DS and may output the output voltage VOUT.

[0058] The output stage 115 may receive the adjusted driving voltage ADI from the slew rate acceleration circuit 120 , and thus, the slew rate of the output stage 115 may be accelerated.

[0059] The slew rate acceleration circuit 120 may include a control circuit 121 and a current detection circuit 123 .

[0060] The control circuit 121 may be connected to the output stage 115 of the operational amplifier 110. The control circuit 121 may accelerate the slew rate of the output stage 115 by providing a regulated drive voltage ADI to the output stage 115. According to one or more embodiments, when the input voltage VIN of the output stage 115 transitions to the output voltage VOUT, the control circuit 121 provides the regulated drive voltage ADI to the output stage 115, thereby causing the input voltage VIN to transition to the output voltage VOUT more quickly, thereby accelerating the slew rate of the output stage 115.

[0061] The current detection circuit 123 may output a control signal CS for controlling the control circuit 121. According to one or more embodiments, the current detection circuit 123 may output the control signal CS to the control circuit 121 based on the difference between the input voltage VIN and the output voltage VOUT. The control circuit 121 may be turned on (or enabled) in response to the control signal CS and may provide the regulated drive voltage ADI to the output stage 115.

[0062] The slew rate acceleration circuit 120 according to one or more embodiments of the subject disclosure may receive a value of an operating current flowing inside the operational amplifier 110 and may accelerate a transition time between an input voltage VIN and an output voltage VOUT based on the value of the operating current.

[0063] Figure 3 is a more detailed description of one or more embodiments according to the present disclosure. Figure 2 The circuit diagram of the block diagram of the buffer circuit.

[0064] Reference Figures 1 to 3 The load stage 113 may include an upper current mirror circuit, a lower current mirror circuit, a first connection circuit, and a second connection circuit.

[0065] The upper current mirror circuit may include PMOS transistors PT31 and PT32 connected in the form of a current mirror. The upper current mirror circuit may include a first output terminal N3. The lower current mirror circuit may include NMOS transistors NT31 and NT32 connected in the form of a current mirror. The lower current mirror circuit may include a second output terminal N4.

[0066] The first connection circuit may include a PMOS transistor PT35 operating in response to a first bias voltage VB31 and an NMOS transistor NT35 operating in response to a second bias voltage VB41. The second connection circuit may include a PMOS transistor PT36 operating in response to a third bias voltage VB32 and an NMOS transistor NT36 operating in response to a fourth bias voltage VB42.

[0067] The upper current mirror circuit and the lower current mirror circuit are electrically connected to the input stage and provide current to the output stage 115. A first connection circuit electrically connects a first gate common terminal N1 of the upper current mirror circuit and a second gate common terminal N2 of the lower current mirror circuit. A second connection circuit electrically connects a first output terminal N3 of the upper current mirror circuit and a second output terminal N4 of the lower current mirror circuit.

[0068] The load stage 113 may include an upper cascode circuit connected between the upper current mirror circuit and the connection circuit. The upper cascode circuit includes a PMOS transistor PT33 and a PMOS transistor PT34. Furthermore, the load stage 113 may include a lower cascode circuit connected between the lower current mirror circuit and the connection circuit. The lower cascode circuit includes an NMOS transistor NT33 and an NMOS transistor NT34. Because the load stage including the cascode circuit has a large output impedance, the buffer circuit including the load stage can achieve a high voltage gain.

[0069] The output stage 115 may be connected to a first power line VL1 and a second power line VL2 and may receive a power supply voltage. For example, the first power line VL1 may be connected to a power supply voltage VDD, and the second power line VL2 may be connected to a ground GND.

[0070] The output stage 115 may include two driving transistors DTR1 and DTR2. According to one or more embodiments, the output stage 115 may include a first driving transistor DTR1 connected between the first power line VL1 and the output node NOUT, and a second driving transistor DTR2 connected between the second power line VL2 and the output node NOUT.

[0071] The gate terminal of the first drive transistor DTR1 is connected to the first output terminal N3 of the upper current mirror circuit. The first drive transistor DRT1 is connected between the power supply voltage VDD and the output node NOUT. The gate terminal of the second drive transistor DTR2 is connected to the second output node N4 of the lower current mirror circuit. The second drive transistor DTR2 is connected between the output node NOUT and the ground GND.

[0072] The first drive transistor DTR1 is turned on / off in response to a first drive signal DS1 transmitted from the load stage 113, and the second drive transistor DTR2 is turned on / off in response to a second drive signal DS2 transmitted from the load stage 113. According to one or more embodiments, the first drive transistor DTR1 may perform a pull-up operation, and the second drive transistor DTR2 may perform a pull-down operation.

[0073] The first drive transistor DTR1 and the second drive transistor DTR2 may operate complementarily. For example, when the first drive transistor DTR1 is turned on, the second drive transistor DTR2 may be turned off, and conversely, when the first drive transistor DTR1 is turned off, the second drive transistor DTR2 may be turned on.

[0074] The control circuit 121 may be connected to the output stage 115. According to one or more embodiments, the control circuit 121 may include two acceleration transistors AT1 and AT2, which provide regulated drive voltages ADI1 and ADI2 to the first and second drive transistors DTR1 and DTR2 that constitute the output stage 115. The first acceleration transistor AT1 may provide the first regulated drive voltage ADI1 to the first drive transistor DTR1. The first regulated drive voltage ADI1 may be a pull-down signal. The second acceleration transistor AT2 may provide the second regulated drive voltage ADI2 to the second drive transistor DTR2. The second regulated drive voltage ADI2 may be a pull-up signal.

[0075] The first accelerating transistor AT1 is connected between the first output terminal N3 of the upper current mirror circuit and the first driving transistor DTR1 constituting the output stage. The second accelerating transistor AT2 is connected between the second output terminal N4 of the lower current mirror circuit and the second driving transistor DTR2 constituting the output stage.

[0076] According to one or more embodiments, the first acceleration transistor AT1 may be a PMOS transistor, and the second acceleration transistor AT2 may be an NMOS transistor. The gate of the first acceleration transistor AT1 may be connected to the current detection circuit 123. The source of the first acceleration transistor AT1 may be connected between the first output terminal N3 of the upper current mirror circuit and the gate terminal of the first drive transistor DTR1. In addition, the drain of the first acceleration transistor AT1 may be connected to the second power line VL2, thereby providing the ground voltage GND. The gate of the second acceleration transistor AT2 may be connected to the current detection circuit 123. The source of the second acceleration transistor AT2 may be connected between the second output terminal N4 of the lower current mirror circuit and the gate terminal of the second drive transistor DTR2. In addition, the drain of the second acceleration transistor AT2 may be connected to the first power line VL1, thereby providing the power supply voltage VDD.

[0077] The first accelerating transistor AT1 can be operated by turning on / off in response to the first and second control signals CS11 and CS12 transmitted from the current detecting circuit 123. The second accelerating transistor AT2 can be turned on / off in response to the third and fourth control signals CS21 and CS22 transmitted from the current detecting circuit 123.

[0078] The current detection circuit 123 may output first to fourth control signals CS11, CS12, CS21, and CS22 for turning on / off the control circuit 121. According to one or more embodiments, the current detection circuit 123 may include a first current sensing transistor MT11, a second current sensing transistor MT12, a third current sensing transistor MT21, and a fourth current sensing transistor MT22.

[0079] The first current sensing transistor MT11 may be connected to the first power line VL1, and the second current sensing transistor MT12 may be connected to the second power line VL2. The first bias transistor BT1 is connected between the first current sensing transistor MT11 and the second current sensing transistor MT12.

[0080] According to one or more embodiments, the first current sensing transistor MT11 may be a PMOS transistor, and the second current sensing transistor MT12 may be an NMOS transistor. The gate of the first current sensing transistor MT11 may be connected to the gate electrodes of the PMOS transistor PT31 and the PMOS transistor PT32 constituting the upper current mirror circuit of the load stage 113. The gate of the second current sensing transistor MT12 may be connected to the gate electrodes of the NMOS transistor NT31 and the NMOS transistor NT32 constituting the lower current mirror circuit of the load stage 113.

[0081] The control circuit 121 has various functions. The first acceleration transistor AT1 can be turned on based on the first drive signal DS1 of the first drive transistor DTR1, the first control signal CS11 of the first current sensing transistor MT11, and the second control signal CS12 of the second current sensing transistor MT12. Specifically, when the voltage difference between the node N3 and the node G1 is greater than or equal to a reference value, the first acceleration transistor AT1 can be turned on. At this time, the first control signal CS11 and the second control signal CS12 can accelerate the reduction of the voltage value of the node G1, which is the gate voltage of the first acceleration transistor AT1. The reference value can be adjusted based on the third bias voltage VB32 of the first bias transistor BT1. When the first acceleration transistor AT1 is turned on, a first regulated drive voltage ADI1 can be provided to the first drive transistor DTR1. The first regulated drive voltage ADI1 can be a pull-down signal.

[0082] Specifically, when the voltage difference between node N3 and node G1 is less than a reference value, the first acceleration transistor AT1 may be turned off. At this point, the first control signal CS11 and the second control signal CS12 may accelerate the voltage at node G1, i.e., the gate voltage of the first acceleration transistor AT1. The reference value may be adjusted based on the third bias voltage VB32 of the first bias transistor BT1.

[0083] The second acceleration transistor AT2 can be turned on based on the second drive signal DS2 of the second drive transistor DTR2, the third control signal CS21 of the third current sensing transistor MT21, and the fourth control signal CS22 of the fourth current sensing transistor MT22. Specifically, when the voltage difference between the node N4 and the node G2 is greater than or equal to the reference value, the second acceleration transistor AT2 can be turned on. At this time, the third control signal CS21 and the fourth control signal CS22 can accelerate the voltage value of the node G2, which is the gate voltage of the second acceleration transistor AT2. The reference value can be adjusted based on the fourth bias voltage VB42 of the second bias transistor BT2. When the second acceleration transistor AT2 is turned on, a second regulated drive voltage ADI2 can be provided to the second drive transistor DTR2. The second regulated drive voltage ADI2 can be a pull-up signal.

[0084] Similarly, the second acceleration transistor AT2 can be turned off based on the second drive signal DS2 of the second drive transistor DTR2, the third control signal CS21 of the third current sensing transistor MT21, and the fourth control signal CS22 of the fourth current sensing transistor MT22. Specifically, when the voltage difference between the node N4 and the node G2 is less than a reference value, the second acceleration transistor AT2 can be turned off. At this time, the third control signal CS21 and the fourth control signal CS22 can accelerate the reduction of the voltage value of the node G2, which is the gate voltage of the second acceleration transistor AT2. The reference value can be adjusted based on the fourth bias voltage VB42 of the second bias transistor BT2.

[0085] Figure 4 and Figure 5 Waveforms of the input signal voltage, the gate voltage of the accelerating transistor, and the output signal voltage are shown.

[0086] Figure 4 is a diagram for describing the case where the input signal rises, and Figure 5 is a diagram used to describe the case where the input signal decreases. Figure 4 and Figure 5 In each of , a waveform diagram of the input signal voltage is shown in (a), a waveform diagram of the gate voltage of the accelerating transistor is shown in (b), and a waveform diagram of the output signal voltage is shown in (c).

[0087] First, refer to Figures 1 to 4 A case where the slew rate is accelerated when the input signal rises (hereinafter, referred to as a rising case) is described.

[0088] exist Figure 4 In (a), the voltage value of the input signal rises from low to high.

[0089] When the operational amplifier 110 starts to rise according to the change of the input signal, the slew rate acceleration circuit 120 can receive the value of the operating current flowing inside the operational amplifier 110 and can accelerate the transition time of the output voltage VOUT based on the value of the operating current.

[0090] The value of the operating current flowing inside the operational amplifier 110 can be detected by the current detection circuit 123 constituting the slew rate acceleration circuit 120 .

[0091] The gate of the first current sensing transistor MT11 is connected to the gate electrodes of the PMOS transistor PT31 and the PMOS transistor PT32 constituting the upper current mirror circuit of the load stage 113. The gate of the second current sensing transistor MT12 is connected to the gate electrodes of the NMOS transistor NT31 and the NMOS transistor NT32 constituting the lower current mirror circuit of the load stage 113. With this connection configuration, the current detection circuit 123 can detect the value of the operating current flowing inside the operational amplifier 110 by mirroring the current flowing through the load stage 113 of the operational amplifier 110.

[0092] In the portion where the input signal of the input stage 111 rises (hereinafter, a rising case), the first current sensing transistor MT11 and the second current sensing transistor MT12 of the current detection circuit 123 output the first control signal CS11 and the second control signal CS12 to the node G1 to which the gate electrode of the first acceleration transistor AT1 is connected, and the gate voltage of the first acceleration transistor AT1 decreases at an accelerated rate.

[0093] When the gate voltage of the first acceleration transistor AT1 decreases at an accelerated rate, the voltage difference between the node N3 and the node G1 becomes greater than or equal to the reference value. Therefore, the first acceleration transistor AT1 turns on. The reference value can be adjusted based on the third bias voltage VB32 of the first bias transistor BT1. When the first acceleration transistor AT1 turns on, the first regulated drive voltage ADI1 can be provided to the first drive transistor DTR1. The first regulated drive voltage ADI1 can be a pull-down signal. Here, the first drive transistor DTR1 is pulled up, and as a result, the output voltage of the operational amplifier 110 increases. In other words, the slew rate of the operational amplifier 110 is accelerated.

[0094] In the portion where the input signal of the rising case becomes a stable state, the first current sensing transistor MT11 and the second current sensing transistor MT12 of the current detection circuit 123 output the first control signal CS11 and the second control signal CS12 to the node G1 to which the gate electrode of the first acceleration transistor AT1 is connected, and Figure 4As shown in (b), the gate voltage of the first acceleration transistor AT1 increases at an accelerated rate. Consequently, the voltage difference between the node N3 and the node G1 becomes smaller than the reference value, turning off the first acceleration transistor AT1. The reference value can be adjusted based on the third bias voltage VB32 of the first bias transistor BT1. The output stage 115 of the operational amplifier 110 then stabilizes, and the output voltage of the operational amplifier 110 maintains a DC output.

[0095] Next, we will refer to Figures 1 to 3 and Figure 5 A case where the slew rate is accelerated when the input signal falls (hereinafter, referred to as a falling case) is described.

[0096] exist Figure 5 In (a), the voltage value of the input signal decreases from high to low.

[0097] When the operational amplifier 110 starts to change downward according to the change of the input signal, the conversion rate acceleration circuit 120 can receive the value of the operating current flowing inside the operational amplifier 110, and can accelerate the transition time between the input voltage VIN and the output voltage VOUT based on the value of the operating current.

[0098] The value of the operating current flowing inside the operational amplifier 110 can be detected by the current detection circuit 123 constituting the slew rate acceleration circuit 120 .

[0099] The gate of the third current sensing transistor MT21 is connected to the gate electrodes of the PMOS transistor PT31 and the PMOS transistor PT32 constituting the upper current mirror circuit of the load stage 113. The gate of the fourth current sensing transistor MT22 is connected to the gate electrodes of the NMOS transistor NT31 and the NMOS transistor NT32 constituting the lower current mirror circuit of the load stage 113. With this connection configuration, the current detection circuit 123 can detect the value of the operating current flowing inside the operational amplifier 110 by mirroring the current flowing through the load stage 113 of the operational amplifier 110.

[0100] In the portion where the input signal falls in the falling condition, the third current sensing transistor MT21 and the fourth current sensing transistor MT22 of the current detection circuit 123 output the third control signal CS21 and the fourth control signal CS22 to the node G2 to which the gate electrode of the second acceleration transistor AT2 is connected, and the gate voltage of the second acceleration transistor AT2 increases at an accelerated rate.

[0101] When the gate voltage of the second acceleration transistor AT2 increases at an accelerated rate, the voltage difference between the node N4 and the node G2 becomes greater than or equal to the reference value. Therefore, the second acceleration transistor AT2 turns on. The reference value can be adjusted based on the fourth bias voltage VB42 of the second bias transistor BT2. When the second acceleration transistor AT2 turns on, the second regulated drive voltage ADI2 can be provided to the second drive transistor DTR2. Here, the second regulated drive voltage ADI2 can be a pull-up signal. Here, the second drive transistor DTR2 is pulled down, and as a result, the output voltage of the operational amplifier 110 decreases. In other words, the slew rate of the operational amplifier 110 is accelerated.

[0102] In the portion where the input signal of the falling case becomes a stable state, the third current sensing transistor MT21 and the fourth current sensing transistor MT22 of the current detection circuit 123 output the third control signal CS21 and the fourth control signal CS22 to the node G2 to which the gate electrode of the second acceleration transistor AT2 is connected, and Figure 5 As shown in (b), the gate voltage of the second accelerating transistor AT2 decreases at an accelerated rate. Consequently, the voltage difference between the node N4 and the node G2 becomes less than the reference value, turning off the second accelerating transistor AT2. The reference value can be adjusted based on the fourth bias voltage VB42 of the second bias transistor BT2. The output stage 115 of the operational amplifier 110 then stabilizes, and the output voltage of the operational amplifier 110 maintains a DC output.

[0103] According to slew rate acceleration circuit 120, according to one or more embodiments of the subject disclosure, current detection circuit 123 detects the value of the operating current flowing inside operational amplifier 110, and performs slew rate control based on the operating current flowing inside operational amplifier 110. Therefore, there is an effect of further improving the slew rate compared to conventional voltage sensing methods.

[0104] Figure 6 A display device including a buffer circuit according to one or more embodiments of the present disclosure is conceptually illustrated.

[0105] Reference Figure 6 , the display device 1000 includes a display panel 200 , a source driver 300 , a gate driver 400 and a timing controller 500 .

[0106] The source driver 300 may further include a timing controller 500 .

[0107] According to one or more embodiments, the display device 1000 can display images or videos. For example, the display device 1000 may include a smartphone, a tablet personal computer (PC), a mobile phone, a video phone, an e-book reader, a computer, a camera, a wearable device, etc. However, the display device 1000 is not limited thereto.

[0108] The display panel 200 may include a plurality of sub-pixels PX arranged in rows and columns. For example, the display panel 200 may be implemented using one of the following: a light emitting diode (LED) display, an organic LED (OLED) display, an active matrix OLED (AMOLED) display, an electrochromic display (ECD), a digital mirror device (DMD), an actuated mirror device (AMD), a grating light valve (GLV), a plasma display panel (PDP), an electroluminescent display (ELD), or a vacuum fluorescent display (VFD). However, the display panel 200 is not limited thereto.

[0109] The display panel 200 includes a plurality of gate lines GL1 to GLn (n is a natural number) arranged in rows, a plurality of data lines DL1 to DLm (m is a natural number) arranged in columns, and subpixels PX formed at the intersections of the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm. The display panel 200 includes a plurality of horizontal lines, and one horizontal line is composed of subpixels PX connected to one gate line. During one horizontal period (1H), the subpixels arranged on one horizontal line are driven, and during the next 1H, the subpixels arranged on another horizontal line can be driven.

[0110] The sub-pixel PX may include a light emitting diode (LED) and a diode driving circuit that independently drives the LED. The diode driving circuit may be connected to one gate line and one data line, and the LED may be connected between the diode driving circuit and a power supply voltage (eg, ground voltage).

[0111] The diode driving circuit may include switching elements, such as thin-film transistors (TFTs), connected to gate lines GL1 to GLn. When a gate-on signal is applied from the gate lines GL1 to GLn and the switching elements are turned on, the diode driving circuit may provide image signals (or pixel signals) received from data lines DL1 to DLm connected to the diode driving circuit to the light-emitting diodes. The light-emitting diodes may then output light signals corresponding to the image signals.

[0112] Each of the sub-pixels PX may be one of a red light-emitting device R that outputs red light, a green light-emitting device G that outputs green light, and a blue light-emitting device B that outputs blue light. In the display panel 200, the red light-emitting device, the green light-emitting device, and the blue light-emitting device may be arranged according to various methods. According to one or more embodiments, the sub-pixels PX of the display panel 200 may be repeatedly arranged in the order of R, G, B, and G, or B, G, R, and G, etc. For example, the pixels PX of the display panel 200 may be arranged according to an RGB stripe structure or an RGB pixel arrangement (Pentile) structure. However, the pixels are not limited thereto.

[0113] The gate driver 400 may sequentially provide gate-on signals to the plurality of gate lines GL1 to GLn in response to a gate control signal GCS. For example, the gate control signal GCS may include a gate start pulse indicating the start of outputting the gate-on signal and a gate shift clock controlling the output timing of the gate-on signal.

[0114] When the gate start pulse is applied, the gate driver 400 may sequentially generate a gate-on signal (e.g., a logic high gate voltage) in response to the gate shift clock, and may sequentially provide the gate-on signal to the plurality of gate lines GL1 to GLn. Here, during a period in which the gate-on signal is not provided to the plurality of gate lines GL1 to GLn, a gate-off signal (e.g., a logic low gate voltage) is provided to the plurality of gate lines GL1 to GLn.

[0115] The source driver 300 may convert the digital image data DATA into analog image signals in response to the data control signal DCS and may provide the converted image signals to the plurality of data lines DL1 to DLm. The source driver 300 may provide image signals corresponding to one horizontal line to the plurality of data lines DL1 to DLm during 1H.

[0116] The source driver 300 may include a buffer circuit 100 that transmits signals to the data lines DL1 to DLm. The buffer circuit 100 may be a reference circuit. Figures 1 to 3 The buffer circuit 100 is described.

[0117] The buffer circuit 100 may transmit a signal to the display panel 200. The source driver 300 may convert the image data DATA into an image signal in response to the data control signal DCS. The source driver 300 may convert the image signal having a grayscale voltage corresponding to the image data DATA and may output the converted image signal to the plurality of data lines DL1 to DLm through the buffer circuit 100.

[0118] The timing controller 500 may receive video image data RGB from the outside and generate image data DATA by performing image processing on the video image data RGB or by converting the video image data RGB to fit the structure of the display panel 200. The timing controller 500 may transmit the image data DATA to the source driver 300.

[0119] The timing controller 500 may receive a plurality of control signals from an external host device. The control signals may include a synchronization signal SYNC and a clock signal DCLK. In addition, the synchronization signal SYNC may include a horizontal synchronization signal Hsync and a vertical synchronization signal Vsync.

[0120] The timing controller 500 may generate a gate control signal GCS and a data control signal DCS for controlling the gate driver 400 and the source driver 300 based on the received control signal. The timing controller 500 may control various operation timings of the gate driver 400 and the source driver 300 based on the gate control signal GCS and the data control signal DCS.

[0121] According to one or more embodiments, the timing controller 500 may control the gate driver 400 based on the gate control signal GCS so that the gate driver 400 drives the plurality of gate lines GL1 to GLn. The timing controller 500 may control the source driver 300 based on the data control signal DCS so that the source driver 300 provides image signals to the plurality of data lines DL1 to DLm.

[0122] Each component of the display device 1000 may be composed of a circuit capable of performing a corresponding function.

[0123] Methods according to one or more embodiments of the subject disclosure may be implemented using instructions stored in a computer-readable storage medium and executable by a processor.

[0124] The storage medium may include, directly and / or indirectly, a relational database, a non-relational database, an in-memory database, and a database that can store data and includes a distributed database, such as other suitable databases that allow access to the data through a storage controller, whether in a raw state, a formatted state, an organized state, or any other accessible state. Furthermore, the storage medium may include primary storage, secondary storage, tertiary storage, offline storage, volatile storage, non-volatile storage, semiconductor storage, magnetic storage, optical storage, and flash storage, hard drive storage, floppy disk drives, magnetic tape, or any other suitable data storage medium.

[0125] In this specification, an instruction may be one of the following: assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, and source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc. and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages.

[0126] As described above, the buffer circuit according to an embodiment of the present disclosure has the effect of reducing quiescent current. Furthermore, the buffer circuit according to this embodiment receives the value of the operating current flowing within the operational amplifier and adjusts the transition time between the input voltage VIN and the output voltage VOUT based on the value of the operating current. Therefore, a slew rate comparable to that of conventional structures can be achieved using a lower quiescent current than that of conventional structures. Furthermore, the buffer circuit according to this embodiment adjusts the transition time between the input voltage VIN and the output voltage VOUT based on the value of the operating current flowing within the operational amplifier, thereby achieving a noise reduction effect and reducing simulation errors compared to conventional voltage sensing methods.

[0127] Although the present disclosure includes specific examples, it will be apparent after understanding the disclosure of this application that various changes in form and detail can be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered merely descriptive and not for purposes of limitation. The description of features or aspects in each example will be considered to be applicable to similar features or aspects in other examples. Suitable results can be achieved if the described techniques are performed in a different order, and / or if the components in the described systems, architectures, devices, or circuits are combined in a different manner, and / or if the components in the described systems, architectures, devices, or circuits are replaced or supplemented by other components or their equivalents. Therefore, the scope of the present disclosure is not limited by the specific embodiments, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be interpreted as included in the present disclosure.

Claims

1. A slew rate acceleration circuit in a buffer circuit, configured to: detecting an operating current flowing through the load stage of the buffer circuit based on a gate voltage of a transistor in at least one current mirror circuit of the load stage; comparing the value of the operating current with an adjustable reference value; as well as Based on the comparison result, providing an adjusted driving voltage to the output stage of the buffer circuit to increase the slew rate of the buffer circuit, The slew rate acceleration circuit includes a bias transistor, and the adjustable reference value is adjusted according to a bias voltage of the bias transistor. 2 . The slew rate acceleration circuit according to claim 1 , comprising a current detection circuit configured to form a current mirror with a current mirror circuit of the load stage.

3. The slew rate acceleration circuit according to claim 2, in, The current detection circuit includes a current sensing transistor configured to perform a current mirror operation on an operating current flowing through the load stage. And the gate electrode of the current sensing transistor is connected to the gate electrode of the transistor constituting the current mirror circuit of the load stage.

4. The slew rate acceleration circuit according to claim 3, in, The output stage comprises at least one driver transistor, And the slew rate acceleration circuit further includes a control circuit configured to provide the regulated driving voltage to the gate electrode of the driving transistor.

5. The slew rate acceleration circuit according to claim 4, in, The control circuit includes at least one accelerating transistor, And the source electrode of the acceleration transistor is connected to the gate electrode of the driving transistor.

6. The slew rate acceleration circuit according to claim 5, in, The current mirror operation is configured to transmit a control signal to the gate electrode of the acceleration transistor, And the acceleration transistor is configured to be turned on / off based on the control signal.

7. The slew rate acceleration circuit according to claim 6, in, The at least one driving transistor includes a first driving transistor and a second driving transistor, The at least one accelerating transistor includes a first accelerating transistor and a second accelerating transistor, The source electrode of the first driving transistor and the drain electrode of the second accelerating transistor are connected to a first power supply voltage, And the source electrode of the second driving transistor and the drain electrode of the first accelerating transistor are connected to a second power supply voltage.

8. The slew rate acceleration circuit according to claim 7, in, The source electrode of the first accelerating transistor and the gate electrode of the first driving transistor are commonly connected to the first output terminal of the current mirror circuit. And the source electrode of the second accelerating transistor and the gate electrode of the second driving transistor are commonly connected to the second output terminal of the current mirror circuit.

9. The slew rate acceleration circuit according to claim 7, in, The first driving transistor and the first accelerating transistor are PMOS transistors, And the second driving transistor and the second accelerating transistor are NMOS transistors.

10. A buffer circuit comprising: an operational amplifier configured to amplify an input voltage and output an output voltage through an output node; a current detection circuit configured to detect an operating current flowing through the load stage of the operational amplifier based on a gate voltage of a transistor in at least one current mirror circuit of the load stage; as well as A control circuit configured to: comparing the value of the operating current with an adjustable reference value; as well as providing a regulated drive voltage to an output stage of the operational amplifier based on a control signal; as well as The slew rate acceleration circuit includes a bias transistor, and the adjustable reference value is adjusted according to the bias voltage of the bias transistor.

11. The buffer circuit according to claim 10, in, The output stage comprises at least one driver transistor, And the control circuit is configured to provide the regulated driving voltage to the gate electrode of the driving transistor.

12. The buffer circuit according to claim 11, in, The current detection circuit includes a current sensing transistor configured to perform a current mirror operation on an operating current flowing through the load stage. And the gate electrode of the current sensing transistor is connected to the gate electrode of the transistor constituting the current mirror circuit of the load stage.

13. The buffer circuit according to claim 12, in, The control circuit includes at least one accelerating transistor, And the source electrode of the acceleration transistor is connected to the gate electrode of the driving transistor.

14. The buffer circuit according to claim 13, in, The current mirror operation is configured to transmit the control signal to the gate electrode of the acceleration transistor, And the acceleration transistor is configured to be turned on / off based on the control signal.

15. The buffer circuit according to claim 14, in, The at least one driving transistor includes a first driving transistor and a second driving transistor, The at least one accelerating transistor includes a first accelerating transistor and a second accelerating transistor, The source electrode of the first driving transistor and the drain electrode of the second accelerating transistor are connected to a first power supply voltage, And the source electrode of the second driving transistor and the drain electrode of the first accelerating transistor are connected to a second power supply voltage.

16. The buffer circuit according to claim 15, in, The source electrode of the first accelerating transistor and the gate electrode of the first driving transistor are commonly connected to the first output terminal of the current mirror circuit. And the source electrode of the second accelerating transistor and the gate electrode of the second driving transistor are commonly connected to the second output terminal of the current mirror circuit.

17. The buffer circuit according to claim 15, in, The first driving transistor and the first accelerating transistor are PMOS transistors, And the second driving transistor and the second accelerating transistor are NMOS transistors.

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