A very small angle tilt etching process method for SiC material

Abstract

The present invention provides a very small angle inclined etching process method for SiC materials. The method first utilizes the reflow characteristics of photoresist during high temperature baking to further fill and smooth the slope of the previous photoresist pattern, thereby obtaining a photoresist mask pattern with a gentler edge angle than the conventional photoresist reflow method, and then uses the photoresist mask pattern as a mask and selects an appropriate etching selection ratio to achieve very small angle inclined etching of SiC materials with an etching angle of less than 1° and an etching depth of not less than 1μm. The process method can be applied to the production of etching terminals for SiC power devices, simplifying the current SiC multi-stage etching terminal solution, and realizing a single-stage etching terminal solution that only requires one etching process. On the one hand, the present invention greatly reduces the process complexity and process cost of the etching terminal production process, and on the other hand, it also solves the problem of narrow etching process window often faced by multi-stage etching terminals.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor process technology, in particular to the field of semiconductor power electronic device process technology, and in particular relates to a very small angle inclined etching process method for SiC materials. Background Art

[0002] As a representative of the third-generation wide bandgap semiconductors, silicon carbide materials have attracted extensive attention from researchers at home and abroad due to their unique advantages such as wide bandgap, high thermal conductivity and high critical breakdown field strength. Various power devices made of SiC materials have also become a hot topic in scientific research and industry.

[0003] For SiC power devices, the design and process manufacturing of the device terminal structure are the key to obtaining a high blocking voltage efficiency. At present, the main methods for realizing the terminal structure of SiC power devices are etching and ion implantation. Compared with the ion implantation method, the etching method has the advantages of less damage to the material crystal quality and no need for high-temperature annealing activation, thereby minimizing the degradation of the material minority carrier lifetime in the device manufacturing process.

[0004] During the process of etching the terminal structure of SiC power devices, the etching angle of the SiC material affects the electric field concentration effect at the edge of the device. To effectively suppress the field concentration effect at the edge of the device, the smaller the etching angle of the SiC material, the better. Especially for SiC high-voltage power devices, since the thickness of the drift layer of such devices is relatively thick (generally between 10 and 100 μm), in order to suppress the field concentration effect at the edge to achieve high withstand voltage efficiency, the etching angle of the SiC material of such devices is usually required to be reduced to below 1°, and the etching depth of the SiC material must be no less than 1 μm.

[0005] At present, the main method for realizing small-angle etching of SiC materials is the photoresist reflow process. This process can reduce the tilt angle of the photoresist edge by high-temperature baking and reflow of the mask photoresist, and then transfer the small-angle morphology to the SiC material through the pattern transfer in the etching process, thereby realizing small-angle tilt etching of SiC materials between 3 and 10 degrees. Figure 1 Some typical experimental results of small-angle etching of silicon carbide using this method in existing literature are shown. It can be seen from the figure that this method cannot achieve extremely small-angle tilted etching of SiC with an angle as low as 1°. Even if the impact on the etchable depth of the material is not considered and the etching selectivity is lowered, the minimum angle that can be obtained by the above-mentioned photoresist reflow method is about 2°. For SiC high-voltage power devices, the SiC terminal structure with this etching tilt angle cannot achieve the effect of suppressing the edge field strength concentration effect.

[0006] In addition, in order to achieve an ultra-high voltage withstand level SiC GTO device, CREE, an American company, proposed an approximately negative-angle SiC etching terminal structure with more than 10 etching levels. Although this multi-step etching structure can approximately simulate an extremely small angle (<1°) SiC slope effect and thus suppress the field strength concentration at the edge of the device, the multi-step etching terminal process scheme greatly increases the process complexity of device manufacturing and reduces the process advantage of the etching terminal compared to the ion implantation terminal. Summary of the invention

[0007] In view of this, the present invention provides a very small angle inclined etching process method for SiC material, which can achieve very small angle inclined etching of SiC material with an etching angle less than 1° and an etching depth of not less than 1 μm.

[0008] To achieve this purpose, the present invention adopts the following technical scheme: a very small angle tilted etching process method for SiC material, the method first uses a later layer of photoresist to fill and further smooth the edge slope of a previous layer of photoresist pattern based on the reflow characteristics of the photoresist during high temperature baking, to obtain a photoresist mask pattern with a very small angle, and then uses the photoresist mask pattern to achieve very small angle tilted etching of the SiC material;

[0009] The method can obtain a SiC etching morphology with a very small angle whose cross section is a trapezoidal step with a small top and a large bottom. The very small angle refers to an etching angle of ≤1°, and the maximum etching depth of the SiC etching morphology is ≥1μm.

[0010] Preferably, the method comprises:

[0011] S1: Spin-coating one or more layers of photoresist on the SiC sample. After each layer of photoresist is spin-coated, the photoresist layer is photolithographically processed and developed to obtain a photoresist pattern. The photoresist pattern is then subjected to high-temperature baking and reflow to obtain a photoresist-cured pattern with a small edge angle.

[0012] S2: Spin-coating a last layer of photoresist on the photoresist-cured pattern finally obtained in step S1, performing photolithography and development on the last layer of photoresist to obtain a photoresist pattern, and performing high-temperature baking and reflow on the photoresist pattern to obtain a photoresist-cured pattern P′ with a small edge angle;

[0013] S3: thinning the photoresist cured pattern P′ to obtain a photoresist cured pattern P with a very small angle edge morphology;

[0014] S4: Using the photoresist cured pattern P as a mask, the SiC material is dry-etched to obtain a SiC etching process morphology with a very small edge tilt angle.

[0015] Preferably, the step S1 comprises:

[0016] S11: Spin-coating a photoresist on the SiC sample, performing photolithography and development on the photoresist, and obtaining a photoresist pattern with a diameter of D1, where D1 is the size of the device active area;

[0017] S12: performing high-temperature baking and reflow on the photoresist pattern obtained in step S11, and cooling after the baking to obtain a photoresist cured pattern P1 with a small edge angle;

[0018] S13: Determine whether to continue to repeat the photoresist spin coating, photolithography and baking reflow process in steps S11 and S12 according to the requirements of the device process for the etching angle and etching depth. If necessary, continue to spin-coat the photoresist on the photoresist pattern with a diameter of D1, and after high-temperature baking and reflow, form a photoresist cured pattern P2 with a diameter of D1+d2, and then use this method to form a photoresist cured pattern P2 with a diameter of D1+…+d2. n-1 Photoresist curing pattern P n-1 , n≥3, until the device process requirements for etching angle and etching depth are met, where d2~d n-1 The values ​​are all between 20 and 200 μm, that is, the diameter of the next-level photoresist pattern is 20 to 200 μm larger than the diameter of the previous-level photoresist pattern.

[0019] Preferably, in the step S11, the thickness of the photoresist is 0.5-10 μm; and the temperature of the high temperature baking reflow in the step S12 is 120-300° C.

[0020] Preferably, in step S2, the thickness of the last layer of photoresist is 1-20 μm.

[0021] Preferably, in step S3, the photoresist cured pattern P′ is thinned by ICP etching or plasma stripping bombardment.

[0022] Preferably, the minimum thickness of the thinning in step S3 is 0 and the maximum thickness is the thickness of the last layer of photoresist.

[0023] Preferably, the dry etching in step S4 adopts an ICP or RIE dry etching process, the etching gas used for etching is SF6 / O2 or CF4 / O2, and the etching selection ratio is 1:3.

[0024] Preferably, the process method is used for manufacturing the terminal structure of SiC power devices, and the SiC power devices include: rectifier type devices PiN, SBD, JBS and MPS, and switch type devices MOSFET, JFET, BJT, GTO and IGBT.

[0025] Preferably, the photoresist cured pattern P with extremely small angle edge morphology obtained in step S3 can be used to perform extremely small angle inclined etching on other materials, and the other materials include SiO2, SiN, GaN, GaAs and Si.

[0026] The beneficial effects of the present invention are as follows: the SiC material extremely small angle tilted etching process provided by the present invention utilizes the reflow characteristics of the photoresist during high temperature baking, and implements multiple photoresist patterning and reflow processes, so that after each photoresist reflow process, the next layer of photoresist reflow will further fill and smooth the slope of the photoresist pattern in the previous process step, thereby obtaining a photoresist pattern edge morphology with a gentler angle than the conventional photoresist reflow method; by designing the thickness and lateral width of the other levels of photoresist patterns before the last layer of photoresist coating, and combining the photoresist thinning process in the final stage of mask making, a photoresist mask pattern with an extremely small edge tilt angle can be finally obtained. Using the photoresist mask pattern, under a suitable photoresist etching selectivity (e.g., 1:3), an extremely small angle tilted etching morphology of SiC material with an etching angle as low as 1° or less and sufficient etching depth can be achieved.

[0027] The method proposed in the present invention can realize SiC extremely small angle inclined etching process morphology with an etching angle of less than 1° and a maximum etching depth of not less than 1μm. The process method is applied to the production of etching terminals of SiC power devices, which can maximize the control of the process complexity of the SiC power device etching terminal production process and reduce the process cost. In addition, it will also completely solve the problem of narrow etching process window often faced by multi-level etching terminals. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Some typical experimental results of making inclined photoresist masks and performing SiC small-angle etching using the traditional single-step photoresist reflow process in the prior art;

[0029] Figure 2 It is a schematic diagram of the principle of forming a very small angle photoresist mask by a two-step photoresist reflow process method in Example 1 of the present invention;

[0030] Figure 3 FIG. 1 is a schematic diagram of forming a photoresist mask with a very small angle by a three-step photoresist reflow process in Embodiment 2 of the present invention;

[0031] Figure 4 The diagram is a principle diagram of the process step (2) in Example 3 of the present invention using the process method proposed by the present invention to perform a very small angle inclined etching process on SiC materials;

[0032] Figure 5The simulation results of the withstand voltage efficiency of the SiC high voltage PiN device in Example 3 of the present invention when having different terminal etching angles;

[0033] In the figure: 101. substrate 102. first layer of photoresist 103. second layer of photoresist 104. third layer of photoresist 105. final mask pattern. DETAILED DESCRIPTION

[0034] A very small angle inclined etching process method for SiC material, the method firstly utilizes the reflow characteristics of photoresist during high temperature baking to achieve filling and further smoothing of the edge slope of the previous layer of photoresist pattern, and obtains a very small angle photoresist mask pattern, and then utilizes the photoresist mask pattern to achieve very small angle inclined etching of the SiC material; the method can obtain a very small angle SiC etching morphology with a cross section of a trapezoidal step that is small at the top and large at the bottom, the very small angle refers to an etching angle of ≤1°, and the maximum etching depth of the SiC etching morphology is ≥1μm.

[0035] The extremely small angle inclined etching process method for SiC materials provided by the present invention can be applied to the production of etching terminals for SiC power devices, and can simplify the multi-stage etching terminal scheme commonly used in current literature into a single-stage etching terminal scheme and solve the problem of narrow etching process window often faced by multi-stage etching terminals.

[0036] For a better understanding of the present invention, the content of the present invention will be further explained below in conjunction with embodiments, but the content of the present invention is not limited to the following embodiments. Those of ordinary skill in the art will appreciate that the embodiments described herein are to help readers understand the principles of the present invention, and should be understood that the protection scope of the present invention is not limited to such special statements and embodiments. Those of ordinary skill in the art can make various other various specific variations and combinations that do not depart from the essence of the present invention based on these technical revelations disclosed by the present invention, and these variations and combinations are still within the protection scope of the present invention.

[0037] Example 1

[0038] In this embodiment, the multi-stage photoresist reflow process method proposed in the present invention is used to form a photoresist mask pattern with an extremely small angle on a substrate through two photoresist patterning and reflow processes. The edge angle of the photoresist mask pattern breaks through the minimum edge tilt angle limit of the traditional single-stage photoresist reflow technology.

[0039] The process of manufacturing the extremely small angle photoresist mask pattern is as follows:

[0040] (1) Spin-coating a first layer of photoresist 102 on the substrate 101, which is AZ4620 photoresist with a thickness of 6 μm, and using the first photoresist plate as a mask, photolithography and development are performed on the photoresist to obtain a photoresist pattern P1′ with a diameter of 3000 μm;

[0041] (2) performing high-temperature baking reflow on the photoresist pattern obtained in step (1), wherein the baking temperature is 180° C. and the baking time is 10 minutes. After the baking is completed, the photoresist pattern is naturally cooled to obtain a first-level photoresist cured pattern P1 with a small edge angle;

[0042] (3) Spin-coating a second layer of photoresist 103 on the substrate, which is also AZ4620 photoresist with a thickness of 6 μm, and using the second photoresist plate as a mask, photolithography and development are performed on the photoresist to obtain a photoresist pattern P2′ with a diameter of 3100 μm;

[0043] (4) performing high-temperature baking reflow on the photoresist pattern obtained in step (3), the baking temperature is 250° C., the baking time is 15 minutes, and the baking is completed. The temperature is naturally cooled to obtain a second-level photoresist cured pattern P2 with a small edge angle;

[0044] (5) The photoresist cured pattern P2 obtained in the above step (4) is subjected to a thinning process by a dry degumming machine, and the thinning thickness is 4 μm, and finally a photoresist pattern mask P with a very small edge angle morphology is obtained;

[0045] The photoresist pattern mask 105 obtained by the above process has a smaller edge tilt angle morphology than the conventional single-stage photoresist reflow curing pattern, and can be used to etch the silicon carbide material at a smaller angle. Figure 2 The schematic diagram of the above process.

[0046] Example 2

[0047] In this embodiment, the multi-stage photoresist reflow process method proposed in the present invention is used to form a photoresist mask pattern with an extremely small angle on a substrate through a total of three photoresist patterning and reflow processes. The edge angle of the photoresist mask pattern breaks through the minimum edge tilt angle limit of the traditional single-stage photoresist reflow technology, and the obtainable edge tilt angle is smaller than the two-stage reflow process in Example 1.

[0048] The process of manufacturing the extremely small angle photoresist mask pattern in this embodiment is similar to that in Embodiment 1, wherein the reflow process of the first photoresist 102 and the second photoresist 103 follows the process conditions of the reflow of the first photoresist in Embodiment 1, and the reflow process of the third photoresist 104 follows the process conditions of the reflow of the second photoresist in Embodiment 1, so the detailed process is not repeated here. Figure 3It is a schematic diagram of the principle of the process of manufacturing the extremely small angle photoresist mask pattern in this embodiment.

[0049] Example 3

[0050] In this embodiment, the SiC material extremely small angle inclined etching process proposed in the present invention is used to realize the terminal structure of the SiC high voltage PiN device. The vertical epitaxial structure of the SiC high voltage PiN device is P+ / P / N- / N+ / substrate from top to bottom, where P+ is the anode cap layer and its doping concentration is 2×10 19 cm -3 , with a thickness of 0.5 μm; P is a buffer depletion layer with a doping concentration of 2×10 17 cm -3 , with a thickness of 1.5 μm; N- is the drift layer, and its doping concentration is 2×10 14 cm -3 , with a thickness of 60 μm; N+ is a buffer layer with a doping concentration of 1×10 18 cm -3 , thickness is 2μm; substrate is N+ 4H-SiC intrinsic substrate, doping concentration is 5×10 18 cm -3 , thickness is 350μm.

[0051] The process of realizing the small angle tilted etching termination of the SiC high voltage PiN device is as follows:

[0052] (1) Clean the SiC sample using the RCA standard cleaning method;

[0053] (2) The SiC material extremely small angle tilt etching process proposed in this patent is used to perform terminal small angle etching on the sample, where the etching tilt angle is 1° and the etching depth is 2.5 μm. The etching process principle is as shown in the attached figure. Figure 4 As shown in;

[0054] (3) The device samples were passivated using a two-step passivation process of thermal oxidation + PECVD deposition of SiO2;

[0055] (4) Opening a SiO2 window on the front of the sample and depositing anode ohmic contact metal;

[0056] (5) depositing cathode ohmic metal on the back of the sample;

[0057] (6) performing RTA high temperature annealing on the sample to form ohmic contacts on the front and back surfaces;

[0058] (7) Making thickened metal layers on the front and back sides and a surface PI passivation layer;

[0059] (8) Bare chip characterization test.

[0060] The device process described above can produce a very small angle tilted etched SiC high voltage PiN device with an edge tilt angle of 1°. The device simulation software was used to simulate the breakdown voltage of the etched terminal device structure with different tilt angles. The simulation results are shown in the attached figure. Figure 5 As shown; it can be clearly seen from the figure that as the terminal etching inclination angle decreases, the voltage resistance efficiency of the device terminal is constantly improving, where the terminal efficiency corresponding to a 4° inclination angle is 52%; the terminal efficiency corresponding to a 3° inclination angle is 60%; the terminal efficiency corresponding to a 2° inclination angle is 72%; and the terminal efficiency corresponding to a 1° inclination angle is 87%.

[0061] This embodiment further proves that the extremely small angle inclined terminal structure has obvious advantages in improving the terminal withstand voltage efficiency of the device. It also illustrates that the extremely small angle inclined etching process method of SiC material proposed in the present invention is of great significance for the preparation of SiC material devices. It not only reduces the process complexity of realizing extremely small angle etching, but also reduces the process window requirements for etching accuracy control in the actual etching process.

Claims

1. A very small angle tilt etching process method for SiC material, characterized in that: The method utilizes the reflow characteristics of the photoresist during high-temperature baking to achieve filling and further smoothing of the edge slope of the previous photoresist pattern, and obtains a photoresist mask pattern with a very small angle, and then utilizes the photoresist mask pattern to achieve very small angle inclined etching of the SiC material; The process steps of the method include: S1: Spin-coating one or more layers of photoresist on the SiC sample. After each layer of photoresist is spin-coated, the photoresist layer is photolithographically processed and developed to obtain a photoresist pattern. The photoresist pattern is then subjected to high-temperature baking and reflow to obtain a photoresist-cured pattern with a small edge angle. S2: Spin-coating a last layer of photoresist on the photoresist-cured pattern finally obtained in step S1, performing photolithography and development on the last layer of photoresist to obtain a photoresist pattern, and performing high-temperature baking and reflow on the photoresist pattern to obtain a photoresist-cured pattern P' with a small edge angle; S3: thinning the photoresist cured pattern P' to obtain a photoresist cured pattern P with a very small angle edge morphology; S4: using the photoresist cured pattern P as a mask, dry etching the SiC material to obtain a SiC etching process morphology with a very small edge tilt angle; The method can obtain a SiC etching morphology with a very small angle whose cross section is a trapezoidal step with a small top and a large bottom. The very small angle refers to an etching angle of ≤1°, and the maximum etching depth of the SiC etching morphology is ≥1μm.

2. The extremely small angle inclined etching process method of SiC material according to claim 1, characterized in that: The step S1 comprises: S11: Spin-coating a photoresist on the SiC sample, performing photolithography and development on the photoresist, and obtaining a photoresist pattern with a diameter of D1, where D1 is the size of the device active area; S12: performing high-temperature baking and reflow on the photoresist pattern obtained in step S11, and cooling after the baking to obtain a photoresist cured pattern P1 with a small edge angle; S13: Determine whether to continue to repeat the photoresist spin coating, photolithography and baking reflow process in steps S11 and S12 according to the requirements of the device process for the etching angle and etching depth. If necessary, continue to spin-coat the photoresist on the photoresist pattern with a diameter of D1, and after high-temperature baking and reflow, form a photoresist cured pattern P2 with a diameter of D1+d2, and then use this method to form a photoresist cured pattern P2 with a diameter of D1+…+d2. n-1 Photoresist curing pattern P n-1 , n≥3, until the device process requirements for etching angle and etching depth are met, where d2~d n-1 The values ​​are all between 20 and 200 μm, that is, the diameter of the next-level photoresist pattern is 20 to 200 μm larger than the diameter of the previous-level photoresist pattern.

3. The extremely small angle inclined etching process method of SiC material according to claim 2, characterized in that: In the step S11, the thickness of the photoresist is 0.5-10 μm; and in the step S12, the temperature of the high temperature baking reflow is 120-300° C.

4. The extremely small angle inclined etching process method of SiC material according to claim 1, characterized in that: In the step S2, the thickness of the last photoresist layer is 1-20 μm, and the diameter of the pattern after the last photoresist layer is cured is 20-200 μm larger than the diameter of the pattern after the previous photoresist layer is cured.

5. The extremely small angle inclined etching process method of SiC material according to claim 1, characterized in that: In the step S3, the photoresist cured pattern P' is thinned by ICP etching or plasma stripping bombardment.

6. The extremely small angle inclined etching process method of SiC material according to claim 1, characterized in that: The minimum thickness of the thinning in step S3 is 0, and the maximum thickness is the thickness of the last layer of photoresist.

7. The extremely small angle inclined etching process method of SiC material according to claim 1, characterized in that: In step S4, the dry etching adopts ICP or RIE dry etching process, the etching gas used for etching is SF6 / O2 or CF4 / O2, and the typical etching selection ratio is 1:

3.

8. The extremely small angle inclined etching process method of SiC material according to claim 1, characterized in that: The process method is used for manufacturing the terminal structure of SiC power devices, and the SiC power devices include: rectifier type devices PiN, SBD, JBS and MPS, and switch type devices MOSFET, JFET, BJT, GTO and IGBT.

9. The extremely small angle inclined etching process method of SiC material according to claim 1, characterized in that: The photoresist cured pattern P with extremely small angle edge morphology obtained in the steps S1-S3 is used for the extremely small angle tilt etching process of other materials other than SiC, and the other materials other than SiC include but are not limited to SiO2 and SiN of dielectric type, and GaN, GaAs and Si of semiconductor type.

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