Power semiconductor module structure based on copper-clad ceramic substrate

Abstract

The invention discloses a power semiconductor module structure based on a copper-clad ceramic substrate. The structure is provided with positive copper-clad lines on both sides of the copper-clad ceramic substrate, and negative copper-clad lines and three-phase copper-clad lines are provided between the positive copper-clad lines. The three-phase copper-clad lines are hollowed out in the middle and provided with an upper bridge gate and a Kelvin source signal line. The negative copper-clad lines are hollowed out in the middle and provided with a lower bridge gate and a Kelvin source signal line. The upper bridge power semiconductor chip is provided on the positive copper-clad lines and connected to the three-phase copper-clad lines via current binding lines, and the gate and the Kelvin source are connected to the upper bridge gate and the Kelvin source signal line via signal binding lines. The lower bridge power semiconductor chip is provided on the three-phase copper-clad lines and connected to the negative copper-clad lines via current binding lines, and the gate and the Kelvin source are connected to the lower bridge gate and the Kelvin source signal line via signal binding lines. The structure realizes the current sharing characteristics of the power semiconductor module, ensures the reliability of the module opening, and improves the service life and performance of the module.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductors, and in particular to a power semiconductor module structure based on a copper-clad ceramic substrate. Background Art

[0002] Power semiconductor modules are circuit modules that combine power semiconductor chips into a whole according to certain functional combinations. They have the advantages of small size and high power density, so they are widely used in the field of new energy vehicles. With the development of high-power and long-range new energy vehicles, the application environment of power semiconductor modules is becoming increasingly harsh, and the current sharing characteristics of power semiconductor modules have received extensive attention.

[0003] With the rapid development of new energy vehicles, Si-based and SiC-based power semiconductor modules have continued to develop. In these high-power application fields, higher and higher requirements are placed on the switching frequency of power semiconductor modules. In order to obtain higher rated currents and lower manufacturing costs, these power semiconductor modules usually adopt a multi-chip parallel packaging structure. However, due to the asymmetry of the current loop of the copper-clad ceramic substrate and the inconsistency of the dynamic and static parameters of the power chip, a large transient unbalanced current will appear between the parallel chips, which brings considerable challenges to the safety and stability of the power semiconductor module.

[0004] In the three-phase AC motor control system, the circuit diagram of the power semiconductor module is as follows Figure 1 As shown, a plurality of power semiconductor chips are connected in parallel in the three-phase circuit, such as the upper bridge power semiconductor chips a1 to a6 and the lower bridge power semiconductor chips b1 to b6 of the U phase in the figure. Figure 2 The U phase circuit diagram is shown in Figure 2 In the circuit diagram, when the upper bridge power semiconductor chips a1 to a6 are turned on and the lower bridge power semiconductor chips b1 to b6 are turned off, the current Ia flows from the positive busbar to the three-phase busbar. The resistance value of the source and gate control loop signals of each power semiconductor chip, the inductance generated by the length, the resistance and inductance between the power semiconductor chips, etc. determine the opening time of each power semiconductor chip. Assuming that the switching time of power semiconductor chip a1 is earlier than that of other power semiconductor chips, a large current will flow through power semiconductor chip a1. In extreme cases, it will cause damage to power semiconductor chip a1. At the same time, if Figure 3As shown, when the lower bridge power semiconductor chips b1 to b6 are turned on and the upper bridge power semiconductor chips a1 to a6 are turned off, the current Ia flows from the three-phase busbar to the negative busbar. In this case, as mentioned above, if the power semiconductor chip b6 closest to the three-phase busbar is turned on earlier than other power semiconductor chips, the current will flow through the power semiconductor chip b6, and in extreme cases, it will damage the power semiconductor chip b6. In this way, the service life and performance of the power semiconductor module are reduced, the control performance of the motor is seriously affected, and there are certain safety hazards.

[0005] Usually, the block diagram of the power semiconductor module in the three-phase AC motor control system is as follows: Figure 4 As shown, it has a positive busbar and a negative busbar on one side of the power semiconductor module and a three-phase busbar on the other side, and multiple power semiconductor chips are connected in parallel in each phase for carrying large current.

[0006] Among SiC power semiconductors designed for high-speed driving, some are designed with Kelvin sources in the power semiconductors. The Kelvin source connection is to separate the source of the power semiconductor chip into two parts, one part is the main path for large current to flow, and the other part is used for the return path of the gate drive signal. The Kelvin source connection is the same as the gate signal line, which makes the wiring length from the signal terminal to the power semiconductor of each power semiconductor uniform, and can weaken the deviation of the switching time of different power semiconductors. In the case of Kelvin source connection, it is preferred that the total length Ltn of the gate signal line and the Kelvin source signal line in each power semiconductor satisfies the following formula:

[0007] Ltn=Lgn+Lkn

[0008] Among them, Ltn is the total length, Lgn is the gate signal line length, and Lkn is the Kelvin source signal line length. Summary of the invention

[0009] The technical problem to be solved by the present invention is to provide a power semiconductor module structure based on a copper-clad ceramic substrate. The structure adjusts the length of the source and gate loop signal lines of the power semiconductor chip through the current pattern design of the copper-clad ceramic substrate and the bonding wire connection, and then adjusts the opening time of each power semiconductor chip, thereby achieving current sharing characteristics, ensuring the opening reliability of the power semiconductor module, and improving the service life and performance of the power semiconductor module.

[0010] In order to solve the above technical problems, the power semiconductor module structure based on the copper-clad ceramic substrate of the present invention includes a copper-clad ceramic substrate, a positive busbar, a negative busbar, a three-phase terminal, a plurality of upper bridge power semiconductor chips and a plurality of lower bridge power semiconductor chips, wherein the positive busbar includes a first positive terminal and a second positive terminal, and the copper-clad ceramic substrate has positive copper-clad lines extending from the upper edge to the lower edge on both sides, and negative copper-clad lines are provided between the positive copper-clad lines on both sides from the upper edge to the middle, and the copper-clad ceramic substrate has a plurality of upper bridge power semiconductor chips and a plurality of lower bridge power semiconductor chips. A three-phase copper-clad pattern is provided between the positive copper-clad patterns on both sides of the lower part, extending from the lower edge to the positive copper-clad patterns and the negative copper-clad patterns on the upper part of the copper-clad ceramic substrate. Moreover, the three-phase copper-clad patterns on the lower part of the copper-clad ceramic substrate are hollowed out in the center, and long strips of upper bridge gate signal patterns and long strips of upper bridge Kelvin source signal patterns are provided at intervals in the hollowed-out parts. The negative copper-clad patterns are hollowed out in the center, and long strips of lower bridge gate signal patterns and long strips of lower bridge Kelvin source signal patterns are provided at intervals in the hollowed-out parts. The first The positive terminal and the second positive terminal are respectively arranged on the positive copper-clad lines on both sides of the copper-clad ceramic substrate and are located at the upper edge, the negative busbar is arranged on the negative copper-clad lines and is located at the upper edge, the three-phase terminal is arranged on the three-phase copper-clad lines and is located at the lower edge, the plurality of upper bridge power semiconductor chips are equally divided and arranged in a single row on the positive copper-clad lines on both sides of the copper-clad ceramic substrate and are located at the lower part of the copper-clad ceramic substrate, and the plurality of upper bridge power semiconductor chips are connected to adjacent three-phase copper-clad lines via current binding wires. The patterns, gates and Kelvin sources are respectively connected to the long strip upper bridge gate signal patterns and the long strip upper bridge Kelvin source signal patterns through signal binding lines; the plurality of lower bridge power semiconductor chips are equally divided and arranged in a single row on the three-phase copper clad patterns and are located on both sides of the negative copper clad patterns; the plurality of lower bridge power semiconductor chips are connected to adjacent negative copper clad patterns through current binding lines; the gates and Kelvin sources are respectively connected to the long strip lower bridge gate signal patterns and the long strip lower bridge Kelvin source signal patterns through signal binding lines.

[0011] Furthermore, the long strip upper bridge gate signal lines and the long strip lower bridge gate signal lines are bent 180 degrees at the farthest ends respectively, and the gates of the plurality of upper bridge power semiconductor chips and the plurality of lower bridge power semiconductor chips are connected to the bent sections respectively via signal binding wires.

[0012] Furthermore, the long strip upper bridge Kelvin source signal lines and the long strip lower bridge Kelvin source signal lines are bent 180° at the farthest ends respectively, and the Kelvin sources of the upper bridge power semiconductor chips and the lower bridge power semiconductor chips are respectively connected to the bent sections via signal binding lines.

[0013] Furthermore, the strip-shaped upper bridge gate signal lines are arranged in parallel and at intervals with the strip-shaped upper bridge Kelvin source signal lines, and the strip-shaped lower bridge gate signal lines are arranged in parallel and at intervals with the strip-shaped lower bridge Kelvin source signal lines.

[0014] Furthermore, the arrangement of the elongated upper bridge gate signal lines and the elongated upper bridge Kelvin source signal lines and the elongated lower bridge gate signal lines and the elongated lower bridge Kelvin source signal lines follows the following rule: if the distance from the gate to the gate signal lines of the power semiconductor chip is the shortest, then the distance from the Kelvin source to the Kelvin source signal lines of the power semiconductor chip is the farthest; if the distance from the gate to the gate signal lines of the power semiconductor chip is the farthest, then the distance from the Kelvin source to the Kelvin source signal lines of the power semiconductor chip is the shortest.

[0015] Furthermore, the difference between the length of the gate-to-gate signal lines of each power semiconductor chip and the sum of the lengths of the Kelvin source-to-Kelvin source signal lines is equal.

[0016] Furthermore, the difference between the sum of the length of the gate-to-gate signal lines and the length of the Kelvin source-to-Kelvin source signal lines of each power semiconductor chip is less than 5 mm.

[0017] Furthermore, the plurality of upper bridge power semiconductor chips and the plurality of lower bridge power semiconductor chips are four or six power semiconductor chips respectively, and are divided into two groups, and the power semiconductor chips in each group are arranged in a single row.

[0018] Since the power semiconductor module structure based on the copper-clad ceramic substrate of the present invention adopts the above-mentioned technical solution, that is, the structure is provided with positive copper-clad patterns on both sides of the copper-clad ceramic substrate, negative copper-clad patterns and three-phase copper-clad patterns are provided between the positive copper-clad patterns on both sides, the upper part of the three-phase copper-clad patterns extends between the positive copper-clad patterns and the negative copper-clad patterns, the three-phase copper-clad patterns are hollowed out in the middle and are provided with upper bridge gate signal patterns and upper bridge Kelvin source signal patterns, the negative copper-clad patterns are hollowed out in the middle and are provided with lower bridge gate signal patterns and lower bridge Kelvin source signal patterns, and the two positive terminals are provided with The positive copper-clad lines on both sides, the negative busbar is arranged on the negative copper-clad lines, the three-phase terminals are arranged on the three-phase copper-clad lines, the upper bridge power semiconductor chip is arranged on the positive copper-clad lines on both sides and connected to the adjacent three-phase copper-clad lines through current binding lines, the gate and Kelvin source are connected to the upper bridge gate signal lines and the upper bridge Kelvin source signal lines through signal binding lines, and the lower bridge power semiconductor chip is arranged on the three-phase copper-clad lines and connected to the adjacent negative copper-clad lines through current binding lines, the gate and Kelvin source are connected to the lower bridge gate signal lines and the lower bridge Kelvin source signal lines through signal binding lines. This structure realizes the current sharing characteristics of the power semiconductor module, ensures the open tube reliability of the power semiconductor module, and improves the service life and performance of the power semiconductor module. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments:

[0020] Figure 1 It is the circuit diagram of the power semiconductor module in the three-phase AC motor control system;

[0021] Figure 2 for Figure 1 Schematic diagram of the flow direction of the upper bridge current of the middle U phase;

[0022] Figure 3 for Figure 1 Schematic diagram of the flow direction of the lower bridge current of the middle U phase;

[0023] Figure 4 This is the block diagram of the power semiconductor module in the three-phase AC motor control system;

[0024] Figure 5 This is a schematic diagram of the structure of a power semiconductor module based on a copper-clad ceramic substrate of the present invention;

[0025] Figure 6 for Figure 5 A magnified schematic diagram of the middle part;

[0026] Figure 7 for Figure 5 The enlarged schematic diagram of the middle B part;

[0027] Figure 8 This is a schematic diagram of the structure of the module structure in which the upper bridge and the lower bridge are four power semiconductor chips respectively;

[0028] Fig. 9 This is a schematic diagram of the bending of the source signal lines of the upper bridge and the lower bridge in this module structure;

[0029] Fig.10 This is a schematic diagram of the bending of the gate signal lines of the four power semiconductor chips in the upper and lower bridges of this module structure;

[0030] Fig.11 It is a schematic diagram of the semiconductor structure in which the positive busbar is located in the middle of the module structure;

[0031] Fig.12 This is a schematic diagram of the gate signal pattern and the Kelvin source signal pattern without bending in the module structure;

[0032] Fig.13 Schematic diagram of the series circuit of inductor L and resistor R. DETAILED DESCRIPTION

[0033] Implementation example Figure 5 , Figure 6 and Figure 7As shown, the power semiconductor module structure based on the copper-clad ceramic substrate of the present invention includes a copper-clad ceramic substrate 1, a positive busbar, a negative busbar 3, a three-phase terminal 4, a plurality of upper bridge power semiconductor chips a1-a6 and a plurality of lower bridge power semiconductor chips b1-b6, the positive busbar includes a first positive terminal 21 and a second positive terminal 22, the copper-clad ceramic substrate 1 has positive copper-clad lines 11 and 12 extending from the upper edge to the lower edge on both sides, a negative copper-clad line 13 is provided between the positive copper-clad lines 11 and 12 on both sides from the upper edge to the middle, and the lower part of the copper-clad ceramic substrate 1 has a plurality of positive copper-clad lines 11 and 12 extending from the upper edge to the lower edge. A three-phase copper-clad pattern 14 is provided between the positive copper-clad patterns 11 and 12 on the side and extends from the lower edge to the positive copper-clad patterns 11 and 12 and the negative copper-clad patterns 13 on the upper part of the copper-clad ceramic substrate 1, and the three-phase copper-clad patterns 14 on the lower part of the copper-clad ceramic substrate 1 are hollowed out in the middle, and a long strip upper bridge gate signal pattern 16 and a long strip upper bridge Kelvin source signal pattern 15 are provided at intervals in the hollowed-out part, the negative copper-clad pattern 13 is hollowed out in the middle, and a long strip lower bridge gate signal pattern 18 and a long strip lower bridge Kelvin source signal pattern 17 are provided at intervals in the hollowed-out part, and the first positive terminal 2 The positive electrode terminals 1 and the second positive electrode terminals 22 are respectively arranged on the positive electrode copper-clad lines 11 and 12 on both sides of the copper-clad ceramic substrate and are located at the upper edge. The negative electrode busbar 3 is arranged on the negative electrode copper-clad lines 13 and is located at the upper edge. The three-phase terminal 4 is arranged on the three-phase copper-clad lines 14 and is located at the lower edge. The plurality of upper bridge power semiconductor chips a1 to a6 are equally divided and arranged in a single row on the positive electrode copper-clad lines 11 and 12 on both sides of the copper-clad ceramic substrate 1 and are located at the lower part of the copper-clad ceramic substrate 1. The plurality of upper bridge power semiconductor chips a1 to a6 are connected to adjacent three-phase copper-clad lines via current binding wires 5. The lines 14, the gate and the Kelvin source are respectively connected to the long strip upper bridge gate signal lines 16 and the long strip upper bridge Kelvin source signal lines 15 through the signal binding line 6, and the plurality of lower bridge power semiconductor chips b1~b6 are equally divided and arranged in a single row on the three-phase copper clad lines 14 and are located on both sides of the negative copper clad lines 13. The plurality of lower bridge power semiconductor chips b1~b6 are connected to the adjacent negative copper clad lines 13 through the current binding line 7, and the gate and the Kelvin source are respectively connected to the long strip lower bridge gate signal lines 18 and the long strip lower bridge Kelvin source signal lines 17 through the signal binding line 8.

[0034] Preferably, the long strip upper bridge gate signal pattern 16 and the long strip lower bridge gate signal pattern 18 are bent 180° at the farthest end respectively, and the gates of the upper bridge power semiconductor chips a1-a6 and the lower bridge power semiconductor chips b1-b6 are connected to the bent sections via signal binding wires 6 and 8 respectively.

[0035] like Fig. 9 and Fig.10As shown, preferably, the long strip upper bridge Kelvin source signal line 15 and the long strip lower bridge Kelvin source signal line 17 are respectively bent 180° at the farthest end, and the Kelvin sources of the several upper bridge power semiconductor chips a1~a6 and the several lower bridge power semiconductor chips b1~b6 are respectively connected to the bent sections via signal binding lines 6 and 8.

[0036] Preferably, the long strip upper bridge gate signal lines 16 are arranged in parallel and spaced apart from the long strip upper bridge Kelvin source signal lines 15 , and the long strip lower bridge gate signal lines 18 are arranged in parallel and spaced apart from the long strip lower bridge Kelvin source signal lines 17 .

[0037] Preferably, the arrangement of the elongated upper bridge gate signal lines 16 and the elongated upper bridge Kelvin source signal lines 15 as well as the elongated lower bridge gate signal lines 18 and the elongated lower bridge Kelvin source signal lines 17 follows the following rule: if the distance from the gate to the gate signal lines of the power semiconductor chip is the shortest, then the distance from the Kelvin source to the Kelvin source signal lines of the power semiconductor chip is the farthest; if the distance from the gate to the gate signal lines of the power semiconductor chip is the farthest, then the distance from the Kelvin source to the Kelvin source signal lines of the power semiconductor chip is the shortest.

[0038] Preferably, the difference between the length of the gate-to-gate signal lines of each power semiconductor chip and the sum of the lengths of the Kelvin source-to-Kelvin source signal lines is equal.

[0039] Preferably, the difference between the sum of the length of the gate-to-gate signal lines and the length of the Kelvin source-to-Kelvin source signal lines of each power semiconductor chip is less than 5 mm.

[0040] Preferably, the plurality of upper bridge power semiconductor chips a1 - a6 and the plurality of lower bridge power semiconductor chips b1 - b6 are four or six power semiconductor chips respectively, and are divided into two groups, and the power semiconductor chips in each group are arranged in a single row.

[0041] In this module structure, the current flowing from the positive busbar is divided into two positive copper-clad patterns 11 and 12 on the left and right. The upper bridge power semiconductor chips a1 to a6 are arranged on the positive copper-clad patterns 11 and 12 respectively. The current flows into the upper bridge power semiconductor chips a1 to a6 arranged on the left and right. Figure 5 and Figure 7 It can be seen that the three power semiconductor chips on the left are a group, and the three power semiconductor chips on the right are a group. The current passes through the upper bridge power semiconductor chips a1 to a6 arranged on the left and right to the three-phase copper clad pattern 14 to transfer the current and flow into the three-phase terminal 4. In addition, the current flowing from the three-phase terminal 4 flows into the lower bridge power semiconductor chips b1 to b6 through the three-phase copper clad pattern 14. Figure 5 and Figure 6It can be seen that the lower bridge power semiconductor chips b1-b6 are located on the three-phase copper-clad pattern 14, the three power semiconductor chips on the left are a group, and the three power semiconductor chips on the right are a group. The current passes through the lower bridge power semiconductor chips b1-b6 to the negative copper-clad pattern 13 and flows into the negative busbar 3; Figure 6 The gates of the three power semiconductor chips on the left side of the middle and lower bridge arms are connected to the gate signal lines 18, and the gates of the three power semiconductor chips on the right side are also connected to the gate signal lines 18; the Kelvin sources of the three power semiconductor chips on the left side are connected to the Kelvin source signal lines 17, and the Kelvin sources of the three power semiconductor chips on the right side are connected to the Kelvin source signal lines 17; the gate signal lines 18 are arranged in parallel with the Kelvin source signal lines 17, the gate signal lines 18 are bent 180 degrees at the farthest end, and the gates are connected to the bent sections, so that the gates of the chips b1, b2, and b3 are closest to the gate signal lines, and the Kelvin sources are farthest from the Kelvin source signal lines; the gates of the chips b4, b5, and b6 are farthest from the gate signal lines, and the Kelvin sources are closest to the Kelvin source signal lines; so that the total length Ltn of the chips b1 to b6 is equal; such as Figure 6 As shown, the specific distance calculation is as follows:

[0042] Ltn=Lgn+Lkn of b1 chip

[0043] Lgn=Ly1+L5+Lx1, Lkn=L3+Lx1+Lx2,

[0044] Since L3+L5=Ly1, Ltn=Lgn+Lkn=2Ly1+2Lx1+Lx2

[0045] Ltn=Lgn+Lkn of b2 chip

[0046] Lgn=Ly1+L4+Lx1, Lkn=L2+Lx1+Lx2,

[0047] Since L2+L4=Ly1, Ltn=Lgn+Lkn=2Ly1+2Lx1+Lx2

[0048] The Ltn of b3 chip is Lgn+Lkn.

[0049] Lgn=L1+Lx1, Lkn=L1+Lx1+Lx2,

[0050] Since L1=Ly1, Ltn=Lgn+Lkn=2Ly1+2Lx1+Lx2

[0051] Among them, L1=Ly1 is the distance between the two ends of the gate signal line and the Kelvin source signal line, L2 is the distance from the proximal end of the gate signal line to the gate terminal of chip b2 and chip b5, L3 is the distance from the proximal end of the gate signal line to the gate terminal of chip b1 and chip b4, L4 is the distance from the gate terminal of chip b2 and chip 5 to the gate terminal of chip b3 and chip b6, L5 is the distance from the gate terminal of chip b1 and chip 4 to the gate terminal of chip b3 and chip b6, Lx1 is the distance from the center of chip b3 to the center of the gate signal line, Lx3 is the distance from the center of chip b6 to the center of the Kelvin source signal line, and Lx2 is the spacing between the gate signal line and the Kelvin source signal line.

[0052] Since the b1 chip is symmetrical with the b4 chip, the b2 chip is symmetrical with the b5 chip, and the b3 chip is symmetrical with the b6 chip, Lx1=Lx3, so the total length Ltn of the b1 to b6 chips is equal; through the above measures, the total length Ltn of each chip of the lower bridge is guaranteed to be equal, so as to control the opening time of each power semiconductor chip to be equal, thereby realizing the current sharing characteristic and ensuring the opening reliability of the power semiconductor module;

[0053] like Figure 7 As shown, the gates of the three power semiconductor chips on the left side of the upper bridge arm are connected to the gate signal lines 16, and the gates of the three power semiconductor chips on the right side are also connected to the gate signal lines 16; the Kelvin sources of the three power semiconductor chips on the left side are connected to the Kelvin source signal lines 15, and the Kelvin sources of the three power semiconductor chips on the right side are connected to the Kelvin source signal lines 15; the gate signal lines 16 are arranged in parallel with the Kelvin source signal lines 15, and the gate signal lines 16 are bent 180 degrees at the farthest end; the gates of the power semiconductor chips are connected to the bent sections, so that the gates of the a1, a2, and a3 chips are closest to the gate signal lines, and the Kelvin sources are farthest from the Kelvin source signal lines; the gates of the a4, a5, and a6 chips are farthest from the gate signal lines, and the Kelvin sources are closest to the Kelvin source signal lines; so that the total length Ltn of the a1 to a6 chips is equal; as shown Figure 7 As shown, the specific distance calculation is as follows:

[0054] Ltn=Lgn+Lkn of a1 chip

[0055] Lgn=Ly2+L9+Lx4, Lkn=L6+Lx4+Lx5,

[0056] Since L6+L9=Ly2, Ltn=Lgn+Lkn=2Ly2+2Lx4+Lx5

[0057] Ltn=Lgn+Lkn of a2 chip

[0058] Lgn=Ly2+L10+Lx4, Lkn=L7+Lx4+Lx5,

[0059] Since L7+L10=Ly2, Ltn=Lgn+Lkn=2Ly2+2Lx4+Lx5

[0060] The Ltn of a3 chip is Lgn+Lkn.

[0061] Lgn=Ly2+L11+Lx4, Lkn=L8+Lx4+Lx5,

[0062] Since L11+L8=Ly2, Ltn=Lgn+Lkn=2LLy2+2Lx4+Lx5

[0063] Among them, Ly2 is the distance between the two ends of the gate signal line and the Kelvin source signal line, L6 is the distance from the proximal end of the gate signal line to the gate terminals of chip a1 and chip a4, L7 is the distance from the proximal end of the gate signal line to the gate terminals of chip a2 and chip a5, L8 is the distance from the proximal end of the gate signal line to the gate terminals of chip a3 and chip a6, L9 is the distance from the far end of the gate signal line to the gate terminals of chip a1 and chip a4, L10 is the distance from the far end of the gate signal line to the gate terminals of chip a2 and chip a5, L11 is the distance from the far end of the gate signal line to the gate terminals of chip a3 and chip a6, Lx4 is the distance from the center of chip a3 to the center of the gate signal line, Lx6 is the distance from the center of chip a6 to the center of the Kelvin source signal line, and Lx5 is the distance between the gate signal line and the Kelvin source signal line.

[0064] Since the a1 chip is symmetrical with the a4 chip, the a2 chip is symmetrical with the a5 chip, and the a3 chip is symmetrical with the a6 chip, Lx4=Lx6, so the total length Ltn of the a1~a6 chips is equal; the above measures ensure that the total length Ltn of each chip on the upper bridge is equal, thereby controlling the opening time of each power semiconductor chip to be equal, thereby achieving current sharing characteristics and ensuring that the opening reliability of the power semiconductor module is optimized.

[0065] Figure 8 The module structure shows that the upper bridge and lower bridge have four power semiconductor chips respectively. For other principles, refer to Figures 5 to 7 Similarly, in this structure, the total length Ltn of the chips a1 to a4 is equal, and the total length Ltn of the chips b1 to b4 is equal; thereby controlling the opening time of each power semiconductor to be equal, achieving the current sharing characteristic, and ensuring the opening reliability of the power semiconductor module.

[0066] like Fig. 9 The module structure shown is Figure 5A variation of the , the upper bridge also has six power semiconductor chips, the lower bridge also has six power semiconductor chips, the difference is that the source signal lines of the upper bridge and the lower bridge are bent 180° at the farthest end, and the source of the chip is connected to the bent section of the source signal line. For other principles, refer to Figures 5 to 7 , thereby ensuring that the total length Ltn of chips a1 to a6 is equal, and the total length Ltn of chips b1 to b6 is equal; and then controlling the opening time of each power semiconductor chip to be equal, achieving the current sharing characteristic, and ensuring the opening reliability of the power semiconductor module.

[0067] Fig.10 The module structure shown is Fig. 9 A variation of the above embodiment, in which the upper bridge has four power semiconductor chips, the lower bridge also has four power semiconductor chips, and the source signal lines of the upper bridge and the lower bridge are bent 180° at the farthest end, and the source of each chip is connected to the bent section of the source signal line. For other principles, refer to Figures 5 to 7 , the total length Ltn of the remote a1~a4 chips is equal, and the total length Ltn of the b1~b4 chips is equal; thereby controlling the opening time of each power semiconductor chip to be equal, achieving the current sharing characteristic, and ensuring the opening reliability of the power semiconductor module.

[0068] like Fig.11 The module structure shown is Figure 5 A variation of the , the upper bridge also has six power semiconductor chips, the lower bridge also has six power semiconductor chips, the difference is that the positive and negative busbars are swapped, the copper cladding pattern is modified accordingly, and other principles refer to Figures 5 to 7 , thereby ensuring that the total length Ltn of chips a1 to a6 is equal, and the total length Ltn of chips b1 to b6 is equal; and then controlling the opening time of each power semiconductor chip to be equal, achieving the current sharing characteristic, and ensuring the opening reliability of the power semiconductor module.

[0069] Fig.12 The figure shows a schematic diagram of the structure of the module structure in which the gate signal lines and the Kelvin source signal lines are not bent. In the figure, the distance between the gate and gate signal lines of the b1 chip is the shortest, and the distance between the Kelvin source and the Kelvin source signal material of the b1 chip is the farthest. The distance between the gate and gate signal lines of the b3 chip is the farthest, and the distance between the Kelvin source and the Kelvin source signal lines of the b3 chip is also the shortest relative to other chips. Therefore, the total length Ltn of the b1~b3 chips is equal to ensure that the switching time of each chip is basically the same. The upper bridge a1~a6 chips are the same to achieve current sharing characteristics and ensure the open tube reliability of the power semiconductor module.

[0070] Through the structural design of this module, Ltn=Lgn+Lkn of the four or six chips in the upper bridge arm is equal, which weakens the deviation of the switching time of different power semiconductor chips in the upper bridge arm; Ltn=Lgn+Lkn of the four or six power semiconductor chips in the lower bridge arm is equal, which weakens the deviation of the switching time of different power semiconductor chips in the lower bridge arm, thereby solving the problem of uneven current of the power semiconductor chips and improving the reliability of the power semiconductor module.

[0071] like Fig.13 As shown, the inductor L represents the inductance between the power semiconductor chips, and the resistor R represents the resistance of the power semiconductor chip when it is turned on. In this circuit, the current i (t) generated instantly when the switch S is turned on is shown in Formula 1:

[0072] (1)

[0073] (2)

[0074] That is, when the inductance is large, even if the voltage E is applied, the current i(t) will not flow immediately. According to this principle, through the application of this module structure, the current in each power semiconductor chip can achieve a gradually increasing effect, thereby reducing the large current generated by the current concentrated through a certain power semiconductor chip, improving the current sharing characteristics of the module, and avoiding chip damage.

Claims

1. A power semiconductor module structure based on a copper-clad ceramic substrate, comprising a copper-clad ceramic substrate, a positive busbar, a negative busbar, a three-phase terminal, a plurality of upper bridge power semiconductor chips and a plurality of lower bridge power semiconductor chips, characterized in that: The positive busbar includes a first positive terminal and a second positive terminal, positive copper clad patterns are extended from the upper edge to the lower edge on both sides of the copper-clad ceramic substrate, negative copper clad patterns are provided between the positive copper clad patterns on both sides from the upper edge to the middle, and three-phase copper clad patterns are extended from the lower edge to the positive copper clad patterns and the negative copper clad patterns on the upper part of the copper-clad ceramic substrate between the positive copper clad patterns on both sides at the lower part of the copper-clad ceramic substrate, and the three-phase copper clad patterns at the lower part of the copper-clad ceramic substrate are hollowed out in the middle, and long strips of upper bridge gate signal patterns and long strips of upper bridge Kelvin source signal patterns are provided at intervals in the hollowed-out parts, the negative copper clad patterns are hollowed out in the middle, and long strips of lower bridge gate signal patterns and long strips of lower bridge Kelvin source signal patterns are provided at intervals in the hollowed-out parts, the first positive terminal and the second positive terminal are respectively provided on the positive copper clad patterns on both sides of the copper-clad ceramic substrate and are located at the upper edge. The negative busbar is arranged on the negative copper-clad pattern and is located at the upper edge. The three-phase terminal is arranged on the three-phase copper-clad pattern and is located at the lower edge. The plurality of upper bridge power semiconductor chips are equally divided and arranged in a single row on the positive copper-clad patterns on both sides of the copper-clad ceramic substrate and are located at the lower part of the copper-clad ceramic substrate. The plurality of upper bridge power semiconductor chips are connected to adjacent three-phase copper-clad patterns via current binding lines, and the gate and Kelvin source are respectively connected to the long strip upper bridge gate signal patterns and the long strip upper bridge Kelvin source signal patterns via signal binding lines. The plurality of lower bridge power semiconductor chips are equally divided and arranged in a single row on the three-phase copper-clad patterns and are located on both sides of the negative copper-clad patterns. The plurality of lower bridge power semiconductor chips are connected to adjacent negative copper-clad patterns via current binding lines, and the gate and Kelvin source are respectively connected to the long strip lower bridge gate signal patterns and the long strip lower bridge Kelvin source signal patterns via signal binding lines.

2. The power semiconductor module structure based on the copper-clad ceramic substrate according to claim 1, characterized in that: The long strip upper bridge gate signal lines and the long strip lower bridge gate signal lines are respectively bent 180 degrees at the farthest ends, and the gates of the plurality of upper bridge power semiconductor chips and the plurality of lower bridge power semiconductor chips are respectively connected to the bent sections via signal binding wires.

3. The power semiconductor module structure based on the copper-clad ceramic substrate according to claim 1, characterized in that: The long strip upper bridge Kelvin source signal lines and the long strip lower bridge Kelvin source signal lines are bent 180° at the farthest ends respectively, and the Kelvin sources of the upper bridge power semiconductor chips and the lower bridge power semiconductor chips are respectively connected to the bent sections via signal binding lines.

4. The power semiconductor module structure based on the copper-clad ceramic substrate according to claim 1, 2 or 3, characterized in that: The strip-shaped upper bridge gate signal lines are arranged in parallel and at intervals with the strip-shaped upper bridge Kelvin source signal lines, and the strip-shaped lower bridge gate signal lines are arranged in parallel and at intervals with the strip-shaped lower bridge Kelvin source signal lines.

5. The power semiconductor module structure based on the copper-clad ceramic substrate according to claim 4, characterized in that: The arrangement of the long strip upper bridge gate signal lines and the long strip upper bridge Kelvin source signal lines and the long strip lower bridge gate signal lines and the long strip lower bridge Kelvin source signal lines follows the following rule: if the distance from the gate to the gate signal lines of the power semiconductor chip is the shortest, then the distance from the Kelvin source to the Kelvin source signal lines of the power semiconductor chip is the farthest; if the distance from the gate to the gate signal lines of the power semiconductor chip is the farthest, then the distance from the Kelvin source to the Kelvin source signal lines of the power semiconductor chip is the shortest.

6. The power semiconductor module structure based on the copper-clad ceramic substrate according to claim 5, characterized in that: The difference between the length of the gate-to-gate signal lines of each power semiconductor chip and the sum of the lengths of the Kelvin source-to-Kelvin source signal lines is equal.

7. The power semiconductor module structure based on a copper-clad ceramic substrate according to claim 5, characterized in that: The difference between the length of the gate-to-gate signal lines of each power semiconductor chip and the sum of the length of the Kelvin source-to-Kelvin source signal lines is less than 5 mm.

8. The power semiconductor module structure based on a copper-clad ceramic substrate according to claim 1, characterized in that: The plurality of upper bridge power semiconductor chips and the plurality of lower bridge power semiconductor chips are four or six power semiconductor chips respectively, and are divided into two groups, and the power semiconductor chips in each group are arranged in a single row.

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