Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for preparing the same. The semiconductor device comprises a substrate, a dielectric layer, an intrinsic semiconductor layer and an N-type doped layer. The intrinsic semiconductor layer comprises a second semiconductor material different from the first semiconductor material, and a portion of the intrinsic semiconductor layer is disposed in the P-type doped layer, and another portion of the intrinsic semiconductor layer is disposed in the dielectric layer. The N-type doped layer is embedded on top of the intrinsic semiconductor layer, which reduces the transition time from the P-type doped layer to the N-type doped layer, and can effectively improve work efficiency.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor processing technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Photodiodes in semiconductor devices are used to convert optical signals into electrical signals. The existing PN junction photodiode PD, such as the conventional Ge-PD, uses photolithography to form a groove pattern in the Si layer on the surface of the SOI substrate, and then uses an epitaxial process to deposit a Ge structure on the pattern in the Si layer. Due to the mismatch between the Si and Ge lattice constants, there will be a large number of defects during epitaxy, which is not conducive to improving work efficiency.

[0003] Therefore, it is necessary to develop a novel semiconductor device and a method for manufacturing the same to overcome the above-mentioned defects of the prior art. Summary of the invention

[0004] The object of the present invention is to provide a novel semiconductor device and a method for manufacturing the same, so as to improve working efficiency.

[0005] To achieve the above object, the semiconductor device of the present invention comprises:

[0006] A substrate, including a P-type doped layer located on top of the substrate and comprising a first semiconductor material;

[0007] A dielectric layer, stacked and arranged on the top surface of the P-type doped layer;

[0008] An intrinsic semiconductor layer, comprising a second semiconductor material different from the first semiconductor material, and a portion of which is disposed in the P-type doped layer and another portion of which is disposed in the dielectric layer;

[0009] The N-type doped layer is embedded on the top of the intrinsic semiconductor layer.

[0010] The beneficial effect of the semiconductor device of the present invention is that: the intrinsic semiconductor layer includes a second semiconductor material different from the first semiconductor material, and a part of it is arranged in the P-type doped layer, and the other part is arranged in the dielectric layer, and the N-type doped layer is embedded on the top of the intrinsic semiconductor layer, which reduces the transition time from the P-type doped layer to the N-type doped layer, and can effectively improve work efficiency.

[0011] Preferably, the semiconductor device also includes an N-type injection doping layer arranged in the P-type doping layer, and an external N-type doping layer arranged in the substrate and electrically contacting the N-type injection doping layer and the N-type doping layer, respectively, and the doping concentration of the N-type injection doping layer is higher than the doping concentration of either the N-type doping layer and the external N-type doping layer.

[0012] Preferably, the semiconductor device further comprises a P-type injection doping layer disposed within the P-type doping layer, and a doping concentration of the P-type injection doping layer is higher than a doping concentration of the P-type doping layer.

[0013] Preferably, a top surface of the N-type doped layer is higher than a top surface of the dielectric layer.

[0014] Preferably, the N-type doped layer comprises a third semiconductor material having the same composition as the first semiconductor material, or having the same composition as the second semiconductor material.

[0015] The method for manufacturing the semiconductor device of the present invention comprises the following steps:

[0016] S0: providing an original substrate, wherein the original substrate comprises a P-type doped layer located at the top and comprising a first semiconductor material, a bottom dielectric layer and an intermediate dielectric layer stacked in sequence on the P-type doped layer, and a first trench penetrating the bottom dielectric layer, the intermediate dielectric layer and a portion of the P-type doped layer;

[0017] S1: performing a low-temperature epitaxial process using a second semiconductor material different from the first semiconductor material to form a first intrinsic semiconductor layer covering the inner wall of the first trench, and performing a laser annealing process on the first intrinsic semiconductor layer;

[0018] S2: performing a high temperature epitaxial process using the second semiconductor material to form a second intrinsic semiconductor layer covering the surface of the first intrinsic semiconductor layer and filling the first trench, wherein the first intrinsic semiconductor layer and the second intrinsic semiconductor layer constitute an intrinsic semiconductor layer;

[0019] S3: after depositing a dielectric material to form a top dielectric layer covering the top surface of the structure obtained in step S2, a portion of the top dielectric layer and a portion of the intrinsic semiconductor layer are removed from the top dielectric layer in a direction pointing to the bottom of the original substrate until a portion of the surface of the intrinsic semiconductor layer is exposed and a second trench is formed;

[0020] S4: performing an epitaxial process using an N-type doped semiconductor material to form an N-type doped layer filling the second trench.

[0021] The beneficial effect of the semiconductor device manufacturing method described in the present invention is that: through the step S1, a second semiconductor material different from the first semiconductor material is used to perform a low-temperature epitaxial process to form a first intrinsic semiconductor layer covering the inner wall of the first groove, so that the growth rate of the first intrinsic semiconductor layer is slow to avoid the first semiconductor material from diffusing into the second semiconductor material as much as possible. Combined with the subsequent laser annealing process on the first intrinsic semiconductor layer acting on the surface of the first intrinsic semiconductor layer, the first intrinsic semiconductor layer can be repaired and improved, preventing the first semiconductor material from diffusing from the interface to reduce the surface roughness, thereby improving the working efficiency of the semiconductor device.

[0022] Preferably, the step S3 also includes removing part of the top dielectric layer, part of the middle dielectric layer, part of the bottom dielectric layer and part of the P-type doped layer starting from the top dielectric layer in a direction pointing to the bottom of the original substrate to form a third trench interconnected with the second trench.

[0023] Preferably, the step S4 further comprises: performing an epitaxial process using the N-type doped semiconductor material to fill the third trench, so as to form an external N-type doped layer electrically contacting the N-type doped layer.

[0024] Preferably, in the step S4, an N-type doped semiconductor material is used to perform an epitaxial process to fill the second trench and the third trench.

[0025] Preferably, after the step S4 is completed, the following steps are performed: a portion of the top dielectric layer, a portion of the middle dielectric layer and a portion of the bottom dielectric layer are removed from the top dielectric layer near the N-type doping layer in a direction pointing to the bottom of the original substrate by a patterning process until a portion of the surface of the P-type doping layer is exposed to form a fourth trench interconnected with the third trench; an ion implantation process is performed using an N-type doping material to form an N-type implanted doping layer embedded in the P-type doping layer and electrically contacting the external N-type doping layer, and the doping concentration of the N-type implanted doping layer is controlled to be higher than the doping concentration of either the N-type doping layer or the external N-type doping layer.

[0026] Preferably, after the step S4 is executed, the following steps are performed: removing part of the top dielectric layer, part of the middle dielectric layer and part of the bottom dielectric layer from the top dielectric layer along the direction toward the bottom of the original substrate through a graphic process until a portion of the surface of the P-type doped layer is exposed; performing an ion implantation process using a P-type doping material to form a P-type injection doping layer embedded in the P-type doping layer, and controlling the doping concentration of the P-type injection doping layer to be higher than the doping concentration of the P-type doping layer.

[0027] Preferably, in step S1, the temperature of the low-temperature epitaxial process is controlled to be 300-600 degrees Celsius, and the temperature of the laser annealing process is controlled to be 500-1000 degrees Celsius.

[0028] Preferably, in step S2, the temperature of the high temperature epitaxial process is controlled to be 400-1000 degrees Celsius. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A top view of a semiconductor device according to an embodiment of the present invention;

[0030] Figure 2 For along Figure 1 The cross-sectional view in the AA direction is shown;

[0031] Figure 3 For along Figure 1 The cross-sectional view along the BB direction is shown;

[0032] Figure 4 is a schematic structural diagram of an initial substrate according to an embodiment of the present invention;

[0033] Figure 5 For Figure 4 A schematic diagram of a structure obtained by removing part of the dielectric layer based on the structure shown;

[0034] Figure 6 For Figure 5 A schematic diagram of a structure obtained after epitaxy of the first intrinsic semiconductor layer based on the structure shown;

[0035] Figure 7 For Figure 6 A schematic diagram of a structure obtained after epitaxy of a second intrinsic semiconductor layer based on the structure shown;

[0036] Figure 8 For Figure 7 A schematic diagram of the structure obtained after depositing a second dielectric layer on the basis of the structure shown;

[0037] Fig. 9 For Figure 8 A top view of a structure obtained by removing a portion of the dielectric layer and a portion of the intrinsic semiconductor layer based on the structure shown;

[0038] Fig.10 For along Fig. 9 A cross-sectional view in the AA direction is shown;

[0039] Fig.11 For Fig.10 A schematic diagram of a structure obtained by depositing an N-type doped layer on the structure shown and removing part of the dielectric layer;

[0040] Fig.12 For along Fig.11A cross-sectional view along the AA direction is shown. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0042] The embodiment of the present invention provides a novel semiconductor device and a method for manufacturing the same, so as to improve work efficiency.

[0043] Reference Figures 1 to 3 , Figures 1 to 3 The semiconductor device shown includes a substrate 1 , a dielectric layer 2 , an intrinsic semiconductor layer 3 and an N-type doped layer 4 .

[0044] In some embodiments, reference Figure 2 The substrate 1 includes a buried oxide layer 11 and a P-type doped layer 12 located on the top and including a first semiconductor material.

[0045] In some embodiments, the substrate 1 further comprises a silicon substrate, and the buried oxide layer 11 and the P-type doping layer 12 are sequentially stacked on the silicon substrate to form an SOI substrate.

[0046] In some embodiments, the first semiconductor material included in the P-type doped layer 12 is silicon. The P-type doped layer 12 is a P-type doped silicon substrate.

[0047] In some embodiments, reference Figure 2 The dielectric layer 2 is stacked on the top surface of the P-type doped layer 12 .

[0048] In some embodiments, reference Figure 2 The dielectric layer 2 includes a bottom dielectric layer 21, a middle dielectric layer 22 and a top dielectric layer 23 which are stacked in sequence.

[0049] In some embodiments, the bottom dielectric layer 21 is made of silicon oxide.

[0050] In some embodiments, the middle dielectric layer 22 is made of silicon nitride or amorphous silicon.

[0051] In some embodiments, the top dielectric layer 23 is made of silicon oxide.

[0052] In some embodiments, reference Figure 2 , a part of the intrinsic semiconductor layer 3 is disposed in the P-type doped layer 12, and another part is disposed in the dielectric layer 2. The intrinsic semiconductor layer 3 comprises a second semiconductor material different from the first semiconductor material, and the N-type doped layer 4 is embedded on the top of the intrinsic semiconductor layer 3, which reduces the transition time from the P-type doped layer 12 to the N-type doped layer 4, and can effectively improve the working efficiency.

[0053] In some embodiments, the second semiconductor material included in the intrinsic semiconductor layer 3 is germanium.

[0054] In some embodiments, the intrinsic semiconductor layer 3 is made of germanium.

[0055] In some embodiments, the N-type doped layer 4 includes a third semiconductor material having the same composition as the first semiconductor material, or having the same composition as the second semiconductor material.

[0056] In some embodiments, the N-type doped layer 4 is made of N-type doped silicon.

[0057] In some embodiments, the N-type doped layer 4 is made of N-type doped germanium.

[0058] In some embodiments, reference Figures 1 to 3 , Figures 1 to 3 The semiconductor device shown also includes an N-type injection doping layer 7 arranged in the P-type doping layer 12, and an external N-type doping layer 41 arranged on the substrate 1 and electrically contacting the N-type injection doping layer 7 and the N-type doping layer 4 respectively, so as to facilitate the output of electrical signals from the semiconductor device to the outside.

[0059] In some embodiments, reference Figure 3 The external N-type doping layer 41 penetrates the dielectric layer 2 and is embedded in the P-type doping layer 12 to achieve electrical contact with the P-type doping layer 12 .

[0060] In some embodiments, the doping concentration of the N-type implanted doping layer 7 is higher than the doping concentration of any one of the N-type doping layer 4 and the external N-type doping layer 41 .

[0061] In some embodiments, the semiconductor device further includes a P-type implantation doping layer to facilitate the output of electrical signals from the semiconductor device. Figure 1 and Figure 2 , Figure 1The semiconductor device shown further includes a first P-type implant doping layer 5 and a second P-type implant doping layer 6 disposed within the P-type doping layer 12 .

[0062] In some embodiments, the number and specific locations of the P-type implanted doping layers are flexibly adjusted according to process requirements.

[0063] In some embodiments, the doping concentration of the P-type implanted doping layer is higher than the doping concentration of the P-type doping layer 12 .

[0064] In some embodiments, reference Figure 2 , the top surface of the N-type doped layer 4 is higher than the top surface of the dielectric layer 2 .

[0065] In some embodiments, reference Figure 3 The N-type doped layer 4 forms a PN junction with the P-type doped layer 12 in contact therewith, and the N-type doped layer 7 forms another PN junction with the P-type doped layer 12 in contact therewith. The two PN junctions are connected, which is beneficial to reducing the carrier transit time, thereby increasing the operating frequency.

[0066] In some embodiments, two connected PN junction structures are formed, and the thickness of the non-doped region Ge is relatively small.

[0067] In some embodiments, the thickness of the Ge layer required to be passed from P-type Si to N-type Si is substantially equal.

[0068] The embodiment of the present invention further provides a method for manufacturing the semiconductor device, comprising steps S0 to S4.

[0069] In the step S0 of some embodiments, referring to Figure 4 and Figure 5 , Figure 5 The original substrate shown is composed of Figure 4 The initial substrate shown is processed. Figure 4 The initial substrate shown includes the buried oxide layer 11 and the P-type doping layer 12 stacked in sequence, and the bottom dielectric layer 21 and the middle dielectric layer 22 are stacked in sequence on the P-type doping layer 12. After etching away a portion of the middle dielectric layer 22, a portion of the bottom dielectric layer 21, and a portion of the P-type doping layer 12 from the middle dielectric layer 22 in a direction toward the buried oxide layer 11, a first trench 91 penetrating the middle dielectric layer 22 and the bottom dielectric layer 21 is formed.

[0070] In step S1 of some embodiments, referring to Figure 5 and Figure 6, a low-temperature epitaxial process is performed using the second semiconductor material to form a first intrinsic semiconductor layer 30 covering the inner wall of the first groove 91, and a laser annealing process is performed on the first intrinsic semiconductor layer 30. Since the lattice constants of the first semiconductor material in the P-type doped layer 12 and the second semiconductor material in the first intrinsic semiconductor layer 30 are not matched, the first intrinsic semiconductor layer 30 is formed by controlling the low-temperature epitaxial process, so that the growth rate of the first intrinsic semiconductor layer 30 can be slowed down to avoid the first semiconductor material in the P-type doped layer 12 from diffusing into the second semiconductor material of the first intrinsic semiconductor layer 30 as much as possible. In combination with the laser annealing process performed on the surface of the first intrinsic semiconductor layer 30, the defects that may exist in the first intrinsic semiconductor layer 30 can be repaired and improved, and the first semiconductor material can be prevented from diffusing from the interface to reduce the surface roughness, thereby improving the working efficiency of the semiconductor device.

[0071] In step S1 of some embodiments, the temperature of the low temperature epitaxy process is controlled to be 300-600 degrees Celsius, and the temperature of the laser annealing process is controlled to be 500-1000 degrees Celsius. The specific operation steps of the low temperature epitaxy process and the laser annealing process are conventional technical means for those skilled in the art.

[0072] In step S2 of some embodiments, referring to Figures 5 to 7 A high-temperature epitaxial process is performed using the second semiconductor material to form a second intrinsic semiconductor layer (not shown in the figure) covering the surface of the first intrinsic semiconductor layer 30 and filling the first trench 91. The second intrinsic semiconductor layer (not shown in the figure) and the first intrinsic semiconductor layer 30 constitute the intrinsic semiconductor layer 3.

[0073] In step S2 of some embodiments, referring to Figure 5 and Figure 7 , controlling the high temperature epitaxial growth process of the second intrinsic semiconductor layer (not shown in the figure) so that the formed intrinsic semiconductor layer 3 fills the first trench 91 , and the top surface of the intrinsic semiconductor layer 3 is higher than the top surface of the intermediate dielectric layer 22 .

[0074] In step S2 of some embodiments, the temperature of the high temperature epitaxial process is controlled to be 400-1000 degrees Celsius. The specific operation steps of the high temperature epitaxial process are conventional technical means for those skilled in the art.

[0075] In step S3 of some embodiments, referring to Figures 8 to 10After using dielectric material to deposit and form a top dielectric layer 23 covering the top surface of the middle dielectric layer 22 and the top surface of the intrinsic semiconductor layer 3, a portion of the top dielectric layer 23 and a portion of the intrinsic semiconductor layer 3 are removed from the top dielectric layer 23 in a direction pointing to the P-type doped layer 12 until a portion of the surface of the intrinsic semiconductor layer 3 is exposed and a second trench 92 is formed.

[0076] In step S4 of some embodiments, referring to Figures 10 to 12 , an N-type doped semiconductor material is used for an epitaxial process to form an N-type doped layer 4 filling the second trench 92 .

[0077] In the step S4 of some embodiments, the formed N-type doped layer 4 is controlled to have a top surface higher than the top dielectric layer 23 in addition to being embedded in the intrinsic semiconductor layer 3 .

[0078] In step S3 of some embodiments, referring to Figures 8 to 10 Preferably, the step S3 also includes removing a portion of the top dielectric layer 23, a portion of the middle dielectric layer 22, a portion of the bottom dielectric layer 21 and a portion of the P-type doped layer 12 from the top dielectric layer 23 in a direction pointing toward the bottom of the original substrate (not shown in the figure) to form a third trench 93 interconnected with the second trench 92.

[0079] In step S3 of some embodiments, in the process of removing a portion of the top dielectric layer 23 and a portion of the intrinsic semiconductor layer 3 along the direction pointing to the P-type doped layer 12 starting from the top dielectric layer 23 to form the second trench 92, a portion of the middle dielectric layer 22, a portion of the bottom dielectric layer 21 and a portion of the P-type doped layer 12 close to the intrinsic semiconductor layer 3 are also synchronously removed to form the third trench 93.

[0080] In step S4 of some embodiments, after the second trench 92 is filled with an N-type doped semiconductor material by an epitaxial process to form the N-type doped layer 4, the third trench 93 is filled with an N-type doped semiconductor material by an epitaxial process to form the external N-type doped layer 41 electrically contacting the N-type doped layer 4.

[0081] In the step S4 of some embodiments, the second trench 92 and the third trench 93 are simultaneously filled during the epitaxial process using N-type doped semiconductor material to form the external N-type doped layer 41 and the N-type doped layer 4 that are in electrical contact with each other.

[0082] After the step S4 of some embodiments is completed, refer to Figure 1 , Figure 2 , Fig. 9 , Fig.11 and Fig.12 , perform the following steps:

[0083] S5: removing part of the top dielectric layer 23, part of the middle dielectric layer 22 and part of the bottom dielectric layer 21 from the top dielectric layer 23 near the N-type doped layer 4 in a direction pointing to the bottom of the original substrate (not shown in the figure) through a patterning process until a part of the surface of the P-type doped layer 12 is exposed, so as to form a fourth trench (not shown in the figure) communicating with the third trench 93;

[0084] S6: Performing an ion implantation process using an N-type doping material to form an N-type implanted doping layer 7 embedded in the P-type doping layer 12 and electrically contacting the external N-type doping layer 41 through the fourth groove (not shown in the figure), and controlling the doping concentration of the N-type implanted doping layer 7 to be higher than the doping concentration of either the N-type doping layer 4 or the external N-type doping layer 41.

[0085] After the step S4 of some embodiments is completed, refer to Figure 1 , Figure 2 , Fig.11 and Fig.12 , perform the following steps:

[0086] S7: removing a portion of the top dielectric layer 23 , a portion of the middle dielectric layer 22 , and a portion of the bottom dielectric layer 21 from the top dielectric layer 23 along a direction toward the bottom of the original substrate (not shown) by a patterning process until a portion of the surface of the P-type doped layer 12 is exposed, thereby forming a fifth trench 94 ;

[0087] S8: Perform an ion implantation process using a P-type doping material to form the first P-type implantation doping layer 5 and the second P-type implantation doping layer 6 embedded in the P-type doping layer 12 through the fifth groove 94, and control the doping concentration of either the first P-type implantation doping layer 5 or the second P-type implantation doping layer 6 to be higher than the doping concentration of the P-type doping layer 12.

[0088] In some embodiments, after the execution of steps S5 to S8, after the dielectric material is deposited on the top surface of the obtained structure, the region where the P-type injection doping layer and the N-type injection doping layer are located is graphically opened to expose at least part of the surface of the P-type injection doping layer and the N-type injection doping layer, and then a conductive material is deposited to form different conductive layers that can be electrically contacted with the P-type injection doping layer and the N-type injection doping layer. After the conductive layer is prepared, the signal is led out through a back-end interconnection process.

[0089] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A semiconductor device, characterized in that: include: A substrate, including a P-type doped layer located on top of the substrate and comprising a first semiconductor material; A dielectric layer, stacked and arranged on the top surface of the P-type doped layer; An intrinsic semiconductor layer, comprising a second semiconductor material different from the first semiconductor material, and having a portion disposed in the P-type doped layer and another portion disposed in a first trench in the dielectric layer; The intrinsic semiconductor layer comprises a first intrinsic semiconductor layer formed by low-temperature epitaxy and laser annealing using the second semiconductor material and covering the inner wall of the first trench, and a second intrinsic semiconductor layer formed by high-temperature epitaxy using the second semiconductor material and covering the surface of the first intrinsic semiconductor layer and filling the first trench, the first intrinsic semiconductor layer and the second intrinsic semiconductor layer constitute the intrinsic semiconductor layer, wherein the first semiconductor material included in the P-type doped layer is silicon, the second semiconductor material included in the intrinsic semiconductor layer is germanium, and the laser annealing acts on the surface of the first intrinsic semiconductor layer; The N-type doped layer is embedded on the top of the intrinsic semiconductor layer.

2. The semiconductor device according to claim 1, wherein: It also includes an N-type injection doping layer arranged in the P-type doping layer, and an external N-type doping layer arranged in the substrate and electrically contacting the N-type injection doping layer and the N-type doping layer respectively, and the doping concentration of the N-type injection doping layer is higher than the doping concentration of any one of the N-type doping layer and the external N-type doping layer.

3. The semiconductor device according to claim 1, wherein: It also includes a P-type injection doping layer disposed in the P-type doping layer, and the doping concentration of the P-type injection doping layer is higher than the doping concentration of the P-type doping layer.

4. The semiconductor device according to claim 1, wherein: The N-type doped layer includes a third semiconductor material having the same composition as the first semiconductor material or the same composition as the second semiconductor material.

5. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: S0: providing an original substrate, wherein the original substrate comprises a P-type doped layer located at the top and comprising a first semiconductor material, a bottom dielectric layer and an intermediate dielectric layer stacked in sequence on the P-type doped layer, and a first trench penetrating the bottom dielectric layer, the intermediate dielectric layer and a portion of the P-type doped layer; S1: performing a low-temperature epitaxial process using a second semiconductor material different from the first semiconductor material to form a first intrinsic semiconductor layer covering the inner wall of the first trench, and performing a laser annealing process on the surface of the first intrinsic semiconductor layer; S2: performing a high temperature epitaxial process using the second semiconductor material to form a second intrinsic semiconductor layer covering the surface of the first intrinsic semiconductor layer and filling the first trench, wherein the first intrinsic semiconductor layer and the second intrinsic semiconductor layer constitute an intrinsic semiconductor layer, wherein the first semiconductor material included in the P-type doped layer is silicon, and the second semiconductor material included in the intrinsic semiconductor layer is germanium; S3: after depositing a dielectric material to form a top dielectric layer covering the top surface of the structure obtained in step S2, a portion of the top dielectric layer and a portion of the intrinsic semiconductor layer are removed from the top dielectric layer in a direction pointing to the bottom of the original substrate until a portion of the surface of the intrinsic semiconductor layer is exposed and a second trench is formed; S4: performing an epitaxial process using an N-type doped semiconductor material to form an N-type doped layer filling the second trench.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The step S3 also includes removing part of the top dielectric layer, part of the middle dielectric layer, part of the bottom dielectric layer and part of the P-type doped layer from the top dielectric layer in a direction pointing to the bottom of the original substrate to form a third trench interconnected with the second trench.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The step S4 further includes performing an epitaxial process using the N-type doped semiconductor material to fill the third trench and form an external N-type doped layer electrically contacting the N-type doped layer.

8. The method for manufacturing a semiconductor device according to claim 6, wherein: In the step S4, an N-type doped semiconductor material is used to perform an epitaxial process to fill the second trench and the third trench.

9. The method for manufacturing a semiconductor device according to claim 7, wherein: After step S4 is completed, the following steps are performed: Removing part of the top dielectric layer, part of the middle dielectric layer and part of the bottom dielectric layer from the top dielectric layer near the N-type doped layer in a direction pointing to the bottom of the original substrate by a patterning process until a portion of the surface of the P-type doped layer is exposed, so as to form a fourth trench interconnected with the third trench; An ion implantation process is performed using an N-type doping material to form an N-type implanted doping layer embedded in the P-type doping layer and electrically contacting the external N-type doping layer, and the doping concentration of the N-type implanted doping layer is controlled to be higher than the doping concentration of either the N-type doping layer or the external N-type doping layer.

10. The method for manufacturing a semiconductor device according to claim 5, wherein: After step S4 is completed, the following steps are performed: Removing part of the top dielectric layer, part of the middle dielectric layer and part of the bottom dielectric layer from the top dielectric layer in a direction toward the bottom of the original substrate by a patterning process until a part of the surface of the P-type doped layer is exposed; An ion implantation process is performed using a P-type doping material to form a P-type implantation doping layer embedded in the P-type doping layer, and the doping concentration of the P-type implantation doping layer is controlled to be higher than the doping concentration of the P-type doping layer.

11. The method for manufacturing a semiconductor device according to claim 5, wherein: In the step S1, the temperature of the low-temperature epitaxial process is controlled to be 300-600 degrees Celsius, and the temperature of the laser annealing process is controlled to be 500-1000 degrees Celsius. In the step S2, the temperature of the high-temperature epitaxial process is controlled to be 400-1000 degrees Celsius.

Images