A method for processing wireless signals in UWB positioning

Abstract

The present invention discloses a method for processing wireless signals in UWB positioning, which adopts modular software radio design, selects functional modules and parameters and system modes through a post-processor, and communicates with an IF circuit and then with a radio frequency (RF) circuit through an IF digital interface, thereby forming a complete signal transceiver system. The signal transceiver system adopts an implementation architecture with variable systems and variable parameters within the system. The variable systems include variable OFDM and SC‑FDE, and variable parameters within the system, namely variable subcarrier parameters, variable channel fading countermeasure processing, and variable modulation FEC error correction. The present invention solves the problem of inaccurate or poor regional positioning in the prior art.

Description

Technical Field

[0001] The invention belongs to the technical field of regional positioning, and in particular relates to a method for processing wireless signals in UWB positioning. Background Art

[0002] The environment for regional positioning is relatively complex, and accurate position calibration of the positioning equipment is required. Multipath effects and obstacles have a great impact on positioning accuracy. To improve such problems, professional technicians are required to combine site drawings and rely on deployment experience to complete installation and deployment. Usually, more manpower and material resources are spent, and because the actual deployment depends heavily on the experience of technicians, there will be problems such as inaccurate positioning or poor results in some areas. Summary of the invention

[0003] The purpose of the present invention is to provide a method for processing wireless signals in UWB positioning, which solves the problem of inaccurate or poor regional positioning in the prior art.

[0004] The technical solution adopted by the present invention is a method for processing wireless signals in UWB positioning, which adopts modular software radio design, selects functional modules and parameters and system modes through a post-processor, and communicates with the IF circuit and then with the radio frequency RF circuit through an IF digital interface, thereby forming a complete signal transceiver system.

[0005] The present invention is also characterized in that:

[0006] The signal transceiver system adopts an implementation architecture with variable system and variable parameters within the system. The variable system means that OFDM and SC-FDE are variable, and the variable parameters within the system means that subcarrier parameters, channel fading countermeasure processing, and modulation FEC error correction are variable.

[0007] The signal transceiver system is divided into four parts: digital interface and digital frequency conversion UDC / DDC logic, Tx / Rx channel preprocessing and clock distribution logic, digital PHY component logic, and data interface and post-processing logic. The digital PHY component logic is the core, and the other three parts are system-wide designs.

[0008] The digital PHY component logic includes two major logical parts: the orthogonal frequency division multiplexing physical layer OFDM PHY and the single carrier frequency domain equalization physical layer SC-FDE PHY. The two share some basic algorithm modules and functional logic modules.

[0009] The OFDM system is used as the main mode, and a parameterized, modular and configurable design concept is adopted. Single carrier frequency domain equalization SC-FDE is taken into consideration as a supplement and forward compatibility for the communication system in high-speed and high-frequency mobile communication channel environments. It shares multiple module designs with the OFDM PHY physical layer, serving as an effective supplement to the OFDM PHY physical layer.

[0010] The physical layer frame structure adopts a multi-layer frame structure of superframe / multiframe / transmission frame, where a superframe refers to an uplink / downlink transmission cycle, consisting of an uplink multiframe, a downlink multiframe, and two protection intervals located between the uplink / downlink multiframes, and adopts an uplink and downlink configurable superframe structure, where the protection interval G0 is used to protect the transmission delay between the uplink and downlink;

[0011] A multiframe is a composite of multiple uplink or downlink transmission frames. The number of transmission frames in a multiframe is variable, so the period of the superframe is variable, depending on the data rate and QoS requirements of the source. The SIGNAL field of the first transmission frame in each multiframe carries multiframe control information, including the number of transmission frames in the multiframe, so that the receiving end knows when reception ends and transmission begins.

[0012] A transmission frame is the basic unit of physical layer transmission and contains all the information required for an independent and complete one-way transmission.

[0013] The state machine FSM for the working state transfer of the digital PHY component logic overall circuit is specifically as follows: the master station circuit immediately enters the sending state after the reset is completed, and is periodically transferred between the sending state and the receiving state by the stimulation of the timer. The slave station immediately enters the receiving state after the reset is completed, and the transfer from the receiving state to the sending state is stimulated by the received uplink multiframe, and the transfer from the sending state to the receiving state is controlled by the timer.

[0014] A flattened implementation method is adopted in the physical layer Tx circuit, that is, all main submodules are controlled by the transmitting state machine FSM_TX, and the logical relationship between each submodule is controlled by the transceiver state machine. The state machine is described as follows: After the system is powered on and RESET is executed, the master station TX circuit is in the data sending state, and it is controlled to change to the receiving state after sending the uplink multiframe; it changes to the sending state after receiving the new superframe, and the slave station TX circuit is in the data receiving state, and it changes to the sending state after receiving the uplink multiframe, and it changes to the receiving state after the data transmission is completed. The corresponding circuit working timing is designed as: rising edge is valid, equal length frame, three TRAIN bits, the last SINGLE bit is used as the beginning of the data segment, the data field is sent and received, and the trailing sample point is used as the frame end bit.

[0015] The Rx circuit consists of a MATCH_FILT matched filter module, a packet detection module FRM_DET, a coarse frame synchronization module FRM_SYNC0, a fine frame synchronization module FRM_SYNC1, a channel estimation module CH_EST, a frequency domain equalization module FDE, a SIGNAL domain demodulation module SIG_RET and a DATA domain demodulation module DAT_RET. According to the two working modes of OFDM and SC-FDE, each module has two parameter configuration states.

[0016] The beneficial effects of the present invention are to improve the anti-interference capability and the identification of interference signals, thereby enhancing the overall positioning effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is the overall framework;

[0018] Figure 2 is a block diagram of the digital PHY circuit system;

[0019] Figure 3 It is a diagram of the physical layer frame structure;

[0020] Figure 4 It is the state transition diagram of the send and receive FSM;

[0021] Figure 5 It is Tx circuit design;

[0022] Figure 6 It is the Tx circuit timing design;

[0023] Figure 7 It is the Rx logical architecture design. DETAILED DESCRIPTION

[0024] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] The present invention discloses a method for processing wireless signals in UWB positioning, which improves anti-interference capability and identification of interference signals, and can reduce dependence on technicians' experience and improve overall positioning effect.

[0026] The overall design adopts a modular software radio design solution, that is, it realizes the main baseband digital PHY (physical layer) functions, provides optional functional modules or parameters, selects functional modules and their parameters and system modes through the post-processor, and connects with the IF circuit and then the RF (radio frequency) circuit through the IF digital interface, thus forming a complete signal transceiver system.

[0027] In response to various channel environments and various rates, communication distances and other application requirements, a variable system (variable OFDM and SC-FDE) and variable parameters within the system (variable subcarrier parameters, variable channel fading countermeasure processing, variable modulation FEC error correction, etc.) are adopted. Its overall framework is as follows Figure 1 As shown:

[0028] The entire system can be divided into four parts: "digital interface and digital frequency conversion UDC / DDC" logic, "Tx / Rx channel preprocessing and clock distribution" logic, "digital PHY component" logic and "data interface and post-processing" logic. The core part is the digital PHY component logic, and the other three parts are system-wide designs using mature technical architecture.

[0029] The "Digital PHY Component" logic is introduced below.

[0030] (1) Overall solution of digital PHY module

[0031] The digital PHY logic component includes two major logic parts: the orthogonal frequency division multiplexing physical layer OFDM PHY and the single carrier frequency domain equalization physical layer SC-FDE PHY. The two share some basic algorithm modules and functional logic modules. Figure 2 shown.

[0032] The Orthogonal Frequency Division Multiplexing (OFDM) system is used as the main mode, and a parameterized, modular, and configurable design concept is adopted.

[0033] Single carrier frequency domain equalization SC-FDE is taken into consideration as a supplement and forward compatibility for the communication system in the channel environment of high-speed and high-frequency mobile communication (high Doppler, weak multipath). It can share multiple module designs with OFDM PHY as an effective supplement to OFDM PHY.

[0034] (2) Digital PHY air interface design (frame structure)

[0035] According to the analysis of the project design objectives and application environment, the physical layer frame structure adopts a multi-layer frame structure of superframe / multiframe / transmission frame, such as Figure 3 shown.

[0036] The superframe in the physical layer refers to an uplink / downlink transmission cycle. It consists of an uplink multiframe, a downlink multiframe, and two protection intervals located between the uplink / downlink multiframes, and adopts an uplink and downlink configurable superframe structure. The protection interval G0 is used to protect the transmission delay between the uplink and downlink.

[0037] A multiframe is a composite of multiple uplink or downlink transmission frames. The number of transmission frames in a multiframe is variable, so the period of the superframe is variable and can be changed according to the data rate requirements and QoS requirements of the source. The SIGNAL field of the first transmission frame in each multiframe carries multiframe control information (such as the number of transmission frames in the multiframe, so that the receiving end knows when reception ends and transmission begins, etc.).

[0038] A transmission frame is the basic unit of physical layer transmission and contains all the information required for an independent and complete one-way transmission.

[0039] (3) Digital PHY circuit operation design

[0040] The FSM (state machine) state transition of the digital PHY overall circuit working state transition is as follows Figure 4 The example shown.

[0041] As can be seen from the figure, the master circuit enters the sending state immediately after the reset, and is periodically transferred between the sending state and the receiving state by the timer. The slave enters the receiving state immediately after the reset, and its transfer from the receiving state to the sending state is stimulated by the received uplink multiframe, and the transfer from the sending state to the receiving state is controlled by the timer.

[0042] (3.1) Tx circuit design

[0043] To simplify the circuit structure, a flattened implementation is adopted in the physical layer Tx circuit, that is, all major submodules are controlled by FSM_TX (transmit state machine). The logical relationship between each submodule is controlled by the transceiver state machine.

[0044] The state machine is described as follows: After the system is powered on and RESET is executed, the master station TX circuit is in the data transmission state, and after the slave sends the "uplink multiframe", it switches to the receiving state; after receiving the "new superframe", it switches to the transmission state. The slave station TX circuit is in the data reception state, and after receiving the "uplink multiframe", it switches to the transmission state, and after the data transmission is completed, it switches to the receiving state. Figure 5 shown.

[0045] Figure 6 Design the working timing of the corresponding circuit.

[0046] The rising edge is valid, equal length frame, three TRAIN bits, and the following SINGLE bit is used as the start of the data segment, the data field is sent and received, and the trailing sample point is used as the end bit of the frame.

[0047] 3.2) Rx circuit design

[0048] The Rx circuit consists of a matched filter module (MATCH_FILT), a packet detection module (FRM_DET), a frame coarse synchronization module (FRM_SYNC0), a frame fine synchronization module (FRM_SYNC1), a channel estimation module (CH_EST), a frequency domain equalization module (FDE), a SIGNAL domain demodulation module (SIG_RET) and a DATA domain demodulation module (DAT_RET). According to the two working modes of OFDM and SC-FDE, each module has two parameter configuration states. The overall logic architecture design of Rx is as follows: Figure 7 shown.

[0049] In summary, UWB wireless signals automatically switch between OFDM and SC-FDE according to different environments (multiple obstructions or severe multipath), and the signal interference can be effectively eliminated by using the signal modulation and processing characteristics of OFDM and SC-FDE. The delay and response design of the frame structure can be used to accurately calibrate the location of the area in a complex environment.

Claims

1. A method for processing wireless signals in UWB positioning, characterized in that: A modular software radio design is adopted. Functional modules, parameters and system modes are selected through the post-processor. The IF digital interface is used to connect with the IF circuit and then the RF circuit to form a complete signal transceiver system. The signal transceiver system adopts a variable system and variable parameters within the system implementation architecture. The variable system means that OFDM and SC-FDE are variable. The variable parameters within the system means that the subcarrier parameters, channel fading countermeasure processing and modulation FEC error correction are variable. The signal transceiver system is divided into four parts: digital interface and digital frequency conversion UDC / DDC logic, Tx / Rx channel preprocessing and clock distribution logic, digital PHY component logic and data interface and post-processing logic. The digital PHY component logic is the core, and the other three parts are system-wide designs. The digital PHY component logic includes orthogonal frequency division multiplexing physical layer OFDM PHY and single carrier frequency domain equalization physical layer SC-FDE PHY has two major logical parts, and the two share some basic algorithm modules and functional logic modules; the orthogonal frequency division multiplexing OFDM system is used as the main mode, and a parameterized modular configurable design concept is adopted. Single carrier frequency domain equalization SC-FDE is taken into consideration as a supplement and forward compatibility for the communication system in the high-speed and high-frequency mobile communication channel environment. It shares multiple module designs with the orthogonal frequency division multiplexing physical layer OFDM PHY. As an effective supplementary solution for the orthogonal frequency division multiplexing physical layer OFDM PHY, the physical layer frame structure adopts a multi-layer frame structure of superframe / multiframe / transmission frame, where a superframe refers to an uplink / downlink transmission cycle, which consists of an uplink multiframe, a downlink multiframe, and two protection intervals located between the uplink / downlink multiframes respectively, and adopts an uplink and downlink configurable superframe structure, where the protection interval G0 is used to protect the transmission delay between uplink and downlink; A multiframe is a composite of multiple uplink or downlink transmission frames. The number of transmission frames in a multiframe is variable, so the period of the superframe is variable, depending on the data rate and QoS requirements of the source. The SIGNAL field of the first transmission frame in each multiframe carries multiframe control information, including the number of transmission frames in the multiframe, so that the receiving end knows when reception ends and transmission begins. The transmission frame is the basic unit of physical layer transmission, which contains all the information required for an independent and complete one-way transmission. The state machine FSM for the working state transition of the digital PHY component logic overall circuit is specifically as follows: the master station circuit immediately enters the sending state after the reset is completed, and is periodically transferred between the sending state and the receiving state by the timer stimulation; the slave station immediately enters the receiving state after the reset is completed, and the transfer from the receiving state to the sending state is stimulated by the received uplink multiframe, and the transfer from the sending state to the receiving state is controlled by the timer; The physical layer Tx circuit adopts a flattened implementation method, that is, all major submodules are controlled by the transmission state machine FSM_TX, and the logical relationship between each submodule is controlled by the transceiver state machine. The state machine is described as follows: After the system is powered on and RESET is executed, the master station TX circuit is in the data transmission state, and it is controlled to change to the receiving state after sending the uplink multiframe; it changes to the transmission state after receiving the new superframe, and the slave station TX circuit is in the data reception state, and it changes to the transmission state after receiving the uplink multiframe, and it changes to the receiving state after the data transmission is completed. The corresponding circuit working timing is designed as: rising edge is valid, equal length frame, three TRAIN bits, the last SINGLE bit is used as the beginning of the data segment, the data field is sent and received, and the trailing sample point is used as the frame end bit; The Rx circuit consists of a MATCH_FILT matched filter module, a packet detection module FRM_DET, a coarse frame synchronization module FRM_SYNC0, a fine frame synchronization module FRM_SYNC1, a channel estimation module CH_EST, a frequency domain equalization module FDE, a SIGNAL domain demodulation module SIG_RET and a DATA domain demodulation module DAT_RET. According to the two working modes of OFDM and SC-FDE, each module has two parameter configuration states.

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