Integrated circuit automatic layout plan generation method and device and example construction method

Abstract

The invention provides an integrated circuit automatic layout planning generation method and device and a construction example method, which are applied to the technical field of integrated circuit design automation and chip layout planning, and are characterized in that top layer pins are created in a specified area, a same-name netlist is generated, and meanwhile, creation parameters of the pins such as name prefixes, the number and distribution areas are set; according to the method, the design accuracy and traceability are ensured, then, the netlist units are automatically constructed and the netlist connection is created based on the defined hierarchical structure and the data flow, so that human errors are effectively reduced, accurate connection between circuit elements is ensured, the design consistency and reliability are improved, required examples can be efficiently constructed, and the design efficiency is improved. According to the method, the complex test function scene is met, the test and verification process is accelerated, the performance of different layout configurations is rapidly evaluated, the optimal layout scheme can be found, and therefore the design performance and efficiency are improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design automation and chip layout planning, and in particular to an integrated circuit automated layout planning generation method, device and construction example method. Background Art

[0002] Layout planning is a crucial part of integrated circuit (IC) design[1]. It determines the specific location of each circuit module on the chip and has a direct impact on the chip's performance, power consumption, area, and manufacturing cost. In the layout planning stage, it is necessary to determine the basic physical structure of the chip based on the read-in design netlist and process information, including the location of each major functional module on the chip, and verify whether the layout is legal and meets the manufacturing process requirements. The traditional verification method is to import existing examples to test the corresponding scenarios to determine whether the corresponding functions are met.

[0003] However, most of the existing traditional examples are derived from industrial examples or based on open source projects. Current internal examples cannot meet all test scenarios of complex functions. Although existing electronic design automation (EDA) layout planning tools provide automated layout planning functions, they lack sufficient flexibility, resulting in inconsistent design results and suboptimal solutions. In addition, constructing real examples is a complex and multi-dimensional task that involves multiple levels of design and process parameters. It usually requires multiple rounds of iterations, which not only consumes a lot of computing resources and storage space, but also is time-consuming and labor-intensive [2].

[0004] Based on this, a new integrated circuit automatic layout planning generation method is needed.

[0005] References:

[0006] [1] Nie Tingyuan, Li Kunlong, Gao Jiuxu. Impact of layout planning constraints on VLSI design performance[J]. Microelectronics and Computers, 2016, 33(11): 104-108.

[0007] [2] Fu Ruihua. Research on automated methods for test case generation[D]. Sichuan: Sichuan University, 2022. Summary of the invention

[0008] In view of this, the embodiments of this specification provide an integrated circuit automatic layout planning generation method, device and construction example method, which are used to automatically generate macro cells (macro) and standard cells (cell) with netlist (net) connections during EDA layout planning, improve the efficiency and accuracy of integrated circuit design, shorten the design cycle, reduce costs, and provide a flexible tuning method. In addition, by automatically constructing examples, it is possible to efficiently construct the required examples, quickly evaluate the impact of different layout configurations on circuit performance, and achieve more optimized layout planning.

[0009] The embodiments of this specification provide the following technical solutions:

[0010] The embodiment of this specification provides a method for generating an automatic layout plan of an integrated circuit, comprising:

[0011] Creating top-level pins in a designated area to be planned for layout, and creating a corresponding netlist with the same name for each top-level pin, wherein the creation parameters of the top-level pins include: a name prefix, a required number, and a distribution area of ​​the pins;

[0012] Traverse each hierarchy according to the hierarchy list, and create macro cells and standard cells according to the area ratios of macro cells and standard cells preset in the current hierarchy;

[0013] According to the preset data flow between each top-level pin, the connection relationship between the macro cell and the standard cell is generated.

[0014] The embodiment of this specification also provides a method for automatically constructing an integrated circuit design example, comprising:

[0015] The integrated circuit automatic layout planning generation method described in any one of the above items is used for construction.

[0016] The embodiment of this specification also provides an integrated circuit automatic layout planning generation device, including:

[0017] A top-level pin creation module creates top-level pins in a designated area to be laid out and creates a corresponding netlist with the same name for each top-level pin, wherein the creation parameters of the top-level pins include: the name prefix, the required number and the distribution area of ​​the pins;

[0018] A macro cell and standard cell creation module, used for traversing each hierarchical structure according to the hierarchical structure list, and creating macro cells and standard cells according to the area ratios occupied by macro cells and standard cells preset in the current hierarchical structure;

[0019] The unit connection generation module is used to generate the connection relationship between the macro unit and the standard unit according to the preset data flow between each top-level pin.

[0020] Compared with the prior art, the at least one technical solution adopted in the embodiments of this specification can achieve the following beneficial effects:

[0021] By creating top-level pins in the specified area and generating a netlist with the same name, while setting pin creation parameters such as name prefix, quantity and distribution area, the accuracy and traceability of the design are ensured. Subsequently, netlist units are automatically constructed and netlist connections are created based on the defined hierarchy and data flow. This not only effectively reduces human errors and ensures accurate connections between circuit elements, improving the consistency and reliability of the design, but also can efficiently construct the required examples to meet complex test function scenarios, accelerate the testing and verification process, and quickly evaluate the performance of different layout configurations, which helps to find the optimal layout solution, thereby improving design performance and efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 It is the overall flow chart of the integrated circuit automatic layout planning generation method in this application;

[0024] Figure 2 It is a flow chart of constructing a netlist unit in this application;

[0025] Figure 3 It is a flow chart for creating a netlist connection in this application;

[0026] Figure 4 It is a flowchart of a single data flow connection diagram in this application. DETAILED DESCRIPTION

[0027] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0028] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0029] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0030] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0031] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0032] Floorplanning is a critical step in integrated circuit (IC) design, which directly affects the performance, power consumption, area and manufacturing cost of the chip. However, the electronic design automation (EDA) floorplanning tools on the market lack flexibility and efficiency when providing automated support in integrated circuit design, resulting in inconsistent design results and suboptimal solutions.

[0033] During the layout planning stage, verifying the legality of the layout and whether it meets the manufacturing process requirements is an essential step. Traditional verification methods rely on importing existing industrial cases or open source cases for scenario testing to evaluate whether the functions meet expectations.

[0034] However, these traditional examples often cannot cover all complex functional test scenarios, and constructing real cases is a complex task involving multiple levels of design and process parameters. Not only do you need to create macrocell LEF files and DEF files that meet specific process nodes, you also need to write Verilog code to describe the behavior and structure of the circuit. Constructing an example usually requires multiple rounds of iterations, and each iteration may require adjustments to the LEF, Verilog or DEF files to solve problems in timing, power consumption, signal integrity, etc., which requires a lot of computing resources and storage space, and is very time-consuming and labor-intensive.

[0035] In view of this, the inventors discovered through research and improvement exploration that the existing methods lack sufficient flexibility in the automated layout planning process, are difficult to adapt to changes in different design needs and process requirements, and are inefficient when dealing with complex layout planning tasks, which not only prolongs the design cycle but also increases costs. In addition, due to the limitations of existing EDA layout planning tools, the design results are often not optimal, and when there are different design cases or different designers using the same tool, inconsistent design results are produced, further limiting the efficiency and quality of layout planning.

[0036] Based on this, the embodiments of this specification propose a method for generating an automated layout plan for an integrated circuit: the overall idea is to achieve automation and precision of the design process by controlling the layout of top-level pins, optimizing the creation of hierarchical units, and defining netlist connections based on data flow during the EDA layout planning process, thereby overcoming the problems of lack of flexibility, low efficiency, and inconsistent design results in the prior art, ensuring that the layout planning is optimal, and thus improving design performance and efficiency.

[0037] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0038] like Figure 1 As shown, the embodiment of this specification provides a method for generating an automatic layout plan of an integrated circuit, comprising:

[0039] Creating top-level pins in a designated area to be planned for layout, and creating a corresponding netlist with the same name for each top-level pin, wherein the creation parameters of the top-level pins include: a name prefix, a required number, and a distribution area of ​​the pins;

[0040] Traverse each hierarchy according to the hierarchy list, and create macro cells and standard cells according to the area ratios of macro cells and standard cells preset in the current hierarchy;

[0041] According to the preset data flow between each top-level pin, the connection relationship between the macro cell and the standard cell is generated.

[0042] Specifically, based on the initial floorplan, the creation parameters of the top pins are specified, including the pin name prefix, the required number, and their distribution area on the chip; based on the above creation parameters, top pins of the same size are evenly created in the specified area of ​​the initial Floorplan, and a net with the same name is automatically generated for each top pin. Among them, the position coordinates of the i-th pin are as shown in Formula 1 and Formula 2:

[0043]

[0044] where x i ,y i are the horizontal and vertical coordinates of the i-th pin, respectively, start x 、start y are the horizontal and vertical coordinates of the start and end of the specified distribution area respectively. x 、end y The horizontal and vertical coordinates of the end of the specified distribution area, num pin The number of pins that need to be created in this area.

[0045] Then, based on actual needs, define the total area percentage occupied by macros and standard cells in each hierarchy, traverse each hierarchy in turn, create macros according to the specified name prefix, length, width and quantity, and create a fixed number of pins for each macro. Initially, all pins can be placed on the left side of the macro. Secondly, create standard cells based on the remaining area of ​​the current layer.

[0046] Define the hierarchy and data flow, including the starting node (from node), the ending node (to node), and the scaling factor (weight) to calculate the number of paths.

[0047] Define the data flow between Top Pins, such as the starting node (from node), the ending node (to node), the expected number of paths and the number of pins, and generate the connection relationship of the unit according to the definition of the data flow.

[0048] At the same time, the maximum depth and minimum depth of the path are defined, and links are generated within the current layer for the remaining units that have no connection relationship, ensuring that the depth of each path is within the maximum and minimum depth range.

[0049] The present application can automatically construct netlist units and create netlist connections based on a defined hierarchy and data flow. This automated process effectively reduces errors, ensures accurate connections between circuit elements, and improves the consistency and reliability of the design.

[0050] In some embodiments, generating a connection relationship between the macro cell and the standard cell according to the preset data stream includes:

[0051] According to the type of data flow, the pin types of the starting node and the ending node are obtained;

[0052] Determining the number of paths of the internal connection paths of each data flow according to the type of the starting node;

[0053] According to the number of determined paths, in the first hierarchical structure and the second hierarchical structure, a start pin and an end pin are selected for each path respectively, and a path connecting the start pin and the end pin is constructed;

[0054] Repeat the process of selecting pins and building paths until all paths are built.

[0055] Specifically, after the netlist unit is constructed, the netlist connection needs to be created. The specific connection process is as follows: Figure 3 As shown, multiple data flows (DataFlow) between Top Pins are defined, including the starting node (from node), the ending node (to node), the expected number of paths and the number of pins passed; each DataFlow is traversed in turn, and the internal connection of a DataFlow (data flow) is as follows Figure 4 As shown:

[0056] Determine the pin types of the starting node (from node) and the ending node (to node) according to the type of data flow. For example, if the data flow type is macro to macro, the pins of the starting point and the ending point should both be macro pins. Determine the number of paths according to the starting point type.

[0057] According to the number of determined paths, in the first hierarchical structure and the second hierarchical structure, a start pin and an end pin are selected for each path respectively, and a path connecting the start pin and the end pin is constructed;

[0058] Repeat the process of selecting pins and building paths until all paths are built.

[0059] In some embodiments, when constructing a path connecting a start pin and an end pin, a pin is randomly selected from the pins in the first hierarchy as the start point of the path, and then other pins in the first hierarchy are connected until the number of connected pins reaches half of a preset number of pins, or there are no more pins in the first hierarchy that can be connected;

[0060] Next, go to the second level structure and continue to connect the pins in the second level structure until the total number of pins reaches the preset number of pins;

[0061] Finally, the output pin selected for the last time is connected to the termination pin selected in the second hierarchical structure to obtain a complete path.

[0062] Specifically, when constructing the first path, a pin in the first hierarchy (from node) is randomly selected as the starting point, and then the pins in the from node level are continuously connected. When the number of pins exceeds half of pinnum or there are no pins to choose from, the pins in the second hierarchy (to node level) are connected until the pin number reaches the specified number (in Figure 4 assuming the specified number is 4), connect the last selected output pin to one of the pins previously selected in the to node.

[0063] In some embodiments, after the first path is constructed, the remaining paths can be constructed in sequence according to the construction process of the path until their number reaches the number of paths previously specified by the user. It should be noted that the pins traversed by the previous path are no longer selectable in the current path.

[0064] In some embodiments, determining the number of paths of the internal connection paths of each data flow according to the type of the starting node includes:

[0065] If the type of the starting node is a hierarchical structure, the number of paths is the preset number of paths;

[0066] If the start node type is a top-level pin, the number of paths is the maximum number of pins in the first hierarchy.

[0067] Specifically, if the node is hierarchical, the number of paths is the number of paths previously defined by the user;

[0068] If the node is a top pin, the number of paths is the maximum number of top pins.

[0069] For example, in Figure 4Assume that the number of paths is 3. (Select pins). After the number of paths is determined, select the pins corresponding to the number of paths in the fromnode and to node. Figure 4 Indicated by filled circles.

[0070] In some embodiments, before creating top-level pins in a designated area to be floorplanned, an initial floorplan is created based on preset design parameters, wherein the design parameters include: basic unit, standard cell size, and chip shape.

[0071] Specifically, an initial floorplan is created based on the user-defined design unit (dbu per micro) and standard unit (site) size, as well as the die (single chip) shape.

[0072] In some embodiments, when creating a macro unit, the macro unit is created according to the area ratio of the macro unit preset at the current level, the height, width, placement angle area and the required number of the macro unit.

[0073] Specifically, Figure 2 As shown, each level is traversed in turn according to the level list, and the area ratio of the macro unit (macro) of the current level is calculated. macro ), the height of the macro unit (macro) macro ) and width (weight macro ) and the macro placement corner area (dir macro ), the required quantity (num macro ) generates a macro, the placement of the macro depends on the macro placement corner area specified by the user (dir macro ), if the placement corner is the lower right corner, then the coordinates of the lower left corner of the i-th macro are as shown in Formula 6 and Formula 7:

[0074]

[0075] In some embodiments, when the area of ​​the hierarchy used to place the macro-units is not less than the total area of ​​the macro-units to be generated, the macro-units are automatically generated, and the formula is as follows:

[0076]

[0077] in, is the area used to place macro units in the i-th hierarchy,

[0078] is the area of ​​the jth macrocell in the current hierarchy,

[0079] Specifically, the system can automatically generate macros if and only if the area of ​​the current level used to place macros is not less than the total area of ​​the macros to be generated, as shown in Formula 3:

[0080]

[0081] in is the area used to place macros in the i-th hierarchy, and the calculation formula is as shown in Formula 4. is the area of ​​the jth macro in the current hierarchy, calculated as shown in Formula 5.

[0082] Specifically, after the macro unit is created, a specified number of pins (pin number) are generated for the macro and are uniformly set at the left edge of the macro.

[0083] In some embodiments, in each hierarchical structure, standard cells are created using the remaining area after creating the macro cells until the remaining area is occupied by the standard cells;

[0084] The formula for generating the number of standard units is as follows:

[0085]

[0086] in, is the area used to place standard units in the i-th hierarchy; is the area of ​​the i-th hierarchy; is the area used to place macro units in the i-th hierarchy; weight cell and height cell are the width and height of the standard cell respectively.

[0087] Specifically, after the macro cell is created, the remaining area for creating the macro at this level is calculated, and cells are created until the remaining area is occupied.

[0088] In this process, the length and width of the cell can be fixed to the length and width of the standard cell (site), and the generation of the cell pin will be performed during the process of creating the netlist connection. The number of cells generated is formula 8:

[0089]

[0090] in is the area used to place cells in the i-th hierarchy, which is calculated as shown in formula 9. cell and heightcell The width and height of the cell are respectively, the width is 20 times the width of the site, and the height is the height of the site.

[0091] Based on the same inventive concept, the present application also provides a method for automatically constructing an integrated circuit design example, comprising:

[0092] The integrated circuit automatic layout planning generation method described in any one of the above items is used for construction. Thus, the required examples can be constructed more efficiently, more complex test function scenarios can be met, the testing and verification process can be accelerated, the performance of different layout configurations can be quickly evaluated, and the optimal layout scheme can be found, thereby improving design performance and efficiency.

[0093] Based on the same inventive concept, the present application also provides an integrated circuit automatic layout planning generation device, comprising:

[0094] A top-level pin creation module creates top-level pins in a designated area to be laid out and creates a corresponding netlist with the same name for each top-level pin, wherein the creation parameters of the top-level pins include: a name prefix, a required number, and a distribution area of ​​the pins;

[0095] A macro cell and standard cell creation module, used for traversing each hierarchy according to the hierarchy list, and creating macro cells and standard cells according to the area ratios occupied by macro cells and standard cells preset in the current hierarchy;

[0096] The unit connection generation module is used to generate the connection relationship between the macro unit and the standard unit according to the preset data flow between each top-level pin.

[0097] The present invention aims to overcome the limitations of the prior art by providing an automated, integrated method to generate macros and cells with netlist connections, and to provide a faster example construction method to achieve efficient tuning and testing.

[0098] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and the relevant parts can be referred to the partial description of the previous embodiments.

[0099] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for generating an automated layout plan for an integrated circuit, characterized in that: include: Creating top-level pins in a designated area to be laid out, and creating a corresponding netlist with the same name for each top-level pin, wherein the creation parameters of the top-level pins include: a name prefix, a required number, and a distribution area of ​​the pins; Traverse each hierarchy according to the hierarchy list, and create macro cells and standard cells according to the area ratios of macro cells and standard cells preset in the current hierarchy; According to the preset data flow between each top-level pin, the connection relationship between the macro cell and the standard cell is generated.

2. The method for generating an automated layout plan according to claim 1, characterized in that: Generating a connection relationship between the macro cell and the standard cell according to the preset data stream includes: According to the type of data flow, the pin types of the starting node and the ending node are obtained; Determining the number of paths of the internal connection paths of each data flow according to the type of the starting node; According to the number of determined paths, in the first hierarchical structure and the second hierarchical structure, a start pin and an end pin are selected for each path respectively, and a path connecting the start pin and the end pin is constructed; Repeat the process of selecting pins and building paths until all paths are built.

3. The method for generating an automated layout plan according to claim 2, characterized in that: When constructing a path connecting the start pin and the end pin, randomly select a pin from the pins of the first hierarchy as the start point of the path, and then connect other pins in the first hierarchy until the number of connected pins reaches half of the preset number of pins, or there are no more pins in the first hierarchy that can be connected; Next, go to the second level structure and continue to connect the pins in the second level structure until the total number of pins reaches the preset number of pins; Finally, the output pin selected for the last time is connected to the termination pin selected in the second hierarchical structure to obtain a complete path.

4. The method for generating an automated layout plan according to claim 2, wherein: The step of determining the number of paths of the internal connection paths of each data flow according to the type of the starting node includes: If the type of the starting node is a hierarchical structure, the number of paths is the preset number of paths; If the start node type is a top-level pin, the number of paths is the maximum number of pins in the first hierarchy.

5. The automated layout planning generation method according to claim 1, characterized in that: Before creating top-level pins in a designated area to be floorplanned, an initial floorplan is created based on preset design parameters, wherein the design parameters include: basic unit, standard cell size and chip shape.

6. The method for generating an automated layout plan according to claim 1, wherein: When creating a macro unit, the macro unit is created according to the area ratio of the macro unit preset at the current level, the height, width, placement corner area and the required number of the macro unit.

7. The method for generating an automated layout plan according to claim 6, wherein: When the area of ​​the macro unit placed in the hierarchy is not less than the total area of ​​the macro units to be generated, the macro unit is automatically generated, and the formula is as follows: in, is the area used to place macro units in the i-th hierarchy, is the area of ​​the jth macrocell in the current hierarchy, 8. The method for generating an automated layout plan according to claim 1, wherein: In each hierarchy, standard cells are created using the remaining area after creating macro cells until the remaining area is filled with standard cells; The formula for generating the number of standard units is as follows: in, in, is the area used to place standard units in the i-th hierarchy; is the area of ​​the i-th hierarchy; is the area used to place macro units in the i-th hierarchy; weight cell and height cell are the width and height of the standard cell respectively.

9. A method for automatically constructing integrated circuit design examples, characterized in that: include: The method for generating an automatic layout plan of an integrated circuit according to any one of claims 1 to 8 is used for construction.

10. An integrated circuit automatic layout planning generation device, characterized in that: include: A top-level pin creation module creates top-level pins in a designated area to be laid out and creates a corresponding netlist with the same name for each top-level pin, wherein the creation parameters of the top-level pins include: a name prefix, a required number, and a distribution area of ​​the pins; A macro cell and standard cell creation module, used for traversing each hierarchy according to the hierarchy list, and creating macro cells and standard cells according to the area ratios occupied by macro cells and standard cells preset in the current hierarchy; The unit connection generation module is used to generate the connection relationship between the macro unit and the standard unit according to the preset data flow between each top-level pin.

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