Transistor, electronic device and method of manufacturing a transistor

Abstract

The transistor of the present application has a gate electrode, a gate insulating film, a semiconductor film, a source electrode, and a drain electrode, and the gate insulating film is a laminated film of SiO x film and SiC y N z film, the total number of the films constituting the laminated film is 3 or more and 18 or less, and the film thickness of each film constituting the laminated film is 25 nm or more and 150 nm or less.

Description

Technical Field

[0001] The present invention relates to a transistor, an electronic device and a method for manufacturing the transistor.

[0002] This application claims priority based on Japanese Patent Application No. 2020-027134, filed in Japan on February 20, 2020, the contents of which are incorporated herein by reference. Background Art

[0003] Thin Film Transistor (TFT) is widely used in liquid crystal display devices and organic electroluminescence (EL) display devices.

[0004] Oxide semiconductors are attracting attention as semiconductor film materials for thin film transistors. Among them, thin film transistors using amorphous oxide semiconductors such as In-Ga-Zn-O (IGZO (indium gallium zinc oxide)) are attracting attention.

[0005] Furthermore, the gate insulating layer of a thin film transistor is formed by CVD (Chemical Vapor Deposition), as described in Patent Document 1. In recent years, display devices are required to have higher performance, and thus a thin film transistor with high insulation performance and high reliability is sought.

[0006] [Prior Art Literature]

[0007] [Patent Document]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-107952 Summary of the Invention

[0009] One aspect of the present invention is a thin film transistor having a gate electrode, a gate insulating film, a semiconductor film, a source electrode, and a drain electrode, wherein the gate insulating film is an alternately stacked layer of SiO x Film and SiC y N z The laminated film is composed of films, the total number of films constituting the laminated film is more than 3 layers and less than 18 layers, and the film thickness of each film constituting the laminated film is more than 25 nm and less than 150 nm. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a schematic diagram of a cross section of an example of a thin film transistor according to this embodiment.

[0011] Figure 2 This is a diagram showing the transistor characteristics of the thin film transistor manufactured in Example 1.

[0012] Figure 3This is a diagram showing the transistor characteristics of the thin film transistor manufactured in Example 2.

[0013] Figure 4 This is a diagram showing the transistor characteristics of the thin film transistor manufactured in Example 3.

[0014] Figure 5 This is a diagram showing the transistor characteristics of the thin film transistor manufactured in Example 4.

[0015] Figure 6 This is a graph showing the transistor characteristics of the thin film transistor manufactured in Comparative Example 1.

[0016] Figure 7 This is a graph showing the transistor characteristics of the thin film transistor manufactured in Comparative Example 2. DETAILED DESCRIPTION

[0017] Thin-film transistors

[0018] This embodiment is a thin film transistor having a gate electrode, a gate insulating film, a semiconductor film, a source electrode, and a drain electrode.

[0019] In this embodiment, the gate insulating film is an alternately stacked SiO x Film and SiC y N z A laminated film made of a film.

[0020] Figure 1 The thin film transistor 1 shown is a bottom gate thin film transistor formed on the surface of a substrate 11. The thin film transistor 1 includes a gate electrode 12, a gate insulating film 13, a semiconductor film 14, a source electrode 15a, and a drain electrode 15b.

[0021] Each configuration will be described below.

[0022] 《Substrate》

[0023] Examples of materials for the substrate 11 include metals, crystalline materials, amorphous materials, conductors, semiconductors, insulators, fibers, glass, ceramics, zeolites, plastics, thermosetting and thermoplastic materials. Furthermore, the substrate 11 may be an optical element, a coated substrate, or a film.

[0024] Examples of the crystalline material include single-crystalline materials, polycrystalline materials, and partially crystalline materials.

[0025] Examples of thermoplastic materials include polyacrylates, polycarbonates, polyurethanes, polystyrenes, cellulose polymers, polyolefins, polyamides, polyimides, polyesters, polyphenylenes, polyethylenes, polyethylene terephthalates, polyethylene naphthalates, polypropylenes, ethylene-vinyl copolymers, and polyvinyl chlorides. These materials may also be doped.

[0026] In this embodiment, the material of the substrate 11 is preferably polyimide or polyethylene naphthalate.

[0027] The softening point of polyimide is 290°C. The softening point of polyethylene naphthalate is 120°C.

[0028] In this embodiment, the substrate 11 is preferably a flexible substrate. Here, flexibility refers to the property that the substrate 11 can be bent without shearing or breaking even when a force equal to its own weight is applied to the substrate 11.

[0029] Furthermore, the property of bending due to the force of its own weight is also considered as flexibility. In this embodiment, the flexibility of the substrate 11 changes according to the material, size, thickness, temperature and other environmental factors of the substrate 11.

[0030] As the flexible substrate 11, a substrate made of a resin material is preferable.

[0031] Furthermore, a single strip-shaped substrate may be used as the substrate 11. Furthermore, in this embodiment, the substrate 11 may be formed by connecting a plurality of unit substrates to form a strip-shaped structure.

[0032] Gate Electrode

[0033] The gate electrode 12 is formed on the surface of the substrate 11. The gate electrode 12 is conductive. The material constituting the gate electrode 12 is not particularly limited. In this embodiment, examples thereof include Al, Mo, Cu, Ti, Au, and Ni.

[0034] The gate electrode 12 may be a laminated body using any of these materials alone, or a laminated body using two or more of these materials in combination.

[0035] Furthermore, alloys containing these materials may also be used. As an alloy used in the gate electrode 12, an alloy of nickel and phosphorus can be given.

[0036] The shape of the gate electrode 12 is not particularly limited. From the perspective of controllability of the channel length and channel width, it is preferably a square in a plan view with the length and width in the channel length and width directions of the thin film transistor as the length and width.

[0037] The size of the gate electrode 12 may be any size as long as it can ensure the channel length and channel width of the thin film transistor.

[0038] Here, the channel length direction of the thin film transistor refers to the opposite direction of the source electrode 15 a and the drain electrode 15 b of the thin film transistor.

[0039] Furthermore, the channel width direction of the thin film transistor refers to a direction perpendicular to the channel length direction of the thin film transistor and parallel to the surface of the substrate 11 .

[0040] The average thickness of the gate electrode 12 may be, for example, not less than 50 nm and not more than 500 nm, or not less than 100 nm and not more than 400 nm.

[0041] Furthermore, in order to improve coverage of the gate insulating film 13, the gate electrode 12 may have a tapered cross section in the thickness direction that expands toward the substrate 11. The inclination angle of the tapered gate electrode 12 is preferably not less than 30° and not more than 40°.

[0042] Gate Insulation Film

[0043] The gate insulating film 13 is formed on one surface of the substrate 11 in such a manner as to cover the gate electrode 12. In this embodiment, the surface of the substrate 11 on which the gate electrode 12 is provided is set as the upper main surface. In this embodiment, the gate insulating film 13 is formed by alternating SiO x Film and SiC y N z A laminated film made of a film.

[0044] SiO x The x of the film is preferably 1.7 to 2.4, more preferably 1.9 to 2.1.

[0045] SiC y N z The y of the film is preferably 1.0 or more and 3.5 or less, and more preferably 1.0 or more and 2.0 or less. y N z The z of the film is preferably greater than 0 and 1.0 or less, and more preferably 0.2 or more and 0.7 or less.

[0046] The total number of films constituting the laminated film is 3 to 18 layers, preferably 4 to 16 layers. In this embodiment, the total number of films constituting the laminated film may be an odd number or an even number, but an even number is more preferred.

[0047] When the total number of films constituting the stacked film is an odd number, it is preferable that the layer in contact with the semiconductor film 14 be SiO x That is, it is preferable to have SiO x Film, SiCy N z Film, SiO x membrane.

[0048] The stacked film is preferably formed by alternating SiC on the gate electrode 12. y N z Film, SiO x Furthermore, it is preferable that the layer in contact with the semiconductor film 14 be SiO x Film formation.

[0049] That is, in the case of the bottom gate type, the stacked film is preferably formed with the uppermost layer on the semiconductor film 14 side being SiO x Film formation.

[0050] In the case of a top gate type, it is preferable that the bottom layer on the semiconductor film 14 side be SiO x Film formation.

[0051] SiO x The film has a barrier property against impurities such as water (H2O) or hydrogen (H2) that affect the characteristics of thin film transistors. In addition, in this embodiment, by forming a laminated film of the above-mentioned layer structure, SiO x The interface of the film increases. These impurities are trapped in each interface. Therefore, the barrier property is improved and impurities are less likely to diffuse into the semiconductor film. As a result, a device with higher reliability can be realized. In addition, by making the stacked film have SiC y N z The membrane can be made into a device that is given flexibility and thus has improved resistance to stress.

[0052] Conventional methods for forming SiO2 thin films using plasma CVD devices include methods that form the film at a high temperature of approximately 200°C to 300°C to improve the insulating properties of the gate insulating film. Furthermore, methods that require a post-annealing treatment at a high temperature are also exemplified.

[0053] If a heat treatment at a high temperature is required as in the conventional method, there are problems such as a decrease in the selectivity of the substrate material and the inability to use a resin substrate.

[0054] According to this embodiment, by alternately forming SiC y N z Film and SiO x The composite insulating film formed by the film can be made into a high-quality gate insulating film at a processing temperature of less than 200° C. even without high-temperature heat treatment.

[0055] Furthermore, by forming a laminated film with the aforementioned layer structure, the gate insulating film stress can be reduced, making it suitable for flexible substrates that can be repeatedly bent.

[0056] The thickness of each film constituting the laminated film is not less than 25 nm and not more than 150 nm, preferably not less than 26 nm and not more than 90 nm, and more preferably not less than 27 nm and not more than 80 nm.

[0057] When the thickness of each film constituting the laminated film is greater than or equal to the aforementioned lower limit, higher insulation properties can be achieved. Furthermore, when the thickness of each film constituting the laminated film is less than or equal to the aforementioned upper limit, hysteresis can be further reduced or eliminated, resulting in a highly reliable device.

[0058] In this embodiment, the total thickness of the laminated film is preferably 500 nm or less. Furthermore, the thickness of each film comprising the laminated film is preferably substantially the same. The thickness of each layer can be adjusted appropriately based on the total number of films. In this embodiment, the thickness of each film comprising the laminated film is preferably substantially the same.

[0059] The shape of the gate insulating film 13 is not limited as long as it can cover the gate electrode 12 . For example, the gate insulating film 13 may cover the entire surface of the substrate 11 .

[0060] The gate insulating film is formed by alternating SiO x Film and SiC y N z The total number of films constituting the laminated film is greater than 3 layers and less than 18 layers, and the thickness of each film constituting the laminated film is greater than 25 nm and less than 150 nm. The above situation can be confirmed by the following method.

[0061] The concentration of oxygen atoms in each layer constituting the gate insulating film can be measured by compositional analysis using Rutherford backscattering spectroscopy and hydrogen forward scattering analysis. Rutherford backscattering spectroscopy is sometimes abbreviated as "RBS" and hydrogen forward scattering analysis is sometimes abbreviated as "HFS."

[0062] RBS or HFS can also be used to measure the silicon atom concentration and carbon atom concentration in each layer constituting the gate insulating film.

[0063] The concentration of hydrogen atoms as impurities present in each layer constituting the gate insulating film can be measured by HFS.

[0064] RBS irradiates the object to be measured with high-speed ions (He + 、H +The energy and yield of a portion of the incident ions elastically (Rutherford) scattered by the nuclei of the target atoms are measured. The energy of the scattered ions varies depending on the mass and position (depth) of the target atoms. Therefore, the elemental composition of the target in the depth direction can be obtained based on the energy and yield of the scattered ions.

[0065] By irradiating the object with high-speed ions (He + The hydrogen in the measured object is scattered forward due to elastic recoil. HFS uses this phenomenon to obtain the depth distribution of elements based on the energy and yield of the recoil hydrogen.

[0066] By measuring the silicon atom concentration and oxygen atom concentration using RBS or HFS, the SiO x The presence of SiC film can be confirmed by measuring the concentration of silicon atoms, carbon atoms and nitrogen atoms using RBS or HFS. y N z By confirming the distribution of these, it can be confirmed whether the SiO x Film and SiC y N z Furthermore, the total number of films constituting the laminated film can be confirmed.

[0067] Semiconductor Films

[0068] Examples of semiconductor materials that constitute the semiconductor film 14 include IGZO (In-Ga-Zn-O system) which has a high carrier mobility and is relatively easy to form a film, transparent amorphous oxide semiconductor (TAOS (Transparent Amorphous Oxide Semiconductor)), zinc oxide (ZnO), nickel oxide (NiO), tin oxide (SnO2), titanium oxide (TiO2), vanadium oxide (VO2), indium oxide (In2O3), strontium titanate (SrTiO3), etc.

[0069] Alternatively, an organic semiconductor may be used as a semiconductor material constituting the semiconductor film 14. As the organic semiconductor material, a p-type semiconductor, fullerenes, or an n-type semiconductor may be used.

[0070] Examples of the p-type semiconductor include copper phthalocyanine (CuPc), fused pentacene, rubrene, fused tetracene, and P3HT (poly(3-hexylthiophene-2,5-diyl)).

[0071] As the fullerenes, C60 may be mentioned.

[0072] Examples of the n-type semiconductor include perylene derivatives such as PTCDI-C8H (N,N'-dioctyl-3,4,9,10-perylene tetracarboxylic diimide).

[0073] The semiconductor material constituting the semiconductor film 14 includes soluble pentacene or an organic semiconductor polymer that is soluble in an organic solvent. Therefore, the semiconductor film can be formed using a wet process. An example of a soluble pentacene is TIPS (6,13-bis(triisopropylsilylethynyl)pentacene).

[0074] The organic semiconductor polymer may, for example, be poly(3-hexylthiophene-2,5-diyl) (P3HT).

[0075] As the organic solvent, toluene is preferably used.

[0076] Source electrode and drain electrode

[0077] The source electrode 15 a and the drain electrode 15 b cover a portion of the gate insulating film 13 and are electrically connected to the semiconductor film 14 at both ends of the channel of the thin film transistor 1 .

[0078] According to the voltage between the gate electrode 12 and the source electrode 15 a and the voltage between the source electrode 15 a and the drain electrode 15 b , the drain current of the thin film transistor 1 flows between the source electrode 15 a and the drain electrode 15 b .

[0079] The material constituting the source electrode 15 a and the drain electrode 15 b is not particularly limited as long as it has conductivity. For example, the same material as that of the gate electrode 12 can be used.

[0080] The average thickness of the source electrode 15 a and the drain electrode 15 b may be 100 nm to 400 nm, or 150 nm to 300 nm.

[0081] The opposing distance between the source electrode 15 a and the drain electrode 15 b , that is, the channel length of the thin film transistor 1 , can be 5 μm to 50 μm, or 10 μm to 30 μm.

[0082] The length of the source electrode 15 a and the drain electrode 15 b in the channel width direction, that is, the channel width of the thin film transistor 1 , may be 100 μm to 300 μm, or 150 μm to 250 μm.

[0083] Although the description is made with respect to a case where a bottom-gate thin film transistor is used as the thin film transistor 1 , a top-gate thin film transistor may also be used as another embodiment.

[0084] (Characteristics of Thin Film Transistors)

[0085] The lower limit of the threshold voltage of the thin film transistor in this embodiment is preferably -1V, more preferably 0V.

[0086] On the other hand, the upper limit of the threshold voltage of the thin film transistor is preferably 3V, and more preferably 2V.

[0087] <Electronic devices>

[0088] This embodiment is an electronic device including the thin film transistor of the embodiment described above. Examples of the electronic device include display devices such as liquid crystal display devices.

[0089] <Thin Film Transistor Manufacturing Method>

[0090] This embodiment relates to a method for manufacturing a thin film transistor.

[0091] The manufacturing method of the thin film transistor of this embodiment comprises the steps of forming a gate insulating film, that is, alternately forming SiO x Film and SiC y N z film, thereby forming a gate insulating film.

[0092] The film forming temperature in the gate insulating film forming step is a temperature that does not reach the softening point of the material constituting the substrate.

[0093] The method for manufacturing the thin film transistor of this embodiment preferably includes, in sequence, a gate electrode film forming step, a gate insulating film film forming step, a semiconductor film film forming step, a source and drain electrode film forming step, and an annealing step.

[0094] <Gate electrode film formation step>

[0095] In the gate electrode film forming step, a gate electrode 12 is formed on the surface of the substrate 11 .

[0096] Specifically, a conductive film is first formed on the surface of the substrate 11 by a known method such as sputtering to a desired thickness. The conditions for forming the conductive film by sputtering are not particularly limited, but can be set as follows: substrate temperature of 20°C to 50°C, film forming power density of 3W / cm 2 Above 4W / cm 2 Below, pressure 0.1Pa to 0.4Pa, carrier gas Ar.

[0097] Next, the conductive film is patterned to form the gate electrode 12. The patterning method is not particularly limited; for example, photolithography followed by wet etching can be used. It is preferable to etch the gate electrode 12 into a tapered cross-section that expands toward the substrate 11 to ensure good coverage with the gate insulating film 13.

[0098] <Gate Insulation Film Formation Step>

[0099] In the gate insulating film forming step, the gate insulating film 13 is formed on the surface side of the substrate 11 so as to cover the gate electrode 12 .

[0100] Specifically, first, SiC is formed on the substrate 11. y N z SiC membrane y N z Film formation steps and SiC y N z SiO is formed on the film x SiO film x Film formation step. By alternately repeating SiC y N z Film formation steps and SiO x Film formation step, can form alternately stacked SiC y N z Film and SiO x A laminated film made of a film.

[0101] SiC y N z Film and SiO x The film can be formed by a chemical vapor deposition (CVD) method using a film forming apparatus described in Japanese Patent No. 5967983, for example.

[0102] [SiC y N z Film formation step]

[0103] SiC y N z The film forming step is to form SiC on the substrate 11 by plasma CVD method using raw material gas. y N z As SiC y N z The raw material gas used in the film formation step may be a raw material gas composed of an organic silicon compound and a compound containing hydrogen atoms. Specifically, a raw material gas containing hexamethyldisilazane (abbreviated as "HMDS") may be used.

[0104] Specifically, for example, a mixed gas of hydrogen and argon and a raw material gas such as HMDS are introduced into the film forming chamber to form SiC y N z The introduction rate of the raw material gas may be 3 sccm or more and 100 sccm or less.

[0105] Preferably, the mixed gas and the raw material gas are introduced into the film forming chamber simultaneously. The introduction rate of the mixed gas can be, for example, not less than 20 sccm and not more than 1000 sccm.

[0106] By introducing mixed gas and raw material gas while generating plasma, a surface reaction is carried out on the surface of the substrate 11, thereby forming SiC on the substrate 11. y N z membrane.

[0107] [SiO x Film formation step]

[0108] SiO x The film forming step uses raw material gas and plasma CVD method to form SiC y N z SiO is formed on the film x As SiO x The raw material gas used in the film formation step may be a raw material gas composed of an organosilicon compound and a compound containing an oxygen atom. Specifically, a raw material gas containing hexamethyldisilazane may be used. Hexamethyldisilazane is referred to as "HMDS."

[0109] Specifically, for example, by introducing raw material gases such as oxygen and HMDS into the film forming chamber, SiO x The introduction rate of the raw material gas may be 3 sccm or more and 20 sccm or less.

[0110] The oxygen gas introduction rate may be 20 sccm or more and 1000 sccm or less.

[0111] By introducing oxygen and raw material gas while generating plasma, SiC y N z The surface of the film undergoes surface reaction, thereby y N z SiO is formed on the film x membrane.

[0112] Furthermore, SiC may be formed on the substrate 11. y N z Before forming the film, a base film is formed on the substrate 11 in any step. If the base film is formed, the gate electrode and the SiC y N zFilm, substrate and SiC y N z Improved film adhesion.

[0113] In this embodiment, the base film that can be formed in any step may be a film formed by plasma CVD and containing at least silicon atoms and oxygen atoms. The base film preferably has an oxygen concentration of 10 to 35 element %.

[0114] In this embodiment, the gate insulating film forming step is performed at a temperature lower than the softening point of the material constituting the substrate.

[0115] Specifically, the temperature is preferably 20° C. or more lower than the softening point of the material constituting the substrate, and more preferably 40° C. or more lower than the softening point of the material constituting the substrate.

[0116] In this embodiment, by alternately forming SiC y N z Film and SiO x The composite insulating film is formed by a film, and the film formation can be carried out at a low temperature lower than the softening point of the material constituting the substrate.

[0117] <Semiconductor film formation step>

[0118] In the semiconductor film forming step, the semiconductor film 14 is formed on the surface of the gate insulating film 13 and directly above the gate electrode 12 .

[0119] Specifically, after forming a semiconductor layer on the surface of the gate insulating film 13 , the semiconductor layer is patterned to form the semiconductor film 14 .

[0120] (Formation of semiconductor layer)

[0121] Specifically, first, a semiconductor layer is formed by sputtering using a known sputtering apparatus, for example, on the surface of the gate insulating film 13. By using the sputtering method, a semiconductor layer having excellent in-plane uniformity of composition and film thickness can be easily formed.

[0122] The sputtering target used in the sputtering method may be an oxide target (IGZO target) containing In, Ga, and Zn.

[0123] The conditions for forming the semiconductor layer by sputtering are not particularly limited, but can be, for example, the following conditions: substrate temperature 20°C to 50°C, film forming power density 2 W / cm 2 Above 3W / cm 2 The pressure is 0.1 Pa to 0.3 Pa, and the carrier gas is Ar. Furthermore, the ambient gas may contain oxygen as an oxygen source. The oxygen content in the ambient gas may be set to 3% by volume to 5% by volume.

[0124] Furthermore, the method of forming the semiconductor layer is not limited to the sputtering method, and a chemical film forming method such as a coating method may also be used.

[0125] (Patterned)

[0126] Next, the semiconductor layer is patterned to form the semiconductor film 14. The method for patterning the semiconductor thin layer is not particularly limited, and for example, a method of performing photoetching followed by wet etching can be used.

[0127] Source and Drain Electrode Formation Steps

[0128] In the source and drain electrode film forming step, a source electrode 15 a and a drain electrode 15 b are formed. The source electrode 15 a and the drain electrode 15 b are electrically connected to the semiconductor film 14 at both ends of the channel of the thin film transistor.

[0129] Specifically, a conductive film is first formed on the surface of the substrate 11 by a known method such as sputtering to a desired thickness. The conditions for forming the conductive film by sputtering are not particularly limited, but can be set as follows: substrate temperature of 20°C to 50°C, film forming power density of 3W / cm 2 Above 4W / cm 2 Below, pressure 0.1Pa to 0.4Pa, carrier gas Ar.

[0130] Next, the conductive film is patterned to form the source electrode 15a and the drain electrode 15b. The patterning method is not particularly limited, and for example, a method of performing photoetching followed by wet etching can be used.

[0131] Annealing step

[0132] Preferably, an annealing step is included, wherein the annealing step is performed at a temperature below 300° C. after the gate insulating film is formed.

[0133] The annealing temperature is more preferably 200° C. or lower.

[0134] The annealing step is preferably performed at the above temperature for 10 minutes to 8 hours.

[0135] [Example]

[0136] The following examples are further described in detail, but the present invention is not limited to the following examples.

[0137] <Example 1>

[0138] [Gate electrode film formation step]

[0139] A 125μm-thick polyimide film (softening point: 290°C) was used as substrate 11. A metal shield (0.08mm thick, SUS430) with a pattern corresponding to the gate electrode was placed on one side of the cleaned substrate 11. A conductive film (50nm Al film), the material for gate electrode 12, was deposited by vacuum deposition using resistance heating. This formed gate electrode 12 on substrate 11.

[0140] [Gate insulation film formation step]

[0141] Next, a gate insulating film 13 is formed on the entire main surface of the substrate 11 in such a manner as to cover the gate electrode 12. The gate insulating film 13 is formed by chemical vapor deposition (CVD) and alternately forming SiO x Film and SiC y N z Made of membrane.

[0142] [Gate insulation film formation step]

[0143] The gate insulating film forming step is to form a gate insulating film 13 on the surface side of the substrate 11 so as to cover the gate electrode 12 .

[0144] SiC y N z Film and SiO x The film was formed by chemical vapor deposition (CVD) using a film forming apparatus described in Japanese Patent No. 5967983.

[0145] [SiC y N z Film formation step]

[0146] Using raw material gas and plasma CVD method, SiC is formed on the substrate 11. y N z Film. On SiC y N z In the film forming step, HMDS gas is used as a raw material gas.

[0147] A mixture of hydrogen and argon and HMDS gas is introduced into the film forming chamber to form SiC y N z The feed gas introduction rate is set to 3-100 sccm.

[0148] The mixed gas and the raw material gas are introduced into the film forming chamber simultaneously. The introduction rate of the mixed gas is set to 20 to 1000 sccm.

[0149] By introducing mixed gas and raw material gas while generating plasma, SiC is formed on the substrate 11. y N z The plasma power is 1-20kW to generate plasma until SiC y N z The film becomes a predetermined thickness.

[0150] [SiO x Film formation step]

[0151] Using raw material gas and plasma CVD method, SiC y N z SiO is formed on the film x . In SiO x In the film forming step, HMDS gas was used as the raw material gas.

[0152] By introducing oxygen and HMDS gas into the film forming chamber, SiO x The introduction rate of HMDS gas is set to 10-100 sccm.

[0153] The oxygen gas introduction rate is set to 20-1000 sccm.

[0154] By introducing oxygen and raw material gas while generating plasma, SiC y N z SiO is formed on the film x The plasma power is 1-20kW to generate plasma until SiO x The film becomes a predetermined thickness.

[0155] The film forming temperature of the gate insulating film forming step is set to 82°C.

[0156] In Example 1, a group of SiC y N z Film formation steps and SiO x The film forming step is counted as one time and is performed twice, thereby forming a gate insulating film composed of four layers. y N z Film formation steps and SiO x The membrane formation step was counted as 1 time.

[0157] The gate insulating film 13 having the four layers formed in Example 1 was analyzed by RBS or HFS. y N z In the film, y is 1.0 or more and 2.0 or less, and z is 0.2 or more and 0.7 or less. x In the film, x is 1.9 or more and 2.1 or less.

[0158] The gate insulating film 13 of the four-layer structure manufactured in Example 1 was analyzed by RBS or HFS. The results showed that the SiC film with a thickness of 100 nm was formed from the side of the gate electrode 12. y N z Film, SiO with a thickness of 100nm x Film, SiC with a thickness of 100nm y N z Film, SiO with a thickness of 100nm x The membrane consists of 4 layers.

[0159] [Semiconductor film formation step]

[0160] Next, a semiconductor film 14 is formed on the gate insulating film 13 .

[0161] The oxide semiconductor film, forming the semiconductor film 14, is formed by sputtering using an InGaZnO target (In2O3-Ga2O3-(ZnO)2) with an atomic composition ratio of In:Ga:Zn of 2:2:1. The semiconductor film 14 is patterned using a metal mask in the same manner as the gate electrode 12.

[0162] Thus, an InGaZnO film with a thickness of 20 nm was formed.

[0163] [Source and drain electrode film formation steps]

[0164] Next, a conductive film (50 nm Al film) is formed as the material for the source and drain electrodes 15a and 15b by vacuum deposition using resistance heating. Furthermore, this film formation is also performed through a metal mask, thereby obtaining the source and drain electrodes 15a and 15b having the desired pattern shapes.

[0165] The source electrode 15 a and the drain electrode 15 b are formed so as to overlap with the gate insulating film 13 and the semiconductor film 14 , respectively.

[0166] The semiconductor film 14 is formed so that a portion thereof is exposed between the source electrode 15a and the drain electrode 15b.

[0167] [Annealing step]

[0168] After the gate insulating film is formed, an annealing step is performed at a temperature below 105° C. for 8 hours to obtain the thin film transistor of Example 1.

[0169] <Example 2>

[0170] A group of SiC y N z Film formation steps and SiO xThe film forming step is counted as one time and performed four times, thereby forming an 8-layer gate insulating film 13. The 8-layer gate insulating film 13 is a SiC film with a thickness of 50 nm from the side of the gate electrode 12. y N z Film, SiO film with a thickness of 50nm x Film, SiC with a thickness of 50nm y N z Film, SiO film with a thickness of 50nm x Film, SiC with a thickness of 50nm y N z Film, SiO film with a thickness of 50nm x Film, SiC with a thickness of 50nm y N z Film, SiO film with a thickness of 50nm x A thin film transistor was manufactured in the same manner as in Example 1 except for the above.

[0171] <Example 3>

[0172] A group of SiC y N z Film formation steps and SiO x The film forming step is counted as one time and is performed 7 times. SiC films with a thickness of 30 nm are formed alternately from the side of the gate electrode 12. y N z film and SiO with a thickness of 30nm x The thin film transistor is manufactured in the same manner as in Example 1 except that a gate insulating film 13 having a 14-layer structure is formed.

[0173] <Example 4>

[0174] SiO x Film formation step, SiC y N z Film formation steps and SiO x In the film forming step, a three-layer gate insulating film 13 is formed. The three-layer gate insulating film 13 is a SiO film with a thickness of 50 nm from the side of the gate electrode 12. x Film, SiC with a thickness of 300nm y N z Film, SiO film with a thickness of 50nm x A thin film transistor was manufactured in the same manner as in Example 1 except for the above.

[0175] <Comparative Example 1>

[0176] Forming SiC film with a thickness of 400nm y N zA thin film transistor was manufactured in the same manner as in Example 1 except that the gate insulating film 13 was formed.

[0177] Comparative Example 2

[0178] A group of SiC y N z Film formation steps and SiO x The film forming step is counted as one time and is performed 10 times. SiC films with a thickness of 20 nm are formed alternately from the side of the gate electrode 12. y N z film and SiO with a thickness of 20nm x The thin film transistor is manufactured in the same manner as in Example 1 except that a gate insulating film 13 having a 20-layer structure is formed.

[0179] <Evaluation of Thin Film Transistor Characteristics>

[0180] The characteristics of the thin film transistors manufactured in Examples 1 to 4 and Comparative Examples 1 and 2 were evaluated.

[0181] The performance of the thin film transistors manufactured in Examples 1 to 4 and Comparative Examples 1 and 2 was evaluated using a semiconductor parameter analyzer (4200A-SCS manufactured by Keithley).

[0182] The voltage Vds between the source and drain electrodes was set to 10 V, and the gate voltage was changed from Vg = -10 V to +20 V, and the current-voltage characteristics (transfer characteristics) were evaluated.

[0183] The results are shown in Figures 2 to 7 The results of Examples 1 to 4 are shown in Figures 2 to 5 The results of Comparative Examples 1 and 2 are shown in Figures 6-7 .

[0184] Figures 2 to 7 In the figure, the vertical axis represents the drain current and the horizontal axis represents the gate voltage.

[0185] Figures 2 to 5 The lower limit of the threshold voltage of Examples 1 to 4 is near 0V, and the negative shift of the threshold voltage is suppressed. Figures 2 to 5 Examples 1 to 4 shown above achieve good thin film transistor characteristics with low hysteresis.

[0186] Among them, it can be confirmed that Figure 3 The embodiment 2 shown, Figure 4 The third embodiment shown does not generate hysteresis and has a high reliability of initial characteristics.

[0187] On the other hand, Figure 6As shown in FIG. 1 , the lower limit of the threshold voltage of Comparative Example 1 shifts to the negative side. Figure 7 Comparative Example 2 shown here did not operate properly. This is probably because the thickness of each layer constituting the gate insulating film was too thin.

[0188] [Explanation of symbols]

[0189] 1: Thin Film Transistor

[0190] 11: Substrate

[0191] 12: Gate electrode

[0192] 13: Gate insulation film

[0193] 14: Semiconductor film (oxide semiconductor)

[0194] 15a: Source electrode

[0195] 15b: Drain electrode

Claims

1. A transistor comprising a gate electrode, a gate insulating film, a semiconductor film, a source electrode, and a drain electrode, and The gate insulating film is alternately formed of SiO x Film and SiC y N z Laminated membrane made of membrane; The above SiO x x in the film is 1.7 or more and 2.4 or less; The above SiC y N z In the film, y is 1.0 or more and 3.5 or less, and z is greater than 0 and 1.0 or less; The total number of films constituting the above-mentioned laminated film is not less than 3 layers and not more than 18 layers; The thickness of each film constituting the above-mentioned laminated film is not less than 25 nm and not more than 150 nm.

2. The transistor according to claim 1, wherein the total film thickness of the stacked film is less than 500 nm.

3. The transistor according to claim 1 or 2, wherein the layer of the stacked film in contact with the semiconductor film is SiO x membrane.

4. The transistor according to claim 1 or 2, wherein the thicknesses of the films constituting the stacked films are substantially the same.

5. The transistor according to claim 1 or 2, formed on a flexible substrate.

6. The transistor according to claim 1 or 2, which is formed on a substrate made of a resin material.

7. An electronic device comprising the transistor according to any one of claims 1 to 6.

8. A method for manufacturing a transistor, comprising manufacturing the transistor according to any one of claims 1 to 6, and The gate insulating film forming step comprises the following steps: forming the SiO x Film and the above SiC y N z film, thereby forming the above-mentioned gate insulating film; The film forming temperature in the above-mentioned gate insulating film forming step is a temperature that does not reach the softening point of the material constituting the substrate.

9. The method for manufacturing a transistor according to claim 8, further comprising an annealing step, wherein the annealing step is performed after the gate insulating film forming step, and the annealing step is performed at a temperature lower than the softening point.

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