Semiconductor structure and method for forming the same, and stacked structure

Abstract

The present invention relates to a semiconductor structure and a method for forming the same. The semiconductor structure comprises: a substrate, including a substrate and a dielectric layer, wherein the substrate has a first front side and a first back side arranged opposite to each other, and the dielectric layer is located on the first front side; a connecting hole, which passes through the substrate and extends to the dielectric layer; a first insulating layer, which is located on the inner wall surface of the connecting hole; a protective barrier layer, which is located on the surface of the first insulating layer and is grounded; a second insulating layer, which is located on the surface of the protective barrier layer; and a connecting structure, which is located on the surface of the second insulating layer and fills the connecting hole. The present application can effectively avoid signal coupling between various connecting structures and between the connecting structures and surrounding semiconductor devices.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a method for forming the same, and a stacking structure. Background Art

[0002] Through Silicon Via (TSV) technology is a technical solution for interconnecting stacked chips in three-dimensional integrated circuits. By effectively stacking chips in three dimensions, TSV technology has become one of the most eye-catching technologies in current electronic packaging technology, as it can produce electronic devices with more complex structures, stronger performance and higher cost efficiency.

[0003] However, due to the electromagnetic field of the transmission signal of the TSV structure, the noise coupling between TSV structures is quite serious. Especially in high-density TSV structure arrays, the influence of coupling capacitance and coupling inductance has become the main factor affecting the electrical performance of the TSV structure. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a formation method and a stacking structure that can reduce noise signal coupling between TSV structures.

[0005] A semiconductor structure comprising:

[0006] A substrate, comprising a substrate and a dielectric layer, wherein the substrate has a first front side and a first back side arranged opposite to each other, and the dielectric layer is located on the first front side;

[0007] A communication hole, penetrating the substrate and extending to the dielectric layer;

[0008] A first insulating layer, located on the inner wall surface of the connecting hole;

[0009] A protective barrier layer, located on the surface of the first insulating layer and grounded;

[0010] A second insulating layer, located on the surface of the protective barrier layer;

[0011] The connecting structure is located on the surface of the second insulating layer and fills the connecting hole.

[0012] In one of the embodiments, a metal layer is disposed in the dielectric layer, and the protective barrier layer is grounded through the metal layer.

[0013] In one of the embodiments, a connecting line is further provided in the dielectric layer, the connecting line connects the protective barrier layer and the metal layer, and the metal layer, the connecting line and the protective barrier layer together constitute an electromagnetic shielding ring.

[0014] In one of the embodiments, an insulating structure is further provided in the dielectric layer, and the insulating structure insulates and seals the connecting wire and the protective barrier layer.

[0015] In one of the embodiments, the insulating structure includes a first insulating portion and a second insulating portion, the first insulating portion is located between the connecting line and the second insulating portion, and the second insulating portion insulates and seals the connecting line and the protective barrier layer.

[0016] In one of the embodiments, the second insulating layer includes a first sub-insulating layer and a second sub-insulating layer that are spaced apart from each other, and the protective barrier layer, the first sub-insulating layer, the connecting structure and the second sub-insulating layer are arranged to form an air gap.

[0017] In one of the embodiments, the air gap penetrates the interface between the substrate and the dielectric layer.

[0018] In one of the embodiments, a width of a portion of the air gap opposite to the dielectric layer is smaller than a width of a portion of the air gap opposite to the substrate.

[0019] In one of the embodiments, the connecting structure includes a blocking layer and a conductive structure, the blocking layer includes a first sub-blocking layer and a second sub-blocking layer connected to each other, the conductive structure includes a first conductive layer and a second conductive layer, the first sub-blocking layer is located on the surface of the first sub-insulating layer, the first conductive layer is located on the surface of the first sub-blocking layer, the second sub-blocking layer is located on the surface of the second sub-insulating layer, the second conductive layer is located on the surface of the second sub-blocking layer, and fills the connecting hole,

[0020] The second conductive layer is separated from the first conductive layer by the second sub-blocking layer, or the second conductive layer is connected to the first conductive layer.

[0021] In one of the embodiments, the thickness of the second sub-barrier layer is greater than the thickness of the first sub-barrier layer.

[0022] A method for forming a semiconductor structure, comprising:

[0023] A substrate is provided, the substrate comprising a substrate and a dielectric base layer, the substrate having a first front side and a first back side arranged opposite to each other, the dielectric base layer being located at the first front side, a connecting hole being formed in the substrate, the connecting hole penetrating the substrate and extending to the dielectric base layer;

[0024] A first insulating layer, a protective barrier layer, a second insulating layer and a connecting structure are formed in the connecting hole.

[0025] The first insulating layer is located on the inner wall surface of the connecting hole;

[0026] The protective barrier layer is located on the surface of the first insulating layer;

[0027] The second insulating layer is located on the surface of the protective barrier layer;

[0028] The connecting structure is located on the surface of the second insulating layer and fills the connecting hole;

[0029] Part of the dielectric base layer is removed so that the protection barrier layer is grounded, and the remaining dielectric base layer constitutes a dielectric layer.

[0030] In one embodiment, the connecting hole is formed by etching from the first back side.

[0031] In one of the embodiments, the dielectric base layer is provided with a metal layer, and the protective barrier layer is grounded through the metal layer.

[0032] In one embodiment, the dielectric substrate has a second front side, the second front side is far away from the first front side;

[0033] The forming of the first insulating layer, the protective barrier layer, the second insulating layer and the connecting structure in the connecting hole comprises:

[0034] forming a first insulating base layer on the inner wall surface of the communicating hole;

[0035] forming a protective barrier base layer on the surface of the first insulating base layer;

[0036] forming a second insulating layer on the surface of the protective barrier base layer;

[0037] forming a connecting structure on the surface of the second insulating layer;

[0038] Etching the dielectric base layer and the first insulating base layer from the second front side of the dielectric base layer to form a groove, wherein the groove exposes the protection barrier base layer and the metal layer, and the remaining dielectric base layer constitutes a dielectric layer, and the remaining first insulating base layer constitutes a first insulating layer;

[0039] forming a connection baseline in the groove;

[0040] Part of the connection base line and part of the protection barrier base layer are removed, the remaining connection base line constitutes a connection line, the remaining protection barrier base layer constitutes a protection barrier layer, and the connection line connects the protection barrier layer and the metal layer.

[0041] In one embodiment, removing part of the connection base line and part of the protection barrier base layer comprises:

[0042] forming a first insulating initial structure on the surface of the connection base line, wherein the first insulating initial structure fills the groove;

[0043] Removing part of the first insulating initial structure to expose part of the connecting baseline, the remaining first insulating initial structure constitutes a first insulating portion, and the distance between the first insulating portion and the second front surface is greater than the distance between the connecting structure and the second front surface;

[0044] Removing the connecting base line and the protecting barrier base layer between the first insulating portion and the second front surface, the remaining connecting base line constitutes a connecting line, and the remaining protecting barrier base layer constitutes a protecting barrier layer;

[0045] A second insulating portion is formed in the groove, and the second insulating portion and the first insulating portion constitute an insulating structure.

[0046] In one of the embodiments, the second insulating layer includes a first sub-insulating layer and a second sub-insulating layer that are spaced apart from each other, and the protective barrier layer, the first sub-insulating layer, the connecting structure and the second sub-insulating layer are arranged to form an air gap.

[0047] In one of the embodiments, the air gap penetrates the interface between the substrate and the dielectric layer.

[0048] In one embodiment, the forming of the second insulating layer on the surface of the protective barrier base layer comprises:

[0049] forming a primary insulating layer on the surface of the protective barrier base layer, wherein the primary insulating layer includes a sidewall portion;

[0050] forming a primary barrier layer on the surface of the primary insulating layer;

[0051] forming a primary conductive layer on the surface of the primary barrier layer;

[0052] removing part of the primary conductive layer and part of the primary barrier layer to expose part of the sidewall portion, the remaining primary conductive layer constituting the first conductive layer, and the remaining primary barrier layer constituting the first sub-barrier layer;

[0053] Removing part of the side wall portion, the remaining primary insulating layer forms a first sub-insulating layer, and the distance between the first sub-insulating layer and the opening of the connecting hole is greater than the distance between the first sub-blocking layer and the opening of the connecting hole;

[0054] forming a second sub-insulating layer on the surface of the protection barrier base layer, wherein the second sub-insulating layer and the first sub-insulating layer constitute the second insulating layer;

[0055] The forming of a connecting structure on the surface of the second insulating layer comprises:

[0056] forming a second sub-blocking layer on the surface of the second sub-insulating layer, the surface of the first sub-blocking layer and the surface of the first conductive layer, wherein the second sub-blocking layer and the first sub-blocking layer constitute the blocking layer;

[0057] A second conductive layer is formed on the surface of the second sub-blocking layer, the second conductive layer and the first conductive layer constitute the conductive structure, and the conductive structure and the blocking layer constitute the connecting structure.

[0058] In one of the embodiments, the thickness of the second sub-barrier layer is greater than the thickness of the first sub-barrier layer.

[0059] A stacked structure is formed by processing the semiconductor structure described in any one of the above items.

[0060] In the above-mentioned semiconductor structure and its formation method, on the one hand, the protective barrier layer located in the connecting hole is used to prevent metal particles such as those in the connecting structure from growing larger during the annealing process, thereby suppressing thermal stress. On the other hand, the protective barrier layer located in the connecting hole is grounded, so that while suppressing stress, it also forms an electromagnetic shielding ring around the connecting structure, thereby effectively avoiding signal coupling between each connecting structure and between the connecting structure and surrounding semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0062] Figure 1 is a flow chart of a method for forming a semiconductor structure provided in one embodiment;

[0063] Figure 2 A flowchart of forming a first insulating layer, a protective barrier layer, a second insulating layer and a connecting structure in the connecting hole provided in one embodiment;

[0064] Figure 3 A flowchart of removing part of the connection baseline and part of the protection barrier base layer provided in an embodiment;

[0065] Figure 4 A flow chart of forming a second insulating layer on the surface of the protective barrier base layer provided in one embodiment;

[0066] Figure 5-Figure 23 It is a schematic diagram of the structure during the manufacturing process of the semiconductor structure;

[0067] Figure 24-Figure 27 Schematic diagrams of semiconductor structures in different embodiments;

[0068] Fig.28 , Fig.29 Schematic diagram of a semiconductor structure after processing for stacking in different embodiments. DETAILED DESCRIPTION

[0069] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0070] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0071] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0072] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0073] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0074] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, and variations from the illustrated shapes as a result, for example, of manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques.

[0075] In one embodiment, see Figure 1 , providing a method for forming a semiconductor structure, comprising:

[0076] Step S100, providing a substrate 100, the substrate 100 includes a substrate 110 and a dielectric base layer 121, the substrate 110 has a first front surface 110a and a first back surface 110b arranged opposite to each other, the dielectric base layer 121 is located on the first front surface 110a, and a connecting hole 100a is formed in the substrate 100, the connecting hole 100a penetrates the substrate 110 and extends to the dielectric base layer 121, see Figure 5 ;

[0077] Step S200, forming a first insulating layer 200, a protective barrier layer 300, a second insulating layer 400 and a connecting structure 500 on the inner wall surface of the connecting hole 100a, wherein the protective barrier layer 300 is grounded, the first insulating layer 200 is located on the inner wall surface of the connecting hole 100a; the protective barrier layer 300 is located on the surface of the first insulating layer 200; the second insulating layer 400 is located on the surface of the protective barrier layer 300; the connecting structure 500 is located on the surface of the second insulating layer 400 and fills the connecting hole 100a; wherein a portion of the dielectric base layer 121 is removed so that the protective barrier layer 300 is grounded, and the remaining dielectric base layer 121 constitutes the dielectric layer 120, see Fig.24 .

[0078] In step S100, the substrate 110 may include but is not limited to a silicon substrate. A shallow trench isolation structure 600 may be formed on the side of the substrate 110 close to the dielectric base layer 121. The shallow trench isolation structure 600 isolates the substrate 110 into multiple active regions. The active regions are used to form various semiconductor devices.

[0079] The dielectric substrate 121 may include but is not limited to an oxide layer (such as a silicon dioxide layer, etc.). The dielectric substrate 121 may have an interconnection via structure and a metal layer electrically connected to the active region, thereby leading out the signal of the semiconductor device or providing an external signal to the semiconductor device.

[0080] The connecting holes 100a are used to form connecting structures 500. When multiple chips formed by semiconductor structures are stacked, the corresponding connecting holes 100a of each chip are aligned, so that the connecting structures 500 in each corresponding connecting hole 100a are electrically connected, thereby realizing interconnection between each chip.

[0081] In step S200, the first insulating layer 200 is located between the protective barrier layer 300 and the inner wall of the connecting hole 100a, thereby achieving electrical isolation between the protective barrier layer 300 and the substrate 110. The material of the first insulating layer 200 can be silicon dioxide, etc. It can be the same as or different from the material of the dielectric base layer 121.

[0082] The material of the first insulating layer 200 can be silicon dioxide or the like.

[0083] The material of the protection barrier layer 300 may be tantalum (Ta) and / or tantalum nitride (TaN), etc. Moreover, the protection barrier layer 300 is connected to the ground.

[0084] The second insulating layer 400 is located between the interconnecting structure 500 and the protective barrier layer 300, thereby achieving electrical isolation between the interconnecting structure 500 and the protective barrier layer 300. The material of the second insulating layer 400 may be silicon dioxide, etc. The material of the second insulating layer 400 may be the same as or different from that of the first insulating layer 200.

[0085] The interconnection structure 500 is a structure that can be electrically connected, and may include multiple film layers. Of course, the interconnection structure 500 may also include only one film layer, and the present application has no limitation on this.

[0086] After the interconnection structure 500 is formed, an annealing treatment is usually performed to make the size of the metal particles in the interconnection structure 500 more uniform, thereby reducing the resistivity and improving the anti-electromigration capability. However, after annealing, the grain size of the metal particles in the interconnection structure 500 becomes significantly larger, so that the surface of the structure formed becomes rough, thereby causing interface stress, and further increasing the possibility of leakage current.

[0087] The material of the protective barrier layer 300 can be tantalum (Ta) and / or tantalum nitride (TaN), which can effectively inhibit the metal particles in the interconnecting structure 500 from growing larger during the annealing process, thereby effectively reducing the interface stress. At the same time, the protective barrier layer 300 can also prevent the metal particles in the interconnecting structure 500 from diffusing to the substrate 110 and the dielectric layer 120.

[0088] The semiconductor structure generally includes a plurality of interconnecting structures 500. Since the electromagnetic field of the interconnecting structures 500 transmits signals, the interconnecting structures 500 are easily affected by noise coupling. In particular, in a high-density interconnecting structure 500 array, it is more susceptible to the influence of coupling capacitance and coupling inductance, thereby affecting the electrical performance of the interconnecting structures 500.

[0089] In this embodiment, on the one hand, the protective barrier layer 300 located in the connecting hole 100b is used to prevent the metal particles in the connecting structure 500 from growing larger during the annealing process, thereby suppressing thermal stress. On the other hand, the protective barrier layer 300 located in the connecting hole 100b is grounded, so that it can suppress stress while forming an electromagnetic shielding ring around the connecting structure 500, thereby effectively avoiding signal coupling between each connecting structure 500 and between the connecting structure 500 and the surrounding semiconductor devices.

[0090] In one embodiment, see Figure 5 , the connecting hole 100a is formed by etching from the first back side 110b.

[0091] As an example, the first back surface 110b may be etched by dry etching. Figure 5 The substrate 100 shown is formed as a base sheet, thereby forming a communication hole 100a.

[0092] The depth of the connecting hole 100 may be 20 μm-150 μm, and the depth of the connecting hole 100 extending into the dielectric substrate 121 may be 0.5 μm-1 μm. The diameter of the connecting hole 100 may be 3 μm-50 μm. The aspect ratio (ie, the ratio of depth to diameter) of the connecting hole 100 may be 0.4-50.

[0093] Since the first back side 110b of the substrate 110 is far away from the semiconductor devices formed in the active area and the circuit structures connecting the semiconductor devices, this embodiment can effectively prevent the semiconductor devices and related circuit structures formed in the active area from being damaged when forming the connecting hole 100a.

[0094] In one embodiment, please refer to FIG. Fig.18 as well as Fig.25 A metal layer 700 is disposed in the dielectric base layer 121. The protective barrier layer 300 is grounded through the metal layer 700.

[0095] Specifically, the metal layer 700 functions to lead out a signal within the semiconductor device or to lead in an external signal.

[0096] The protection barrier layer 300 of the present application is grounded through the metal layer 700, so that an electromagnetic shielding ring can be formed simply and effectively.

[0097] In one embodiment, the dielectric base layer 122 has a second front surface 120a. The second front surface 120a is away from the first front surface 110a of the substrate 110. Fig.19 .

[0098] See also Figure 2 , step S200 includes:

[0099] Step S210, forming a first insulating base layer 210 on the inner wall surface of the connecting hole 100a, see Figure 6 ;

[0100] Step S220, forming a protective barrier layer 310 on the surface of the first insulating layer 210, see Figure 7 ;

[0101] Step S230, forming a second insulating layer 400 on the surface of the protective barrier layer 310, see Fig.14 ;

[0102] Step S240, forming a connecting structure 500 on the surface of the second insulating layer 400, see Fig.15 or Fig.16 or Fig.17 or Fig.18 .

[0103] Step S250, etching the dielectric base layer 122 and the first insulating base layer 210 from the second front surface 120a of the dielectric base layer 122 to form a groove 120c, the groove 120c exposes the protective barrier base layer 310 and the metal layer 700, the remaining dielectric base layer 122 constitutes the dielectric layer 120, and the remaining first insulating base layer 210 constitutes the first insulating layer 200, see Fig.19 ;

[0104] Step S260, forming a connection base line 810 in the groove 120c, see Fig. 20 ;

[0105] Step S270, remove part of the connection base line 810 and part of the protection barrier base layer 310, the remaining connection base line 810 constitutes the connection line 800, the remaining protection barrier base layer 310 constitutes the protection barrier layer 300, the connection line 800 connects the protection barrier layer 300 and the metal layer 700, see Fig.23 .

[0106] In step S210, a silicon dioxide film layer may be formed on the inner wall of the communication hole 100a by a chemical vapor deposition (CVD) method based on silane (SiH4) or tetraethyl orthosilicate (TEOS) as the first insulating base layer 210. The thickness of the first insulating base layer 210 may be 0.2 μm-2 μm.

[0107] In step S220, a physical vapor deposition (PVD) method may be used to deposit and further form the protective barrier layer 310. The primary barrier layer 2111 may be made of tantalum (Ta) and / or tantalum nitride (TaN), etc., and its thickness may be 0.05 μm-0.1 μm.

[0108] In step S230, the material of the second insulating layer 400 may be the same as that of the first insulating base layer 210. Of course, the second insulating layer 400 may also be different from the first insulating base layer 210. This application has no limitation on this.

[0109] In step S240 , the material of the communication structure 500 may include metal or the like.

[0110] In step S250 , the trench 120 c may be formed by dry etching. The dielectric layer 120 and the first insulating layer 200 may be made of the same material.

[0111] In step S260, a connection base line 810 may be formed by PVD deposition or the like. The connection base line 810 covers the dielectric layer 120, the metal layer 700 and the protective barrier layer 310 on the inner wall of the trench 120c.

[0112] In step S270 , the protective barrier layer 300 is effectively connected to the metal layer 700 via the connecting wire 800 .

[0113] In this embodiment, the protective barrier layer 300 is connected to the metal layer 700 by using the connecting wire 800 , so that the protective barrier layer 300 can be grounded through the metal layer 700 .

[0114] Of course, in other embodiments, other methods may be used to connect the protective barrier layer 300 to the ground through the metal layer 700. For example, the dielectric base layer 122 and the first insulating base layer 210 may be etched from the second front surface 120a of the dielectric base layer 122 to form a groove 120c, and then a metal layer for leading out a signal is formed in the groove 120c, so that the protective barrier layer 300 is directly connected to the metal layer and connected to the ground through the metal layer.

[0115] In one embodiment, see Figure 3 , step S270 includes:

[0116] Step S271, forming a first insulating initial structure 911 on the surface of the connection base line 810, the first insulating initial structure 911 fills the groove 120c, see Fig.21 ;

[0117] Step S272, removing part of the first insulating initial structure 911 to expose part of the connection baseline 810, the remaining first insulating initial structure 911 constitutes a first insulating portion 910, the distance between the first insulating portion 910 and the second front surface 120a is greater than the distance between the protective barrier layer 300 and the second front surface 120a, see Fig. 22 ;

[0118] Step S273, removing the exposed connection line 810 and the protective barrier layer 310 between the first insulating portion 910 and the second front surface 120a, the remaining connection line 810 constitutes the connection line 800, and the remaining protective barrier layer 310 constitutes the protective barrier layer 300, see Fig.23 ;

[0119] Step S274, forming a second insulating portion 920 in the trench 120c, the second insulating portion 920 and the first insulating portion 910 constitute an insulating structure 900, see Fig.24 .

[0120] In step S271 , a first insulating initial structure material (such as silicon dioxide material) may be first deposited on the surface of the connection base line 810 , and then polished to form a first insulating initial structure 911 .

[0121] In step S272 , after a portion of the first insulating initial structure 911 is removed, the remaining first insulating initial structure 911 constitutes the first insulating portion 910 .

[0122] At this time, the exposed portion of the connecting line 810 is the portion that needs to be removed to form the connecting line 800 .

[0123] In step S273, the connection base line 810 between the first insulating portion 910 and the second front surface 120a and the protection barrier base layer 310 may be removed by wet etching, and the second sub-insulating layer 420 is exposed.

[0124] In step S274, a second insulating initial structure material (such as silicon dioxide material) may be first deposited in the trench 120c, and then polished to form the second insulating portion 920. The second insulating portion 920 and the first insulating portion 910 form an insulating structure 900.

[0125] In this embodiment, the connecting wire 800 and the protective barrier layer 300 are insulated and sealed by the insulating structure 900, so as to stably ground the protective barrier layer 300. At this time, the protective barrier layer 300, the connecting wire 800 and the metal layer 700 together form an electromagnetic shielding ring to prevent the connecting structure 500 from interfering with the surrounding signals.

[0126] Meanwhile, in the present embodiment, the insulating structure 900 that insulates and seals the connecting wire 800 and the protective barrier layer 300 includes a second insulating portion 920 and a first insulating portion 910 .

[0127] Of course, in other embodiments, it is also possible to form structures having other forms by other methods. For example, after step S273, the first insulating portion 910 may be removed, and then deposited and polished again to form an insulating structure.

[0128] In one embodiment, see Fig.24 , the second insulating layer 400 includes a first sub-insulating layer 410 and a second sub-insulating layer 420 that are spaced apart. The protective barrier layer 300, the first sub-insulating layer 410, the interconnecting structure 500, and the second sub-insulating layer 420 are arranged to form an air gap 100b. Since air has poor thermal conductivity, the air gap 100b formed in this embodiment can effectively prevent the heat generated by the interconnecting structure 500 from diffusing to the semiconductor devices or dielectric layers around it.

[0129] Moreover, at this time, the air gap 100b can also effectively isolate the connecting structure 500 from the surrounding substrate 110 and / or dielectric layer 120, thereby effectively preventing the substrate 110 and / or dielectric layer 120 from stress deformation due to the thermal expansion of the connecting structure 500, and further effectively preventing the substrate 110 and / or dielectric layer 120 from generating interface cracks.

[0130] In one embodiment, see Fig.24 The air gap 100 b penetrates the interface between the substrate 110 and the dielectric layer 120 .

[0131] The interface between the substrate 110 and the dielectric layer 120 is easily affected by the thermal expansion of the connecting structure 500 and thus generates stress deformation, thereby generating interface cracks.

[0132] In this embodiment, the air gap 100b penetrates the interface between the substrate 110 and the dielectric layer 120, so that the air gap 100b isolates the interface between the substrate 110 and the dielectric layer 120 from the connecting structure 500, thereby effectively preventing interface cracks from occurring at the interface between the two.

[0133] Meanwhile, semiconductor devices are densely distributed around the interface between the substrate 110 and the dielectric layer 120 , and the semiconductor device structure usually runs through both sides of the interface between the substrate 110 and the dielectric layer 120 .

[0134] The air gap 100b penetrates the interface between the substrate 110 and the dielectric layer 120, so that the air gap 100b isolates the connection structure 500 from the substrate 110 and the dielectric layer 120 on both sides of the interface. Therefore, this embodiment can also effectively provide heat insulation protection for semiconductor devices around the air gap 100b, and can prevent the semiconductor devices around the air gap 100b from being affected in performance due to stress deformation of the substrate 110 and / or the dielectric layer 120.

[0135] In one embodiment, the width of a portion of the air gap 100 b opposite to the dielectric layer 120 is smaller than the width of a portion of the air gap 100 b opposite to the substrate 110 .

[0136] The dielectric layer 120 is a film layer formed on the substrate 110, and its thickness is much smaller than that of the substrate 110. Therefore, in this embodiment, the width of the portion of the air gap 100b opposite to the dielectric layer 120 is smaller, thereby effectively preventing the air gap 100b from causing the dielectric layer 120 to be unstable.

[0137] Moreover, the heat generated in the dielectric layer 120 is relatively large. At this time, the width of the air gap 100b opposite to the substrate 110 is relatively large, which will cause the heat to flow to the position with a larger gap, thereby being more conducive to heat dissipation and preventing the influence on the surrounding devices.

[0138] In one embodiment, see Figure 4 , step S230 includes:

[0139] Step S231, forming a primary insulating layer 411 on the surface of the protective barrier base layer 310, the primary insulating layer 411 includes a sidewall portion 4111, see Figure 8 ;

[0140] Step S232, forming a primary barrier layer 5111 on the surface of the primary insulating layer 411, see Fig. 9

[0141] Step S233, forming a primary conductive layer 5211 on the surface of the primary barrier layer 5111, see Fig.10 ;

[0142] Step S234, removing part of the primary conductive layer 5211 and part of the primary barrier layer 5111 to expose part of the sidewall portion 411, the remaining primary conductive layer 5211 constitutes the first conductive layer 521, and the remaining primary barrier layer 5111 constitutes the first sub-barrier layer 511, see Fig.11 ;

[0143] Step S235, remove part of the side wall portion 4111, and the remaining primary insulating layer 411 forms a first sub-insulating layer 410, and the distance H1 between the first sub-insulating layer 410 and the opening of the connecting hole 100a is greater than the distance H2 between the first sub-blocking layer 511 and the opening of the connecting hole 100a, see Fig.12 ;

[0144] Step S236, forming a second sub-insulating layer 420 on the surface of the protective barrier layer 310, the second sub-insulating layer 420 and the first sub-insulating layer 410 constitute a second insulating layer 400, see Fig.13 ;

[0145] At this time, step S240 includes:

[0146] Step S241, forming a second sub-blocking layer 512 on the surface of the second sub-insulating layer 410, the surface of the first sub-blocking layer 511 and the surface of the first conductive layer 521, the second sub-blocking layer 512 and the first sub-blocking layer 511 constitute a blocking layer 510, see Fig.14 ;

[0147] Step S242, forming a second conductive layer 522 on the surface of the second sub-blocking layer 512, the second conductive layer 522 and the first conductive layer 521 constitute a conductive structure 520, and the conductive structure 520 and the blocking layer 510 constitute a connecting structure 500, see Fig.15 ;

[0148] In step S231 , the material of the primary insulating layer 411 may be an insulating material such as silicon dioxide.

[0149] As an example, when the material of the primary insulating layer 411 is silicon dioxide, a 0.2 μm-2 μm thick silicon dioxide film layer can be deposited on the inner wall of the connecting hole 100a by a chemical vapor deposition (CVD) method based on silane (SiH4) or tetraethyl orthosilicate (TEOS) to serve as the primary insulating layer 411.

[0150] In step S232, the primary barrier layer 5111 may also be formed by physical vapor deposition (PVD) method. The primary barrier layer 5111 may be made of tantalum (Ta) and / or tantalum nitride (TaN), and its thickness may be 0.05 μm-0.1 μm.

[0151] In step S233, the material of the primary conductive layer 5211 may be metal copper (Cu) or the like. Specifically, a copper seed layer may be formed on the surface of the primary barrier layer 5111 by a PVD method. Then, electroplating growth is performed on the surface of the copper seed layer to form electroplated copper, and the copper seed layer and the electroplated copper together constitute the primary conductive layer 5211.

[0152] More specifically, since the subsequent step S234 will further remove part of the primary conductive layer 5211 to form the air gap 100b, the primary conductive layer 5211 grown on the surface of the primary barrier layer 5111 may not fill the connecting hole 100a. As an example, the filling thickness of the central portion of the primary conductive layer 5211 may be 20%-70% of the depth of the connecting hole 100a.

[0153] In step S234, part of the primary barrier layer 5111 and part of the primary conductive layer 5211 covering the side wall portion 4111 can be removed by a mixed acid solution, thereby partially exposing the side wall portion 4111 of the primary insulating layer 411, and forming the first sub-blocking layer 511 and the first conductive layer 521 at the same time.

[0154] The first sub-blocking layer 511 and the subsequently formed second sub-blocking layer 512 form a blocking layer, which suppresses the thermal expansion stress generated by the conductive structure 520. Therefore, the materials of the first sub-blocking layer 511 and the second sub-blocking layer 512 are Ta or TaN or other materials that can block thermal stress.

[0155] After the sidewall portion 4111 of the primary insulating layer 411 is partially exposed, step S550 is performed, so that the air gap 100 b can be more easily realized.

[0156] In step S235 , the sidewall portion 4111 of the primary insulating layer 411 (eg, silicon dioxide film layer) in the communication hole 100 a may be etched by hydrofluoric acid or dry etching to form a first sub-insulating layer 410 .

[0157] Specifically, after removing part of the sidewall portion 4111, the distance H1 between the surface of the first sub-insulating layer 410 formed by the remaining primary insulating layer 411 and the opening of the connecting hole 100a is greater than the distance H2 between the surface of the first sub-blocking layer 511 and the opening of the connecting hole 100a. Fig.11In the middle direction, after removing part of the side wall portion 4111 , the surface of the first sub-insulating layer 410 formed by the remaining primary insulating layer 411 is lower than the surface of the first sub-blocking layer 511 .

[0158] In step S236, specifically, the second sub-insulating layer 420 may be formed by chemical vapor deposition. The material of the second sub-insulating layer 420 may be the same as that of the first sub-insulating layer 410, or may be different therefrom.

[0159] In step S241 , the material of the second sub-blocking layer 512 may be the same as that of the first sub-blocking layer 511 , or they may be different.

[0160] At the same time, since the second sub-blocking layer 512 is formed on the surface of the second sub-insulating layer 410, the surface of the first sub-blocking layer 511 and the surface of the first conductive layer 521, the second sub-blocking layer 512 and the first sub-blocking layer 511 are interconnected, thereby effectively suppressing the thermal expansion stress of the conductive structure 330 therein.

[0161] In step S242 , the material of the second conductive layer 522 may be the same as that of the first conductive layer 521 , or may be different, and the present application has no limitation on this.

[0162] As an example, when the material of the second conductive layer 522 and the material of the first conductive layer 521 are both copper, the formation process thereof can be similar to the formation process of the primary conductive layer 5211. A copper seed layer can be formed first, and then electroplated copper is formed on the copper seed layer to form the second conductive layer 522.

[0163] In this embodiment, the air gap 100 b can be formed conveniently and effectively by forming the primary insulating layer 411 and then partially removing the sidewall portion 4111 thereof.

[0164] In this embodiment, there is a second sub-blocking layer 512 between the second conductive layer 522 and the first conductive layer 521. Therefore, the second sub-blocking layer 512 can effectively prevent the second conductive layer 522 and the first conductive layer 521 formed in two stages from being inconsistent in grain size and other factors, and from being affected by thermal stress and causing cracks to form at the interface during the subsequent annealing process.

[0165] Of course, the present application is not limited thereto. In other embodiments, in step S241 , the second sub-blocking base layer may be formed on the surface of the second sub-insulating layer 410 , the surface of the first sub-blocking layer 511 , and the surface of the first conductive layer 521 .

[0166] Afterwards, at least a portion of the second sub-blocking layer on the surface of the first conductive layer 521 may be removed, and the remaining second sub-blocking layer constitutes the second sub-blocking layer 512 . The second sub-blocking layer 512 and the first sub-blocking layer 511 constitute the blocking layer 520 .

[0167] Then, a second conductive layer 522 is formed on the surface of the second sub-blocking layer 512 and the exposed surface of the first conductive layer 521. Fig.16 or Fig.17 .

[0168] At this time, the second conductive layer 522 is in contact with and connected to the first conductive layer 521 , thereby reducing the contact resistance between the second conductive layer 522 and the first conductive layer 521 .

[0169] See also Fig.17 When the second sub-blocking layer 512 covering the surface of the first conductive layer 521 is partially removed, the contact resistance can be reduced and the thermal stress between the second conductive layer 522 and the first conductive layer 521 formed in two sections can be prevented.

[0170] At the same time, if the central portion of the second sub-blocking layer 512 covering the surface of the first conductive layer 521 is removed and the edge portion is retained, the retained edge portion can also help prevent the connection between the second sub-blocking layer 512 and the first sub-blocking layer 511 from affecting the thermal expansion stress of the internal conductive structure 520 (including the first conductive layer 521 and the second conductive layer 522) due to poor contact.

[0171] In one embodiment, the thickness of the second sub-blocking layer 512 is greater than the thickness of the first sub-blocking layer 511. Fig.15 or Fig.16 or Fig.17 .

[0172] At this time, the second sub-blocking layer 512 can be effectively prevented from affecting the thermal expansion stress suppression of the conductive structure 520 (including the first conductive layer 521 and the second conductive layer 522 ) therein due to poor contact at the connection between the second sub-blocking layer 512 and the first sub-blocking layer 511 .

[0173] It should be understood that although Figures 1 to 4 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figures 1 to 4At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0174] In one embodiment, a semiconductor structure is also provided. Fig.25 The semiconductor structure includes a substrate 100 , a connecting hole 100 a , a first insulating layer 200 , a protective barrier layer 300 , a second insulating layer 400 and a connecting structure 500 .

[0175] The substrate 100 includes a substrate 110 and a dielectric layer 120. The substrate 110 has a first front side 110a and a first back side 110b that are arranged opposite to each other, and the dielectric layer 120 is located on the first front side 110a. The connecting hole 100a passes through the substrate 110 and extends to the dielectric layer 120. The first insulating layer 200 is located on the inner wall surface of the connecting hole 100a. The protective barrier layer 300 is located on the surface of the first insulating layer 200 and is grounded. The second insulating layer 400 is located on the surface of the protective barrier layer 300. The connecting structure 500 is located on the surface of the second insulating layer 400 and fills the connecting hole 100a.

[0176] In this embodiment, on the one hand, the protective barrier layer 300 located in the connecting hole 100b is used to prevent the metal particles in the connecting structure 500 from growing larger during the annealing process, thereby suppressing thermal stress. On the other hand, the protective barrier layer 300 located in the connecting hole 100b is grounded, so that it can suppress stress while forming an electromagnetic shielding ring around the connecting structure 500, thereby effectively avoiding signal coupling between each connecting structure 500 and between the connecting structure 500 and the surrounding semiconductor devices.

[0177] In one embodiment, please refer to Fig.25 A metal layer is provided in the dielectric layer 120, and the protective barrier layer 300 is grounded through the metal layer.

[0178] In one embodiment, please refer to Fig.25 A connecting line 800 is also provided in the dielectric layer 120. The connecting line 800 connects the protective barrier layer 300 and the metal layer 700. The metal layer 700, the connecting line 800 and the protective barrier layer 300 together form an electromagnetic shielding ring.

[0179] In one embodiment, please refer to Fig.25 An insulating structure 900 is also provided in the dielectric layer 120 , and the insulating structure 900 insulates and seals the connecting wire 800 and the protective barrier layer 300 .

[0180] In one embodiment, please refer to Fig.25 The insulating structure 900 includes a first insulating portion 910 and a second insulating portion 920. The first insulating portion 910 is located between the connecting wire 800 and the second insulating portion 920, and the second insulating portion 920 insulates and seals the connecting wire 800 and the protective barrier layer 300.

[0181] In one embodiment, see Fig.24 or Fig.26 or Fig. 27 The second insulating layer 400 includes a first sub-insulating layer 410 and a second sub-insulating layer 420 that are spaced apart. The protective barrier layer 300, the first sub-insulating layer 410, the connecting structure 500 and the second sub-insulating layer 420 are arranged to form an air gap 100b.

[0182] In one embodiment, see Fig.24 The air gap 100 b penetrates the interface between the substrate 110 and the dielectric layer 120 .

[0183] In one embodiment, the width of a portion of the air gap 100 b opposite to the dielectric layer 120 is smaller than the width of a portion of the air gap 100 b opposite to the substrate 110 .

[0184] In one embodiment, see Fig.26 or Fig. 27 The interconnection structure 500 includes a barrier layer 510 and a conductive structure 520. The barrier layer 510 includes a first sub-barrier layer 511 and a second sub-barrier layer 512 connected to each other. The conductive structure 520 includes a first conductive layer 521 and a second conductive layer 522. The first sub-barrier layer 511 is located on the surface of the first sub-insulating layer 410, and the first conductive layer 521 is located on the surface of the first sub-barrier layer 511. The second sub-barrier layer 512 is located on the surface of the second sub-insulating layer 420, and the second conductive layer 522 is located on the surface of the second sub-barrier layer 512, and fills the interconnection hole 100a.

[0185] The second conductive layer 522 and the first conductive layer 521 are separated by a second sub-blocking layer 512 (see Fig. 27 Alternatively, the second conductive layer 522 is connected to the first conductive layer 521 (see Fig.26 ).

[0186] In one embodiment, see Fig. 27 , the thickness of the second sub-barrier layer 512 is greater than the thickness of the first sub-barrier layer 511.

[0187] In one embodiment, a stacked structure is further provided, wherein the stacked structure is formed based on any one of the above semiconductor structures.

[0188] Specifically, when forming a stacked structure, the semiconductor structure needs to be processed by etching or planarization to expose the interconnecting structure 500 in the dielectric layer 120 (see Fig.28 or Fig.29 ), so that when it is stacked with an adjacent semiconductor structure, the connecting structure 500 in the connecting hole 100a can be conductively connected to perform signal transmission.

[0189] More specifically, when the connecting structure 500 includes the barrier layer 510 and the conductive structure 520 , the conductive structure 520 needs to be exposed so as to perform signal transmission.

[0190] For the specific limitations and technical effects of the semiconductor structure, please refer to the limitations on the method for forming the semiconductor structure in the above text, which will not be repeated here.

[0191] Of course, it is understandable that the semiconductor structure of the present application is not limited to being formed by the semiconductor structure forming method in the above embodiment.

[0192] In the description of this specification, the description with reference to the terms "one embodiment", "ideal embodiment", etc. means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0193] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0194] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, comprising a substrate and a dielectric layer, wherein the substrate has a first front side and a first back side arranged opposite to each other, and the dielectric layer is located on the first front side; A communication hole, penetrating the substrate and extending to the dielectric layer; A first insulating layer, located on the inner wall surface of the connecting hole; A protective barrier layer, located on the surface of the first insulating layer and grounded; a second insulating layer, located on the surface of the protective barrier layer; the second insulating layer comprises a first sub-insulating layer and a second sub-insulating layer which are spaced apart, and the protective barrier layer, the first sub-insulating layer, the connecting structure and the second sub-insulating layer are arranged to form an air gap; The connecting structure is located on the surface of the second insulating layer and fills the connecting hole.

2. The semiconductor structure according to claim 1, characterized in that: A metal layer is disposed in the dielectric layer, and the protection barrier layer is grounded through the metal layer.

3. The semiconductor structure according to claim 2, characterized in that: A connecting line is also arranged in the dielectric layer, and the connecting line connects the protective barrier layer and the metal layer. The metal layer, the connecting line and the protective barrier layer together form an electromagnetic shielding ring.

4. The semiconductor structure according to claim 3, characterized in that: An insulating structure is also provided in the dielectric layer, and the insulating structure insulates and seals the connecting wire and the protective barrier layer.

5. The semiconductor structure according to claim 4, characterized in that: The insulating structure includes a first insulating portion and a second insulating portion, wherein the first insulating portion is located between the connecting wire and the second insulating portion, and the second insulating portion insulates and seals the connecting wire and the protective barrier layer.

6. The semiconductor structure according to claim 1, characterized in that The air gap penetrates the interface between the substrate and the dielectric layer.

7. The semiconductor structure according to claim 6, characterized in that: A width of a portion of the air gap facing the dielectric layer is smaller than a width of a portion of the air gap facing the substrate.

8. The semiconductor structure according to claim 1, characterized in that: The connecting structure includes a blocking layer and a conductive structure, the blocking layer includes a first sub-blocking layer and a second sub-blocking layer connected to each other, the conductive structure includes a first conductive layer and a second conductive layer, the first sub-blocking layer is located on the surface of the first sub-insulating layer, the first conductive layer is located on the surface of the first sub-blocking layer, the second sub-blocking layer is located on the surface of the second sub-insulating layer, and the second conductive layer is located on the surface of the second sub-blocking layer and fills the connecting hole. The second conductive layer is separated from the first conductive layer by the second sub-blocking layer, or the second conductive layer is connected to the first conductive layer.

9. The semiconductor structure according to claim 8, characterized in that: The thickness of the second sub-barrier layer is greater than that of the first sub-barrier layer.

10. A method for forming a semiconductor structure, characterized in that: include: A substrate is provided, the substrate comprising a substrate and a dielectric base layer, the substrate having a first front side and a first back side arranged opposite to each other, the dielectric base layer being located at the first front side, a connecting hole being formed in the substrate, the connecting hole penetrating the substrate and extending to the dielectric base layer; A first insulating layer, a protective barrier layer, a second insulating layer and a connecting structure are formed in the connecting hole. The first insulating layer is located on the inner wall surface of the connecting hole; The protective barrier layer is located on the surface of the first insulating layer; The second insulating layer is located on the surface of the protective barrier layer; the second insulating layer includes a first sub-insulating layer and a second sub-insulating layer that are spaced apart, and the protective barrier layer, the first sub-insulating layer, the connecting structure and the second sub-insulating layer are surrounded to form an air gap; The connecting structure is located on the surface of the second insulating layer and fills the connecting hole; Part of the dielectric base layer is removed so that the protection barrier layer is grounded, and the remaining dielectric base layer constitutes a dielectric layer.

11. The method for forming a semiconductor structure according to claim 10, characterized in that: The connecting hole is formed by etching from the first back surface.

12. The method for forming a semiconductor structure according to claim 10, wherein: The dielectric base layer is provided with a metal layer, and the protection barrier layer is grounded through the metal layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: The dielectric substrate has a second front surface, and the second front surface is far away from the first front surface; The forming of the first insulating layer, the protective barrier layer, the second insulating layer and the connecting structure in the connecting hole comprises: forming a first insulating base layer on the inner wall surface of the communicating hole; forming a protective barrier base layer on the surface of the first insulating base layer; forming a second insulating layer on the surface of the protective barrier base layer; forming a connecting structure on the surface of the second insulating layer; Etching the dielectric base layer and the first insulating base layer from the second front side of the dielectric base layer to form a groove, wherein the groove exposes the protection barrier base layer and the metal layer, and the remaining dielectric base layer constitutes a dielectric layer, and the remaining first insulating base layer constitutes a first insulating layer; forming a connection baseline in the groove; Part of the connection base line and part of the protection barrier base layer are removed, the remaining connection base line constitutes a connection line, the remaining protection barrier base layer constitutes a protection barrier layer, and the connection line connects the protection barrier layer and the metal layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: The removing of part of the connection base line and part of the protection barrier base layer comprises: forming a first insulating initial structure on the surface of the connection base line, wherein the first insulating initial structure fills the groove; Removing part of the first insulating initial structure to expose part of the connecting baseline, the remaining first insulating initial structure constitutes a first insulating portion, and the distance between the first insulating portion and the second front surface is greater than the distance between the connecting structure and the second front surface; Removing the connecting base line and the protecting barrier base layer between the first insulating portion and the second front surface, the remaining connecting base line constitutes a connecting line, and the remaining protecting barrier base layer constitutes a protecting barrier layer; A second insulating portion is formed in the groove, and the second insulating portion and the first insulating portion constitute an insulating structure.

15. The method for forming a semiconductor structure according to claim 10, wherein: The air gap penetrates the interface between the substrate and the dielectric layer.

16. The method for forming a semiconductor structure according to claim 10, wherein: The forming of a second insulating layer on the surface of the protection barrier base layer comprises: forming a primary insulating layer on the surface of the protective barrier base layer, wherein the primary insulating layer includes a sidewall portion; forming a primary barrier layer on the surface of the primary insulating layer; forming a primary conductive layer on the surface of the primary barrier layer; removing part of the primary conductive layer and part of the primary barrier layer to expose part of the sidewall portion, the remaining primary conductive layer constituting the first conductive layer, and the remaining primary barrier layer constituting the first sub-barrier layer; Removing part of the side wall portion, the remaining primary insulating layer forms a first sub-insulating layer, and the distance between the first sub-insulating layer and the opening of the connecting hole is greater than the distance between the first sub-blocking layer and the opening of the connecting hole; forming a second sub-insulating layer on the surface of the protection barrier base layer, wherein the second sub-insulating layer and the first sub-insulating layer constitute the second insulating layer; The forming of a connecting structure on the surface of the second insulating layer comprises: forming a second sub-blocking layer on the surface of the second sub-insulating layer, the surface of the first sub-blocking layer and the surface of the first conductive layer, wherein the second sub-blocking layer and the first sub-blocking layer constitute the blocking layer; A second conductive layer is formed on the surface of the second sub-blocking layer, the second conductive layer and the first conductive layer constitute the conductive structure, and the conductive structure and the blocking layer constitute the connecting structure.

17. The method for forming a semiconductor structure according to claim 16, wherein: The thickness of the second sub-barrier layer is greater than that of the first sub-barrier layer.

18. A stacking structure, characterized in that: The semiconductor structure is formed by processing based on any one of claims 1 to 9.

Images