A SPAD readout circuit based on event-driven time-to-digital converter

Abstract

The present invention discloses a SPAD readout circuit based on an event-driven time digital converter, which belongs to the technical field of semiconductor image sensing. The SPAD readout circuit structure includes a bias circuit module, a column address encoding module, a pixel array module, a TDC array module and an arbitration module. The SPAD readout method includes the occurrence of a photon event, converting the event into a narrow pulse signal, the pixel array outputting an event bus and a row address bus, quantifying the flight time, performing priority arbitration and giving a response, and finally outputting event flight time data and two-dimensional address data. The present invention reduces the circuit area through a column-level time digital converter sharing scheme, and completes the independent output of event-level data through the proposed E-TDC combined with the address event representation method, which not only realizes the dynamic adjustment of circuit power consumption, but also reduces the generation of redundant data.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor image sensing, and in particular relates to a SPAD readout circuit and method based on an event-driven time-to-digital converter. Background Art

[0002] Single-photon avalanche photodiodes (SPADs) have become the mainstream sensor devices in three-dimensional image sensing systems due to their high gain, high integration, and single-photon detection capabilities. In recent years, with the continuous development of CMOS process technology, the emergence of SPADs based on silicon-based processes has enabled three-dimensional image sensing systems to achieve higher levels of integration and has also enabled the technology to be developed in more application scenarios.

[0003] In the SPAD readout chip based on the traditional architecture, each readout pixel has a separate sensor and pixel-level time-to-digital conversion circuit (TDC), and its working mode is based on the frame signal, that is, in each frame signal cycle, all pixels are in working state, waiting to receive photon signals and perform time-to-digital conversion processing. This type of architecture can avoid the loss of photon information to the greatest extent, but when the sensor pixel scale is large, this method will also cause the system to have a large power consumption; and due to the existence of high-precision pixel-level TDC, it often requires a large chip area. In addition, affected by the usage scenario, the TDC in the SPAD readout circuit often has a large data bit width, which will put great pressure on the chip output bandwidth in large-scale image sensor arrays.

[0004] A typical application scenario of SPAD-based three-dimensional image sensors is single-photon signal detection in low-light environments. However, unlike traditional image sensors, photon detection itself has the characteristics of an asynchronous process, that is, in each detection cycle, not all readout pixels can receive photon signals, and the data output by the readout circuit based on the synchronous architecture will contain a large amount of redundant data, which seriously affects the transmission rate of effective data. Therefore, the traditional image sensor architecture based on frame signals is not suitable as the main architecture of the SPAD readout circuit. In some special architectures, the reasonable allocation of circuit resources is achieved by using a shared TDC structure, which improves system efficiency to a certain extent; but for ultra-large-scale readout arrays, even if a shared TDC architecture is used, it will still lead to problems such as excessive data output. Summary of the invention

[0005] The present invention provides a SPAD readout circuit and method for an event-driven time-to-digital converter, aiming to solve the problems of the existing SPAD readout architecture being too large in area, too high in power consumption, and generating a large amount of redundant data.

[0006] The following will compare Figure 1 , Figure 3 , Figure 6 and Figure 7 , a specific technical solution for the SPAD readout circuit structure based on an event-driven time-to-digital converter is given.

[0007] A SPAD readout circuit based on an event-driven time-to-digital converter comprises a bias circuit module, a column address encoding module, a pixel array module, a TDC array module and an arbitration module;

[0008] The pixel array module is composed of M×N array pixel units; each pixel unit is composed of a single-photon avalanche photodiode (SPAD), a quenching recovery circuit, a monostable trigger, a row address encoding circuit, an event generation circuit, and a data bus; in the pixel unit, the non-common end of the single-photon avalanche photodiode is connected to the input end of the quenching recovery circuit; the output end of the quenching recovery circuit is connected to the input end of the monostable trigger; the output end of the monostable trigger is connected to the input end of the row address bus; the output end of the row address encoding circuit is connected to the row address bus in the data bus, and the event generation circuit is connected to the event bus in the data bus; each column of pixel units shares a set of row address buses and event buses, the event bus is connected to the input end of the column address encoding circuit, and the output end of the column address encoding circuit and the row address bus are combined into an address data port, which is connected to the address input end of the TDC array;

[0009] The TDC array module is composed of N TDC chains corresponding to the N columns of pixel units of the pixel array module. The TDC chain is composed of K E-TDC units (event-driven TDC units) and an enable control circuit. The event input terminal EVENT of each E-TDC unit is short-circuited, the address input terminal ADDR is short-circuited, and the K output ports of the enable control circuit are respectively connected to the enable input terminal of each E-TDC unit. The E-TDC unit is composed of a TDC, a monostable trigger 1, a monostable trigger 2, a storage unit array, and a logic gate (such as Figure 3As shown); the event input terminal EVENT and the enable input terminal EN of the E-TDC unit are respectively connected to the two input terminals of the two-input AND gate AND1, and the output terminal of AND1 is simultaneously connected to the stop signal input terminal (STOP) of the TDC and the input terminal of the monostable trigger 1. The output terminal of the monostable trigger 1 is simultaneously connected to the clock input terminal of the D flip-flop DFF1 and the write signal port of the storage cell array, the data input terminal of DFF1 is connected to the power supply voltage, and the data output terminal of DFF1 is output as the request signal port of the E-TDC unit; the reset terminal and the response signal input terminal of the E-TDC unit are respectively connected to the two input terminals of the two-input NAND gate NAND1, and the output terminal of NAND1 is connected to the reset terminal of DFF1. At the same time, the reset terminal of the E-TDC unit is also connected to the input terminal of the monostable trigger 2, the output terminal of the monostable trigger 2 is connected to the read signal port of the storage cell array, the address input terminal of the E-TDC unit and the TDC data output terminal are connected to the input terminal of the storage cell array, and the output terminal of the storage cell array is used as the data output port of the E-TDC unit; the enable control module (as shown Figure 6 As shown), it consists of a counter and logic gates. The event input terminal EVENT of the E-TDC unit is connected to the clock input terminal of the counter. The data output terminal of the counter generates an enable signal EN[0:K-1] which is the same as the number of E-TDC units in the TDC chain after passing through the logic gate, and is respectively connected to the enable input terminal of each E-TDC unit.

[0010] The arbitration module (such as Figure 7 (a) shows), which is composed of arbitration units cascaded step by step to form an arbitration tree structure. The request signal port of the top arbitration unit (the arbitration unit at the top of the arbitration tree structure) is connected to the response signal port of the arbitration unit after an inverter, and the data output end of the top arbitration unit is used as the data output end of the read system; the arbitration unit (such as Figure 7 (b) is composed of a priority arbitration module and an external data transmission module. The request signals REQ1 and REQ2 are input to the arbitration unit. REQ1 and REQ2 are used as the input of the two-input NAND gate NAND1 after passing through an inverter, and the output of NAND1 is connected to the S port of the RS latch; REQ2 and REQ1 are used as the input of the two-input NAND gate NAND2 after passing through an inverter, and the output of NAND2 is connected to the R port of the RS latch. The QB port of the RS latch is connected to the selection port of the data selector MUX to control the selected data channel. The input of the multiplexer is connected to the D flip-flop DFF2; the response signals ACK1 and ACK2 are connected to the clock input of DFF2 after passing through the two-input AND gate; the output of DFF2 is used as the output port of the arbitration unit.

[0011] A SPAD readout method based on an event-driven time-to-digital converter, the process is divided into the following steps:

[0012] Step 1: When a photon event occurs, all TDC units start timing based on the START signal;

[0013] Step 2: The quenching recovery circuit in the pixel unit converts the photon signal into a pulse signal, and the monostable trigger converts the pulse signal into a narrow pulse signal;

[0014] Step 3: The row address encoding circuit in the pixel unit generates a row address on the row address bus, transmits a pulse signal to the event bus, and then triggers the column address encoding circuit outside the pixel array to generate a column address;

[0015] Step 4: The event signal EVENT in the event bus drives the TDC array to record the pulse signal in the event bus in sequence, generate a STOP signal, measure its flight time, and the STOP signal triggers the monostable trigger 1 to generate a write signal to record the two-dimensional address information of each event in the storage unit. At the same time, the TDC unit that records the event initiates a data transmission request to the arbitration module;

[0016] Step 5: The arbitration module gives each TDC unit a corresponding response signal ACK according to the arbitration rule of the arbitration unit, and the response signal ACK triggers the monostable trigger 2 to generate a read signal;

[0017] Step 6: The TDC unit that receives the valid response signal outputs its recorded event flight time data and two-dimensional address data.

[0018] In step 4, the generation of the write signal is more specifically: when an event signal EVENT arrives on the data bus in the pixel array, if the enable signal EN of the E-TDC is valid, the rising edge of the event signal EVENT will trigger the monostable trigger 1 to generate a pulse signal with a fixed width. The pulse signal will be used as a write signal for the memory to write the flight time information at this moment into the memory for temporary storage.

[0019] In step 5, the generation of the read signal is more specifically: the generation of the read signal is more specifically: when an event signal EVENT arrives on the data bus in the pixel array, the event signal EVENT will also generate a request signal REQ through the D flip-flop DFF1, which will be output as the request signal of the E-TDC unit to the subsequent arbitration circuit. When the arbitration circuit responds to the unit through the acknowledgment signal ACK, the signal ACK resets the D flip-flop DFFI and cancels the request signal REQ; after the priority arbitration is completed, the falling edge of the received acknowledgment signal ACK will generate a read signal of the memory through the monostable trigger 2, that is, the timestamp information stored in the memory can be output at this time.

[0020] The present invention has the beneficial effects:

[0021] A column-level TDC architecture is proposed, which consists of a TDC chain. Each TDC chain consists of K and an event-driven time-to-digital converter (E-TDC). Each E-TDC unit in the TDC chain is enabled in turn, and the event pulse in the bus controls the enable switch, so that after each photon event is detected, the switch to the next E-TDC unit is effective. Using column-level multi-channel TDC for measurement can achieve the same photon detection rate as pixel-level TDC while consuming the smallest circuit area.

[0022] In the proposed event-driven TDC, the memory temporarily stores the data measured by the TDC unit, the STOP signal triggers the monostable trigger to generate a write signal, and the ACK signal triggers the monostable trigger to generate a read signal, so that data reading and writing can be realized without a global clock. The output pulse width of the monostable trigger can be adjusted by the bias current provided by the external device, and can be adjusted according to the photon event density in actual use to achieve the appropriate speed and energy consumption.

[0023] The address encoding circuit in the pixel array encodes the event row address, and the address encoding circuit outside the pixel array encodes the event column address. After the TDC unit generates the measurement data, it initiates a request to the arbitration module. The arbitration module adopts an arbitration tree structure, processes the requests initiated by each unit according to the corresponding arbitration rules and handshake mechanism, and gives a response to realize the output of the measurement data and address data of each TDC unit. The final output data only contains the flight time data and two-dimensional address data of the photon event, and does not contain other redundant data.

[0024] In the embodiment 3 listed, power consumption analysis simulation is performed on it based on the Virtuoso platform and the Spectre tool. The simulation results show that when the input event rate varies in the investigated range of 200MHz to 650MHz, the power consumption of a single TDC chain shows an approximately linear growth trend with the increase of the input event rate, indicating that the power consumption of the proposed circuit architecture can be automatically adjusted with the frequency of event occurrence.

[0025] In the example 3 listed, transient simulation analysis is performed on it based on the Virtuoso platform and the Spectre tool. The simulation results show that in the absence of event conflicts, the time required from the occurrence of an event to the output of valid data at the output end is about 5.3ns. Theoretically, the maximum speed of a single TDC link receiving events can reach 750MHz, which can complete the reception of high-speed event signals.

[0026] In summary, the asynchronous readout method proposed in the present invention can reduce the circuit area through the column-level time-to-digital converter sharing scheme, and complete the independent output of event-level data through the proposed event-driven time-to-digital conversion circuit in conjunction with the address event representation method, which can not only realize the dynamic adjustment of circuit power consumption, but also reduce the generation of redundant data. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is the overall architecture diagram of the readout circuit based on event-driven TDC of the present invention;

[0028] Figure 2 is a flow chart of photon signal processing based on event-driven according to the present invention;

[0029] Figure 3 It is the event-driven TDC chain architecture diagram of the present invention;

[0030] Figure 4 is an event-driven TDC signal processing flow chart of the present invention;

[0031] Figure 5 It is the event-driven TDC working timing diagram of the present invention;

[0032] Figure 6 It is each TDC channel enabling control circuit and working timing diagram of the present invention;

[0033] Figure 7 It is a schematic diagram of the arbitration tree and arbitration unit structure of the present invention;

[0034] Figure 8 It is a working timing diagram of the arbitration unit data transmission module of the present invention;

[0035] Fig. 9 is a graph showing the relationship between the power consumption of a TDC unit and the speed of an input event according to Embodiment 1 of the present invention;

[0036] Fig.10 It is a diagram of transient simulation results of the readout circuit when the input event frequency is 650 MHz in Example 1 of the present invention. DETAILED DESCRIPTION

[0037] Example 1 SPAD readout circuit architecture

[0038] The readout circuit of the present invention is fully compatible with the standard CMOS process. Based on the 0.18 μm standard CMOS process, an 8×8 pixel array readout circuit based on a 4-channel event-driven TDC is described in detail below in conjunction with the accompanying drawings and embodiments.

[0039] The system architecture of this embodiment adopts Figure 1As shown in the structure, the pixel array module adopts an 8×8 scale structure, and the peripheral circuit includes the necessary bias circuit module, TDC array module, column address encoding module, and arbitration tree module.

[0040] The bias circuit is mainly composed of a reference module and a current mirror module. The output end of the reference module is connected to the input end of the current mirror. The output end of the current mirror is connected to the bias end of each pixel unit and the monostable trigger in the TDC array to provide corresponding bias current.

[0041] The pixel array module is composed of 8×8 array pixel units; each pixel unit is composed of a single-photon avalanche photodiode (SPAD), a quenching recovery circuit, a monostable trigger, a row address encoding circuit, an event generating circuit and a data bus; in the pixel unit, the non-common end of the single-photon avalanche photodiode is connected to the input end of the quenching recovery circuit; the output end of the quenching recovery circuit is connected to the input end of the monostable trigger; the output end of the monostable trigger is connected to the input end of the row address bus; the output end of the row address encoding circuit is connected to the row address bus in the data bus, and the event generating circuit is connected to the event bus in the data bus; each column of pixel units shares a set of row address buses and event buses, the event bus is connected to the input end of the column address encoding circuit, the output end of the column address encoding circuit and the row address bus are combined into an address data port, and connected to the address input end of the TDC array.

[0042] The TDC array below the pixel array consists of TDC chains, with each column of pixels sharing one TDC chain, and each TDC chain contains four event-driven TDC (E-TDC) units. Figure 3 The diagram shows a schematic diagram of the TDC chain structure and an E-TDC unit circuit architecture diagram, wherein the E-TDC unit is composed of a TDC and an external timing control circuit; in an event-driven TDC unit (E-TDC), the event signal EVENT and the E-TDC unit enable signal EN are connected to the input of the monostable trigger 1 through a two-input AND gate, and are also connected to the clock input CLK of the D trigger DFF1. The data input of the D trigger DFF1 is connected to a high potential, and its output is used as a request signal for the E-TDC unit. The output of the monostable trigger 1 is connected to the memory write signal port. The global reset signal RST and the response signal ACK are connected to the reset end of the D trigger through a two-input NAND gate, and the response signal ACK is connected to the input of the monostable trigger 2, and the output of the monostable trigger 2 is connected to the memory read signal port.

[0043] Figure 6The figure shows the principle diagram of the TDC chain enable control circuit and its working timing logic diagram. In this embodiment, the number of E-TDC unit channels in the TDC chain is 4, and the chain structure enable control circuit is composed of a 2-bit counter and a logic circuit. Among them, the event signal EVENT is used as the counter input clock signal, and a 4-bit enable control signal is output after the decoding circuit.

[0044] Figure 7 (a) shows a schematic diagram of the arbitration tree circuit structure. In this embodiment, 8 groups of column-level TDC chain structures are used. A maximum of 32 E-TDC units request to send data in the same period. Therefore, a 32-to-1 arbitration tree structure is used to arbitrate the data transmission path priority. Figure 7 (b) shows the circuit architecture diagram of the arbitration unit that constitutes Zhongshu. The arbitration unit consists of a priority arbitration module and an external data transmission module.

[0045] Embodiment 2 SPAD readout method

[0046] Figure 2 This is a flowchart of photon signal processing based on event-driven. At the start time, all TDCs in the TDC array continuously quantify the flight time after the system global start signal START is enabled. When a photon event occurs, the quenching recovery circuit in the pixel unit converts the light signal into a pulse signal, and the monostable trigger converts the pulse front into a narrow pulse signal. The row address encoding circuit and the event generation circuit transmit the pulse signal to the row address bus and the time bus. The event signal triggers the column address encoding circuit, and the generated column address data is combined with the row address data in the row address bus into two-dimensional address data, which is input into the TDC array.

[0047] Figure 5The figure shows the working timing diagram of the E-TDC unit. When an event signal EVENT arrives on the data bus in the pixel array, if the enable signal EN of the E-TDC is valid, the rising edge of the event signal EVENT will trigger the monostable trigger 1 to generate a pulse signal with a fixed width. The pulse signal will be used as a write signal for the memory to write the flight time information at this moment into the memory for temporary storage. At the same time, the EVENT signal will also generate a request signal REQ through the D trigger DFF1, which will be output to the subsequent arbitration circuit as the request signal of the E-TDC unit. When the arbitration circuit responds to the unit through the response signal ACK, the signal ACK resets the D trigger DFF1 and cancels the request signal REQ. After the priority arbitration is completed, the falling edge of the received response signal ACK will generate a read signal for the memory through the monostable trigger 2, that is, the timestamp information stored in the memory can be output at this time. At the same time, the address data output in the pixel array row address bus is also controlled by the memory read and write signals, so that it can be output synchronously with the timestamp data. That is, the E-TDC unit realizes the access of TDC measurement data based on the event signal EVENT and the response signal ACK mechanism without global clock control.

[0048] The multiple E-TDC units in the chain E-TDC architecture can receive multiple photon event pulses and perform measurements in a short period of time, avoiding the loss of photon events due to the E-TDC being in the request state or dead time. The event pulse signal EVENT is used as the counter clock signal, and the decoder decodes the counter output data and uses the result as the enable signal of each E-TDC unit in the chain structure. Through this method, each event pulse signal will enable the next E-TDC to be in the state to be tested, and it can also ensure that there is only one E-TDC unit in the chain structure in the state to be tested at the same time. For example, in the initial state, EN[0] is valid, and the E-TDC[0] channel is enabled. After receiving the first photon signal, the falling edge of EVENT triggers the enable signal state change, EN[1] is valid, and the E-TDC[1] channel is enabled, and so on. The factor that limits the maximum speed of a single TDC link receiving events is the processing time of a single event. For the TDC chain composed of four E-TDC units in this embodiment, the enable signal is polled once every four events. That is, under the polling enable control, the 4-channel TDC chain architecture can increase the maximum speed of a single channel processing events by 4 times.

[0049] The arbitration tree structure is used to reasonably allocate the data transmission priority generated by each E-TDC unit; when multiple E-TDC units generate data at the same time, these units initiate requests step by step through the arbitration tree structure, and the top of the arbitration tree processes the request signal and then responds. When the E-TDC unit trying to send data receives the response signal, it reads out the stored data. The arbitration unit is composed of a priority arbitration module and a data transmission module. The priority arbitration module is used to receive the request signal initiated by the data sending unit, and judge the request signal through the internal arbitration mechanism, continue to initiate requests to the arbitration unit at the next level, and transmit a response signal to the sending unit based on the arbitration result. The response signal indicates that the sending unit that initiated the request can now perform data transmission. The priority arbitration module does not belong to the scope of the present invention, and is only an important circuit module that plays a judgment role in the readout circuit system. Figure 8 The figure shows the working timing logic diagram of the arbitration unit. When only REQ1 is valid, the rising edge of REQ1 triggers the multiplexer to select DATA1 to be valid, and when the arbitration unit generates the response signal ACK1, its falling edge triggers DFF2 to output the selected DATA1 data; when only REQ2 is valid, the same applies. When REQ1 and REQ2 are valid at the same time in a short period of time, the first request signal (assuming it is REQ1) will trigger the selection signal S, DATA1 is selected, and DATA1 data is read outward at the falling edge of ACK1; because REQ2 has not been responded to yet, the REQ2 pulse will be maintained, causing the selection signal S to select MUX to DATA2 at the end of the REQ1 pulse, and DATA2 data is read outward at the falling edge of ACK2.

[0050] Example 3 Simulation Verification

[0051] The examples 1 and 2 were simulated and verified based on the virtuoso design platform and the 0.18 μm standard CMOS process. Fig. 9 The figure shows the power consumption analysis diagram of the TDC module under different input event rates. The simulation results show that the power consumption of this architecture varies approximately linearly with the input event frequency, which means that it can achieve automatic adjustment of the system power consumption and has better energy efficiency performance. Fig.10 This is the transient simulation result of the TDC link when the input event frequency is 650MHz. In the absence of event conflicts, the time required from the occurrence of an event to the output of valid data at the output end is about 5.3ns. Theoretically, the maximum speed of a single TDC link receiving events can reach 750MHz, which can complete the reception of high-speed event signals.

Claims

1. A SPAD readout circuit based on an event-driven time-to-digital converter, comprising a bias circuit module and a column address encoding module, characterized in that: The structure also includes a pixel array module, a TDC array module and an arbitration module; The pixel array module is composed of M×N array pixel units; each pixel unit is composed of a single-photon avalanche photodiode, a quenching recovery circuit, a monostable trigger, a row address encoding circuit, an event generation circuit, and a data bus; in the pixel unit, the non-common end of the single-photon avalanche photodiode is connected to the input end of the quenching recovery circuit; The output terminal of the quenching recovery circuit is connected to the input terminal of the monostable trigger; The output end of the monostable trigger is connected to the input end of the row address bus; the output end of the row address encoding circuit is connected to the row address bus in the data bus, and the event generation circuit is connected to the event bus in the data bus; Each column of pixel units shares a set of row address bus and event bus, the event bus is connected to the input end of the column address encoding circuit, the output end of the column address encoding circuit and the row address bus are combined into an address data port, which is connected to the address input end of the TDC array; The TDC array module is composed of N TDC chains corresponding to N columns of pixel units of the pixel array module, and the TDC chain is composed of K E-TDC units and an enable control circuit; the event input terminal EVENT of each E-TDC unit is short-circuited, the address input terminal ADDR is short-circuited, and the K output ports of the enable control circuit are respectively connected to the enable input terminal of each E-TDC unit; wherein the E-TDC unit is composed of a TDC, a monostable trigger 1, a monostable trigger 2, a storage unit array and a logic gate; the event input terminal EVENT and the enable input terminal EN of the E-TDC unit are respectively connected to the two input terminals of a two-input AND gate AND1, and the output terminal of AND1 is simultaneously connected to the stop signal input terminal STOP of the TDC and the input terminal of the monostable trigger 1; The output end of the monostable trigger 1 is simultaneously connected to the clock input end of the D trigger DFF1 and the write signal port of the storage cell array, the data input end of DFF1 is connected to the power supply voltage, and the data output end of DFF1 is output as the request signal port of the E-TDC unit; the reset end and the response signal input end of the E-TDC unit are respectively connected to the two input ends of the two-input NAND gate NAND1, and the output end of NAND1 is connected to the reset end of DFF1; at the same time, the reset end of the E-TDC unit is also connected to the input end of the monostable trigger 2, the output end of the monostable trigger 2 is connected to the read signal port of the storage cell array, the address input end and the TDC data output end of the E-TDC unit are connected to the input end of the storage cell array, and the output end of the storage cell array is used as the data output port of the E-TDC unit; The enable control module is composed of a counter and a logic gate. The event input terminal EVENT of the E-TDC unit is connected to the clock input terminal of the counter. The data output terminal of the counter generates an enable signal EN equal to the number of E-TDC units in the TDC chain after the logic gate, and is respectively connected to the enable input terminal of each E-TDC unit. The arbitration module is composed of arbitration units cascaded step by step to form an arbitration tree structure, the request signal port of the top arbitration unit is connected to the response signal port of the arbitration unit after an inverter, and the data output end of the top arbitration unit is used as the data output end of the read system; The arbitration unit is composed of a priority arbitration module and an external data transmission module. The request signals REQ1 and REQ2 are input to the arbitration unit. REQ1 and REQ2 are used as the input of the two-input NAND gate NAND1 after passing through an inverter, and the output of NAND1 is connected to the S port of the RS latch; REQ2 and REQ1 are used as the input of the two-input NAND gate NAND2 after passing through an inverter, and the output of NAND2 is connected to the R port of the RS latch; the QB port of the RS latch is connected to the selection port of the data selector MUX to control the selected data channel; the input of the multiplexer is connected to the D flip-flop DFF2; the response signals ACK1 and ACK2 are connected to the clock input of DFF2 after passing through the two-input AND gate; The output end of DFF2 serves as the output port of the arbitration unit.

2. A SPAD readout method based on an event-driven time-to-digital converter, the process is divided into the following steps: Step 1: When a photon event occurs, all TDC units start timing based on the START signal; Step 2: The quenching recovery circuit in the pixel unit converts the photon signal into a pulse signal, and the monostable trigger converts the pulse signal into a narrow pulse signal; Step 3: The row address encoding circuit in the pixel unit generates a row address on the row address bus, transmits a pulse signal to the event bus, and then triggers the column address encoding circuit outside the pixel array to generate a column address; Step 4: The event signal EVENT in the event bus drives the TDC array to record the pulse signal in the event bus in sequence, generate a STOP signal, measure its flight time, and the STOP signal triggers the monostable trigger 1 to generate a write signal to record the two-dimensional address information of each event in the storage unit. At the same time, the TDC unit that records the event initiates a data transmission request to the arbitration module; Step 5: The arbitration module gives each TDC unit a corresponding response signal ACK according to the arbitration rule of the arbitration unit, and the response signal ACK triggers the monostable trigger 2 to generate a read signal; Step 6: The TDC unit that receives the valid response signal outputs its recorded event flight time data and two-dimensional address data.

3. The SPAD readout method based on an event-driven time-to-digital converter according to claim 2, characterized in that: In step 4, the generation of the write signal is more specifically: when an event signal EVENT arrives on the data bus in the pixel array, if the enable signal EN of the E-TDC is valid, the rising edge of the event signal EVENT will trigger the monostable trigger 1 to generate a pulse signal with a fixed width. The pulse signal will be used as a write signal for the memory to write the flight time information at this moment into the memory for temporary storage.

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