A method for fabricating a high-density self-aligned silicon carbide MOS device

Abstract

The application provides a preparation method of a high-density self-aligned silicon carbide MOS device, and relates to the technical field of semiconductors, and comprises the following steps: depositing a first polysilicon layer on a substrate to etch and then ion implant to form a well region; growing a silicon dioxide layer around the first polysilicon layer, then sequentially depositing a silicon nitride layer and a second polysilicon layer to form a first stack and a second stack; dividing the top region of the first stack and the second stack into two first regions and a second region, etching the second polysilicon layer of the second region, and etching the silicon nitride layer of the first region and the second region and the silicon dioxide layer to form a side wall; using the first stack and the side wall as a hard mask to perform source region implantation to form a double self-aligned first-type source implantation region; forming a second-type source implantation region on the substrate of the first region; and corresponding source electrodes and gate electrodes are formed to obtain the high-density self-aligned silicon carbide MOS device. The size of a silicon carbide MOS device cell is effectively reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and in particular to a preparation method of a high-density self-aligned silicon carbide MOS device. BACKGROUND

[0002] Silicon carbide semiconductor has excellent physical and electrical properties such as wide band gap, high critical breakdown field, high thermal conductivity, and high carrier saturation drift velocity, making it have a wide application prospect in the field of high-temperature, high-frequency, and high-power electronic devices. Since silicon carbide can obtain silicon dioxide through thermal oxidation, the development and application of MOSFET devices and circuits based on silicon carbide materials are possible. Compared with other types of silicon carbide power devices, SiC MOSFET has the advantages of high switching speed, high reverse blocking voltage, low on-resistance, and simple driving circuit, and is compatible with existing silicon-based power devices, which is a new type of power switch device that has attracted much attention and has extremely outstanding potential and advantages.

[0003] However, as countries begin to pay more and more attention to energy saving and carbon reduction and sustainable development, the power consumption and conversion efficiency of power MOS devices are increasingly required. In the case of low application frequency, power consumption is mainly determined by on-state loss, which is mainly affected by the size of on-resistance; the smaller the on-resistance, the smaller the on-state loss. As one of the key parameters of MOS devices, how to further reduce the on-resistance has been the goal pursued by device design engineers. SUMMARY

[0004] In view of the problems in the prior art, the present application provides a preparation method of a high-density self-aligned silicon carbide MOS device, comprising:

[0005] Step S1, providing a substrate, depositing a first polysilicon layer as a hard mask on both side edges of the upper surface of the substrate, and then etching the substrate to form a well region by ion implantation;

[0006] Step S2, growing a silicon dioxide layer around the first polysilicon layer, then sequentially depositing a silicon nitride layer and a second polysilicon layer to form a first layer stack comprising the silicon dioxide layer, the silicon nitride layer, and the second polysilicon layer, and a second layer stack comprising the silicon dioxide layer and the silicon nitride layer located on both sides of the first layer stack, the top of the first layer stack being flush with the top of the second layer stack;

[0007] Step S3, dividing the top region of the first stack and the second stack into two first regions and a second region between the two first regions, etching the second polysilicon layer of the second region, and then removing the silicon nitride layer of the first region and the second region and etching the silicon dioxide layer to form a side wall around each of the first polysilicon layers;

[0008] Step S4, using the first stack and the two side walls as a hard mask in the first region and using the two side walls as a hard mask in the second region, performing source region implantation to form a double self-aligned first-type source implantation region;

[0009] Step S5, forming a second-type source implantation region on the substrate corresponding to the position of the first stack in the first region;

[0010] Step S6, forming a source electrode based on the first-type source implantation region and the second-type source implantation region, forming a polysilicon gate electrode, and forming a drain electrode on the lower surface of the substrate to obtain the high-density self-aligned silicon carbide MOS device.

[0011] Preferably, in step S2, after sequentially depositing the silicon nitride layer and the second polysilicon layer on the silicon dioxide layer, the top of the first stack is made flush with the top of the second stack by chemical mechanical polishing of the second polysilicon layer.

[0012] Preferably, a source implantation mask is further provided, including two non-light-transmitting regions corresponding to the first regions and a light-transmitting region corresponding to the second region between the two non-light-transmitting regions,

[0013] In step S3, the top region of the first stack and the second stack is divided into two first regions and a second region between the two first regions by the source implantation mask, and the second polysilicon layer of the second region is etched.

[0014] Preferably, step S5 includes:

[0015] Step S51, removing the two first polysilicon layers and the corresponding two side walls of the first region, the first stack of the first region, and the two first polysilicon layers and the corresponding two side walls of the second region to expose the substrate, and then performing high-temperature activation and diffusion;

[0016] Step S52, depositing a third polysilicon layer on the substrate as a hard mask, etching a contact region on the substrate corresponding to the position of the first stack in the first region, and then performing source region implantation on the contact region to form the second-type source implantation region.

[0017] Preferably, the step S6 comprises:

[0018] Step S61, depositing an oxide layer on the substrate, and etching active regions corresponding to the locations where the first type source implantation region and the second type source implantation region are located;

[0019] Step S62, growing a sacrificial oxide layer on the active regions, then removing the sacrificial oxide layer and growing a gate oxide layer, then depositing a fourth polysilicon layer to etch a polysilicon gate;

[0020] Step S63, depositing a dielectric layer on the fourth polysilicon layer, and etching gate and source contact holes corresponding to the locations where the active regions are located;

[0021] Step S64, sputtering a top layer of metal on the dielectric layer and the source contact holes, and etching the top layer of metal to form the source and the gate;

[0022] Step S65, depositing an oxide layer on the top layer of metal as a passivation layer, and etching the passivation layer to complete the fabrication of the top layer structure;

[0023] Step S66, depositing a back metal on the lower surface of the substrate to form the drain, to obtain the high-density self-aligned silicon carbide MOS device.

[0024] Preferably, in the step S3, the silicon nitride layer is removed by a wet method, and the silicon dioxide layer is etched by a dry method.

[0025] Preferably, in the step S51, the two first polysilicon layers and the corresponding two sidewalls in the first region, the first stack in the first region, and the two first polysilicon layers and the corresponding two sidewalls in the second region are removed by a wet method.

[0026] Preferably, in the step S62, the sacrificial oxide layer is removed by a wet method.

[0027] Preferably, in the step S66, the back metal forming the drain is deposited on the lower surface of the substrate by sputtering or evaporation.

[0028] Preferably, the first type source implantation region is an N-type source implantation region, and the second type source implantation region is a P-type source implantation region, to obtain an N-type MOS device;

[0029] or the first type source implantation region is a P-type source implantation region, and the second type source implantation region is an N-type source implantation region, to obtain a P-type MOS device.

[0030] The technical scheme has the following advantages or beneficial effects:

[0031] 1) The multi-layer structure formed by depositing the silicon dioxide layer, the silicon nitride layer and the polysilicon layer is used as a hard mask to perform source region lithography etching, to form a multi-layer structure and a silicon dioxide sidewall hard mask, and then the hard mask is used to perform source region implantation, to form a double self-aligned source implantation region, so that the minimum implantation window of the first source implantation region can be determined by the thickness of the silicon nitride layer, and thus the size can be very small, without being limited by the lithography process machine capacity;

[0032] 2) On the premise of ensuring the contact area of the second source implantation region, the source region window of the first source implantation region can be minimized, so that the size of the cell is reduced, and a silicon carbide MOS device with extremely high density of cells is formed;

[0033] 3) The preparation method is compatible with the existing process steps, and is safe and reliable. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 For the preferred embodiment of the present application, a flowchart of a preparation method of a high-density self-aligned silicon carbide MOS device is shown.

[0035] Figure 2 For the preferred embodiment of the present application, a structure diagram of a well region is shown.

[0036] Figure 3 For the preferred embodiment of the present application, a structure diagram of a first stack and a second stack is shown.

[0037] Figure 4 For the preferred embodiment of the present application, a top view of a source implantation mask is shown.

[0038] Figure 4-1 For the preferred embodiment of the present application, a cross-sectional view of AA' after etching with a source implantation mask is shown. Figure 4

[0039] Figure 4-2 For the preferred embodiment of the present application, a cross-sectional view of BB' after etching with a source implantation mask is shown. Figure 4

[0040] Figure 5 For the preferred embodiment of the present application, a top view of a sidewall is shown.

[0041] Figure 5-1 For the preferred embodiment of the present application, a cross-sectional view of AA' is shown. Figure 5

[0042] Figure 5-2 For the preferred embodiment of the present application, a cross-sectional view of BB' is shown. Figure 5 ​​​Cross-sectional view along BB' of Fig. 1 1 ;

[0043] Figure 6 In a preferred embodiment of the present application, the first type source implant region is formed as a top view;

[0044] Figure 6-1 In a preferred embodiment of the present application, Figure 6 Cross-sectional view along AA' of Fig. 1 1 ;

[0045] Figure 6-2 In a preferred embodiment of the present application, Figure 6 Cross-sectional view along BB' of Fig. 1 1 ;

[0046] Figure 7 In a preferred embodiment of the present application, a sub-flow diagram of step S5 is shown;

[0047] Figure 8 In a preferred embodiment of the present application, a top view of the structure formed after performing step S51 is shown;

[0048] Figure 8-1 In a preferred embodiment of the present application, Figure 8 Cross-sectional view along AA' of Fig. 1 1 ;

[0049] Figure 8-2 In a preferred embodiment of the present application, Figure 8 Cross-sectional view along BB' of Fig. 1 1 ;

[0050] Figure 9 In a preferred embodiment of the present application, a top view of the second type source implant region is shown;

[0051] Figure 9-1 In a preferred embodiment of the present application, Figure 9 Cross-sectional view along AA' of Fig. 1 1 ;

[0052] Figure 9-2 In a preferred embodiment of the present application, Figure 9 Cross-sectional view along BB' of Fig. 1 1.

[0053] Figure 10 In a preferred embodiment of the present application, a sub-flow diagram of step S6 is shown;

[0054] Figure 11 In a preferred embodiment of the present application, a top view of the source contact hole is shown;

[0055] Figure 11-1 In a preferred embodiment of the present application, Figure 11 Cross-sectional view along AA' of Fig. 1 1 ;

[0056] Figure 11-2 In a preferred embodiment of the present application, Figure 11 Cross-sectional view along BB' of Fig. 1 1

[0057] Figure 12 As a preferred embodiment of the present application, a cross-sectional view of the prepared high-density self-aligned silicon carbide MOS device cell at the contact hole of the second-type source injection region is shown in the figure;

[0058] Figure 13 As a preferred embodiment of the present application, a cross-sectional view of the prepared high-density self-aligned silicon carbide MOS device cell at the contact hole of the first-type source injection region is shown in the figure. DETAILED DESCRIPTION

[0059] The present application will be described in detail below with reference to the accompanying drawings and specific embodiments. The present application is not limited to this embodiment, and other embodiments can also fall within the scope of the present application as long as they comply with the main idea of the present application.

[0060] As a preferred embodiment of the present application, based on the above-mentioned problems existing in the prior art, a preparation method of a high-density self-aligned silicon carbide MOS device is provided, as shown in the figure, comprising: Figure 1

[0061] Step S1, providing a substrate, depositing a first polysilicon layer as a hard mask on both side edges of the upper surface of the substrate, and then performing ion implantation after etching the substrate to form a well region;

[0062] Step S2, growing a silicon dioxide layer around the first polysilicon layer, and then sequentially depositing a silicon nitride layer and a second polysilicon layer to form a first stack layer comprising the silicon dioxide layer, the silicon nitride layer and the second polysilicon layer, and a second stack layer comprising the silicon dioxide layer and the silicon nitride layer located on both sides of the first stack layer, the top of the first stack layer being flush with the top of the second stack layer;

[0063] Step S3, dividing the top region of the first stack layer and the second stack layer into two first regions and a second region located between the two first regions, and etching the second polysilicon layer of the second region, and then removing the silicon nitride layer of the first region and the second region and etching the silicon dioxide layer to form a side wall around the two first polysilicon layers, respectively;

[0064] Step S4, performing source region implantation in the first region with the first stack layer and the two side walls as a hard mask, and in the second region with the two side walls as a hard mask to form a double self-aligned first-type source injection region;

[0065] Step S5, forming a second-type source injection region on the substrate corresponding to the position of the first stack layer in the first region;

[0066] Step S6, forming a source electrode based on the first-type source injection region and the second-type source injection region, forming a polysilicon gate electrode, and forming a drain electrode on the lower surface of the substrate to prepare a high-density self-aligned silicon carbide MOS device.

[0067] ​Specifically, since the channel resistance accounts for a large proportion of the on-resistance of the silicon carbide MOSFET, the drift region resistance and the substrate resistance account for a relatively small proportion, especially for the power device with a low breakdown voltage such as 750V and 1200V for the silicon carbide material, the proportion of the channel resistance can reach 35% to 50% of the total on-resistance, and thus the on-resistance of the silicon carbide MOSFET device can be significantly reduced by considering reducing the channel resistance. Generally, reducing the cell size of the power device can increase the number of channels in the unit area and increase the current path, so as to reduce the channel resistance of the device and further reduce the on-resistance of the device. The present application provides a preparation method of a high-density self-aligned silicon carbide MOS device, which can reduce the cell size of the device and further reduce the on-resistance of the silicon carbide MOSFET device.

[0068] Further specifically, in the embodiment, the substrate is a silicon carbide substrate, including but not limited to 4H-SiC, 6H-SiC, 3C-SiC or 15R-SiC crystal type silicon carbide, and the corresponding well region can be N-type or P-type. Taking the N-type substrate required for manufacturing an N-type planar gate MOSFET as an example, a first polysilicon layer is deposited on both side edges of the upper surface of the substrate as a hard mask to etch the substrate and form a P-type well region by ion implantation. If a P-channel planar gate MOSFET is needed, the N-type and P-type in the description are simply interchanged.

[0069] Preferably, as shown in Figure 2 The substrate 1 is an epitaxial silicon carbide substrate, a corresponding mask can be used for lithography and etching to form a well region 2 by ion implantation. Subsequently, a layer of silicon dioxide 4 is grown around the first polysilicon layer 3 by thermal oxidation. As shown in Figure 3 The thickness of the silicon dioxide layer 4 determines the channel length of the designed high-density self-aligned silicon carbide MOS device, which can be set according to the electrical requirements of the device design. Subsequently, a certain thickness of a silicon nitride layer 5 and a second polysilicon layer 6 are deposited in sequence on the silicon dioxide layer 4, wherein the thickness a of the silicon nitride layer 5 determines the minimum implantation window of the first type source implantation region in the subsequent process, and the thickness of the second polysilicon layer 6 is appropriate to fill the MESA (mesa) between the two first polysilicon layers 3 in the cell region.

[0070] As can be seen, after the silicon nitride layer 5 and the second polysilicon layer 6 are sequentially deposited on the silicon dioxide layer 4, two kinds of stack structures are formed on the substrate 1, wherein, a first stack of the silicon dioxide layer 4, the silicon nitride layer 5 and the second polysilicon layer 6 is formed in the middle region above the well region 2, and a second stack of the first polysilicon layer 3, the silicon dioxide layer 4, the silicon nitride layer 5 and the second polysilicon layer 6 is formed in the edge region of the substrate. At this time, the upper surface of the silicon nitride layer 5 is completely covered by the second polysilicon layer 6. In order to facilitate subsequent etching, in the preferred embodiment of the present application, after the silicon nitride layer 5 and the second polysilicon layer 6 are sequentially deposited on the silicon dioxide layer 4 in step S2, the top of the first stack and the top of the second stack are made flush by performing chemical mechanical polishing on the second polysilicon layer 6, as shown in Figure 4-1 .

[0071] Further, in the preferred embodiment of the present application, as shown in Figure 4 , a source implantation mask is further provided, which includes two light opaque regions corresponding to the first regions 7 and a light transparent region corresponding to the second region 8 between the two light opaque regions,

[0072] In step S3, the top regions of the first stack and the second stack are divided into two first regions and a second region between the two first regions by the source implantation mask, and the second polysilicon layer of the second region is etched, and then the photoresist is removed.

[0073] Specifically, in the present embodiment, as shown in Figure 4-1 and Figure 4-2 , wherein the stack structure of the two first regions 7 remains unchanged, the second polysilicon layer 6 of the second region 8 is etched and the silicon nitride layer 5 is completely exposed.

[0074] In the preferred embodiment of the present application, after the second polysilicon layer 6 of the second region 8 is etched, in step S3, the silicon nitride layer 5 of the first region 7 and the second region 8 is then removed by wet etching to expose the underlying silicon dioxide layer 4, wherein the silicon nitride layer 5 below the second polysilicon layer 6 of the first region 7 is retained due to the presence of the top second polysilicon layer 6 of the first stack in this region. Then, the exposed silicon dioxide layer 4 is etched by dry etching to form a side wall 9 around each of the two first polysilicon layers 3, forming a structure as shown in Figure 5 , Figure 5-1 and Figure 5-2 . As can be seen, as shown in Figure 5-1 , two source region implantation windows 10 are formed in the first region 7, as shown in Figure 5-2As shown, a source region injection window 10 is formed in the second region 8, and then the first type source injection region 11 is formed by source region injection into the corresponding source region injection window in the first region with the first stack and the two side walls as hard masks and in the second region with the two side walls as hard masks, as shown in Figure 6 、 Figure 6-1 and Figure 6-2 . In the first region 7, the two source region injection windows 10 formed are the minimum injection windows of the first type source injection region 11, and the thickness of the silicon nitride layer 5 is the thickness of the two source region injection windows 10. Therefore, the thickness a of the silicon nitride layer 5 determines the minimum injection window of the first type source injection region, and the size of the first type source injection region can be very small and is not limited by the photolithography machine.

[0075] After the first type source injection region 11 is formed, the second type source injection region is formed on the substrate in the position corresponding to the first stack in the first region, as shown in Figure 7 . The step S5 includes:

[0076] Step S51, the two first polysilicon layers and the corresponding two side walls in the first region, the first stack in the first region, and the two first polysilicon layers and the corresponding two side walls in the second region are removed to expose the substrate, and then high-temperature activation and diffusion are performed.

[0077] Step S52, a third polysilicon layer is deposited on the substrate as a hard mask, and a contact region is etched on the substrate in the position corresponding to the first stack in the first region, and then source region injection is performed on the contact region to form the second type source injection region.

[0078] Specifically, in this embodiment, after the two first polysilicon layers 3, the corresponding two side walls 9, and the first stack in the first region 7 are removed, the well region 2, the two first type source injection regions 11, and part of the substrate 1 in the first region 7 are completely exposed. After the two first polysilicon layers 3 and the corresponding two side walls 9 in the second region 8 are removed, the well region 2, the first type source injection region 11, and part of the substrate 1 in the second region 8 are completely exposed, and the structure shown in Figure 8 、 Figure 8-1 and Figure 8-2 is formed, and then high-temperature activation and diffusion are performed. Then, the third polysilicon layer (not shown in the figure) deposited as a hard mask is used to etch a contact region between the two first type source injection regions 11 in the first region 7, and source region injection is performed to form the second type source injection region 12, and the structure shown in Figure 9 、 Figure 9-1 and Figure 9-2 is formed.

[0079] After the first type source implantation region 11 and the second type source implantation region 12 are formed, a source is formed based on the first type source implantation region and the second type source implantation region, a polysilicon gate is formed, and a drain is formed on the lower surface of the substrate to obtain the high-density self-aligned silicon carbide MOS device. In the preferred embodiment of the present application, as shown in Figure 10 Step S6 includes:

[0080] Step S61, a field oxide layer is deposited on the substrate, and active regions are etched on the positions corresponding to the first type source implantation region and the second type source implantation region.

[0081] Step S62, a sacrificial oxide layer is grown on the active regions, and then a gate oxide layer is grown after the sacrificial oxide layer is removed, and then a fourth polysilicon layer is deposited to etch the polysilicon gate.

[0082] Step S63, a dielectric layer is deposited on the fourth polysilicon layer, and gate and source contact holes are etched on the positions corresponding to the active regions.

[0083] Step S64, a top layer metal is sputtered on the dielectric layer and the source contact hole, and the top layer metal is etched to form the source and the gate.

[0084] Step S65, a passivation layer is deposited on the top layer metal as an oxide layer, and the passivation layer is etched to complete the fabrication of the top layer structure.

[0085] Step S66, a back metal is deposited on the lower surface of the substrate to form a drain to obtain the high-density self-aligned silicon carbide MOS device.

[0086] Specifically, in the embodiment, as shown in Figure 11 , Figure 11-1 , Figure 11-2 The field oxide layer and the sacrificial oxide layer are not shown in the figure. In step S62, after the field oxide layer 13 is grown and the fourth polysilicon layer 14 is deposited, the polysilicon gate is etched by using a corresponding mask and lithography. Similarly, after the dielectric layer 15 is deposited on the fourth polysilicon layer 14, the gate and source contact hole 16 is etched by using a corresponding mask and lithography. Further, as shown in Figure 12 and Figure 13 The top layer metal 17 is sputtered on the dielectric layer 15, and then the top layer metal 17 is etched by using a corresponding mask and lithography to form the source and the gate of the device. The gate, the source, the passivation layer, and the drain are not shown in the figure and are not the main points of the present technical solution.

[0087] In the preferred embodiment of the present application, in step S51, the two first polysilicon layers and the corresponding two side walls in the first region, the first stack in the first region, and the two first polysilicon layers and the corresponding two side walls in the second region are removed by using a wet method.

[0088] In the preferred embodiment of the present application, the sacrificial oxide layer is removed by wet etching in step S62.

[0089] In the preferred embodiment of the present application, the back metal is deposited on the lower surface of the substrate to form the drain by sputtering or evaporation in step S66.

[0090] In the preferred embodiment of the present application, the first type of source implantation region is N-type source implantation region, and the second type of source implantation region is P-type source implantation region, so that the high-density self-aligned silicon carbide MOS device is an N-type MOS device.

[0091] or the first type of source implantation region is P-type source implantation region, and the second type of source implantation region is N-type source implantation region, so that the high-density self-aligned silicon carbide MOS device is a P-type MOS device.

[0092] The above description is only the preferred embodiment of the present application, and is not intended to limit the implementation and protection scope of the present application. It should be realized by those skilled in the art that any equivalent replacement and obvious changes made according to the present application and drawings should be included in the protection scope of the present application.

Claims

1. A method of fabricating a self-aligned silicon carbide MOS device, comprising: The method comprises the following steps: S1, providing a substrate, depositing a first polysilicon layer as a hard mask on both side edges of the upper surface of the substrate, and performing ion implantation after etching the substrate to form a well region; S2, growing a silicon dioxide layer around the first polysilicon layer, then sequentially depositing a silicon nitride layer and a second polysilicon layer to form a first stack comprising the silicon dioxide layer, the silicon nitride layer and the second polysilicon layer, and a second stack comprising the silicon dioxide layer and the silicon nitride layer on both sides of the first stack, the top of the first stack being flush with the top of the second stack; S3, dividing the top region of the first stack and the second stack into two first regions and a second region between the two first regions in the length direction of the active region, etching the second polysilicon layer of the second region, then removing the silicon nitride layer of the first region and the second region and etching the silicon dioxide layer to form a side wall around the two first polysilicon layers respectively; S4, performing source region implantation in the first region with the first stack and the two side walls as a hard mask, and in the second region with the two side walls as a hard mask to form a double self-aligned first type source implantation region; S5, forming a second type source implantation region on the substrate corresponding to the position of the first stack in the first region; S6, forming a source electrode based on the first type source implantation region and the second type source implantation region, forming a polysilicon gate electrode, and forming a drain electrode on the lower surface of the substrate to obtain the self-aligned silicon carbide MOS device.

2. The production method according to claim 1, characterized by, In the step S2, after sequentially depositing the silicon nitride layer and the second polysilicon layer on the silicon dioxide layer, the top of the first stack is flush with the top of the second stack by chemical mechanical polishing of the second polysilicon layer.

3. The preparation method according to claim 1, characterized in that, A source implantation mask is also provided, comprising two light-tight regions corresponding to the first regions and a light-transmitting region corresponding to the second region between the two light-tight regions, In the step S3, the top region of the first stack and the second stack is divided into two first regions and a second region between the two first regions by the source implantation mask, and the second polysilicon layer of the second region is etched.

4. The method of claim 1, wherein, The step S5 comprises: S51, removing the two first polysilicon layers and the corresponding two side walls of the first region, the first stack of the first region, and the two first polysilicon layers and the corresponding two side walls of the second region to expose the substrate, and then performing high-temperature activation and diffusion; S52, depositing a third polysilicon layer as a hard mask on the substrate, etching a contact region on the substrate corresponding to the position of the first stack in the first region, and then performing source region implantation on the contact region to form the second type source implantation region.

5. The preparation method according to claim 1, characterized in that, The step S6 comprises: S61, depositing a field oxide layer on the substrate, and etching an active region corresponding to the positions of the first type source implantation region and the second type source implantation region. Step S62, growing a sacrificial oxide layer on the active region, then removing the sacrificial oxide layer and growing a gate oxide layer, then depositing a fourth polysilicon layer to etch a polysilicon gate; Step S63, depositing a dielectric layer on the fourth polysilicon layer, and etching a gate and source contact hole corresponding to the location of the active region; Step S64, sputtering a top layer of metal on the dielectric layer and the source contact hole, and etching the top layer of metal to form the source and the gate; Step S65, depositing an oxide layer on the top layer of metal as a passivation layer, and etching the passivation layer to complete the fabrication of the top layer structure; Step S66, depositing a back metal on the lower surface of the substrate to form the drain, to obtain the self-aligned silicon carbide MOS device.

6. The method of claim 1, wherein, In step S3, the silicon nitride layer is removed by wet etching, and the silicon dioxide layer is etched by dry etching.

7. The preparation method according to claim 4, characterized in that, In step S51, the two first polysilicon layers and the corresponding two sidewalls in the first region, the first stack in the first region, and the two first polysilicon layers and the corresponding two sidewalls in the second region are removed by wet etching.

8. The preparation method according to claim 5, characterized in that, In step S62, the sacrificial oxide layer is removed by wet etching.

9. The preparation method according to claim 5, characterized in that, In step S66, the back metal is deposited on the lower surface of the substrate to form the drain by sputtering or evaporation.

10. The method of claim 1, wherein, The first type of source implant region is an N-type source implant region, and the second type of source implant region is a P-type source implant region, to obtain an N-type MOS device; Or the first type of source implant region is a P-type source implant region, and the second type of source implant region is an N-type source implant region, to obtain a P-type MOS device.

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