A silicon-based III-V axial heterojunction vertical nanowire array APD device and production process

Abstract

The present invention discloses a silicon-based III-V axial heterojunction vertical nanowire array device and a production process that can improve the heterojunction interface quality of Si and InGaAs and has low dark current, low noise and high performance. The silicon-based III-V axial heterojunction vertical nanowire array device comprises a substrate; an insulating dielectric layer is arranged on the substrate; a vertical nanowire array is arranged in the insulating dielectric layer; the production process adopts a silicon dioxide nanotube template-assisted epitaxy method and a multiplication layer separation structure (SAGCM) to prepare a Si-InGaAs axial heterojunction vertical nanowire array on an n+Si(111) substrate; the silicon-based III-V axial heterojunction vertical nanowire array device and the production process use silicon as a substrate, the process is compatible with the existing integrated circuit industry, and has the prospect of industrialization.

Description

Technical Field

[0001] The invention relates to a semiconductor device for detecting optical signals, in particular to a silicon-based III-V group axial heterojunction vertical nanowire array APD device and a production process. Background Art

[0002] Avalanche Photodiode (APD) refers to a semiconductor device that uses the avalanche multiplication effect of photogenerated carriers in semiconductors under strong electric fields to amplify light signals, thereby realizing the detection of weak light signals. APD has high sensitivity and can detect weak light signals without the need for additional external amplifiers. Near-infrared band APD has been widely used in military and civilian fields such as quantum communication, atmospheric monitoring, infrared remote sensing, autonomous driving, biomedicine, and aerospace. Because near-infrared band APD has important applications and scientific prospects, it has received widespread attention from governments and industries around the world and is a hot frontier area of ​​international research.

[0003] Noise and speed are the major bottlenecks facing near-infrared APDs at this stage, and the after-pulse effect is also one of the key factors affecting the operating speed of APDs in Geiger mode. Although some complex active suppression systems have been developed for the after-pulse effect, the detector count rate rarely exceeds 100kHz. This is not suitable for high-speed detection and systems where the time for photons to arrive at the detector is unknown, such as lidar and time-resolved fluorescence spectroscopy.

[0004] For traditional planar near-infrared avalanche photodetectors, if the heterogeneous crystalline material grows beyond the critical thickness, the lattice mismatch will lead to the formation of dislocations in the material, which will seriously affect the performance of the device. Due to the limitation of lattice matching, the design and detection wavelength range of planar near-infrared APD devices are greatly restricted.

[0005] At present, the most widely used APD in the near-infrared band is the InP-based InGaAs absorption layer, gradient layer, charge layer, and multiplication layer separation structure (Separate Absorption Grading Charge and Multiplication, SAGCM), which has the advantages of high gain-bandwidth product, high quantum efficiency and low dark current. However, the planar InP / InGaAs SAGCM APD is a high-quality detector with InGaAs as the absorption layer. Due to the need to match the InP substrate lattice, the composition is limited to In=0.53, which limits the detection wavelength range. If the lattice does not match, a large number of dislocations will be generated, which will seriously affect the performance of the device. In the near-infrared band, the absorption coefficient of InGaAs is not high enough, such as the optical fiber communication band, ~10 4 cm-1 In order to obtain an external quantum efficiency of >90%, the absorption region thickness needs to be 2.5μm, which limits the operating speed of the device. Usually, there are many deep energy level defects in InP epitaxial materials. In the Geiger working mode, a large number of carriers generated by avalanche are captured by these deep energy level defects. After the measured light signal stops, these carriers escape from the trap and continue to cause avalanche, resulting in a serious after-pulse effect, which limits the photon counting frequency of the device. InP is used as a multiplication layer, and the collision ionization coefficients of holes and electrons in the material are slightly different, resulting in large device noise. InP is used as a substrate, which is expensive, limiting the scope of use of the device and making it difficult to apply it to low-cost civilian products.

[0006] In summary, the currently widely used near-infrared planar InP-based InGaAs APD has bottlenecks such as limited detection wavelength range, high noise and severe after-pulse effect, which greatly restricts its further development.

[0007] In contrast, for nanowire near-infrared avalanche photodetectors, the lattice mismatch stress of the material can be effectively released on the surface of the nanowire. The critical thickness of axial and core-shell nanowire heterostructures is greater than that of planar-grown thin film samples. Since the lattice mismatch that nanowires can tolerate is relatively large, this brings great flexibility to the selection of substrates and the design of heterojunctions. Therefore, the use of nanowire materials can reduce the problem of limited wavelength range of detectors caused by lattice matching. Nanowire structures provide new ideas for solving the problem. Summary of the invention

[0008] The technical problem to be solved by the present invention is to provide a silicon-based III-V axial heterojunction vertical nanowire array APD device and a production process which can improve the heterojunction interface quality of Si and InGaAs and have low dark current, low noise and high performance.

[0009] The technical solution adopted by the present invention to solve the technical problem is: a silicon-based III-V group axial heterojunction vertical nanowire array APD device, comprising a substrate; an insulating dielectric layer is arranged on the substrate; a vertical nanowire array is arranged in the insulating dielectric layer;

[0010] The nanowire array comprises a contact layer, an absorption layer, a gradient layer, a charge layer, and a multiplication layer from top to bottom; the outer layer of the nanowire array is provided with a SiO2 shell;

[0011] The upper surface of the insulating dielectric layer is provided with a metal vapor-deposited layer to form an upper electrode; the upper end of each nanowire in the nanowire array extends out of the insulating dielectric layer; the outer surface of one end of the nanowire extending out of the insulating dielectric layer is provided with a metal vapor-deposited layer; the metal vapor-deposited layer is electrically connected to the upper electrode;

[0012] The substrate on the other side of the insulating dielectric layer forms a lower electrode; and the upper surface of the insulating dielectric layer is provided with a light inlet corresponding to each nanowire in the nanowire array.

[0013] Furthermore, the light inlet includes a first metal vapor deposition layer opening on the insulating dielectric layer at one side of the nanowire and a second metal vapor deposition layer opening on the nanowire at the same side.

[0014] Furthermore, the thickness of the contact layer is 100-300nm; the thickness of the absorption layer is 400-1000nm; the thickness of the gradient layer is 40-60nm; the thickness of the charge layer is 50-300nm; the thickness of the multiplication layer is 400-1000nm; and the thickness of the SiO2 shell is 10-20nm.

[0015] Furthermore, the substrate is n+Si(111); the contact layer is heavily doped p+In y Ga 1-y As;

[0016] The absorption layer is unintentionally doped InGaAs; the gradient layer is In x Ga 1-x As; the charge layer is p-type Si; and the multiplication layer is unintentionally doped Si.

[0017] The present invention also discloses a production process of a silicon-based III-V axial heterojunction vertical nanowire array APD device, comprising the following steps:

[0018] S1, depositing amorphous silicon by magnetron sputtering;

[0019] S2, using EBL and reactive ion etching technology to prepare Si and amorphous silicon axial vertical nanowire arrays;

[0020] S3, depositing a SiO2 nanotube shell layer on the Si and amorphous silicon axial vertical nanowire arrays using plasma enhanced chemical vapor deposition (PECVD) technology;

[0021] S4, using dry etching to open the top of the nanowire, and then etching away the amorphous silicon nanowire portion on the top of the Si nanowire;

[0022] S5, etching with chemical reagents to obtain a silicon dioxide nanotube array template;

[0023] S6. Epitaxially grow a graded layer In on top of the Si nanowire in the nanotube using CVD or MBE technology x Ga 1-x As, absorption layer InGaAs and heavily doped p+In y Ga 1-yAs electrode contact layer, growing Si-InGaAs nanowire APD;

[0024] S7. Fill the prepared high-quality Si-InGaAs vertical heterojunction nanowire array material with insulating dielectric benzocyclobutene (BCB) and prepare upper and lower electrodes.

[0025] The beneficial effects of the present invention are that it has the following advantages over the prior art:

[0026] 1. The silicon-based III-V axial heterojunction vertical nanowire array APD device and production process described in the present invention adopts the SAGCM type silicon-based Si-InGaAs axial heterojunction vertical nanowire array APD structure. The vertical nanowire array can enhance the absorption of light and improve the working speed of the device. The SAGCM nanowire array APD structure reduces the number of carriers captured by the trap center during the avalanche multiplication process because the avalanche occurs in a tiny area of ​​a single nanowire, which can reduce the device after-pulse effect and dark current. The method of preparing a SAGCM type Si-InGaAs axial heterojunction vertical nanowire array APD device on an n+Si(111) substrate using a silicon dioxide nanotube template-assisted epitaxy is proposed for the first time.

[0027] 2. The silicon-based III-V axial heterojunction vertical nanowire array APD device and production process described in the present invention adopts a silicon dioxide nanotube template to assist in growth, thereby eliminating the lateral growth problem of the axial heterojunction nanowire. Since the growth of the III-V nanowire material in the nanotube is similar to the layered growth mode of the bulk material, there is no longitudinal migration of atoms or molecules on the surface of the nanowire during the heterojunction growth, which can fundamentally avoid the lateral growth problem of the axial heterojunction nanowire. Since the nanotube wall is thin, the stress can be released on the nanotube surface, which helps to obtain a high-quality heterojunction.

[0028] 3. The silicon-based III-V axial heterojunction vertical nanowire array APD device and production process described in the present invention adopt a structure in which InGaAs nanowires are epitaxially grown on the top of Si nanowires. Stress can be effectively released on the surface of the nanowires, and the InGaAs and Si-InGaAs heterojunction interfaces grown on the silicon nanowires can obtain very high crystal quality. APB (antiphase boundary) defects and threading dislocations that have an important influence on optoelectronic performance are suppressed, which helps to improve device performance.

[0029] 4. The silicon-based III-V axial heterojunction vertical nanowire array APD device and production process described in the present invention use silicon as a substrate, and the process is compatible with the existing integrated circuit industry and has industrial prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1is a three-dimensional diagram of a silicon-based III-V axial heterojunction vertical nanowire array APD device according to an embodiment of the present invention;

[0031] Figure 2 Schematic diagram of the structure of a silicon-based III-V group axial heterojunction vertical nanowire array APD device according to an embodiment of the present invention;

[0032] Figure 3 is a schematic diagram of the structure of a single nanowire APD in an embodiment of the present invention;

[0033] Figure 4 It is a simplified flow chart of the production process of a silicon-based III-V axial heterojunction vertical nanowire array APD device in an embodiment of the present invention; DETAILED DESCRIPTION

[0034] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0035] like Figures 1 to 4 As shown, a silicon-based III-V axial heterojunction vertical nanowire array APD device according to the present invention comprises a substrate 100; an insulating dielectric layer 200 is disposed on the substrate 100; and a vertical nanowire array 300 is disposed in the insulating dielectric layer 200;

[0036] The nanowire array 300 includes a contact layer 305, an absorption layer 304, a gradient layer 303, a charge layer 302, and a multiplication layer 301 from top to bottom; the outer layer of the nanowire array 300 is provided with a SiO2 shell 306;

[0037] The upper surface of the insulating dielectric layer 200 is provided with a metal vapor deposition layer to form an upper electrode 500; the upper end of each nanowire in the nanowire array 300 extends out of the insulating dielectric layer 200; the outer surface of one end of the nanowire extending out of the insulating dielectric layer 200 is provided with a metal vapor deposition layer; the metal vapor deposition layer is electrically connected to the upper electrode 500;

[0038] The substrate 100 on the other side of the insulating dielectric layer 200 forms a lower electrode 400 ; the upper surface of the insulating dielectric layer 200 is provided with a light inlet 600 corresponding to each nanowire in the nanowire array 300 .

[0039] Specifically, the light inlet 600 includes a first metal vapor deposition layer opening 601 on one side of the nanowire on the insulating dielectric layer 200 and a second metal vapor deposition layer opening 602 on the side of the nanowire.

[0040] Specifically, the thickness of the contact layer 305 is 100-300nm; the thickness of the absorption layer 304 is 400-1000nm; the thickness of the gradient layer 303 is 40-60nm; the thickness of the charge layer 302 is 50-300nm; the thickness of the multiplication layer 301 is 400-1000nm. The thickness of the SiO2 shell 306 is 10-20nm. The substrate 100 is n+Si(111); the contact layer 305 is heavily doped with p+In y Ga 1-y As;

[0041] The absorption layer 304 is unintentionally doped InGaAs; the gradient layer 303 is In x Ga 1-x As; the charge layer 302 is p-type Si; the multiplication layer 301 is unintentionally doped Si.

[0042] The single nanowire APD structure of the silicon-based III-V group axial heterojunction vertical nanowire array APD device of the present invention is as follows: Figure 3 As shown, first, the heavily doped p+In y Ga 1-y As and the underlying n+Si(111) substrate serve as the device electrodes, followed by unintentionally doped InGaAs as the APD light absorption layer; In x Ga 1-x As is used as a gradient layer to reduce the energy band barrier between the absorption layer and the multiplication layer, thereby increasing the carrier transport speed; p-type Si is used as a charge layer to adjust the relative electric field strength between the absorption layer and the multiplication layer; unintentionally doped Si is used as a multiplication layer to produce avalanche multiplication and amplify the signal; the outer layer of the nanowire is a SiO2 nanotube template, which also serves as a shell layer and as a passivation layer of the nanowire APD to suppress the influence of surface states on the device.

[0043] The structure diagram of the nanowire array APD device of a silicon-based III-V group axial heterojunction vertical nanowire array APD device of the present invention is as follows: Figure 3 As shown, the top of the nanowire and the substrate are evaporated with metal as electrodes. When the top electrode is evaporated by magnetron sputtering, the sample is tilted 45 degrees. The shaded area in the figure is the part without metal coating, which can be used as a light incident window. The middle part of the nanowire array is filled with benzocyclobutene BCB (Benzocyclobutene), which plays the role of passivating the SiO2 shell and insulating between the electrodes, which can reduce the surface leakage current and improve the performance of the device.

[0044] In the previous planar InP / InGaAs APD, InP was used as the multiplication layer. The impact ionization coefficients of holes and electrons in InP were slightly different, resulting in large noise. There were many deep energy level defects in the InP epitaxial material, and the after-pulse effect was serious when working in the Geiger mode.

[0045] The silicon-based III-V axial heterojunction vertical nanowire array APD device described in the present invention uses Si nanowires as multiplication layers. The impact ionization coefficients of holes and electrons in silicon differ greatly, which can reduce noise. The trap energy and density in silicon are relatively low, which can reduce the after-pulse effect. The present invention adopts a structure in which InGaAs nanowires are epitaxially grown on the top of Si nanowires. Stress can be effectively released on the surface of the nanowires. The InGaAs grown on the silicon nanowires and the Si-InGaAs heterojunction interface can obtain very high crystal quality. APB defects and threading dislocations that have an important influence on optoelectronic performance are suppressed, which helps to improve device performance.

[0046] The silicon-based III-V group axial heterojunction vertical nanowire array APD device described in the present invention adopts a SAGCM type silicon-based Si-InGaAs axial heterojunction vertical nanowire array APD structure, which can reduce the device dark current and after-pulse effect and improve the device operating speed on the basis of achieving efficient light absorption and avalanche multiplication amplification.

[0047] The present invention also provides a production process of a silicon-based III-V group axial heterojunction vertical nanowire array APD device, comprising the following steps:

[0048] S1, depositing amorphous silicon by magnetron sputtering;

[0049] S2, using EBL and reactive ion etching technology to prepare Si and amorphous silicon axial vertical nanowire arrays;

[0050] S3, depositing a SiO2 nanotube shell layer on the Si and amorphous silicon axial vertical nanowire arrays using plasma enhanced chemical vapor deposition (PECVD) technology;

[0051] S4, using dry etching to open the top of the nanowire, and then etching away the amorphous silicon nanowire portion on the top of the Si nanowire;

[0052] S5, etching with chemical reagents to obtain a silicon dioxide nanotube array template;

[0053] S6. Epitaxially grow a graded layer In on top of the Si nanowire in the nanotube using CVD or MBE technology x Ga 1-x As, absorption layer InGaAs and heavily doped p+In y Ga 1-yAs electrode contact layer, growing Si-InGaAs nanowire APD;

[0054] S7. Fill the prepared high-quality Si-InGaAs vertical heterojunction nanowire array material with insulating dielectric benzocyclobutene (BCB) and prepare upper and lower electrodes.

[0055] The production process of a silicon-based III-V axial heterojunction vertical nanowire array APD device described in the present invention adopts a silicon dioxide nanotube template-assisted epitaxy method and a multiplication layer separation structure SAGCM to prepare a Si-InGaAs axial heterojunction vertical nanowire array APD on an n+Si(111) substrate to solve the bottleneck problems faced by traditional planar near-infrared band InP / InGaAs APDs, such as limited detection wavelength range, large noise and severe after-pulse effect.

[0056] The present invention patent uses nanotubes to assist in the preparation of nanowire APD. Other materials can be selected for the material. For example, the substrate can also use P+Si or other more extensive other substrates. In addition, the device structure uses SAGCM, but due to the different electron and hole ionization coefficients of different multiplication zone materials, the order and direction of the functional layers of the device will also be different, that is, the layout of the device functional layer is determined by the hole / electron ionization coefficient ratio. In addition, the method of using nanotubes to assist the growth of nanowires can also be applied to other device structures.

Claims

1. A silicon-based III-V axial heterojunction vertical nanowire array APD device, characterized in that: It comprises a substrate (100); an insulating dielectric layer (200) is arranged on the substrate (100); and a vertical nanowire array (300) is arranged in the insulating dielectric layer (200); The nanowire array (300) comprises, from top to bottom, a contact layer (305), an absorption layer (304), a gradient layer (303), a charge layer (302), and a multiplication layer (301); the outer layer of the nanowire array (300) is provided with a SiO2 shell (306); The upper surface of the insulating dielectric layer (200) is provided with a metal vapor deposition layer to form an upper electrode (500); the upper end of each nanowire in the nanowire array (300) extends out of the insulating dielectric layer (200); the outer surface of one end of the nanowire extending out of the insulating dielectric layer (200) is provided with a metal vapor deposition layer; the metal vapor deposition layer is electrically connected to the upper electrode (500); The substrate (100) on the other side of the insulating dielectric layer (200) forms a lower electrode (400); and the upper surface of the insulating dielectric layer (200) is provided with a light inlet (600) corresponding to each nanowire in the nanowire array (300).

2. The silicon-based III-V axial heterojunction vertical nanowire array APD device according to claim 1, characterized in that: The light inlet (600) comprises a first metal vapor deposition layer opening (601) on the insulating medium layer (200) on one side of the nanowire and a second metal vapor deposition layer opening (602) on the same side of the nanowire.

3. The silicon-based III-V axial heterojunction vertical nanowire array APD device according to claim 2, characterized in that: The thickness of the contact layer (305) is 100-300nm; the thickness of the absorption layer (304) is 400-1000nm; the thickness of the gradient layer (303) is 40-60nm; the thickness of the charge layer (302) is 50-300nm; the thickness of the multiplication layer (301) is 400-1000nm; and the thickness of the SiO2 shell (306) is 10-20nm.

4. The silicon-based III-V axial heterojunction vertical nanowire array APD device according to claim 3, characterized in that: The substrate (100) is n+Si (111); the contact layer (305) is heavily doped p+In y Ga 1-y As; The absorption layer (304) is unintentionally doped InGaAs; the gradient layer (303) is In x Ga 1-x As; the charge layer (302) is p-type Si; and the multiplication layer (301) is unintentionally doped Si.

5. The production process of the silicon-based III-V axial heterojunction vertical nanowire array APD device according to claim 1, 2, 3 or 4, characterized in that: The following steps are involved: S1, depositing amorphous silicon by magnetron sputtering; S2, using EBL and reactive ion etching technology to prepare Si and amorphous silicon axial vertical nanowire arrays; S3, depositing a SiO2 nanotube shell layer on the Si and amorphous silicon axial vertical nanowire arrays using plasma enhanced chemical vapor deposition (PECVD) technology; S4, using dry etching to open the top of the nanowire, and then etching away the amorphous silicon nanowire portion on the top of the Si nanowire; S5, etching with chemical reagents to obtain a silicon dioxide nanotube array template; S6. Epitaxially grow a graded layer In on top of the Si nanowire in the nanotube using CVD or MBE technology x Ga 1-x As, absorption layer InGaAs and heavily doped p+In y Ga 1-y As electrode contact layer, growing Si-InGaAs nanowire APD; S7. Fill the prepared high-quality Si-InGaAs vertical heterojunction nanowire array material with insulating dielectric benzocyclobutene (BCB) and prepare upper and lower electrodes.

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