Chip testing methods, systems, devices, and media

Abstract

The present disclosure provides a chip testing method, system, device and medium, relating to the technical field of chip testing. The method is applied to a chip testing system, which comprises a test board, and the test board is provided with a plurality of groups of test units independent of each other, each group of test units comprises at least one driving power supply for providing driving signals to a plurality of to-be-tested chips, and the state of at least one driving power supply in each group of test units is acquired. If at least one driving power supply in a group of test units is found to be abnormal, the at least one driving power supply is controlled to be turned off, and the group of test units is controlled to be turned off. The chip testing method, system, device and medium provided by the present disclosure can acquire the state of the driving power supply in real time, accurately turn off the abnormal driving power supply and the test unit related to the abnormal driving power supply when the driving power supply is abnormal, improve the production capacity, and reduce the testing cost.

Description

Technical Field

[0001] This disclosure relates to the field of chip testing technology, and in particular to a chip testing method, a chip testing system, an electronic device, and a computer-readable storage medium. Background Technology

[0002] A chip, also known as a microcircuit, microchip, or integrated circuit, is a small silicon wafer containing integrated circuits. It is a crucial component of electronic devices such as computers. Due to its unique structure, complex manufacturing process, and intricate procedures, potential defects can easily occur during chip production, preventing the chip from meeting standard requirements and causing malfunctions during use. To ensure chip quality, various tests are typically performed, including electrical parameter measurements and functional tests, to differentiate product grades.

[0003] In related technologies, testing equipment is typically used to automatically test chips, classifying them into good, substandard, and defective products based on the test results. During testing, the testing machine monitors the current of each test board. When an abnormal overload is detected, the testing resources on the entire test board are shut down, thus protecting the testing equipment. However, this anomaly handling method results in most normal chips being deemed defective due to the influence of some abnormal chips, preventing the completion of testing and reducing product yield.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This disclosure provides a chip testing method, a chip testing system, an electronic device, and a computer-readable storage medium. When the driving power supply is abnormal, it can accurately shut down the abnormal driving power supply and the test units related to the abnormal driving power supply, thereby increasing production capacity and reducing testing costs. It overcomes, to some extent, the problem that existing chip testing methods provided in related technologies cannot complete the testing of some normal chips and reduce product yield.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0007] According to one aspect of this disclosure, a chip testing method is provided, applied to a chip testing system, the chip testing system including a test board, the test board having multiple sets of independent test units, each set of test units including at least one drive power supply for providing drive signals to multiple chips under test, the method comprising:

[0008] Acquire the status of at least one of the drive power supplies within each test unit group;

[0009] If at least one drive power supply in a set of test units is found to be abnormal, then the at least one drive power supply is shut down, and the set of test units is shut down.

[0010] In one embodiment of this disclosure, after detecting at least one drive power supply anomaly within a set of test units, the method further includes:

[0011] Obtain the driving mode of the at least one abnormal driving power supply;

[0012] When the driving mode of the at least one abnormal driving power supply is the first driving mode, the operation of controlling the shutdown of the at least one driving power supply and controlling the shutdown of the group of test units is executed.

[0013] In one embodiment of this disclosure, the method further includes:

[0014] When the driving mode of the at least one abnormal driving power supply is the second driving mode, the control shuts down multiple sets of the test units.

[0015] In one embodiment of this disclosure, the driving mode of the power supply is stored in a status register.

[0016] The driving method for obtaining the at least one abnormal driving power supply includes:

[0017] Obtain the driving mode of the abnormal driving power supply from the status register; or, receive the driving mode of the abnormal driving power supply reported by the status register.

[0018] In one embodiment of this disclosure, obtaining the state of at least one of the drive power supplies within each test unit group includes:

[0019] The status of the drive power supply is periodically obtained from the status register.

[0020] In one embodiment of this disclosure, obtaining the state of at least one of the drive power supplies within each test unit group includes:

[0021] When the status of the drive power supply stored in the status register is an abnormal status, the abnormal status of the drive power supply reported by the status register is received.

[0022] In one embodiment of this disclosure, the method further includes:

[0023] The status register stores the status of the drive power supply, wherein the status register is updated to reflect the status of the drive power supply after a status change.

[0024] In one embodiment of this disclosure, before acquiring the state of at least one of the drive power supplies within each set of test units, the method includes:

[0025] During the test, the electrical signal output by at least one of the drive power supplies in each test unit is monitored in real time.

[0026] When the electrical signal output by the drive power supply meets the preset overload protection conditions, the drive power supply is determined to be abnormal.

[0027] In one embodiment of this disclosure, the method further includes:

[0028] When the electrical signal output by the drive power supply does not meet the preset overload protection condition, the drive power supply is determined to be normal.

[0029] In one embodiment of this disclosure, before the control shuts down the set of test units, the method further includes:

[0030] Obtain a correspondence table, wherein the correspondence table is used to indicate the correspondence between at least one of the driving power supplies and each group of test units;

[0031] According to the correspondence table, find the test unit corresponding to the at least one drive power supply in the abnormal state;

[0032] The control to shut down the group of test units includes:

[0033] The test unit found by the control is turned off.

[0034] In one embodiment of this disclosure, before obtaining the correspondence table, the method further includes:

[0035] A correspondence table is constructed, wherein the correspondence table is used to indicate the correspondence between at least one of the driving power supplies and each group of test units.

[0036] According to another aspect of this disclosure, a chip testing system is provided, including a test board and a control module. The test board is provided with multiple sets of independent test units, and each set of test units includes at least one drive power supply for providing drive signals to multiple chips under test.

[0037] The control module is used to acquire the status of at least one of the driving power supplies in each group of test units; if at least one driving power supply in a group of test units is found to be abnormal, the control module controls the shutdown of the at least one driving power supply and controls the shutdown of the group of test units.

[0038] In one embodiment of this disclosure, a drive power supply in each test unit is electrically connected to multiple chips under test via a relay, and the relay is electrically connected to the control module.

[0039] According to another aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the chip testing method described above by executing the executable instructions.

[0040] According to another aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the chip testing method described above.

[0041] According to another aspect of this disclosure, a computer program product is provided, including executable instructions stored in a computer-readable storage medium, wherein a processor of an electronic device reads the executable instructions from the computer-readable storage medium and executes the executable instructions, causing the electronic device to perform any of the chip testing methods described in the above embodiments.

[0042] This disclosure provides a chip testing method, system, device, and medium. By setting multiple independent test units on a test board, with at least one driving power supply in each test unit, the status of the driving power supply is acquired in real time. When the driving power supply is found to be in an abnormal state, the abnormal driving power supply and the test unit associated with the abnormal driving power supply are precisely shut down. Compared with related technologies, this method can effectively screen out normal chips that are not affected by the abnormal driving power supply, thereby continuing to test the normal chips, increasing production capacity and reducing testing costs.

[0043] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0044] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0045] Figure 1 A framework diagram of the driver section of a chip testing system in related technologies is shown;

[0046] Figure 2 This diagram illustrates a framework of the driver section of a chip testing system provided in an embodiment of this disclosure.

[0047] Figure 3 This diagram illustrates a test board structure according to an embodiment of the present disclosure.

[0048] Figure 4 This diagram illustrates another test board structure provided in an embodiment of the present disclosure.

[0049] Figure 5 This diagram shows a flowchart of a chip testing method provided in an embodiment of the present disclosure;

[0050] Figure 6 This diagram illustrates a flowchart of another chip testing method provided in an embodiment of this disclosure;

[0051] Figure 7 This diagram illustrates a flowchart of yet another chip testing method provided in an embodiment of the present disclosure;

[0052] Figure 8 This diagram illustrates the structure of a chip testing system provided in an embodiment of the present disclosure.

[0053] Figure 9 A frame diagram of an electronic device provided in an embodiment of this disclosure is shown;

[0054] Figure 10 This diagram illustrates a computer program product provided in an embodiment of the present disclosure. Detailed Implementation

[0055] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0056] The terms "first" and "second" used in this document are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly stated.

[0057] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0058] The following disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0059] Figure 1 This diagram illustrates the framework of the driver section of a chip testing system in related technologies. (Example:) Figure 1 As shown, the chip testing system in the related technology includes a test board (not shown in the attached figure) and a driver section. The test board has multiple chips under test (DUTs) mounted on it, and the driver section provides test signals to the multiple DUTs to enable them to execute corresponding test programs. It should be noted that the test program depends on the test items, and test items may include one or more, such as read / write operation tests and aging tests of the DUTs.

[0060] like Figure 1 As shown, the driving part of the chip testing system in the related technology includes a driving power supply 101, an electrical parameter testing module 102, an anomaly judgment module 103, a status register 104, and an alarm operation module 105, etc.

[0061] During chip testing, the driving power supply 101 is used to provide driving signals and power to the chip under test. There may be one or more driving power supplies 101, and each driving power supply 101 may include at least one driving signal output. Figure 1 In this system, two drive power supplies are included. Figure 1 The following explanation will be based on the example of drive power supply 1011 and drive power supply 1012, each of which includes two drive signal outputs.

[0062] The first drive signal output of the drive power supply 101 can be adjusted independently, while the second drive signal output cannot be adjusted independently. Therefore, the two drive power supplies 101 can be combined to produce three outputs: drive power supply 1011 can be adjusted independently to output a drive signal; drive power supply 1012 can be adjusted independently to output a drive signal; and drive power supplies 1011 and 1012 can jointly output a drive signal. The drive power supply 101 can be a programmable power supply or other current source.

[0063] For example, two chips under test (DUTs) share the same drive power supply 1011 and drive power supply 1012 to jointly output drive signals. When the two DUTs have different operating voltages, or when it is necessary to test the operating current of the two DUTs at different operating voltages, the first drive signal output of drive power supply 1011 can be connected to the input terminal of the first DUT, and the first drive signal output of drive power supply 1012 can be connected to the input terminal of the second DUT, thereby realizing the simultaneous measurement of the two DUTs.

[0064] The electrical parameter testing module 102 is used to test the electrical parameters of the drive signal output by the drive power supply 101. For example, the electrical parameter testing module 102 can test the drive current value, drive voltage value, or output power of the drive power supply 101, so as to monitor the status of the drive power supply 101 in real time during the test, so that the anomaly judgment module 103 can promptly determine whether the drive power supply 101 is abnormal. It should be noted that the number of electrical parameter testing modules 102 depends on the output lines of the drive power supply 101, such as... Figure 1 The system includes four electrical parameter testing modules (1021-1024).

[0065] The electrical parameter testing module 102 is used to test the electrical parameters of the drive power supply 101, which include the power supply voltage reference signal Vm or the power supply current reference signal Im.

[0066] The anomaly judgment module 103 is used to compare the electrical parameters obtained by the electrical parameter test module 102 with the preset corresponding electrical parameter thresholds. When the preset conditions are met (e.g., the current exceeds the limit value ILMT or the voltage exceeds the limit value VLMT), the drive power supply 101 is judged to be abnormal. When the preset conditions are not met, the drive power supply 101 is judged to be normal.

[0067] For example, the electrical parameter testing module 1021 tests the power supply current reference signal Im of the first drive signal output of the drive power supply 1011. When the power supply current reference signal Im is greater than or equal to a preset current threshold, the anomaly judgment module 1031 determines that the first drive signal output of the drive power supply 1011 has overcurrent protection; when the power supply current reference signal Im is less than the preset current threshold, the anomaly judgment module 1031 determines that the first drive signal output of the drive power supply 1011 is normal. The principles of the electrical parameter testing module 1022 and the anomaly judgment module 1032 are similar to the above scheme, and will not be described again here. It should be noted that the preset current threshold depends on the actual situation, and this application does not impose a specific limitation.

[0068] For example, the electrical parameter testing module 1023 is used to test the power current reference signal or power voltage reference signal output by the second drive signal of the drive power supply 1011, and the electrical parameter testing module 1024 is used to test the power current reference signal or power voltage reference signal output by the second drive signal of the drive power supply 1012. When the instantaneous current OVRC or instantaneous voltage OVRV of the equivalent power supply after the combination of drive power supply 1011 and drive power supply 1012 meets the preset conditions, the anomaly judgment module 1033 determines that the equivalent power supply is abnormal; when the instantaneous current OVRC or instantaneous voltage OVRV of the equivalent power supply does not meet the preset conditions, the anomaly judgment module 1033 determines that the equivalent power supply is normal, that is, drive power supply 1011 and drive power supply 1033 are normal.

[0069] Status register 104 is used to store the status of drive power supply 101, which includes normal status and abnormal status of drive power supply 101.

[0070] The alarm operation module 105 is used to control the stop of all test units when the status of the drive power supply 101 stored in the status register 104 is in an abnormal state.

[0071] In related technologies, current test equipment supports shutting down all test resources (or test units in this disclosure) on the current test board when a current overload is detected during the test. All chips under test will stop testing due to the current overload, so as to protect the test equipment from damage caused by the current overload.

[0072] The current overload of the drive power supply 101 is only caused by some of the chips under test. Most of the other chips under test can complete the test normally. The chips under test that pass the test can still be sold as normal products. However, due to the current overcurrent protection mechanism, all the chips under test on the test board stop testing, which greatly wastes production capacity and increases testing costs.

[0073] Therefore, how to distinguish the part of the chip under test that causes current overload so that the normal chip under test can continue to complete the test has become one of the urgent problems to be solved.

[0074] To facilitate a comprehensive understanding of the technical solutions provided by the embodiments of this disclosure, the chip testing system provided by the embodiments of this disclosure will be described first.

[0075] Figure 2 A schematic diagram of a chip testing system driver section provided in an embodiment of this disclosure is shown. Figure 2 As shown, the chip testing system includes a test board ( Figure 3 or Figure 4 As shown in the figure, the test board is equipped with multiple independent test units. Each test unit includes at least one drive power supply 101 for providing drive signals to multiple chips under test. The drive part includes an electrical parameter test module 102, an anomaly judgment module 103, a status register 104, a first alarm processing module 1051, a second alarm processing module 1052, and a control module 106.

[0076] The following sections will describe each module in turn. It should be noted that the functions of the drive power supply 101, electrical parameter testing module 102, and anomaly detection module 103 are the same as those of the modules in related technologies, and will not be repeated here.

[0077] In this disclosure, in addition to storing the state of the drive power supply 101, the status register 104 is also used to record the driving mode of the drive power supply 101. The driving mode of the drive power supply 101 includes independent driving mode and combined driving mode. In the independent driving mode, the driving signal output by the drive power supply 101 can be adjusted independently; in the combined driving mode, the driving signal output by the drive power supply 101 cannot be adjusted independently.

[0078] For example, when the drive power supply 101 stored in the status register 104 has an abnormal state in the independent drive mode, the status register 104 can report the abnormal state of the drive power supply 101 to the control module 106, or the control module 106 can periodically obtain the status of the drive power supply from the status register 104. At the same time, the control module 106 sends a control signal to the first alarm processing module 1051, and the first alarm processing module 1051 shuts down the abnormal drive power supply 101 and related test units according to the control signal.

[0079] For example, when the drive power supply 101 stored in the status register 104 has an abnormal state in the combined drive mode, the status register 104 can report the abnormal state of the drive power supply 101 to the control module 106, or the control module 106 can periodically obtain the status of the drive power supply from the status register 104. The control module 106 sends a control signal to the second alarm processing module 1052, and the second alarm processing module 1052 shuts down the drive power supply 101 according to the control signal to control all test units to stop.

[0080] It should be noted that the first alarm processing module 1051 and the second alarm processing module 1052 can be relays that control the power supply 101 to turn on or off, and the relays are electrically connected to the control module 106.

[0081] The control module 106 is used to determine the test unit related to the abnormal drive power supply 101 based on the abnormal state of the drive power supply 101 stored in the status register 104, and control the shutdown of the related test unit.

[0082] Figure 3 A schematic diagram of a test board structure provided in an embodiment of this disclosure is shown. Figure 3 As shown, the test board has multiple independent test units, each containing multiple chips under test (DUTs). These DUTs complete their respective tests under the same drive signal output from the same power supply. For example... Figure 3 The test array is configured with 6 columns * n rows of chips under test (DUTs). Each column of DUTs has a different drive power supply channel, and each column of DUTs serves as an independent test unit. For example... Figure 3 As shown, when the third column programmable power supply PPS0 is in an abnormal state, the status register updates the PPS0 status to abnormal. When the control module 106 detects the abnormal state of PPS0 in the status register, the control module 106 sends a control signal to the relay connected to PPS0 to control PPS0 to shut down, thereby stopping the testing of the third column of chips under test controlled by PPS0. It should be noted that since the drive power supply channels between different columns are relatively independent, there are no other chips under test affected by PPS0, and the chips under test in other columns can still continue to be tested.

[0083] Figure 4 A schematic diagram of the test board structure provided in an embodiment of this disclosure is shown. Figure 4 As shown, the test board has multiple independent test units, each containing multiple chips under test (DUTs). These DUTs complete corresponding tests under the influence of different drive signals from different power supplies. For example, Figure 4The test board has two independent test units. For example, DUT1, DUT2, DUT5, and DUT6 are in the first group, and DUT3, DUT4, DUT7, and DUT8 are in the second group. The multiple chips under test in each test unit are divided into two columns. DUT1 and DUT5 are in the first column of the first group, and DUT2 and DUT6 are in the second column of the first group. The first input terminals of the two columns of chips under test are driven by the drive signal output by a drive power supply. The first input terminals of the first column of chips under test in the first group and the first input terminals of the second column of chips under test in the first group are connected to the output terminal of the same drive power supply. The second input terminals of the first column of chips under test in the first group are connected to the programmable power supply PPS0, and the second input terminals of the second column of chips under test in the first group are connected to the programmable power supply PPS1. When an abnormality is detected in the programmable power supply PPS0, the control module 106 controls the programmable power supply PPS0 to shut down. At the same time, since the test units (or test resources) related to the programmable power supply PPS0 (i.e., the first group of second column of the chip under test, the programmable power supply PPS1, and the drive power supply connected to the first input terminal of the first group of first column of the chip under test) are all identified as the relevant test resources of the programmable power supply PPS0, the relevant test resources are controlled to shut down.

[0084] Based on this, the embodiments of this disclosure provide real-time monitoring of the working status of the driving power supply in each test unit. When an abnormality in the driving power supply is detected, the abnormal driving power supply is promptly shut down, and the test resources related to the driving power supply are also shut down. This effectively prevents the test equipment from being damaged by the abnormal chip under test, filters out defective chips, and allows some normal chips to continue testing, thereby improving product yield.

[0085] It should be noted that, unless otherwise specified, the embodiments of the present invention and the technical features thereof can be combined with each other.

[0086] The following detailed description of this exemplary implementation method is provided in conjunction with the accompanying drawings and embodiments.

[0087] Figure 5 A flowchart illustrating a chip testing method provided in an embodiment of this disclosure is shown. Figure 5 As shown, the chip testing method provided in this embodiment is applied to a chip testing system. The chip testing system includes a test board, which is provided with multiple sets of independent test units. Each set of test units includes at least one drive power supply for providing drive signals to multiple chips under test. The method includes:

[0088] S501. Obtain the status of at least one drive power supply in each test unit group.

[0089] In this embodiment, the test resources in each test unit are the test resources related to at least one of the above-mentioned driving power supplies. For example, the related test resources may be the chip under test in the same group as the driving power supply, other driving power supplies in the same group, etc.

[0090] The status of the power supply includes normal and abnormal states. When the power supply is in normal state, it can provide drive signals that meet the test requirements of multiple chips under test in the same group. When the power supply is in abnormal state, it cannot provide drive signals that meet the test requirements of multiple chips under test.

[0091] S502. If at least one drive power supply in a group of test units is found to be abnormal, control to shut down at least one drive power supply and control to shut down a group of test units.

[0092] In this embodiment, during chip testing, when an abnormality is detected in the drive power supply, the abnormal drive power supply is shut down to prevent damage. Simultaneously, test resources related to the drive power supply, i.e., the test unit containing the abnormal drive power supply, are promptly shut down. Once the drive power supply returns to normal, the testing continues until the chip under test completes all test items.

[0093] If at least one drive power supply in a set of test units is found to be abnormal, then the at least one drive power supply and the set of test units are controlled to be shut down. This means controlling the shutdown of at least one abnormal drive power supply and controlling the shutdown of the set of test units associated with the at least one abnormal drive power supply.

[0094] This embodiment of the present disclosure sets up multiple independent test units on the test board, with at least one driving power supply in each test unit. The status of the driving power supply is acquired in real time. When the driving power supply is found to be in an abnormal state, the abnormal driving power supply and the test unit associated with the abnormal driving power supply are precisely shut down. Compared with related technologies, this can effectively screen out normal chips that are not affected by the abnormal driving power supply, so as to continue to conduct subsequent tests on the normal chips, thereby increasing production capacity and reducing testing costs.

[0095] Figure 6 A flowchart illustrating another chip testing method provided by an embodiment of this disclosure is shown. Figure 6 As shown, in this embodiment, S501 acquires the status of at least one drive power supply in each test unit, specifically including:

[0096] S5022. During the test, monitor the electrical signal output by at least one drive power supply in each test unit in real time.

[0097] S5024. Determine whether the electrical signal output by the drive power supply meets the preset overload protection conditions. If it does, execute S5026.

[0098] S5026. Determine that the drive power supply has overload protection and confirm that the drive power supply is abnormal.

[0099] The electrical signals output by the drive power supply in this embodiment include the power supply voltage reference signal Vm, the power supply current reference signal Im, and the output power, etc. The electrical signals output by the drive power supply can be obtained in real time through the electrical parameter testing module.

[0100] The preset overload protection conditions include a power supply voltage reference signal Vm greater than or equal to a preset voltage threshold (or preset voltage range), and / or a power supply current reference signal Im greater than or equal to a preset current threshold (or preset current range), and / or an output power greater than or equal to a preset power threshold (or preset power range), etc. These preset overload protection conditions can be pre-set within the anomaly detection module. It should be noted that this application does not specifically limit the specific implementation method for drive power supply anomalies.

[0101] like Figure 6 As shown, in one embodiment, the chip testing method further includes:

[0102] S5028. When the electrical signal output by the drive power supply does not meet the preset overload protection conditions, the drive power supply is determined to be normal.

[0103] This disclosure monitors the electrical signal output by the drive power supply to determine whether the output signal meets the preset overload protection conditions, thereby determining the state of the drive power supply. By setting multiple abnormal drive power supply judgment conditions, the state of the drive power supply is effectively monitored, thus providing a basis for screening normal chips that are not affected by abnormal drive power supplies.

[0104] Figure 7 A flowchart illustrating yet another chip testing method provided in an embodiment of this disclosure is shown. For example... Figure 7 As shown, in one embodiment, the chip testing method includes:

[0105] S702, At least one drive power supply abnormality was detected in a group of test units;

[0106] S704, Obtain the driving mode of at least one abnormal driving power supply;

[0107] S706. When the driving mode of at least one abnormal driving power supply is the first driving mode, perform the operation of controlling to shut down at least one driving power supply and controlling to shut down a group of test units.

[0108] It should be noted that the driving mode of the power supply can be stored in the state memory. The control module periodically obtains the state and driving mode of the power supply, or, when the power supply malfunctions, the state memory simultaneously reports the driving mode and state of the power supply.

[0109] In this embodiment, the first driving mode of the driving power supply is the independent driving mode, that is, the driving power supply can adjust the strength, period and other parameters of the output driving signal according to the requirements.

[0110] In the first driving mode, if the driving power supply malfunctions, the control module sends a control signal to the relay connected to the malfunctioning driving power supply to shut it down. The control module also identifies the test resources associated with the malfunctioning driving power supply and shuts them down. In other words, the first driving mode is an independent driving mode; when the driving power supply malfunctions, both the malfunctioning driving power supply and the associated test resources are shut down.

[0111] like Figure 7 As shown, in one embodiment, the chip testing method further includes:

[0112] S708. When at least one abnormal drive power supply is in the second drive mode, control to shut down multiple test units.

[0113] In this embodiment, the second driving mode of the driving power supply is a non-independent driving mode, that is, the driving signal output by the driving power supply cannot be adjusted independently, and it needs to cooperate with other driving power supplies according to the test requirements to generate a test signal that meets the test requirements.

[0114] When the drive power supply is in the second drive mode, if the drive power supply malfunctions, the control module sends control signals to the relays connected to the drive power supply in multiple test units, controlling the shutdown of multiple test units. That is, the second drive mode is a non-independent drive mode; when the drive power supply malfunctions, all test resources are shut down.

[0115] In one embodiment, the driving mode of the power supply is stored in a status register.

[0116] Obtaining the driving mode of the at least one abnormal driving power supply includes:

[0117] The driving mode that obtains the abnormal driving power from the status register; or the driving mode that receives the abnormal driving power reported by the status register.

[0118] In this embodiment of the present disclosure, when the driving power supply is abnormal, the driving mode of the driving power supply is obtained, and different control methods are adopted for different driving modes, so as to effectively shut down the abnormal chip under test and related test resources to prevent the abnormal chip under test from damaging the test equipment, while allowing the normal chip under test to continue to complete the subsequent test items.

[0119] In one embodiment, S502 acquires the status of at least one drive power supply within each group of test units, including:

[0120] The status of the drive power supply is periodically obtained from the status register.

[0121] In this embodiment, the control module periodically obtains the status of the drive power supply from the status register. For example, the control module obtains the status of the drive power supply every 2 seconds. When the status of the drive power supply obtained from the status register is 0, it indicates that the drive power supply is normal; when the status of the drive power supply obtained is 1, it indicates that the drive power supply is abnormal. It should be noted that the selection of the period depends on the actual situation, and this application does not impose a specific limitation.

[0122] In one embodiment, S502 acquires the status of at least one drive power supply within each group of test units, including:

[0123] When the status of the drive power supply stored in the status register is an abnormal status, the abnormal status of the drive power supply reported by the status register is received.

[0124] In this embodiment, the status register stores the status of the driving power supply. For example, when the driving power supply is in normal condition, the status register stores the driving power supply status as 0; when the driving power supply is in abnormal condition, the status register stores the driving power supply status as 1. When the status register stores 1, the status register actively reports the abnormal driving power supply to the control module.

[0125] It should be noted that, in addition to the control module periodically acquiring the drive power status or the status register actively reporting the drive power status, other methods that enable the control module to acquire the drive power status are also applicable, and this application does not impose specific limitations.

[0126] In one embodiment, the method further includes:

[0127] The status register stores the state of the drive power supply, and updates the status of the drive power supply after a state change.

[0128] It should be noted that the status register stores the state of the drive power supply. When the state of the drive power supply changes, the state of the drive power supply stored in the status register is also updated.

[0129] The control module of this embodiment periodically acquires the status of the drive power supply or actively reports abnormal drive power supply status from the status register, so that the control module can promptly determine whether there is an abnormality in the drive power supply in order to complete the monitoring of subsequent test items.

[0130] In one embodiment, the method further includes, before controlling the shutdown of a set of test units:

[0131] Obtain the correspondence table, which indicates the correspondence between at least one drive power supply and each group of test units;

[0132] According to the correspondence table, find the test unit corresponding to at least one drive power supply in the abnormal state;

[0133] Among them, controlling the shutdown of a group of test units includes:

[0134] The found test units are turned off.

[0135] It should be noted that the correspondence table can be pre-configured in the control module or in the status register. When the drive power supply is abnormal, the number, output port and other information of the abnormal drive power supply can be determined. Based on the abnormal drive power supply, the corresponding test unit can be found in the correspondence table, so that the control module can quickly and timely shut down the test unit, that is, shut down the test resources related to the abnormal drive power supply.

[0136] In this embodiment, before obtaining the corresponding relationship table, the method further includes:

[0137] Construct a correspondence table, which indicates the correspondence between at least one drive power supply and each group of test units.

[0138] Typically, in a test equipment, the driving power supply and the corresponding test unit are relatively fixed. That is, each driving power supply provides a driving signal to the chip under test in a certain group of test units. At this time, a correspondence table can be constructed based on the correspondence between the driving power supply and the test unit. The correspondence table can be stored in the control module or in the state memory. This application does not make any specific limitation.

[0139] It should be noted that the correspondence table may include the number of the driving power supply, the output port of the driving power supply, etc., but this application does not impose specific restrictions.

[0140] In addition to using a correspondence table to determine the relevant test resources corresponding to the abnormal drive power supply, it can also be determined manually; this application does not impose any specific limitations.

[0141] This embodiment of the disclosure establishes a correspondence table to create a relationship between the driving power supply and the test unit, thereby establishing a relationship between the driving power supply and related test resources. This allows for the quick lookup of the relevant test resources corresponding to the abnormal driving power supply using the correspondence table, enabling the timely shutdown of the relevant test resources and greatly improving the speed of anomaly handling.

[0142] Based on the same inventive concept, this disclosure also provides a chip testing system, as described in the following embodiments. Since the principle by which this system embodiment solves the problem is similar to that of the method embodiment described above, the implementation of this system embodiment can refer to the implementation of the method embodiment described above, and repeated details will not be repeated.

[0143] Figure 8 This diagram illustrates the structure of a chip testing system provided in an embodiment of this disclosure. Figure 8 As shown, the chip testing system of this embodiment includes a test board and a control module 106. The test board is provided with multiple sets of independent test units 801. Each set of test units 801 includes at least one drive power supply 101 for providing drive signals to multiple chips under test 8011.

[0144] The control module 106 is used to monitor the status of at least one drive power supply 101 in each test unit 801 in real time; if an abnormality is detected in at least one drive power supply 101 in a test unit 801, the control module 106 controls at least one drive power supply 101 to be turned off, and controls the test unit 801 to be turned off.

[0145] In one embodiment, a drive power supply 101 within each test unit 801 is electrically connected to multiple chips under test via a relay, and the relay is electrically connected to the control module 106.

[0146] In one embodiment of this disclosure, the control module 106 further includes an acquisition submodule and an execution submodule (not shown in the figures), wherein,

[0147] The acquisition submodule is used to acquire the driving mode of at least one abnormal driving power supply after acquiring at least one abnormal driving power supply in a set of test units.

[0148] The execution submodule is used to control the shutdown of at least one drive power supply and control the shutdown of a group of test units when the drive mode of at least one abnormal drive power supply is the first drive mode.

[0149] In one embodiment of this disclosure, an execution submodule is configured to control the shutdown of multiple test units when the driving mode of at least one abnormal driving power supply is the second driving mode.

[0150] In one embodiment, the status register is used to store the driving mode of the driving power supply;

[0151] The acquisition submodule is used to obtain the driving mode of the abnormal driving power supply from the status register; or, to receive the driving mode of the abnormal driving power supply reported by the status register.

[0152] It should be noted that the acquisition submodule is also used to periodically acquire the status of the drive power supply from the status register.

[0153] In one embodiment, the acquisition submodule is further configured to receive the abnormal status of the drive power supply reported by the status register when the status of the drive power supply stored in the status register is an abnormal status.

[0154] In one embodiment of this disclosure, the status register is also used to store the status of the drive power supply and update the status after the drive power supply undergoes a status change.

[0155] In one embodiment of this disclosure, the system further includes an electrical parameter testing module and an anomaly detection module, wherein,

[0156] The electrical parameter testing module is used to monitor the electrical signals output by at least one drive power supply in each test unit in real time during the test process, before acquiring the status of at least one drive power supply in each test unit.

[0157] The anomaly detection module is used to determine that the drive power supply is abnormal when the electrical signal output by the drive power supply meets the preset overload protection conditions.

[0158] In one embodiment of this disclosure, the anomaly detection module is further configured to determine that the drive power supply is normal when the electrical signal output by the drive power supply does not meet the preset overload protection conditions.

[0159] In one embodiment of this disclosure, the acquisition submodule is further configured to acquire a correspondence table before controlling the shutdown of a group of test units, wherein the correspondence table is used to indicate the correspondence between at least one drive power supply and each group of test units;

[0160] The system also includes a search module, in which,

[0161] The lookup module is used to find the test unit corresponding to at least one drive power supply in an abnormal state according to the correspondence table.

[0162] The execution submodule is also used to control the shutdown of the found test units.

[0163] In one embodiment, the system further includes a construction module for constructing a correspondence table before obtaining the correspondence table, wherein the correspondence table is used to indicate the correspondence between at least one drive power supply and each group of test units.

[0164] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented in the following forms: entirely hardware implementations, entirely software implementations (including firmware, microcode, etc.), or implementations combining hardware and software aspects, collectively referred to herein as “circuits,” “modules,” or “systems.”

[0165] This disclosure provides a chip testing method and system. By setting up multiple independent test units on a test board, with at least one driving power supply in each test unit, the system can acquire the status of the driving power supply in real time. When the driving power supply is found to be in an abnormal state, the abnormal driving power supply and the test unit associated with the abnormal driving power supply can be precisely shut down. Compared with related technologies, this method can effectively screen out normal chips that are not affected by the abnormal driving power supply, thereby continuing to test the normal chips, increasing production capacity and reducing testing costs.

[0166] The following reference Figure 9 To describe an electronic device 900 according to this embodiment of the present invention. Figure 9 The electronic device 900 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0167] like Figure 9 As shown, the electronic device 900 is manifested in the form of a general-purpose computing device. The components of the electronic device 900 may include, but are not limited to: at least one processing unit 910, at least one storage unit 920, and a bus 930 connecting different system components (including the storage unit 920 and the processing unit 910).

[0168] The storage unit stores program code that can be executed by the processing unit 910, causing the processing unit 910 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit 910 can perform actions such as... Figure 5 The method shown is applied to a chip testing system, which includes a test board with multiple independent test units. Each test unit includes at least one drive power supply for providing drive signals to multiple chips under test. The status of at least one drive power supply in each test unit is acquired. If at least one drive power supply in a test unit is found to be abnormal, the at least one drive power supply is controlled to be turned off, and the test unit is controlled to be turned off.

[0169] Storage unit 920 may include readable media in the form of volatile storage units, such as random access memory (RAM) 9201 and / or cache memory 9202, and may further include read-only memory (ROM) 9203.

[0170] Storage unit 920 may also include a program / utility 9204 having a set (at least one) program module 9205, such program module 9205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0171] Bus 930 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0172] Electronic device 900 can also communicate with one or more external devices 940 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with the system 900, and / or with any device that enables the electronic device 900 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 950. Furthermore, system 900 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 960. Figure 9 As shown, network adapter 960 communicates with other modules of electronic device 900 via bus 930. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in conjunction with electronic device 900, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0173] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0174] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, which may be a readable signal medium or a readable storage medium. Figure 10 This illustration shows a computer-readable storage medium provided in an embodiment of the present disclosure, such as... Figure 10 As shown, the computer-readable storage medium 1000 stores a program product capable of implementing the methods described above. In some possible embodiments, various aspects of the present invention can also be implemented as a program product comprising program code that, when the program product is run on a user device, causes the user device to perform the steps of the various exemplary embodiments of the present invention described in the "Exemplary Methods" section of this specification.

[0175] According to embodiments of the present invention, a program product for implementing the above-described method may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a user device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, a readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0176] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0177] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0178] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0179] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0180] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0181] Furthermore, although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0182] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, mobile terminal, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0183] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A chip testing method, characterized in that, An application is made in a chip testing system, the chip testing system including a test board, the test board having multiple sets of independent test units, each test unit including at least one drive power supply for providing drive signals to multiple chips under test, the drive power supply being electrically connected to the multiple chips under test via relays, the method including: During the test, the electrical signal output by at least one of the drive power supplies in each test unit is monitored in real time. When the electrical signal output by the drive power supply meets the preset overload protection conditions, the drive power supply is determined to be abnormal. When the electrical signal output by the drive power supply does not meet the preset overload protection condition, the drive power supply is determined to be normal. Acquire the status of at least one of the drive power supplies within each test unit group; If at least one drive power supply in a group of test units is found to be abnormal, then the at least one drive power supply and the group of test units are shut down, including: obtaining the drive mode of the at least one abnormal drive power supply; when the drive mode of the at least one abnormal drive power supply is a first drive mode, performing the operation of shutting down the at least one drive power supply and shutting down the group of test units; when the drive mode of the at least one abnormal drive power supply is a second drive mode, then shutting down multiple groups of test units, wherein the first drive mode is an independent drive mode and the second drive mode is a non-independent drive mode. Before the control shuts down the set of test units, the method further includes: Obtain a correspondence table, wherein the correspondence table is used to indicate the correspondence between at least one of the driving power supplies and each group of test units; According to the correspondence table, find the test unit corresponding to the at least one drive power supply in the abnormal state; The control to shut down the group of test units includes: The test unit found by the control is turned off.

2. The chip testing method according to claim 1, characterized in that, The driving mode of the power supply is stored in the status register. The driving method for acquiring at least one abnormal driving power supply includes: Obtain the driving mode of the abnormal driving power supply from the status register; or, receive the driving mode of the abnormal driving power supply reported by the status register.

3. The chip testing method according to claim 1, characterized in that, The step of obtaining the state of at least one of the drive power supplies within each test unit group includes: The status of the drive power supply is periodically obtained from the status register.

4. The chip testing method according to claim 1, characterized in that, The step of obtaining the state of at least one of the drive power supplies within each test unit group includes: When the status of the drive power supply stored in the status register is an abnormal status, the abnormal status of the drive power supply reported by the status register is received.

5. The chip testing method according to claim 3 or 4, characterized in that, The method further includes: The status register stores the status of the drive power supply, wherein the status register is updated to reflect the status of the drive power supply after a status change.

6. The chip testing method according to claim 1, characterized in that, Before obtaining the corresponding relationship table, the method further includes: A correspondence table is constructed, wherein the correspondence table is used to indicate the correspondence between at least one of the driving power supplies and each group of test units.

7. A chip testing system, applied to the chip testing method as described in any one of claims 1-6, characterized in that, It includes a test board and a control module. The test board is provided with multiple sets of independent test units. Each set of test units includes at least one drive power supply for providing drive signals to multiple chips under test. The control module is used to acquire the status of at least one of the driving power supplies in each group of test units; if at least one driving power supply in a group of test units is found to be abnormal, the control module controls the shutdown of the at least one driving power supply and controls the shutdown of the group of test units.

8. The chip testing system according to claim 7, characterized in that, In each test unit, a drive power supply is electrically connected to multiple chips under test via a relay, and the relay is electrically connected to the control module.

9. An electronic device, characterized in that, include: processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the chip testing method as described in any one of claims 1-6 by executing the executable instructions.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the chip testing method as described in any one of claims 1-6.

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