A method for generating a time domain P1 code signal

Abstract

The present invention discloses a method for generating a time domain P1 code signal. The method comprises the steps of: generating a P1 code phase and a frequency control word lookup table; performing sampling processing on a quarter-cycle cosine signal with a number of points that meets the use requirement to obtain a cosine signal lookup table with a corresponding number of points; performing integer quantization on the P1 code word coefficient; a field programmable gate array (Field Programmable Gate Array FPGA) generates a frequency control word lookup table address according to a P1 code phase generation formula; and a direct digital frequency synthesis DDS generates a P1 code signal according to the frequency control word. The present invention realizes the real-time generation of a P1 code signal based on a field programmable gate array (Field Programmable Gate Array FPGA).

Description

Technical Field

[0001] The invention relates to a time domain P1 code signal generation method, which is used in communication and radar signal processing occasions. Background Art

[0002] With the development of electronic countermeasure technology, low probability of intercept radar technology has been valued by all countries. The polyphase code signal is developed on the basis of the linear frequency modulation signal. The P1 code signal is derived after the linear frequency modulation wave is approximated by the ladder. The P1 code signal combines the advantages of phase coding and frequency modulation signals, has the characteristics of high range resolution and large Doppler tolerance, and is widely used in low probability of intercept radar systems.

[0003] The development and functional verification of low acquisition radar systems require the use of P1 codeword signal generators, which are required to have high sampling rates and real-time requirements, and to be able to flexibly configure waveforms. The existing technology lacks real-time, high-precision P1 code signal generation technology, and with the development of radar technology, a real-time, high-precision P1 code signal generation technology is urgently needed. The existing technology lacks real-time, high-precision P1 code signal generation technology, which cannot meet actual needs. Summary of the invention

[0004] In view of the lack of real-time P1 code signal generation technology in the prior art, the purpose of the present invention is to provide a time domain P1 code signal generation method, build a digital circuit in FPGA, and use hardware circuits to complete the real-time generation of P1 code signals to meet the needs of application scenarios with high real-time requirements.

[0005] In order to achieve the above purpose, the following technical solutions are adopted:

[0006] A method for generating a time domain P1 code signal, characterized in that it comprises the following steps

[0007] 1) Quantify the P1 code phase difference step value according to the Field Programmable Gate Array (FPGA) quantization requirements;

[0008] 2) Perform nested loops according to sequential logic to generate the real-time phase of the P1 code signal. The P1 code phase is split into three parts according to the formula, and each part is generated by internal loop accumulation;

[0009] 3) Determine the waveform lookup table;

[0010] 4) Digital frequency synthesis DDS generates multiple parallel P1 signal real-time waveforms according to the phase;

[0011] 5) After parallel-to-serial conversion, a serial P1 signal is obtained;

[0012] 6) The obtained P1 signal is converted into digital form to output the analog P1 signal waveform; wherein, the digital frequency synthesis DDS design adopts the following method:

[0013] The signal amplitude bit width is recorded as I, and the number of sampling points of the 1 / 4 period cosine signal is recorded as N. Using the BlockRAM (Random Access Memory-RAM) resources in the FPGA, a RAM with a bit width of I and a depth of N is established to store the cosine signal lookup table. The BlockRAM is a specific hardware resource in the FPGA.

[0014] Among them, the P1 code signal phase is generated using the following method:

[0015] P1 codeword modulation phase

[0016]

[0017] i=0,1,2···,M-1j=0,1,2···,M-1, M is the number of phases contained in one coding cycle;

[0018] Formula (1) requires more multipliers to implement the phase method. When implemented in FPGA, real-time performance cannot be guaranteed and resource consumption is large. Formula (1) is pipelined and converted into formula (2)

[0019]

[0020] Formula (2) shows that Mj-2j 2 -j is related to the j dimension Only relevant to the i dimension. Related to j and i.

[0021] Mj-2j 2 -j=j(M-1)-2j 2 (3)

[0022] Mj-2j 2 -j performs the transformation shown in formula (3), where j(M-1) is transformed in the j dimension by accumulation, j 2 It is generated by iterative method using formula (4).

[0023] j 2 =(j-1+1) 2 =(j-1) 2 +2(j-1)+1 (4)

[0024] Perform cumulative changes in the i-dimension, The data is quantized in advance on the host computer side and sent to the FPGA.

[0025]

[0026] If the formula (5) is directly implemented on the FPGA side, two multipliers are required. The following uses linear accumulation to avoid using multipliers to implement formula (5). When j is a certain step number, the phase accumulation factor is The phase accumulation factor is Accumulation Phase accumulation when i changes Only an adder is required to implement formula (5).

[0027] Among them, the P1 code signal parameter quantization adopts the following method:

[0028] FPGA implementation of floating-point numbers is relatively complex, so the parameters need to be quantized. Determine the number of phases M and codeword width Tb contained in a coding cycle, and quantize M into the parameter M required for FPGA calculation according to formula (6): n .

[0029]

[0030] The codeword width Tb(us) is calculated according to the clock frequency to become the number of clock cycles code w , as shown in formula (7):

[0031] code w =Tb*f clk (7)

[0032] Furthermore, the real-time phase value is generated by formula (1):

[0033]

[0034] Furthermore, in order to save on-chip RAM resources, the lookup table uses a quarter cycle to perform a mirror transformation on the phase of the generated signal to obtain the corresponding amplitude value.

[0035] Furthermore, the multiplication in formula (1) is implemented in FPGA by accumulation.

[0036] Furthermore, the FPGA operation data is 2 N Quantization processing improves the efficiency of the algorithm running on FPGA.

[0037] Furthermore, the encoding codeword length is converted into the number of FPGA operating clock cycles through formula (7).

[0038] code w =Tb*f clk (7)

[0039] Furthermore, the above P1 code signal generation method is generated by FPGA, which ensures high precision and real-time performance of signal generation.

[0040] The present invention provides a method for generating a time domain P1 code signal, which has the following beneficial effects:

[0041] 1) Implement complex multiplication operations through cyclic accumulation, saving the multiplier resources inside the chip.

[0042] 2) Split complex calculation formulas into multiple parts for simultaneous calculation, generate signals through pipelines, and ensure the real-time nature of the generated signals.

[0043] 3) The present invention is implemented through FPGA calculation, which ensures that the processing delay is fixed and controllable and reduces the transmission delay to the greatest extent.

[0044] 4) Parameters can be flexibly configured to improve the diversity and flexibility of generated signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a flow chart of P1 code generation according to an embodiment of the present invention;

[0046] Figure 2 is a flow chart of P1 code phase generation in an embodiment of the present invention;

[0047] Figure 3 It is a frequency domain diagram of the P1 code signal generated by an embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to fully explain the purpose, technical content and advantages of the present invention, the present invention is introduced and described in detail in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0049] The present invention provides a time domain P1 code signal generation method for solving the demand for real-time P1 code signal generation in existing communication and radar signal processing occasions. To better illustrate the process of the present invention, the following describes the eight-phase P1 code signal generation process.

[0050] refer to Figure 1 The time domain P1 code signal generation method provided by the embodiment of the present invention includes parameter quantization, phase generation, signal generation, and parallel-to-serial conversion, a total of four steps. The preferred implementation method of each step is as follows:

[0051] (1) Signal parameter quantization method:

[0052] FPGA implementation of floating point numbers is relatively complex, so the signal parameters to be generated are first quantized and calculated using formula (1). First, determine the number of phases M contained in a coding cycle. In this example, M = 8, and the codeword width is Tb. Quantize M into the parameter M required for FPGA calculation according to formula (1). n .

[0053]

[0054] The codeword width Tb(us) depends on the clock frequency f clk Calculate the number of clock cycles code w , as shown in formula (2):

[0055] code w =Tb*f clk (2)

[0056] This step corresponds to Figure 1 (1) module in .

[0057] (2) Parameter transmission

[0058] The calculation parameters are transmitted from the PC to the ZYNQ chip through the Ethernet port. This step corresponds to Figure 1 in (2).

[0059] (3) Signal phase generation method:

[0060] The P1 codeword modulation phase is shown in formula (1):

[0061]

[0062] i=0,1,2···,M-1j=0,1,2···,M-1

[0063] Formula (3) requires more multipliers to implement the phase method. When implemented in FPGA, real-time performance cannot be guaranteed and resource consumption is large. The formula is pipelined and converted into formula (4):

[0064]

[0065] Formula (4) shows that Mj-2j 2 -j is related to the j dimension Only relevant to the i dimension. Related to j and i.

[0066] phase3=Mj-2j 2 -j=j(M-1)-2j 2 (5)

[0067] Mj-2j 2-j performs the transformation shown in formula (5), where j(M-1) is transformed in the j dimension by accumulation, j 2 It is generated by iterative method using formula (6).

[0068] j 2 =(j-1+1) 2 =(j-1) 2 +2(j-1)+1 (6)

[0069] like Figure 2 As shown, formula (5) Figure 2 The specific implementation of phase_3 is shown in the figure. Figure 2 In the formula, init_phase0 and (M-1) are accumulated to correspond to j(M-1), init_phase1 is realized by accumulating j*2+1, and i provides the operation control signal for the adder.

[0070] Accumulate changes in the i-dimension, perform quantization processing on the host computer side in advance and send it to the FPGA. Figure 2 As shown, phase 2 is obtained by accumulating the parameter M_n, which is calculated by the computer. And quantify the calculation.

[0071]

[0072] If formula (7) is implemented directly on the FPGA side, two multipliers are required. The following linear accumulation method is used to avoid using multipliers to implement formula (7). Figure 2 As shown, when j is a certain step number, the phase accumulation factor The phase accumulation factor is Accumulation Phase accumulation when i changes Only an adder is needed to implement formula (7). Figure 2 The specific implementation of phase_1 is shown in the figure. Figure 2 As shown, delta_phase is accumulated in each operation cycle. Accumulate detla by i change phase Implement phase_1, where phase_1 is the

[0073] Phase_2 accumulates the quantization parameter shown in formula (1) each time i is accumulated, achieving

[0074] The final real-time phase of the P1 codeword is obtained by adding the three parameters phase_1, phase_2, and phase_3. Figure 2 As shown, phase_out is the current real-time phase of the P1 codeword, which is obtained by adding the three parameters phase_1, phase_2, and phase_3. This step corresponds to Figure 1 (3) Modules in

[0075] (4) Digital frequency synthesis DDS design method:

[0076] The signal amplitude bit width is recorded as 16, the data bit width is 15 bits, the highest bit is the sign bit, and the cosine signal coe file with 1024 sampling points in 1 / 4 period is generated by Matlab software. The BlockRAM (Random Access Memory-RAM) resources in the FPGA are used to establish a RAM with a bit width of 16 and a depth of 1024 to store the cosine signal lookup table. The BlockRAM is a specific hardware resource in the FPGA. The cosine file coe file is imported into the IP core. The real-time phase range is 0 to 4095. When it exceeds 1024, the phase value is mapped to a value between 0 and 1023 according to the symmetry characteristics of the cosine signal for DDS table lookup, and the amplitude value of the phase between 1024 and 3071 is changed to a negative number according to the x-axis symmetry characteristics. This step corresponds to Figure 1 (4) module in .

[0077] The frequency domain diagram of the final eight-phase P1 code signal is: Figure 3 shown.

[0078] This design uses Xilinx xczu19eg-ffvc1760 chip as the core device for the design of the entire digital part.

[0079] (5) Serial-to-parallel conversion design method:

[0080] like Figure 2 As shown, establish 4 Figure 3 The same phase generator generates four adjacent phase values ​​in real time, and four DDSs generate four adjacent amplitude values ​​in real time through four phases. The four-bit output signal is converted into a high-precision serial signal through the serial-to-parallel conversion function of the DA chip (such as TI's dac38rf8x). This step corresponds to Figure 1 in (5).

[0081] (6) Signal output port design:

[0082] The digital signal is converted into an analog signal through the DA chip, and the signal is output through a standard SMA connector. Figure 1 in (6).

[0083] It should be noted that the specific embodiment described above is only an example of the present invention, and its purpose is to further explain the purpose, technical content and advantages of the present invention, so that everyone can more easily understand the content of the present invention, and it is not used to limit the present invention. The protection scope of the present invention is explained in the attached claims, and any obvious modifications, equivalent substitutions and improvements made within the purpose of the present invention shall fall within the protection scope of the present invention.

Claims

1. A method for generating a time domain P1 code signal, characterized in that: The following steps are included 1) Quantize the P1 code phase difference step value according to the field programmable gate array quantization requirements; 2) Perform nested loops according to sequential logic to generate the real-time phase of the P1 code signal. The P1 code phase is split into three parts according to the formula, and each part is generated by internal loop accumulation; 3) Determine the waveform lookup table; 4) Digital frequency synthesis DDS generates multiple parallel P1 signal real-time waveforms according to the phase; 5) After parallel-to-serial conversion, a serial P1 signal is obtained; 6) The obtained P1 signal is converted into digital form to output the analog P1 signal waveform; wherein, the digital frequency synthesis DDS design adopts the following method: The signal amplitude bit width is recorded as I, the number of sampling points of the 1 / 4 period cosine signal is recorded as N, and a RAM with a bit width of I and a depth of N is established by using the BlockRAM resources in the FPGA to store the cosine signal lookup table; Among them, the P1 code signal phase is generated using the following method: P1 codeword modulation phase i=0,1,2···,M-1;j=0,1,2···,M-1;M is the number of phases contained in one coding cycle; Formula (1) is pipelined to become formula (2) In formula (2): <h2 style=";text-align:left;direction:ltr">Mj-2j<h2 style=";text-align:left;direction:ltr"> 2 <h2 style=";text-align:left;direction:ltr"> -j = j(M-1)-2j<h2 style=";text-align:left;direction:ltr"> 2 <h2 style=";text-align:left;direction:ltr"> (3) Mj-2j 2 -j performs the transformation shown in formula (3), where j(M-1) is transformed in the j dimension by accumulation, j 2 Generated by iterative method of formula (4); I 2 =(j-1+1) 2 =(d-1) 2 +2(j-1)+1 (4) Perform cumulative changes in the i-dimension, The data is quantized in advance on the host computer side and sent to the FPGA. When j is a certain step number, the phase accumulation factor The phase accumulation factor is Accumulation Phase accumulation when i changes Among them, the P1 code signal parameter quantization adopts the following method: Determine the number of phases M and codeword width Tb contained in a coding cycle, and quantize M into the parameter M required for FPGA calculation according to formula (6) n ; The codeword width Tb is calculated based on the clock frequency to become the number of clock cycles code w , the unit of codeword width Tb is us, as shown in formula (7): code w =Tb*f clk (7)。 2. A method for generating a time domain P1 code signal as claimed in claim 1, characterized in that: The real-time phase value is generated by formula (1) 3. A method for generating a time domain P1 code signal as claimed in claim 1, characterized in that: In order to save on-chip RAM resources, the lookup table uses a quarter cycle to perform a mirror transformation on the generated signal phase to obtain the corresponding amplitude value.

4. A method for generating a time domain P1 code signal as claimed in claim 1, characterized in that: The multiplication in formula (1) is implemented in FPGA by accumulation.

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