Protection address determination circuit and method, protection circuit and method, and device

Abstract

The present disclosure relates to a hammer protection address determination circuit, a hammer protection address determination method, a hammer protection circuit, a hammer protection method and an electronic device, and relates to the field of integrated circuit technology. The hammer protection address determination circuit includes: a first hammer monitoring module, which is arranged outside a plurality of arrays, and is used to trigger an external hammer protection enable signal when a hammer protection instruction is detected; a second hammer monitoring module, which is arranged inside each array, and is used to trigger an internal hammer protection enable signal after detecting an activation instruction of the array; an address determination module, which is used to determine a valid protection address in an array with an activation instruction and an invalid address in an array without an activation instruction under the joint action of the external hammer protection enable signal and the internal hammer protection enable signal. The present disclosure provides a method for avoiding waste of resources in the process of protecting hammer damaged addresses.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a hammer protection address determination circuit, a hammer protection address determination method, a hammer protection circuit, a hammer protection method, and an electronic device. Background Art

[0002] In the application field of integrated circuits, the memory capacity in a memory chip is usually divided into multiple arrays for manufacturing, and the memory contains multiple logic arrays.

[0003] In actual applications, some arrays are vulnerable to row hammer attacks (bit flip attacks). Bit flip attacks exploit the mutual influence of electrons between adjacent memory cells, causing the value of a cell to become erroneous after a sufficient number of accesses. This attack is also called a hammer attack.

[0004] Among multiple memory arrays, the arrays that are actually subjected to hammer attacks will provide valid hammer-damaged addresses, while the arrays that are not subjected to hammer attacks will provide undamaged addresses. If these undamaged addresses are protected, it will cause a waste of internal resources.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0006] The purpose of the present disclosure is to provide a hammer protection address determination circuit, a hammer protection address determination method, a hammer protection circuit, a hammer protection method and an electronic device, so as to provide a method for avoiding resource waste during the protection process of a hammer damaged address.

[0007] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0008] According to a first aspect of the present disclosure, there is provided a hammer protection address determination circuit for an electronic device having multiple arrays, the circuit comprising:

[0009] A first hammer monitoring module is provided outside the plurality of arrays and is configured to trigger an external hammer protection enabling signal when a hammer protection instruction is detected;

[0010] A second hammer monitoring module is provided inside each of the arrays, and is used to trigger an internal hammer protection enable signal after detecting an activation instruction of the array;

[0011] The address determination module is used to determine the valid protection address in the array with the activation instruction and determine the invalid address in the array without the activation instruction under the joint action of the external hammer protection enable signal and the internal hammer protection enable signal.

[0012] Optionally, the address determination module includes: a hammer damaged address determination submodule, an address decoder and an address output control submodule; wherein,

[0013] The hammer damaged address determination submodule is used to determine the attack address in the array and determine the hammer damaged address according to the attack address;

[0014] The address decoder is used to obtain the hammer damaged address, decode the hammer damaged address, and output the decoded address;

[0015] The address output control submodule is used to control the output of the decoded address or the output of the invalid address under the combined action of the external hammer protection enable signal and the internal hammer protection enable signal.

[0016] Optionally, the address output control submodule includes a first logic gate and a second logic gate; wherein,

[0017] The input of the first logic gate is the external hammer protection enable signal and the internal hammer protection enable signal;

[0018] The input of the second logic gate is the decoded address and the output signal of the first logic gate;

[0019] In an array with the activation instruction, the output of the second logic gate is the decoded address; in an array without the activation instruction, the output of the second logic gate is the invalid address.

[0020] Optionally, when the valid output of the address decoder is valid at a low level, the internal hammer protection enable signal input to the first logic gate is negated; and the first logic gate is an AND gate, and the second logic gate is an OR gate.

[0021] Optionally, when the valid output of the address decoder is high level valid, the internal hammer protection enable signal input to the first logic gate is negated; and the first logic gate is a NAND gate, and the second logic gate is an AND gate.

[0022] Optionally, it also includes: a multiplexer; wherein,

[0023] The control end of the multiplexer is connected to the first hammer monitoring module, the first input end of the multiplexer is connected to the hammer damaged address determination submodule, and the second input end of the multiplexer is connected to the address in the array;

[0024] The output end of the multiplexer is connected to the input end of the address decoder.

[0025] Optionally, also include:

[0026] The array address providing module is used to provide an address in the array.

[0027] Optionally, the hammer damaged address determination submodule includes a counting unit, a grabbing unit and a determining unit; wherein,

[0028] The counting unit is used to count the number of activation instructions and refresh instructions that appear in the array within a preset time;

[0029] The capture unit is used to determine the attack address in the array according to the statistically obtained number of activation instructions and the number of refresh instructions, and latch the attack address;

[0030] The determining unit is configured to determine the hammer damaged address according to the latched attack address.

[0031] Optionally, the capture unit includes a connected comparator and a latch; wherein,

[0032] The comparator is used to compare the input activation instruction number and the refresh instruction number, so as to determine the address in the array whose access number exceeds a preset condition as the attack address;

[0033] The latch is used to latch the attack address determined by the comparator.

[0034] Optionally, the determining unit includes an operator; wherein,

[0035] The operator is used to perform addition and / or subtraction operations on the attack address to determine an address adjacent to the attack address in the array as the hammer damaged address.

[0036] Optionally, the first hammer monitoring module includes a first NAND gate, a second NAND gate and a NOT gate; wherein,

[0037] The input end of the first NAND gate is connected to the activation instruction and the output signal of the second NAND gate;

[0038] The input end of the second NAND gate is connected to the refresh instruction and the output signal of the first NAND gate;

[0039] The input end of the NOT gate is connected to the output end of the first NAND gate, and the output end of the NOT gate outputs the hammer protection enable signal.

[0040] According to a second aspect of the present disclosure, a hammer protection address determination method is provided, which is used in the above-mentioned hammer protection address determination circuit. The method includes:

[0041] By means of a first hammer monitoring module disposed outside the plurality of arrays, when a hammer protection instruction is detected, an external hammer protection enabling signal is triggered;

[0042] A second hammer monitoring module disposed within each array triggers an internal hammer protection enable signal upon detecting an activation instruction of the array;

[0043] Through the address determination module, under the joint action of the external hammer protection enable signal and the internal hammer protection enable signal, a valid protection address is determined in the array with the activation instruction, and an invalid address is determined in the array without the activation instruction.

[0044] Optionally, the method further includes:

[0045] Determine the attack address in the array through the hammer damaged address determination submodule, and determine the hammer damaged address according to the attack address;

[0046] Obtaining the hammer damaged address through an address decoder, decoding the hammer damaged address, and outputting a decoded address;

[0047] The address output control submodule controls the output of the decoded address or the output of the invalid address under the combined action of the external hammer protection enable signal and the internal hammer protection enable signal.

[0048] According to a third aspect of the present disclosure, there is provided a hammer protection circuit comprising a refresh circuit and the above-mentioned hammer protection address determination circuit;

[0049] The output end of the hammer protection address determination circuit is connected to the input end of the refresh circuit, and the refresh circuit is used to perform a refresh protection operation on the hammer protection address output by the hammer protection address determination circuit.

[0050] According to a fourth aspect of the present disclosure, there is provided a hammer protection method, comprising:

[0051] Determine the hammer protection address according to the above-mentioned hammer protection address determination method;

[0052] The hammer protection address is refreshed and protected.

[0053] According to a fifth aspect of the present disclosure, there is provided an electronic device, including:

[0054] multiple arrays;

[0055] A plurality of array control units, each of which is provided with the above-mentioned hammer protection address determination circuit;

[0056] One array control unit corresponds to one array.

[0057] Optionally, the first hammer monitoring module in the hammer protection address determination circuit is provided outside the array control unit;

[0058] A plurality of array control units share one first hammer monitoring module.

[0059] The technical solution provided by the present disclosure may have the following beneficial effects:

[0060] The hammer protection address determination circuit provided in the exemplary embodiment of the present disclosure, on the one hand, determines invalid addresses in arrays without activation instructions. These invalid addresses refer to addresses that do not exist in the array and are unrecognizable addresses for the array, that is, addresses that cannot be hammer protected in the array. Naturally, hammer protection actions will not be performed in these arrays. Therefore, in arrays without activation instructions, even if an external hammer protection enable signal is received, the addresses determined by these arrays are invalid, so meaningless hammer protection actions will not be performed, thereby reducing the operating current and achieving the purpose of saving resources. On the other hand, the hammer protection address determination circuit provided in the exemplary embodiment of the present disclosure, by setting the second hammer monitoring module inside the array, occupies a smaller area inside the array; and only setting a first hammer monitoring module outside the array, can reduce the area of ​​the bus occupied by the hammer monitoring module, reduce the pressure on the bus, and at the same time achieve the purpose of reducing the bus width.

[0061] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort. In the drawings:

[0063] Figure 1Schematically shows a schematic diagram of an internal array structure of an existing dynamic random access memory according to an exemplary embodiment of the present disclosure;

[0064] Figure 2 Schematically shows a block diagram of a hammer protection address determination circuit according to an exemplary embodiment of the present disclosure;

[0065] Figure 3 Schematically shows a structural diagram of a hammer protection address determination circuit according to an exemplary embodiment of the present disclosure;

[0066] Figure 4 Schematically shows a circuit structure diagram of a hammer monitoring module according to an exemplary embodiment of the present disclosure;

[0067] Figure 5 Schematically shows Figure 4 The schematic diagram of the signal waveform corresponding to the circuit of the hammer monitoring module shown;

[0068] Figure 6 Schematically shows a schematic diagram of a hammer-damaged address location according to an exemplary embodiment of the present disclosure;

[0069] Figure 7 Schematically shows another schematic diagram of the location of a hammer-damaged address according to an exemplary embodiment of the present disclosure;

[0070] Figure 8 Schematically shows a structural diagram of another hammer protection address determination circuit according to an exemplary embodiment of the present disclosure;

[0071] Figure 9 Schematically shows a circuit structure diagram of a hammer damaged address determination submodule according to an exemplary embodiment of the present disclosure;

[0072] Figure 10 A flowchart of a method for determining a hammer protection address according to an exemplary embodiment of the present disclosure is schematically shown;

[0073] Figure 11 A flowchart of a hammer protection method according to an exemplary embodiment of the present disclosure is schematically shown;

[0074] Figure 12 The figure schematically shows a structural diagram of an electronic device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0075] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the drawings represent like or similar parts, and thus repetitive description thereof will be omitted.

[0076] In addition, the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, well-known structures, methods, devices, implementations, materials or operations are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0077] The blocks shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically separate entities. Specifically, these functional entities may be implemented in software, or in one or more software-hardened modules, or in different networks and / or processor devices and / or microcontroller devices.

[0078] Inside the chip, memory data is written into a matrix in bits. Each unit is called a CELL. By specifying a row and a column, you can accurately locate a CELL. This is the basic principle of memory chip addressing.

[0079] This array is typically referred to as a memory chip's bank, also known as a logical bank. Due to manufacturing limitations, this array cannot be made too large, so memory chips are typically manufactured by dividing the memory capacity into several banks. As chip capacity continues to increase, the number of logical banks also increases.

[0080] Reference Figure 1 , shows a schematic diagram of the internal array structure of an existing dynamic random access memory (DRAM). Figure 1In this example, the DRAM has 16 banks, designated BANK0 through BANK15. BANK0 through BANK3 form the first bank group (Bank Group 0); BANK4 through BANK7 form the second bank group (Bank Group 1); BANK8 through BANK11 form the third bank group (Bank Group 2); and BANK12 through BANK15 form the fourth bank group (Bank Group 3).

[0081] Sixteen array control units 110 and a hammer monitoring module 120 are provided on the external circuits of the four array groups, namely the first array group, the second array group, the third array group and the fourth array group. BankCtrl0-BankCtrl15 in the figure represent the 16 array control units 110, and BankCtrl0 is connected to BANK0 for controlling BANK0; BankCtrl1 is connected to BANK1 for controlling BANK1; and so on, BankCtrl15 is connected to BANK15 for controlling BANK15.

[0082] Furthermore, the hammer monitoring module 120 in the external circuit is connected to the 16 array control units 110. Upon detecting a hammer protection command, it simultaneously provides a hammer protection enable signal RH_EN to all 16 array control units 110. Upon receiving the hammer protection enable signal RH_EN, each of the 16 array control units 110 provides hammer-damaged addresses and inputs them to the corresponding arrays 130 for protection, preventing bit flips at these addresses.

[0083] In actual applications, some arrays are determined to have been subjected to hammer attacks. Therefore, the array control unit 110 corresponding to these arrays can provide a valid, hammer-damaged address for protection. However, for arrays not subjected to hammer attacks, driven by the hammer protection enable signal RH_EN, only one unattacked address can be provided and protected. If this situation accumulates within the DRAM, it will result in a significant waste of DRAM resources.

[0084] Based on this, an exemplary embodiment of the present disclosure provides a hammer protection address determination circuit, which is used in an electronic device having multiple arrays, for example, the above-mentioned DRAM having 16 arrays. Figure 2 and Figure 3 As shown, the hammer protection address determination circuit 200 includes: a first hammer monitoring module 220, a second hammer monitoring module 240 and an address determination module 260; wherein,

[0085] The first hammer monitoring module 220 is set outside the plurality of arrays and is used to trigger the external hammer protection enable signal when a hammer protection instruction is detected. The function of the first hammer monitoring module 220 is similar to Figure 1 The hammer monitoring module 120 in FIG. 1 is configured to simultaneously provide a hammer protection enable signal RH_EN to each of the 16 array control units 110 upon detecting a hammer protection instruction. The first hammer monitoring module 220 in the exemplary embodiment of the present disclosure is also configured to send an external hammer protection enable signal to multiple arrays upon detecting a hammer protection instruction. Specifically, the hammer protection enable signal RH_EN is also sent to the array control units corresponding to the arrays. Therefore, the external hammer protection enable signal is also referred to herein as RH_EN.

[0086] As shown above, the first hammer monitoring module 220 is provided on the external circuit of the array, and the first hammer monitoring module 220 is used to provide the array with an external hammer protection enable signal RH_EN when a hammer protection instruction is detected. Figure 4 As shown, the first hammer monitoring module 220 includes a first NAND gate 122, a second NAND gate 124 and a NOT gate 126; wherein, the input end of the first NAND gate 122 is connected to the activation instruction ACT_CMD and the output signal of the second NAND gate 124; the input end of the second NAND gate 124 is connected to the refresh instruction REF_CMD and the output signal of the first NAND gate 122; the input end of the NOT gate 126 is connected to the output end of the first NAND gate 122, and the output end of the NOT gate 126 outputs the external hammer protection enable signal RH_EN.

[0087] Reference Figure 5As shown, when signals such as ACT_CMD, REF_CMD, and RH_EN are low-level signals, when the activation instruction signal ACT_CMD input to the input terminal of the first NAND gate 122 is generated, the first NAND gate 122 will generate a high-level 1 signal. After passing through the NOT gate 126, this high-level 1 signal will generate the external hammer protection enable signal RH_EN. If the refresh instruction signal REF_CMD is generated at the input terminal of the second NAND gate 124, the second NAND gate 124 will output a high-level 1 signal. At this time, the activation instruction ACT_CMD is also a high-level 1 signal. After these two high-level 1 signals are input to the first NAND gate 122, the first NAND gate 122 will generate a low-level 0 signal, resulting in the signal output from the NOT gate 126 being a high-level 1 signal, achieving the effect of turning off the external hammer protection enable signal RH_EN. That is, the external hammer protection enable signal RH_EN acts between adjacent activation instructions ACT_CMD and refresh instructions REF_CMD. After the activation instruction ACT_CMD triggers the external hammer protection enable signal RH_EN, as long as the refresh instruction REF_CMD is generated, the external hammer protection enable signal RH_EN will be terminated. The above effect can also be achieved when the ACT_CMD, REF_CMD and RH_EN signals are high-level signals, which will not be repeated here.

[0088] The second hammer monitoring module 240 is set inside each array and is used to trigger the internal hammer protection enable signal RH_EN_inner after monitoring the activation instruction ACT_CMD of the array in which it is located. The structure of the second hammer monitoring module 240 is the same as the internal structure of the first hammer monitoring module 220, except that: the activation instruction ACT_CMD monitored by the first hammer monitoring module 220 is the activation instruction in all arrays. As long as the activation instruction is generated in one array, the first hammer monitoring module 220 will be triggered to send the external hammer protection enable signal RH_EN; the activation instruction ACT_CMD monitored by the second hammer monitoring module 240 is the activation instruction in the array in which it is located. Only when the activation instruction is generated in the array in which it is located will the second hammer monitoring module 240 be triggered to send the internal hammer protection enable signal RH_EN_inner.

[0089] In an exemplary embodiment of the present disclosure, the address determination module 260 is configured to determine a valid protection address in an array with an activation instruction and an invalid address in an array without an activation instruction under the combined action of the external hammer protection enable signal RH_EN and the internal hammer protection enable signal RH_EN_inner.

[0090] In actual applications, arrays with activation instructions are usually arrays that are subject to hammer attacks. In these arrays, hammer-damaged addresses that are subject to hammer attacks can be determined, and these hammer-damaged addresses are valid protection addresses. In arrays without activation instructions, there are no addresses subject to hammer attacks. The exemplary embodiments of the present disclosure, by determining invalid addresses in arrays without activation instructions, these invalid addresses refer to addresses that do not exist in the array and are unrecognizable to the array, that is, addresses that cannot be hammer-protected in the array. Naturally, hammer protection actions will not be performed in these arrays. Therefore, in arrays without activation instructions, even if an external hammer protection enable signal is received, the addresses determined by these arrays are invalid, and meaningless hammer protection actions will not be performed, thereby reducing the operating current and achieving the purpose of saving resources.

[0091] On the other hand, the hammer protection address determination circuit provided in the exemplary embodiment of the present disclosure occupies a smaller area inside the array by setting the second hammer monitoring module inside the array; and only setting a first hammer monitoring module outside the array, thereby reducing the area of ​​the bus occupied by the hammer monitoring module, reducing the pressure on the bus, and at the same time achieving the purpose of reducing the bus width.

[0092] In the exemplary embodiment of the present disclosure, referring to Figure 3 As shown, the address determination module 260 may include: a hammer damaged address determination submodule 262 , an address decoder 264 and an address output control submodule 266 .

[0093] Specifically, the hammer-damaged address determination submodule 262 can be used to determine the attack address in the array and determine the hammer-damaged address based on the attack address. The address decoder 264 is used to obtain the hammer-damaged address, decode the hammer-damaged address, and output the decoded address. For an array that has actually been subjected to a hammer attack, a meaningful hammer-damaged address can be determined and decoded to obtain the decoded address. The address output control submodule 266 can be used to control the output of the decoded address or the output of an invalid address under the combined action of the external hammer protection enable signal RH_EN and the internal hammer protection enable signal RH_EN_inner.

[0094] The attack address described in the hammer damaged address determination submodule 262 of the exemplary embodiment of the present disclosure refers to a frequently accessed address in the array. Because the attack address is frequently accessed, it can affect adjacent addresses and even cause bit flips due to the mutual influence of electrons. To prevent bit flips from occurring, it is necessary to determine the hammer damaged address that may be attacked in advance based on the attack address so that refresh protection can be applied to the hammer damaged address before a bit flip occurs.

[0095] In practical applications, addresses adjacent to the attack address can be determined as hammer-damaged addresses based on actual circumstances. In the exemplary embodiments of the present disclosure, addresses immediately adjacent to the attack address can be determined as hammer-damaged addresses, or addresses adjacent to the attack address that are one address away from the attack address can be determined as hammer-damaged addresses, and the exemplary embodiments of the present disclosure do not specifically limit this.

[0096] Reference Figure 6 and Figure 7 As shown, in Figure 6 In the example, the first address 401 is a frequently accessed address, and the second address 402 and the third address 403 are hammer damaged addresses adjacent to the first address 401 and may be affected by the first address 401 and may have bit flips. Figure 7 In the example, if the first address 401 is repaired by the fourth address 501, the fifth address 502 and the sixth address 503 adjacent to the fourth address 501 will become hammer damaged addresses. In other words, the address repaired by the attack address will become a new attack address, and the addresses adjacent to the new attack address will also become hammer damaged addresses, which also has the risk of bit flipping.

[0097] In an exemplary embodiment of the present disclosure, in the process of determining an attack address, an address in the array whose access times exceed a preset condition may be determined as an attack address.

[0098] In actual applications, the preset condition can be determined according to actual needs. For example, the preset condition can be the condition that the number of accesses within two adjacent refresh intervals exceeds the preset number of accesses. In adjacent refresh intervals, if the number of accesses to a certain address exceeds the preset number of accesses, the address is considered to be an attack address, and its adjacent addresses may be hammered by the attack address and bit flipped. The preset number of accesses can be, for example, 150-1500 times or other times. For example, in two adjacent refresh intervals, if the number of accesses to a certain address in the array exceeds the above-mentioned 1500 times, that is, if between two adjacent refresh instructions REF_CMD, the activation instruction ACT_CMD received by a certain address accumulates to more than 1500 times, then the address is determined to be an attack address. It should be noted that the preset condition can also be other conditions, and the exemplary embodiments of the present disclosure do not specifically limit this.

[0099] In practical applications, there are usually two types of arrays: the target array that is subject to hammer attacks and the non-target array that is not subject to hammer attacks. For the target array, there are real attack addresses that are frequently accessed many times. The corresponding hammer-damaged addresses can be determined based on these real attack addresses.

[0100] In other words, the target array can provide a real and effective hammer-damaged address for protection. However, for the non-target array, there are no real, frequently accessed attack addresses. Therefore, driven by the external hammer protection enable signal RH_EN, the non-target array can only provide a meaningless hammer-damaged address. For the non-target array, the hammer-damaged address determined by the hammer-damaged address determination submodule 262 is typically the initial reset address.

[0101] In actual applications, the hammer-damaged address determined by the hammer-damaged address determination submodule 262 is primarily sent to the address decoder 264 for decoding, which then outputs the decoded address. The hammer protection address determination circuit provided in the exemplary embodiment of the present disclosure further includes a multiplexer 268, which is disposed between the hammer-damaged address determination submodule 262 and the address decoder 264.

[0102] Specifically, the control terminal of the multiplexer 268 is connected to the first hammer monitoring module 220, and the output signal is controlled by the external hammer protection enable signal RH_EN provided by the first hammer monitoring module 220. The first input terminal of the multiplexer 268 is connected to the hammer damage address determination submodule 262, and the first input terminal receives the hammer damage address. The second input terminal of the multiplexer 268 receives the array address RA. The output terminal of the multiplexer 268 is connected to the input terminal of the address decoder 264. The array address RA is provided by the array address providing module 280.

[0103] In actual applications, the external hammer protection enable signal RH_EN is mainly used to control the output of the address input by the first input terminal. Therefore, when the external hammer protection enable signal RH_EN is high-level enabled, the first input terminal is the 1 input terminal; when the external hammer protection enable signal RH_EN is low-level enabled, the first input terminal is the 0 input terminal; when there is no external hammer protection enable signal RH_EN, the multiplexer 268 outputs the address RA in the array input by the second input terminal. The address RA is input to the address decoder 264 for decoding and can be used for conventional memory access operations.

[0104] For the target array, the address determined by the hammer-damaged address determination submodule 262 is the hammer-damaged address; for the non-target array, the address determined by the hammer-damaged address determination submodule 262 is the initial reset address, which has no protection value. In other words, the address input from the multiplexer 268 to the address decoder 264 includes: the hammer-damaged address, the initial reset address, or the array address RA. These addresses are decoded by the address decoder 264 to obtain a decoded address.

[0105] As shown above, when the external hammer protection enable signal RH_EN is enabled, the address input from multiplexer 268 to address decoder 264 primarily includes the hammer-damaged address or the initial reset address. In this exemplary embodiment of the present disclosure, to avoid meaningless protection of the decoded initial reset address and thus conserve resources, an address output control submodule 266 is provided.

[0106] Specifically, the address output control submodule 266 mainly includes a first logic gate 2661 and a second logic gate 2662, wherein the input of the first logic gate 2661 is the external hammer protection enable signal RH_EN and the internal hammer protection enable signal RH_EN_inner; the input of the second logic gate 2662 is the decoded address and the output signal of the first logic gate 2661, such as Figure 3 shown.

[0107] In an exemplary embodiment of the present disclosure, through the setting of the address output control submodule 266, in an array with an activation instruction, that is, a target array, the output of the second logic gate 2662 is a decoding address; in an array without an activation instruction, that is, a non-target array, the output of the second logic gate 2662 is an invalid address.

[0108] The exemplary embodiments of the present disclosure are mainly described in terms of the case where the external hammer protection enable signal RH_EN and the internal hammer protection enable signal RH_EN_inner are enabled at high levels, and the case where the low levels are enabled may refer to the settings.

[0109] When the valid output of the address decoder 264 is low level, as shown in FIG. Figure 3 As shown, the first logic gate 2661 is an AND gate, the second logic gate 2662 is an OR gate, and the internal hammer protection enable signal RH_EN_inner input to the first logic gate 2661 needs to be negated, that is, a NOT gate is set between the second hammer monitoring module 240 and the first logic gate 2661.

[0110] Here, the working principle of the address output control submodule 266 is described in detail by taking the address decoder 264 as a 2-4 decoder as an example:

[0111] A 2-4 decoder is an address decoder used to convert a series of codes into valid signals that correspond to each one. A 2-4 decoder has two inputs, four outputs, and an enable pin. When the enable pin is active, only one of the outputs is active for each set of input codes; the remaining outputs are at the opposite level. The output signals can be active high or active low. Specifically, the two input variables A0 and A1 have four different state combinations, resulting in the decoder producing four output signals, Y0-Y3.

[0112] Table 1 shows the truth table of the 2-4 decoder when the output is active low:

[0113] Table 1

[0114]

[0115]

[0116] As shown in Table 1, when the enable controller E is 1, all outputs are 1 regardless of the state of A0 and A1, and the decoder is in a non-operating state. When E is 0, for a certain combination of the corresponding states of A0 and A1, only one output is 0, and only the 0 output is valid.

[0117] In the above-mentioned address output control submodule 266, for the target array, when the external hammer protection enable signal RH_EN and the internal hammer protection enable signal RH_EN_inner are enabled at the same time, for example, when the external hammer protection enable signal RH_EN and the internal hammer protection enable signal RH_EN_inner are both 1 signals, since the internal hammer protection enable signal RH_EN_inner needs to be not 0, the signals entering the first logic gate 2661 are 1 and 0 respectively, and after passing through the first logic gate 2661 which is an AND gate, the output is 0.

[0118] For the second logic gate 2662, the input signals are 0 and the address decoded by the address decoder 264. Since the second logic gate 2662 is an OR gate, the address decoded from the address decoder 264 does not change after passing through the second logic gate 2662, that is, the output of the second logic gate 2662 is the decoded address, and the decoded address is the address after decoding the hammer damaged address when the internal hammer protection enable signal RH_EN_inner is enabled.

[0119] That is, for the target array, when the external hammer protection enable signal RH_EN and the internal hammer protection enable signal RH_EN_inner are enabled at the same time, the address output control submodule 266 outputs the decoded address of the hammer damaged address.

[0120] For the non-target array, when the external hammer protection enable signal RH_EN is enabled and the internal hammer protection enable signal RH_EN_inner is not enabled, for example, when the external hammer protection enable signal RH_EN is a 1 signal and the internal hammer protection enable signal RH_EN_inner is a 0 signal, since the internal hammer protection enable signal RH_EN_inner needs to be negated to 1, the signals entering the first logic gate 2661 are all 1 signals, and after passing through the first logic gate 2661 which is an AND gate, the output is 1.

[0121] For the second logic gate 2662, the input signals are 1 and the address decoded by the address decoder 264. Since the second logic gate 2662 is an OR gate, the address decoded by the address decoder 264 becomes a high level after passing through the second logic gate 2662. For a decoder whose output is valid at a low level, a high level is an invalid signal. Therefore, in this case, the output of the second logic gate 2662 is an invalid address, and subsequent protection actions cannot be performed.

[0122] That is to say, for non-target arrays, when the external hammer protection enable signal RH_EN is enabled and the internal hammer protection enable signal RH_EN_inner is not enabled, the address output control submodule 266 outputs an invalid address and there is no need to protect the invalid address, thereby achieving the purpose of saving resources.

[0123] In the case where there is no hammer protection instruction, that is, in the normal memory access situation, the external hammer protection enable signal RH_EN and the internal hammer protection enable signal RH_EN_inner are both not enabled. For example, when the external hammer protection enable signal RH_EN is a 0 signal and the internal hammer protection enable signal RH_EN_inner is a 0 signal, since the internal hammer protection enable signal RH_EN_inner needs to be negated to 1, the signals entering the first logic gate 2661 are both 1 and 0 signals. After passing through the first logic gate 2661 which is an AND gate, the output is 0.

[0124] For second logic gate 2662, the input signals are 0 and the address decoded by address decoder 264. Since second logic gate 2662 is an OR gate, the address decoded by address decoder 264 does not change after passing through second logic gate 2662. That is, the output of second logic gate 2662 is the decoded address, and this decoded address is the array address RA provided by array address providing module 280. In other words, this address output control submodule 266 does not affect the output of normal memory access addresses. In other words, the hammer protection address determination circuit provided in the exemplary embodiment of the present disclosure not only provides effective protection against hammer-damaged addresses, but also does not affect the transmission of normal memory access addresses in non-hammer protection situations.

[0125] Reference Figure 8 As shown, a hammer protection address determination circuit is provided when the effective output of the address decoder 264 is high level effective. Figure 8 In the example, the internal hammer protection enable signal RH_EN_inner inputted by the first logic gate 2661 needs to be negated; and the first logic gate 2661 is a NAND gate, and the second logic gate 2662 is an AND gate. The function and working principle of the array address providing module 280 are the same as those described above. Figure 3 The similarities are not repeated here.

[0126] In practical applications, the hammer damaged address determination submodule 262 can be determined based on specific preset conditions. Figure 9As shown, the hammer damaged address determination submodule 262 may include a counting unit 311, a capture unit 313, and a determination unit 315. The counting unit 311 is configured to count the number of activation instructions and refresh instructions that appear in the array within a preset time. The counting unit 311 includes multiple counters. The inputs of the counting unit 311 are connected to the activation instructions and the refresh instructions. The counting unit 311 can calculate the number of activation instructions between two refresh instructions and send the counted number to the capture unit 313.

[0127] Capture unit 313 is used to determine an attack address in the array based on the number of activation instructions and refresh instructions counted by counting unit 311, and latch the attack address. Specifically, the attack address is determined based on a preset condition. For example, if the preset condition is that an address in the array that has been accessed more than 1500 times between two adjacent refresh instructions is an attack address, that is, an address that has received more than 1500 activation instructions between two adjacent refresh instructions is an attack address. Capture unit 313 can then determine the attack address based on the counted number of activation instructions and refresh instructions, and send the determined attack address to determination unit 315.

[0128] In actual applications, the capture unit may include a connected comparator and a latch; wherein the comparator can be used to compare the number of activation instructions and the number of refresh instructions input to determine the address in the array that has been accessed more than a preset condition as the attack address; the latch can be used to latch the attack address determined by the comparator and provide it to the determination unit 315 according to actual needs.

[0129] In an exemplary embodiment of the present disclosure, the determination unit 315 is configured to determine a hammer-damaged address based on the latched attack address. Typically, the hammer-damaged address affected by the attack address is an address adjacent to the attack address. Therefore, in an exemplary embodiment of the present disclosure, the determination unit 315 may include an arithmetic unit configured to perform addition and / or subtraction operations on the attack address to determine an address adjacent to the attack address in the array as the hammer-damaged address.

[0130] In practical applications, the array address providing module 280 is used to identify and provide addresses in the array. In the exemplary embodiment of the present disclosure, the array address providing module 280 is connected to the hammer damaged address determining submodule 262 and the multiplexer 268 .

[0131] The exemplary embodiment of the present disclosure also provides a method for determining a hammer protection address. Figure 10 The hammer protection address determination method may specifically include the following steps:

[0132] Step S102: triggering an external hammer protection enable signal when a hammer protection instruction is detected by a first hammer monitoring module disposed outside the plurality of arrays;

[0133] Step S104: triggering an internal hammer protection enable signal via a second hammer monitoring module disposed within each array after detecting an activation instruction of the array;

[0134] Step S106: Through the address determination module, under the joint action of the external hammer protection enable signal and the internal hammer protection enable signal, a valid protection address is determined in the array with the activation instruction, and an invalid address is determined in the array without the activation instruction.

[0135] In some embodiments of the present disclosure, the attack address in the array is determined by a hammer damaged address determination submodule, and the hammer damaged address is determined based on the attack address; the hammer damaged address is obtained by an address decoder, and the hammer damaged address is decoded to output a decoded address; and the address output control submodule controls the output of the decoded address or the output of the invalid address under the joint action of the external hammer protection enable signal and the internal hammer protection enable signal.

[0136] The specific details of each step in the above-mentioned hammer protection address determination method have been described in detail in the corresponding hammer protection address determination circuit, so they will not be repeated here.

[0137] The exemplary embodiments of the present disclosure further provide a hammer protection circuit, comprising a refresh circuit and the aforementioned hammer protection address determination circuit. The output of the hammer protection address determination circuit is connected to the input of the refresh circuit, and the refresh circuit is configured to perform a refresh protection operation on the hammer protection address output by the hammer protection address determination circuit. The hammer protection address determined by the hammer protection address determination circuit can be refresh protected in the refresh circuit. The refresh circuit primarily performs a refresh read operation on the hammer protection address. In practical applications, reference can be made to conventional circuits for performing refresh operations, and the specific structure of the refresh circuit is not particularly limited herein.

[0138] In the exemplary embodiment of the present disclosure, the specific structural form of the hammer protection address determination circuit in the hammer protection circuit has been described in detail in the above embodiment, and thus will not be repeated here.

[0139] The exemplary embodiment of the present disclosure also provides a hammer protection method, referring to Figure 11 The hammer protection method may specifically include the following steps:

[0140] Step S111: determining a hammer protection address according to the above-mentioned hammer protection address determination method;

[0141] Step S113: Refresh protection on the hammer protection address.

[0142] The hammer protection address mentioned above refers to a valid protection address determined in an array with an activation instruction, and an invalid address determined in an array without an activation instruction.

[0143] The specific details of each step in the above-mentioned hammer protection method have been described in detail in the corresponding hammer protection address determination method and hammer protection circuit, so they will not be repeated here.

[0144] The exemplary embodiment of the present disclosure further provides an electronic device, Figure 12 As shown, the electronic device may include: multiple arrays 1210 and multiple array control units 1230, with one array control unit 1230 corresponding to one array 1210. Each array control unit 1230 is provided with the aforementioned hammer protection address determination circuit, which is used to determine the hammer protection address in the corresponding array 1210. The specific structural details of the hammer protection address determination circuit have been described in detail in the above embodiment and will not be repeated here.

[0145] It should be noted that the first hammer monitoring module 220 in the above-mentioned hammer protection address determination circuit is set outside the array control unit 1230; and multiple array control units 1230 share one first hammer monitoring module 220, which is used to provide the array control unit 1230 with an external hammer protection enable signal RH_EN.

[0146] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present disclosure is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that can be integrated with one or more media. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)). In the embodiment of the present disclosure, the computer may include the device described above.

[0147] Although the present disclosure is described herein in conjunction with various embodiments, in the process of implementing the disclosure for which protection is sought, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple components. A single processor or other unit may implement several functions listed in the claims. The fact that certain measures are recorded in mutually different dependent claims does not mean that these measures cannot be combined to produce good results.

[0148] Although the present disclosure has been described with reference to specific features and embodiments thereof, it will be apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present disclosure. Accordingly, this specification and the drawings are merely illustrative of the present disclosure as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present disclosure. Obviously, those skilled in the art may make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, the present disclosure is intended to encompass such modifications and variations if they fall within the scope of the claims of the present disclosure and their equivalents.

Claims

1. A hammer protection address determination circuit for an electronic device having multiple arrays, characterized in that: The circuit comprises: A first hammer monitoring module is provided outside the plurality of arrays and is configured to trigger an external hammer protection enabling signal when a hammer protection instruction is detected; A second hammer monitoring module is provided inside each of the arrays, and is used to trigger an internal hammer protection enable signal after detecting an activation instruction of the array; The address determination module is used to determine the valid protection address in the array with the activation instruction and determine the invalid address in the array without the activation instruction under the joint action of the external hammer protection enable signal and the internal hammer protection enable signal.

2. The hammer protection address determination circuit according to claim 1, characterized in that: The address determination module includes: a hammer damaged address determination submodule, an address decoder and an address output control submodule; wherein, The hammer damaged address determination submodule is used to determine the attack address in the array and determine the hammer damaged address according to the attack address; The address decoder is used to obtain the hammer damaged address, decode the hammer damaged address, and output the decoded address; The address output control submodule is used to control the output of the decoded address or the output of the invalid address under the combined action of the external hammer protection enable signal and the internal hammer protection enable signal.

3. The hammer protection address determination circuit according to claim 2, characterized in that: The address output control submodule includes a first logic gate and a second logic gate; wherein, The input of the first logic gate is the external hammer protection enable signal and the internal hammer protection enable signal; The input of the second logic gate is the decoded address and the output signal of the first logic gate; In an array with the activation instruction, the output of the second logic gate is the decoded address; in an array without the activation instruction, the output of the second logic gate is the invalid address.

4. The hammer protection address determination circuit according to claim 3, characterized in that: When the effective output of the address decoder is low-level active, the internal hammer protection enable signal input to the first logic gate is negated; and the first logic gate is an AND gate, and the second logic gate is an OR gate.

5. The hammer protection address determination circuit according to claim 3, characterized in that: When the effective output of the address decoder is high level, the internal hammer protection enable signal input to the first logic gate is negated; and the first logic gate is a NAND gate, and the second logic gate is an AND gate.

6. The hammer protection address determination circuit according to any one of claims 2 to 5, characterized in that: Also includes: A multiplexer; wherein, The control end of the multiplexer is connected to the first hammer monitoring module, the first input end of the multiplexer is connected to the hammer damaged address determination submodule, and the second input end of the multiplexer is connected to the address in the array; The output end of the multiplexer is connected to the input end of the address decoder.

7. The hammer protection address determination circuit according to claim 6, characterized in that: Also includes: The array address providing module is used to provide an address in the array.

8. The hammer protection address determination circuit according to any one of claims 2 to 5, characterized in that: The hammer damaged address determination submodule includes a counting unit, a grabbing unit and a determining unit; wherein, The counting unit is used to count the number of activation instructions and refresh instructions that appear in the array within a preset time; The capture unit is used to determine the attack address in the array according to the statistically obtained number of activation instructions and the number of refresh instructions, and latch the attack address; The determining unit is configured to determine the hammer damaged address according to the latched attack address.

9. The hammer protection address determination circuit according to claim 8, characterized in that: The capture unit includes a connected comparator and a latch; wherein, The comparator is used to compare the input activation instruction number and the refresh instruction number, so as to determine the address in the array whose access number exceeds a preset condition as the attack address; The latch is used to latch the attack address determined by the comparator.

10. The hammer protection address determination circuit according to claim 8, characterized in that: The determining unit includes an operator; wherein, The operator is used to perform addition and / or subtraction operations on the attack address to determine an address adjacent to the attack address in the array as the hammer damaged address.

11. The hammer protection address determination circuit according to claim 1, characterized in that: The first hammer monitoring module includes a first NAND gate, a second NAND gate and a NOT gate; wherein, The input end of the first NAND gate is connected to the activation instruction and the output signal of the second NAND gate; The input end of the second NAND gate is connected to the refresh instruction and the output signal of the first NAND gate; The input end of the NOT gate is connected to the output end of the first NAND gate, and the output end of the NOT gate outputs the hammer protection enable signal.

12. A method for determining a hammer protection address, used in the hammer protection address determination circuit according to any one of claims 1 to 11, characterized in that: The method comprises: By means of a first hammer monitoring module disposed outside the plurality of arrays, when a hammer protection instruction is detected, an external hammer protection enabling signal is triggered; A second hammer monitoring module disposed within each array triggers an internal hammer protection enable signal upon detecting an activation instruction of the array; Through the address determination module, under the joint action of the external hammer protection enable signal and the internal hammer protection enable signal, a valid protection address is determined in the array with the activation instruction, and an invalid address is determined in the array without the activation instruction.

13. The method for determining a hammer protection address according to claim 12, wherein: The method further comprises: Determine the attack address in the array through the hammer damaged address determination submodule, and determine the hammer damaged address according to the attack address; Obtaining the hammer damaged address through an address decoder, decoding the hammer damaged address, and outputting a decoded address; The address output control submodule controls the output of the decoded address or the output of the invalid address under the combined action of the external hammer protection enable signal and the internal hammer protection enable signal.

14. A hammer protection circuit, characterized in that: comprising a refresh circuit and a hammer protection address determination circuit according to any one of claims 1 to 11; The output end of the hammer protection address determination circuit is connected to the input end of the refresh circuit, and the refresh circuit is used to perform a refresh protection operation on the hammer protection address output by the hammer protection address determination circuit.

15. A hammer protection method, characterized in that: include: Determining the hammer protection address according to the hammer protection address determination method of claim 12 or 13; The hammer protection address is refreshed and protected.

16. An electronic device, characterized in that: include: multiple arrays; A plurality of array control units, each of which is provided with a hammer protection address determination circuit according to any one of claims 1 to 11; One array control unit corresponds to one array.

17. The electronic device according to claim 16, wherein: The first hammer monitoring module in the hammer protection address determination circuit is arranged outside the array control unit; A plurality of array control units share one first hammer monitoring module.

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