A printed circuit board structure and a method for manufacturing the same

Abstract

The present invention relates to the technical field of integrated circuits, and provides a printed circuit board structure and a preparation method thereof, including through silicon vias and through glass vias, wherein the through silicon vias are distributed with dense wiring areas and non-dense wiring areas, and the through silicon vias are formed with grooves, and the dense wiring areas and non-dense wiring areas are exposed from the grooves; the through glass vias are distributed with dense wiring areas and non-dense wiring areas, and the dense wiring areas are distributed with first dense wiring areas, second dense wiring areas and third dense wiring areas, and the first dense wiring areas, second dense wiring areas and third dense wiring areas are distributed with dense wiring area pads and dense wiring; the dense wiring area of ​​the through silicon vias corresponds vertically to the dense wiring area of ​​the through glass vias, and the non-dense wiring area of ​​the through silicon vias corresponds vertically to the non-dense wiring area of ​​the through glass vias. The structure integrates the advantages of through silicon vias and through glass vias fan-out wiring, and realizes partitioned fan-out wiring. At the same time, the embedded design shortens the signal line, reduces loss, and reduces device electromagnetic interference.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a printed circuit board structure and a preparation method thereof. Background Art

[0002] Existing technologies often use through silicon via technology, such as TSMC's patent publication number CN110534507B, "Through Silicon Via Design, Three-Dimensional Integrated Circuit and Manufacturing Method Thereof", which uses through silicon via (TSV) design to stack IC chips, increase wiring density and reduce power consumption.

[0003] Huawei's patent publication number CN114287057A "A chip stacking package and terminal device" was published on April 5, 2022. The limitations of this patent are: the chips are interconnected by staggering, which is beneficial to the heat dissipation of the chips, but the interconnection of the two vertical chips in this structure is limited by the processing density. This structure has a high application value in analog chips (large circuits), but it is not suitable for the interconnection of digital chips (nm-level line width). Directly interconnecting two digital chips with nm-level line widths poses great challenges to the processing of the RDL layer. At the same time, staggering the two chips and the heterogeneous design causes a combined stress problem (easy to break) at the junction of the RDL layer and the digital chip.

[0004] The patent publication number CN107393900B of the 58th Institute of China Electronics Technology Group Corporation, "Buried TSV adapter board structure with extremely multi-layer wiring", discloses that: a wiring adapter board with extremely multi-layer wiring is buried in an adapter board body, thereby increasing the number of wiring layers of the adapter board body, compensating for the deficiency of the TSV adapter board body being limited by the number of RDL wiring layers, and meeting the application requirements of high-performance, high-integration-density microsystem packaging.

[0005] At present, there are two main problems with TSV adapters: 1) high cost. The production of through silicon vias (TSV) uses silicon etching process, and then the through silicon vias require oxidation insulation layer, thin wafer and other technologies; 2) poor electrical performance. Silicon material is a semiconductor material. When the transmission line transmits the signal, the signal and the substrate material have a strong electromagnetic coupling effect, and eddy current phenomenon is generated in the substrate, resulting in poor signal integrity (insertion loss, crosstalk, etc.). As a material that may replace silicon-based adapters, through glass via (TGV) adapters are becoming a research hotspot for semiconductor companies and research institutes at home and abroad due to their many advantages. Compared with silicon-based adapters, the advantages of glass adapters are mainly reflected in the following aspects: 1) low cost; 2) excellent high-frequency electrical properties; 3) large-size ultra-thin glass substrates are easy to obtain; 4) simple process flow. However, unlike TSV, TGV has a larger aperture and is mostly through-hole, so the electroplating time is long and the cost is high. On the other hand, unlike silicon materials, the glass surface is smooth and has poor adhesion to commonly used metals (such as Cu), which can easily cause delamination between the glass substrate and the metal layer, leading to curling or even falling off of the metal layer. Summary of the invention

[0006] In order to overcome the above-mentioned shortcomings, the present invention provides a printed circuit board structure, through which the printed circuit board structure solves the technical problems of Huawei patent CN114287057A, such as the combined stress problem of easy breakage, the fan-out limitation of fine line wiring, and the large aperture of the prior art TGV, which limits the wiring density.

[0007] In the first aspect, the present invention protects a printed circuit board structure, which is as follows:

[0008] It includes a through silicon via, a through glass via, and an insulating layer, and is characterized in that: the through silicon via is distributed with a through silicon via dense wiring area and a through silicon via non-dense wiring area, the through silicon via is formed with a through silicon via groove, and the through silicon via dense wiring area and the through silicon via non-dense wiring area are exposed from the through silicon via groove.

[0009] The through glass via is distributed with a through glass via dense wiring area and a through glass via non-dense wiring area, the through glass via dense wiring area is distributed with a through glass via first dense wiring area, a through glass via second dense wiring area and a through glass via third dense wiring area, and the through glass via first dense wiring area, the through glass via second dense wiring area and the through glass via third dense wiring area are distributed with through glass via dense wiring area pads and through glass via dense wiring;

[0010] The TSV dense wiring area corresponds vertically to the TSV dense wiring area, and the TSV non-dense wiring area corresponds vertically to the TSV non-dense wiring area.

[0011] The insulating layer plastic-seales the through silicon via and the through glass via.

[0012] The silicon via dense wiring area is distributed with a first dense wiring area, a second dense wiring area, a third dense wiring area and a fourth dense wiring area. The first dense wiring area, the second dense wiring area, the third dense wiring area and the fourth dense wiring area form a first pad in the dense wiring area, a second pad in the dense wiring area and wiring in the dense wiring area.

[0013] The active device is bonded to the first pad of the dense wiring area and the second pad of the dense wiring area, and fan-out wiring is performed through the dense wiring area.

[0014] Preferably, the active devices are stacked such that a pin of at least one of the active devices faces upward and the pin is exposed from the insulating layer.

[0015] The first dense wiring area of ​​the through glass via corresponds vertically to the first dense wiring area of ​​the through silicon via dense wiring area; the second dense wiring area of ​​the through glass via corresponds vertically to the second dense wiring area of ​​the through silicon via dense wiring area.

[0016] The active devices in the through silicon via dense wiring area are fanned out to the through glass vias through the pins facing upward, the pads in the through glass via dense wiring area, and the through glass via dense wiring.

[0017] The silicon via non-dense wiring area is distributed with a first non-dense wiring area and a second non-dense wiring area. The first non-dense wiring area and the second non-dense wiring area form a first pad in the non-dense wiring area, a second pad in the non-dense wiring area, a third pad in the non-dense wiring area, a fourth pad in the non-dense wiring area and wiring in the non-dense wiring area.

[0018] The second pad of the non-dense wiring area of ​​the first non-dense wiring area is bonded to a passive device, and the third pad of the non-dense wiring area of ​​the second non-dense wiring area is bonded to a passive device, and the passive devices are electrically interconnected through the wiring of the non-dense wiring area.

[0019] The second pad of the non-dense wiring area of ​​the first non-dense wiring area is connected to the through glass via through a solder ball, and the third pad of the non-dense wiring area of ​​the second non-dense wiring area is connected to the through glass via through a solder ball.

[0020] A heat sink fin is placed in the TSV non-dense wiring area of ​​the TSV groove. The heat sink fin includes a heat sink fin cavity and a heat sink fin body. The heat sink fin body includes a heat sink fin body substrate and a heat sink fin body protrusion. The heat sink fin body protrusion extends to the outside of the TSV.

[0021] Preferably, the heat sink fins are stacked vertically, and the projections of the overlapping cavities of the heat sink fins can cover the through silicon via dense wiring area.

[0022] The heat dissipation fin body is fixed by plastic sealing of the insulating layer, abuts against the through silicon via and the through glass via, and the heat dissipation fin body protrusion of the heat dissipation fin body is exposed from the insulating layer.

[0023] In the second aspect, the present invention protects a method for preparing a printed circuit board structure, which is as follows:

[0024] S1: Provide a silicon-based wafer, perform mask protection on the non-etching area, use the existing etching process to etch to form a through-silicon via groove, grind, and polish;

[0025] S2: masking the through silicon via grooves to protect them, and using existing through silicon via processing technology and conventional CMOS process to process them layer by layer to form non-dense wiring area wiring;

[0026] S3: Removing the mask, performing mask protection on the formed non-dense wiring area, and performing deep processing using the existing through silicon via processing technology and conventional CMOS process or stacked CMOS process to form dense wiring area wiring with an aspect ratio of 5 to 15;

[0027] S4: performing pad ball planting or additive method on the through silicon via with formed step, forming copper pillars and bumps, bonding the active device and the passive device to the through silicon via, plastic-sealing the insulating layer, and leveling the plate to expose the solder balls, copper pillars or bumps required for the active device to conduct;

[0028] S5: performing deep processing of the glass through hole by using at least one of a photosensitive glass method, a plasma etching method, an electrochemical method or a laser induced etching method, and forming an RDL layer layer by layer by using a conventional CMOS process;

[0029] S6: Alignment and calibration, pressing the glass through hole formed in step S5 to connect with the silicon through hole, interconnecting and conducting through at least one of solder balls, copper pillars or bumps, and performing secondary glue filling and plastic sealing.

[0030] In a third aspect, the present invention protects a packaging module made of the above-mentioned printed circuit board structure, which is specifically as follows:

[0031] 1) comprising at least one of the above-mentioned printed circuit board structures, a carrier board and at least one active device, wherein the carrier board is electrically connected to the glass through-hole of the printed circuit board structure through the solder balls;

[0032] 2) The active device is electrically connected to the TGL dense wiring area pads of the first TGL dense wiring area, the second TGL dense wiring area, and the third TGL dense wiring area, and fans out the wiring to the TGL;

[0033] 3) The insulating layer plastic-seales the printed circuit board structure, the carrier board and the active devices.

[0034] Preferably, the heat dissipation fins may be placed between the printed circuit board structure and the carrier board to increase the heat dissipation efficiency of the side edges.

[0035] Preferably, the insulating layer is at least one of polypropylene, epoxy resin and ABF.

[0036] The present invention provides a printed circuit board structure, which has the following beneficial effects:

[0037] (1) forming a through silicon via with a step-difference structure and forming a dense wiring area in the through silicon via groove, the dense wiring area is used for electrical connection of active devices, which is beneficial to the fan-out of fine lines of active devices;

[0038] (2) forming a through silicon via with a step-difference structure, and forming a non-dense wiring area in the through silicon via groove, the non-dense wiring area is used for electrical connection of passive devices, and partitioned fan-out wiring can be realized;

[0039] (3) A through silicon via with a step-difference structure is formed, and a dense wiring area is formed in the through silicon via groove, and the interconnection signal line is shortened, which is beneficial to reducing the loss of active device signals;

[0040] (4) The silicon via with a step-difference structure is conducive to the embedding of devices, reducing the thickness of the entire board caused by surface mounting, the size out of tolerance, and reducing the electromagnetic interference between devices;

[0041] (5) The silicon vias that form the step-difference structure can meet the specifications of the active device wiring fan-out, design the vertical distance of the upper and lower stacked active devices, and adjust the step size. Devices of different stack sizes can be embedded according to the step size, thereby improving the device integration density;

[0042] (6) Using the existing CMOS technology to form a silicon through-hole via with dense wiring and a small through-hole diameter, and crimping a glass through-hole with limited dense wiring and a large through-hole diameter, the dense wiring area of ​​the glass through-hole is aligned with the dense wiring area of ​​the silicon through-hole, which is conducive to fanning out the wiring layer by layer to the micron level. At the same time, the glass through-hole has limited dense wiring and a large through-hole diameter, and can be bonded to conduct analog chips with large circuits;

[0043] (7) In the cavity structure formed by the through silicon via and the through glass via, cross-layer conduction can be achieved through solder balls and copper pillars, and heat dissipation fins can also be provided to increase the heat dissipation efficiency in the XY horizontal direction of the side of the printed circuit board structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 This is a front view of the through silicon via structure of Example 1;

[0045] Figure 2 This is a front view of the through silicon via structure of the first embodiment;

[0046] Figure 3 is a front view of another through silicon via structure of the first embodiment;

[0047] Figure 4 This is a front view of the through-glass hole in the second embodiment;

[0048] Figure 5 is a front view of the printed circuit board structure of the second embodiment;

[0049] Figure 6 It is a front view of the printed circuit board structure electrically connected to the carrier board of Example 3;

[0050] Figure 7 This is a front view of the printed circuit board structure packaging module of Example 3;

[0051] Figure 8 It is another front view of the printed circuit board structure packaging module of the third embodiment;

[0052] Fig. 9 This is a front view of the printed circuit board structure packaging module of the fourth embodiment;

[0053] Fig.10 is a top view of the heat dissipation fins in the printed circuit board structure of the fourth embodiment;

[0054] Fig.11 is a top view projection diagram of stacked heat sink fins in the printed circuit board structure of the fourth embodiment;

[0055] Fig.12 It is a left view of the heat dissipation fins in the printed circuit board structure of the fourth embodiment.

[0056] Icons: Through Silicon Via 100, Through Silicon Via dense wiring area 101, first dense wiring area 101a, second dense wiring area 101b, third dense wiring area 101c, fourth dense wiring area 101d, Through Silicon Via non-dense wiring area 102, first non-dense wiring area 102a, second non-dense wiring area 102b, dense wiring area first pad 103a, dense wiring area second pad 103b, non-dense wiring area first pad 103c, non-dense wiring area second pad 103d, non-dense wiring area third pad 103e, non Fourth pad 103f in dense wiring area, wiring 104a in dense wiring area, wiring 104b in non-dense wiring area, silicon layer 105, first through silicon via groove 1001, second through silicon via groove 1002, step difference h1, step difference h2, first through silicon via groove width L1, second through silicon via groove width L2, active device 106a, active device 106b, active device 106c, active device 106d, passive device 107, passive device 107a, passive device 107b, solder ball 108a, solder ball 108b, solder ball 108c , solder ball 108d, solder ball 108e, solder wire 109, through glass via 200, through glass via 200a, through glass via 200b, through glass via dense wiring area 201, through glass via first dense wiring area 201a, through glass via second dense wiring area 201b, through glass via third dense wiring area 201c, through glass via non-dense wiring area 202, through glass via non-dense first wiring layer 202a, through glass via non-dense second wiring layer 202b, through glass via dense wiring area pad 203, through glass via dense wiring 204, Glass substrate 205, active device 206a, active device 206b, active device 206c, active device 206d, printed circuit board structure POP packaging module 300, heat sink fin 301, heat sink fin cavity 3001, heat sink fin body 3002, heat sink fin body substrate 3002a, heat sink fin body protrusion 3002b, heat sink fin body inner and outer diameter difference L3, heat sink fin cavity width L4, heat sink fin body protrusion width h3, heat sink fin body protrusion interval h4, heat sink fin body protrusion height h5. DETAILED DESCRIPTION

[0057] The embodiments of the present invention are described in detail below. The following embodiments are implemented on the premise of the technical solution of the present invention, and detailed implementation methods and specific operation processes are given, but the protection scope of the present invention is not limited to the following embodiments.

[0058] The preferred specific embodiments of the present invention are described in detail above. It should be understood that ordinary technicians in the field can make many modifications and changes based on the concept of the present invention without creative work. Therefore, all technical solutions that can be obtained by technicians in the technical field based on the concept of the present invention through logical analysis, reasoning or limited experiments on the basis of the prior art should be within the scope of protection determined by the claims.

[0059] Embodiment 1:

[0060] A printed circuit board structure, such as Figure 1 , as follows:

[0061] Figure 1 The through silicon via 100 structure of the printed circuit board structure forms a first through silicon via groove 1001 with a step difference of h1 and a second through silicon via groove 1002 with a step difference of h2 in the silicon layer 105. The width of the first through silicon via groove is L1, and the width of the second through silicon via groove is L2. The through silicon via 100 structure forms a through silicon via dense wiring area 101 and a through silicon via non-dense wiring area 102, wherein the through silicon via dense wiring area 101 forms a first dense wiring area 101a, a second dense wiring area 101b, a third dense wiring area 101c and a fourth dense wiring area 101d, and the left and right through silicon via non-dense wiring areas 102 form a first non-dense wiring area 102a and a second non-dense wiring area 102b.

[0062] The first dense wiring area 101a, the second dense wiring area 101b and the left TSV non-dense wiring area 102a are exposed from the first TSV groove 1001; the third dense wiring area 101c and the fourth dense wiring area 101d and the right second non-dense wiring area 102b are exposed from the second TSV groove 1002.

[0063] The first dense wiring area 101a and the second dense wiring area 101b form the second pad 103b in the dense wiring area and the second pad 103d in the non-dense wiring area, and the second pad 103b in the dense wiring area and the second pad 103d in the non-dense wiring area are exposed from the first through silicon via groove 1001; the left through silicon via non-dense wiring area 102a also forms the first pad 103c in the non-dense wiring area. The second pad 103b in the dense wiring area, the second pad 103d in the non-dense wiring area and the first pad 103c in the non-dense wiring area are interconnected and connected through the dense wiring area wiring 104a and the non-dense wiring area wiring 104b.

[0064] The third dense wiring area 101c and the fourth dense wiring area 101d form the first pad 103a of the dense wiring area and the third pad 103e of the non-dense wiring area, and the first pad 103a of the dense wiring area and the third pad 103e of the non-dense wiring area are exposed from the second through silicon via groove 1002; the right through silicon via non-dense wiring area 102b also forms the fourth pad 103f of the non-dense wiring area. The first pad 103a of the dense wiring area, the third pad 103e of the non-dense wiring area and the fourth pad 103f of the non-dense wiring area are interconnected and connected through the dense wiring area wiring 104a and the non-dense wiring area wiring 104b.

[0065] The step difference h1 and the step difference h2 can be adjusted and designed according to the number of vertically stacked components and the thickness of the components; the first silicon via groove width L1 and the second silicon via groove width L2 can be adjusted and designed according to the number of horizontally placed components and the length and width of the components.

[0066] In some specific embodiments, Figure 2 The dense wiring area wiring 104a formed by the through silicon via dense wiring area 101 is a thin line, which is electrically connected to the active device 106a and the active device 106b through the dense wiring area first pad 103a and the solder ball 108a (which may contain a solder wire 109) to fan out the dense wiring of the active device 106a and the active device 106b. The active device 106a and the active device 106b are bonded to the third dense wiring area 101c and the fourth dense wiring area 101d in the through silicon via dense wiring area 101 respectively. At the same time, the vertically stacked active devices 106a and the active devices 106b can be packaged face up through the solder ball 108c.

[0067] In some specific embodiments, Figure 2 The first non-dense wiring area 102a and the second non-dense wiring area 102b in the through silicon via non-dense wiring area 102 can realize electrical interconnection of the passive device 107 through the non-dense wiring area wiring 104b.

[0068] In some specific embodiments, Figure 2 The first non-dense wiring area 102a and the second non-dense wiring area 102b in the through silicon via non-dense wiring area 102 can be electrically interconnected across layers through the non-dense wiring area wiring 104b and the solder balls 108b.

[0069] In some specific embodiments, Figure 3, the first through silicon via groove 1001 can encapsulate active devices 106c, active devices 106d, and passive devices 107b; the second through silicon via groove 1002 can encapsulate active devices 106a, active devices 106b, and passive devices 107a. Active devices 106a, active devices 106b, active devices 106c, and active devices 106d are encapsulated in the through silicon via dense wiring area 101, and passive devices 107a and passive devices 107b are encapsulated in the through silicon via non-dense wiring area 102. Active devices 106a, active devices 106b, active devices 106c, and active devices 106d can be electrically interconnected with passive devices 107a and passive devices 107b through dense wiring area wiring 104a and non-dense wiring area wiring 104b.

[0070] Embodiment 2:

[0071] A printed circuit board structure, such as Figures 4-5 , as follows:

[0072] like Figure 4 The invention discloses a through glass via 200 based on a glass substrate 205 of a printed circuit board structure, wherein the through glass via 200 forms a through glass via dense wiring area 201 and a through glass via non-dense wiring area 202, wherein the through glass via dense wiring area 201 includes a through glass via first dense wiring area 201a, a through glass via second dense wiring area 201b and a through glass via third dense wiring area 201c, through glass via dense wiring area pads 203 are formed in the through glass via first dense wiring area 201a, the through glass via second dense wiring area 201b and the through glass via third dense wiring area 201c, and the lines between the through glass via first dense wiring area 201a, the through glass via second dense wiring area 201b and the through glass via third dense wiring area 201c are connected through the through glass via dense wiring 204. The TNV non-dense wiring area 202 includes a TNV first wiring layer 202a and a TNV second wiring layer 202b. The TNV first wiring layer 202a and the TNV second wiring layer 202b can be connected across layers.

[0073] like Figure 5, through glass vias 200a and through glass vias 200b are respectively pressed onto the printed circuit board structure 100 of the first embodiment, wherein the through glass via first dense wiring area 201a and the through glass via second dense wiring area 201b in the through glass via 200a are respectively bonded to the active devices 106a and 106b in the through silicon via 100 through solder balls 108c, and the through glass via first non-dense wiring layer 202a is connected to the through silicon via 100 through solder balls 108b; the through glass via first dense wiring area 201a and the through glass via second dense wiring area 201b in the through glass via 200b are respectively bonded to the active devices 106c and 106d in the through silicon via 100 through solder balls 108c, and the through glass via first non-dense wiring layer 202a is connected to the through silicon via 100 through solder balls 108b.

[0074] A printed circuit board structure, the preparation method of which comprises the following steps:

[0075] S1: providing a silicon-based wafer, performing mask protection on the non-etching area, etching using an existing etching process to form a first through silicon via groove 1001 and a second through silicon via groove 1002, and grinding and polishing;

[0076] S2: masking the first through silicon via groove 1001 and the second through silicon via groove 1002, and using the existing through silicon via processing technology and conventional CMOS process to process layer by layer to form non-dense wiring area wiring;

[0077] S3: Removing the mask, performing mask protection on the formed non-dense wiring area, and performing deep processing using the existing through silicon via processing technology and conventional CMOS process or stacked CMOS process to form dense wiring area wiring with an aspect ratio of 5 to 15;

[0078] S4: Perform pad ball planting or additive method to form copper pillars and bumps on the TSV structure with formed step difference, bond the active device and passive device to the TSV structure, perform plastic encapsulation, grind and level the board to expose the solder balls, copper pillars or bumps required for the active device to conduct;

[0079] S5: performing deep processing of the glass through hole by using at least one of a photosensitive glass method, a plasma etching method, an electrochemical method or a laser induced etching method, and forming an RDL layer layer by layer by using a conventional CMOS process;

[0080] S6: Alignment and calibration, pressing the glass through hole formed in step S5 to connect with the silicon through hole, interconnecting and conducting through at least one of solder balls, copper pillars or bumps, and performing secondary glue filling and plastic sealing.

[0081] Embodiment three:

[0082] A printed circuit board structure packaging module, such as Figures 6 to 8 , as follows:

[0083] like Figure 6 The printed circuit board structure in the second embodiment is debonded and leveled to expose the non-dense first wiring layer 202a of the through glass via 200b or the non-dense second wiring layer 202b of the through glass via, and an IC subtract is provided. The IC subtract is conductively connected to the non-dense first wiring layer 202a of the through glass via or the non-dense second wiring layer 202b of the through glass via in the printed circuit board structure in the second embodiment through the solder ball 108b.

[0084] like Figure 7 The printed circuit board structure in the second embodiment is debonded and leveled to expose the non-dense first wiring layer 202a of the through glass via 200b or the non-dense second wiring layer 202b of the through glass via, and the through glass via dense wiring area pad 203 of the through glass via third dense wiring area 201c is exposed. The active device 206a is bonded by at least one of solder balls 108e, copper pillars or bumps.

[0085] like Figure 8 In some specific embodiments, the printed circuit board structure in the second embodiment is debonded and leveled to expose the non-dense first wiring layer 202a of the through glass via 200a or the non-dense second wiring layer 202b of the through glass via, and the through glass via dense wiring area pad 203 of the through glass via third dense wiring area 201c is exposed. Active devices 206b, 206c, and 206d are bonded by at least one of solder balls 108f, copper pillars, or bumps.

[0086] Embodiment 4:

[0087] A printed circuit board structure packaging module, such as Figures 9 to 12 , as follows:

[0088] like Fig. 9 , is a printed circuit board structure POP packaging module 300, including the printed circuit board structure of the third embodiment and the heat sink fin 301, the heat sink fin 301 is placed in the first silicon via groove 1001 and the second silicon via groove 1002, and abuts against the glass through hole 200a and the glass through hole 200b. The heat sink fin 301 includes a heat sink fin cavity 3001 and a heat sink fin body 3002, the heat sink fin body 3002 includes a heat sink fin body substrate 3002a and a heat sink fin body protrusion 3002b, and the heat sink fin body protrusion 3002b extends to the outside of the printed circuit board structure of the third embodiment.

[0089] like Figures 10-12, are the top view and left view projections of the heat sink fins. The difference between the inner and outer diameters of the heat sink fin body L3 is smaller than the first through silicon via groove width L1 and the second through silicon via groove width L2. The width L4 of the vertically stacked heat sink fin cavity projection is larger than the width of the through silicon via dense wiring area 101, so that the heat sink fins can be accommodated by the first through silicon via groove and the second through silicon via groove. The width h3 of the heat sink fin body protrusion and the interval h4 of the heat sink fin body protrusion are both smaller than the step difference h1 and the step difference h2, and the height h5 of the heat sink fin body protrusion is smaller than the first through silicon via groove width L1 and the second through silicon via groove width L2.

[0090] The present invention provides a printed circuit board structure, which has the following beneficial effects: (1) a dense wiring area is formed in a through silicon via groove, and the dense wiring area is used for the electrical connection of active devices, which is beneficial to the fan-out of fine lines of active devices; (2) a non-dense wiring area is formed in the through silicon via groove, and the non-dense wiring area is used for the electrical connection of passive devices, which can realize partitioned fan-out wiring; (3) a dense wiring area is formed in the through silicon via groove, and the interconnection signal line is shortened, which is beneficial to reducing the loss of active device signals; (4) the through silicon via of the printed circuit board structure with a step-difference structure is beneficial to the embedding of devices, reducing the thickness of the entire board caused by surface mounting, and the size exceeds the tolerance, and reducing the electromagnetic interference between devices; (5) the through silicon via of the printed circuit board structure with a step-difference structure can pass According to the fan-out specification requirements of the active device wiring, the vertical distance between the upper and lower stacked active devices is designed to adjust the step size. Devices of different stack sizes can be embedded according to the step size to improve the device integration density; (6) Silicon through vias with dense wiring and small through hole diameter are formed in the printed circuit board structure, and the glass through holes with limited dense wiring and large through hole diameter are crimped. The dense wiring area of ​​the glass through hole is aligned with the dense wiring area of ​​the silicon through hole, which is conducive to the fan-out of the wiring layer by layer to the micron level. At the same time, the glass through hole has limited dense wiring and a large through hole diameter, and can be bonded to conduct analog chips with large circuits; (7) In the cavity structure formed by the silicon through vias and the glass through holes of the printed circuit board structure, cross-layer conduction can be achieved through solder balls and copper pillars, and heat dissipation fins can also be set to increase the heat dissipation efficiency in the XY horizontal direction of the side of the printed circuit board structure.

[0091] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0092] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. The protection scope of the patent of the present invention shall be based on the attached claims.

Claims

1. A printed circuit board structure, comprising a through silicon via (100), a through glass via (200), and an insulating layer, characterized in that: The through silicon via (100) is distributed with a through silicon via dense wiring area (101) and a through silicon via non-dense wiring area (102), the through silicon via (100) is formed with a through silicon via groove (1001 / 1002), and the through silicon via dense wiring area (101) and the through silicon via non-dense wiring area (102) are exposed from the through silicon via groove (1001 / 1002); The through glass via (200) is provided with a through glass via dense wiring area (201) and a through glass via non-dense wiring area (202); the through glass via dense wiring area (201) is provided with a through glass via first dense wiring area (201a), a through glass via second dense wiring area (201b) and a through glass via third dense wiring area (201c); the through glass via first dense wiring area (201a), the through glass via second dense wiring area (201b) and the through glass via third dense wiring area (201c) are provided with through glass via dense wiring area pads (203) and through glass via dense wiring (204); The through silicon via dense wiring area (101) vertically corresponds to the through glass via dense wiring area (201), and the through silicon via non-dense wiring area (102) vertically corresponds to the through glass via non-dense wiring area (202); The insulating layer plastic-seales the through silicon via (100) and the through glass via (200).

2. The printed circuit board structure according to claim 1, characterized in that: The through silicon via dense wiring area (101) is distributed with a first dense wiring area (101a), a second dense wiring area (101b), a third dense wiring area (101c) and a fourth dense wiring area (101d); the first dense wiring area (101a), the second dense wiring area (101b), the third dense wiring area (101c) and the fourth dense wiring area (101d) form a first pad (103a) of the dense wiring area, a second pad (103b) of the dense wiring area and a dense wiring area wiring (104a).

3. The printed circuit board structure according to claim 2, characterized in that: The active device is bonded to the first pad (103a) of the dense wiring area and the second pad (103b) of the dense wiring area, and fan-out wiring is performed through the dense wiring area wiring (104a); The active devices are stacked such that a pin of at least one of the active devices faces upward and the pin is exposed from the insulating layer.

4. The printed circuit board structure according to claim 3, characterized in that: The first dense wiring area (201a) of the through glass via corresponds vertically to the first dense wiring area (101a) of the through silicon via dense wiring area (101); the second dense wiring area (201b) of the through glass via corresponds vertically to the second dense wiring area (101b) of the through silicon via dense wiring area (101); The active devices in the through silicon via dense wiring area (101) are fanned out to the through glass via (200) through the pins facing upward, the through glass via dense wiring area pads (203) and the through glass via dense wiring (204).

5. The printed circuit board structure according to claim 1, characterized in that: The silicon through hole non-dense wiring area (102) is distributed with a first non-dense wiring area (102a) and a second non-dense wiring area (102b); the first non-dense wiring area (102a) and the second non-dense wiring area (102b) form a first pad (103c) of the non-dense wiring area, a second pad (103d) of the non-dense wiring area, a third pad (103e) of the non-dense wiring area, a fourth pad (103f) of the non-dense wiring area and wiring (104b) of the non-dense wiring area.

6. The printed circuit board structure according to claim 5, characterized in that: The second pad (103d) of the non-dense wiring area of ​​the first non-dense wiring area (102a) is bonded to a passive device (107), and the third pad (103e) of the non-dense wiring area of ​​the second non-dense wiring area (102b) is bonded to a passive device (107), and the passive device (107) is electrically interconnected through the non-dense wiring area wiring (104b).

7. The printed circuit board structure according to claim 6, characterized in that: The second solder pad (103d) of the first non-dense wiring area (102a) is connected to the glass through hole (200) through a solder ball, and the third solder pad (103e) of the second non-dense wiring area (102b) is connected to the glass through hole (200) through a solder ball.

8. The printed circuit board structure according to claim 1, characterized in that: A heat sink fin (301) is placed in the TSV non-dense wiring area (102) of the TSV groove, the heat sink fin (301) comprising a heat sink fin cavity (3001) and a heat sink fin body (3002), the heat sink fin body (3002) comprising a heat sink fin body substrate (3002a) and a heat sink fin body protrusion (3002b), and the heat sink fin body protrusion (3002b) extends to the outside of the TSV; The heat sink fins (301) are stacked vertically, and the projection of the overlapping heat sink fin cavities (3001) can cover the through silicon via dense wiring area (101); The heat dissipation fin body (3002) is fixed by plastic sealing of the insulating layer, abutting the through silicon via (100) and the through glass via (200), and the heat dissipation fin body protrusion (3002b) of the heat dissipation fin body (3002) is exposed from the insulating layer.

9. The packaging module of the printed circuit board structure according to any one of claims 1 to 8, characterized in that: The invention comprises at least one printed circuit board structure according to any one of claims 1 to 8, a carrier board and at least one active device, wherein the carrier board is electrically connected to the through glass via (200) of the printed circuit board structure through solder balls, and the active device is electrically connected to the through glass via dense wiring area pads (203) of the first through glass via dense wiring area (201a), the second through glass via dense wiring area (201b) and the third through glass via dense wiring area (201c), so as to fan out the wiring to the through glass via (200); The insulating layer plastic-seales the printed circuit board structure, the carrier board and the active device.

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