Method and system for testing integrated circuits

Abstract

The present application relates to a method and a test system for testing an integrated circuit. A method for testing an integrated circuit on a test circuit board includes: performing, by a processor, a simulation of a first thermal distribution across an entire integrated circuit design; manufacturing the integrated circuit according to the integrated circuit design; and simultaneously performing a burn-in test and an automated test on the integrated circuit. The burn-in test includes a minimum burn-in temperature for the integrated circuit and a burn-in thermal distribution across the integrated circuit. The integrated circuit design corresponds to the integrated circuit. The integrated circuit is coupled to the test circuit board. The integrated circuit includes a collection of circuit blocks and a first collection of heaters.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a method and a testing system for testing integrated circuits. Background Art

[0002] The recent trend toward miniaturization of integrated circuits (ICs) has resulted in smaller devices that consume less power but provide functionality at higher speeds. Miniaturization also creates stricter design and manufacturing specifications. Various electronic design automation (EDA) tools generate, optimize, and verify semiconductor device designs while ensuring that design and manufacturing specifications are met. However, testing semiconductor devices is a time-consuming process. Summary of the Invention

[0003] According to a first aspect of the present disclosure, there is provided A method for testing an integrated circuit on a test circuit board, the integrated circuit including a set of circuit blocks and a first set of heaters, the method comprising: performing, by a processor, a simulation of a first heat distribution across an integrated circuit design, the integrated circuit design being configured to operate at a simulated design power level and to generate the first heat distribution, the integrated circuit design corresponding to the integrated circuit; manufacturing the integrated circuit according to the integrated circuit design; and simultaneously performing a burn-in test on the integrated circuit and an automated test on the integrated circuit, the integrated circuit being configured to operate according to the simulated design power level, and the integrated circuit being coupled to the test circuit board, wherein the burn-in test has a minimum burn-in temperature of the integrated circuit and a burn-in heat distribution across the integrated circuit.

[0004] According to a second aspect of the present disclosure, there is provided A method for testing an integrated circuit on a test circuit board, the method comprising: performing, by a processor, a simulation of a first thermal distribution in an entire integrated circuit design, the integrated circuit design comprising a set of circuit blocks and a set of heaters, the integrated circuit design being configured to operate at a simulated design power level and generate the first thermal distribution, the simulated design power level comprising configuration power information, and performing the simulation comprising: determining a thermal signature of the integrated circuit design based on the configuration power information and position information of each circuit block in the set of circuit blocks and each heater in the set of heaters included in the integrated circuit design, the thermal signature comprising a thermal value distributed throughout the integrated circuit design; determining whether the thermal value of the thermal signature of the integrated circuit design is within a thermal range of the integrated circuit design; and modifying the integrated circuit design in response to determining that the thermal value of the thermal signature of the integrated circuit design is not within the thermal range; and manufacturing an integrated circuit based on the integrated circuit design.

[0005] According to a third aspect of the present disclosure, there is providedA test system includes: an integrated circuit; a test circuit board coupled to the integrated circuit; a carrier wafer coupled to at least the integrated circuit or the test circuit board; and a first system electrically coupled to the integrated circuit, the first system including: a non-transitory computer-readable medium configured to store executable instructions; and a processor coupled to the non-transitory computer-readable medium, wherein the processor is configured to execute the executable instructions to perform the following operations: perform a simulation of a first thermal distribution across an entire integrated circuit design, the integrated circuit design configured to operate at a simulated design power level and generating the first thermal distribution, and the integrated circuit design corresponding to the integrated circuit; wherein the test system is configured to simultaneously perform a burn-in test on the integrated circuit and an automated test on the integrated circuit, the integrated circuit configured to operate according to the simulated design power level, wherein the burn-in test has a minimum burn-in temperature of the integrated circuit and a burn-in thermal distribution across the entire integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure will be best understood by the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a block diagram of a system according to some embodiments.

[0008] Figure 2 is a diagram of a wafer according to some embodiments.

[0009] Figure 3 is a diagram of a carrier wafer according to some embodiments.

[0010] Figure 4 is a flow chart of a method of testing an integrated circuit according to some embodiments.

[0011] Figure 5 is a flow chart of a method according to some embodiments.

[0012] Figure 6 is a table according to some embodiments.

[0013] Figure 7 is a block diagram of an integrated circuit design according to some embodiments.

[0014] Figure 8 is a flow chart of a method for determining a thermal signature of an integrated circuit design according to some embodiments.

[0015] Figure 9A is a diagram of a power map according to some embodiments.

[0016] Figure 9B is a block diagram of an integrated circuit design according to some embodiments.

[0017] Figure 9C is a diagram of a heat map according to some embodiments.

[0018] Figure 10 is a flow chart of a method of modifying an integrated circuit design according to some embodiments.

[0019] Figure 11A is a diagram of a power diagram and integrated circuit design according to some embodiments.

[0020] Figure 11B is a diagram of a power diagram and integrated circuit design according to some embodiments.

[0021] Figure 11C is a diagram of a power diagram and integrated circuit design according to some embodiments.

[0022] Figure 12 is a flow chart of a method for simultaneously performing a burn-in test on an integrated circuit and an automated test on the integrated circuit according to some embodiments.

[0023] Figure 13 is a cross-sectional view of a heater according to some embodiments.

[0024] Figure 14 is a schematic diagram of a system for designing an IC layout design, simulating an IC design, and manufacturing an IC circuit, according to some embodiments.

[0025] Figure 15 is a block diagram of an IC manufacturing system and an IC manufacturing flow associated therewith according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] The following disclosure provides different embodiments or examples of features for implementing the claimed subject matter. Specific examples of components, materials, values, steps, or arrangements, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not restrictive. Other components, materials, values, steps, or arrangements, etc. are contemplated. For example, in the description below, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0027] Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0028] According to some embodiments, a method of testing an integrated circuit includes performing a simulation of a first thermal distribution throughout an integrated circuit design; manufacturing the integrated circuit according to the integrated circuit design; and concurrently performing a burn-in test on the integrated circuit and an automated test on the integrated circuit.

[0029] In some embodiments, by simultaneously performing a burn-in test on an integrated circuit and an automated test on the integrated circuit, a method for testing an integrated circuit has a shorter test time than other methods that perform a burn-in test after an automated test. In some embodiments, the burn-in test is stopped after a failure of the integrated circuit is detected, thereby reducing the burn-in test time.

[0030] system

[0031] Figure 1 is a block diagram of system 100 according to some embodiments.

[0032] In some embodiments, the system 100 is a test system configured to test a wafer 102. In some embodiments, the system 100 is configured to test an integrated circuit 201 (e.g., Figure 2 shown).

[0033] The system 100 includes a wafer 102 coupled to each of a test circuit board 104 and a carrier wafer 106. The wafer 102 includes a plurality of integrated circuits 201 (e.g., Figure 2 shown).

[0034] Test circuit board 104 is configured to perform one or more tests on wafer 102. Test circuit board 104 is electrically coupled to wafer 102. In some embodiments, test circuit board 104 is an automated test equipment (ATE) board and is configured to perform one or more automated tests on wafer 102. Test circuit board 104 is electrically coupled between wafer 102 and system 110. Test circuit board 104 is electrically coupled to system 110 via link 120. In some embodiments, wafer 102 is electrically coupled to system 110 via test circuit board 104. Other configurations of wafer 102 or test circuit board 104 are within the scope of the present disclosure.

[0035] Carrier wafer 106 is configured to carry wafer 102. Carrier wafer 106 includes one or more heater chips 108. Carrier wafer 106 and heater chips 108 are electrically coupled to system 110 via link 122. In some embodiments, at least link 120 or 122 is a conductive wire. In some embodiments, at least link 120 or 122 is a data link configured to exchange data. In some embodiments, heater chip 108 includes one or more dies electrically coupled to system 110 via link 122, and these dies are configured to generate heat during burn-in testing of wafer 102. Other configurations of carrier wafer 106 or heater chips 108 are within the scope of the present disclosure.

[0036] The system 110 is electrically coupled to the integrated circuits within the wafer 102 through the test circuit board 104. The system 110 is electrically coupled to one or more heater chips 108 of the carrier wafer 106 through a link 122.

[0037] System 110 is configured to simultaneously perform a burn-in test on one or more integrated circuits in wafer 102 and one or more automated tests on the one or more integrated circuits in wafer 102. In some embodiments, the one or more automated tests on the one or more integrated circuits in wafer 102 are performed by test circuit board 104 and system 110.

[0038] In some embodiments, the burn-in test includes testing wafer 102 for early failures of the integrated circuits within wafer 102. In some embodiments, the burn-in test is configured to apply thermal and environmental stresses to the integrated circuits within wafer 102, thereby inducing detectable failures in the integrated circuits within wafer 102. In some embodiments, the failures are caused by failures in the manufacturing process of wafer 102. In some embodiments, the burn-in test is configured to apply a minimum burn-in temperature T for a period of time. BI In some embodiments, the burn-in test is used to generate a burn-in thermal profile on the integrated circuits within the wafer 102. In some embodiments, the minimum burn-in temperature T BI The range is from about 120 degrees Celsius (C) to about 160° C. In some embodiments, the duration of the aging test is in the range of about 12 hours to about 72 hours.

[0039] In some embodiments, the one or more automated tests performed by test circuit board 104 and system 110 include voltage measurements, current measurements, timing measurements, or reliability tests. In some embodiments, the one or more automated tests include operational testing of one or more integrated circuits in wafer 102 .

[0040] In some embodiments, the system 110 is an electronic design automation (EDA) tool configured to design and simulate circuits that can be used to manufacture the integrated circuit 201 ( Figure 2 ) of the integrated circuit design 700 (eg Figure 7 shown) performance.

[0041] Other configurations of system 110 are within the scope of this disclosure.

[0042] In some embodiments, by simultaneously performing a burn-in test on one or more integrated circuits in wafer 102 and one or more automated tests (e.g., ATE) on one or more integrated circuits in wafer 102, system 100 can reduce test time compared to other approaches that perform burn-in testing after ATE testing. For example, in some embodiments, burn-in testing can be stopped after a failure of an integrated circuit in wafer 102 is detected, thereby reducing burn-in test time.

[0043] In some embodiments, by configuring the carrier wafer 106 with one or more heater chips 108, the heater chips 108 are configured as a heat source for burn-in testing of the wafer 102 and thereby provide a uniform baking solution, enabling the system 100 to perform burn-in testing without using a burn-in board or oven, thereby reducing costs compared to other methods using a burn-in board or oven.

[0044] Other configurations of system 100 are within the scope of this disclosure.

[0045] wafer

[0046] Figure 2 is a diagram of wafer 200 according to some embodiments.

[0047] Wafer 200 is Figure 1 The embodiment of the wafer 102 is omitted for similar detailed description. Figures 1 to 15 The same or similar components in one or more drawings are denoted by the same reference numerals, and thus their detailed description is omitted.

[0048] The wafer 200 includes a plurality of integrated circuits 201 arranged in an array.

[0049] Region 202 of wafer 200 corresponds to integrated circuit 203 in plurality of integrated circuits 201. Integrated circuit 203 corresponds to a single integrated circuit in plurality of integrated circuits 201. In some embodiments, each integrated circuit in plurality of integrated circuits 201 is identical. In some embodiments, at least one integrated circuit in plurality of integrated circuits 201 is different from another integrated circuit in plurality of integrated circuits 201.

[0050] In some embodiments, details of integrated circuit 203 are applicable to one or more of the plurality of integrated circuits 201 , and similar detailed descriptions are omitted for the sake of brevity.

[0051] Other configurations of the plurality of integrated circuits 201 are within the scope of this disclosure.

[0052] Integrated circuit 203 includes a circuit block set 204 and a heater set 206 .

[0053] Circuit block set 204 includes at least a central processing unit (CPU) 204a, CPU 240b, CPU 204c, CPU 204d, a graphics processing unit (GPU) 204e, or a phase-locked loop (PLL). Other numbers of circuits in circuit block set 204 are within the scope of the present disclosure.

[0054] The CPU, GPU, and PLL are used for illustration, and other types of circuits in the set of circuit blocks 204 are within the scope of various embodiments. For example, in some embodiments, the set of circuit blocks 204 includes an embedded processor including a processor core, a digital signal processing (DSP) core, an embedded GPU, an interface (e.g., a universal serial bus (USB) controller, ETHERNET, PCI-E, WIFI, WIMAX, or Bluetooth), a peripheral device (e.g., a universal asynchronous receiver transmitter (UART) or a power management block), or a memory module and / or controller.

[0055] At least the CPU 204 a, CPU 204 b, CPU 204 c, CPU 204 d, GPU 204 e, or PLL 204 f in the circuit block set 204 is configured to generate heat by being operated. In some embodiments, at least the CPU 204 a, CPU 204 b, CPU 204 c, CPU 204 d, GPU 204 e, or PLL 204 f in the circuit block set 204 is configured to generate heat by being operated during burn-in testing and ATE testing of the integrated circuit 200.

[0056] Heater assembly 206 includes at least heater 206a or heater 206b. At least heater 206a or 206b in heater assembly 206 is configured to generate heat. In some embodiments, at least heater 206a or 206b in heater assembly 206 is configured to generate heat during burn-in testing and ATE testing of integrated circuit 203. In some embodiments, when heater assembly 206 is not used for testing, at least heater 206a or 206b in heater assembly 206 is not configured to be operational and therefore does not generate heat.

[0057] In some embodiments, at least heater 206a or 206b in heater set 206 includes one or more interconnects 1302a and 1302b (e.g., Figure 13 In some embodiments, at least heater 206a or 206b in heater assembly 206 includes one or more circuit components configured to generate heat by being operated.

[0058] In some embodiments, the circuit block set 204 and the heater set 206 are configured as a heat source set for at least a burn-in test or ATE test performed by the system 100 to generate a thermal signature of the integrated circuit 203. In some embodiments, the thermal signature corresponds to a thermal profile of the entire integrated circuit. Figure 9C An example of a thermal profile 900C is shown in FIG.

[0059] In some embodiments, the set of circuit blocks 204 and the set of heaters 206 are configured to generate a uniform heat distribution throughout the integrated circuit 203. In some embodiments, the uniform heat distribution corresponds to a uniform heat distribution within a heat range HR (e.g., Figure 5 In some embodiments, the heat range is determined by the system 100 or the method 500 (e.g., FIG. 5 ). Figure 5 In some embodiments, the caloric range is between a minimum caloric value and a maximum caloric value.

[0060] In some embodiments, the thermal distribution of the entire integrated circuit 203 or the integrated circuit set 201 is modified by changing at least the position of the circuit block set 204 and the heater set 206, the number of circuit elements, the size, or the configured power. In some embodiments, at least the position of the circuit block set 204 and the heater set 206, the number of circuit elements, the size, or the configured power can be adjusted to generate a uniform thermal distribution across the entire integrated circuit 203. In some embodiments, if the integrated circuit 203 or the integrated circuit set 201 has a uniform thermal distribution, the system 100 is configured to perform a burn-in test while reducing Figure 1 The number of active elements in the heater chip 108 is determined.

[0061] In some embodiments, the circuit block set 204 and the heater set 206 are modified to generate the power at configured power levels corresponding to the simulated design power levels (e.g., Figure 6 In some embodiments, in response to the integrated circuit 203 or the integrated circuit set 201 having a uniform thermal distribution, the system 100 is configured to generate a uniform thermal distribution throughout the integrated circuit 203. Figure 1 A burn-in test is performed on the heater chip 108 as an active component.

[0062] Other configurations of the circuit block set 204 and the heater set 206 are within the scope of the present disclosure.

[0063] Other configurations of wafer 200 are within the scope of the present disclosure.

[0064] Carrier wafer

[0065] Figure 3 is a diagram of a carrier wafer 300 according to some embodiments.

[0066] The carrier wafer 300 is Figure 1 Embodiments of the carrier wafer 106 are discussed above, and therefore similar detailed descriptions are omitted.

[0067] The carrier wafer 300 includes a plurality of integrated circuit dies 301 arranged in an array.

[0068] Region 302 of carrier wafer 300 corresponds to an integrated circuit die 303 in the plurality of integrated circuit dies 301. Integrated circuit die 303 corresponds to a single integrated circuit die in the plurality of integrated circuit dies 301. In some embodiments, each integrated circuit die in the plurality of integrated circuit dies 301 is identical to another integrated circuit die in the plurality of integrated circuit dies. In some embodiments, at least one integrated circuit die in the plurality of integrated circuit dies 301 is different from another integrated circuit die in the plurality of integrated circuit dies 301.

[0069] Region 302 has the same area as region 202 of wafer 200. In some embodiments, region 302 has a different area than region 202 of wafer 200.

[0070] Each integrated circuit die in the plurality of integrated circuit dies 301 is associated with each corresponding integrated circuit in the plurality of integrated circuits 201 of wafer 200. In some embodiments, each corresponding integrated circuit die in the plurality of integrated circuit dies 301 is located at the same corresponding location as each corresponding integrated circuit in the plurality of integrated circuits 201 of wafer 200.

[0071] Each integrated circuit die in the plurality of integrated circuit dies 301 has the same area as each integrated circuit in the plurality of integrated circuits 201 of wafer 200. In some embodiments, at least one integrated circuit die in the plurality of integrated circuit dies 301 has a different area than at least one integrated circuit in the plurality of integrated circuits 201 of wafer 200.

[0072] In some embodiments, details of the integrated circuit die 303 apply to one or more of the plurality of integrated circuit dies 301 , and similar detailed descriptions are omitted for the sake of brevity.

[0073] Other configurations of the plurality of integrated circuit dies 301 are within the scope of the present disclosure.

[0074] Integrated circuit die 303 includes circuit die set 304 . Circuit die set 304 is an array of dies including at least die 304 a , 304 b , . . . , 304 y , or 304 z , where z is a positive integer corresponding to the number of dies in circuit die set 304 .

[0075] Each die in the circuit die-set 304 is identical to every other die in the circuit die-set. In some embodiments, at least one die in the circuit die-set 304 is different from at least one other die in the circuit die-set 304.

[0076] Each die in the circuit die set 304 has the same area as every other die in the circuit die set. In some embodiments, at least one die in the circuit die set 304 has a different area than at least another die in the circuit die set 304.

[0077] Each die in circuit die set 304 is configured to operate as a corresponding heater in heater set 306 .

[0078] Heater set 306 includes at least heaters 306a, 306b, ..., 306y, or 306z. Each heater in heater set 306 is configured to generate heat. In some embodiments, at least one or more heaters in heater set 306 are configured to generate heat during burn-in testing and ATE testing of integrated circuit 203.

[0079] In some embodiments, the thermal profile of the entire integrated circuit die 303 or integrated circuit die set 301 is modified by adjusting the configured power or turning on or off corresponding dies in the circuit die set 304. In some embodiments, by turning off a subset of dies in the die set 304, the heaters in the corresponding subset of heater set 306 are turned off and thus no heat is generated. In some embodiments, by turning on a subset of dies in the die set 304, the heaters in the corresponding subset of heater set 306 are turned on, thereby generating heat.

[0080] In some embodiments, the circuit die set 304 and the heater set 306 are configured as another set of heat sources for at least a burn-in test or an ATE test performed by the system 100 to generate another thermal signature of the integrated circuit die 203 .

[0081] In some embodiments, the heat signature generated by the integrated circuit 203 is combined with another heat signature of the integrated circuit die 303 to generate a uniform heat distribution throughout the integrated circuit 203. In some embodiments, by generating a uniform heat distribution throughout the integrated circuit 203, the burn-in test performed on the integrated circuit 203 and the integrated circuit die 303 achieves the above-mentioned Figure 1 One or more of the benefits discussed in .

[0082] In some embodiments, the integrated circuit die 303 or the integrated circuit die set 301 is configured as a supplemental heat source that, when combined with the heat source of the integrated circuit 303 or the integrated circuit die set 301 , creates a uniform heat distribution across the integrated circuit 303 .

[0083] In some embodiments, the number of heaters in heater set 306 is adjusted by adjusting the number of operating or turned-on dies in die set 304 , thereby adjusting the amount of heat generated by integrated circuit die 303 , and thus integrated circuit die 303 serves as a supplemental heat source to the heat source for integrated circuit 203 .

[0084] Other configurations of circuit die set 304 and heater set 306 are within the scope of the present disclosure.

[0085] Other configurations of carrier wafer 300 are within the scope of the present disclosure.

[0086] method

[0087] Figure 4 is a flow chart of a method 400 of testing an integrated circuit according to some embodiments.

[0088] In some embodiments, Figure 4 Yes Figure 1 System 100, Figure 14 Flowchart of a method of operating the system 1400 or the IC manufacturing system 1500.

[0089] To understand, at least Figure 4 The method described in 400, Figure 5 The method 500 described in Figure 8 The method 800 described in Figure 10 The method 1000 or Figure 12 Additional operations may be performed before, during, and / or after method 1200 depicted in the foregoing, and some other operations may be only briefly described herein. In some embodiments, other orders of operations of at least method 400, method 500, method 800, method 1000, or method 1200 are within the scope of the present disclosure. In some embodiments, one or more operations of at least method 400, method 500, method 800, method 1000, or method 1200 are not performed.

[0090] At least method 400, method 500, method 800, method 1000, or method 1200 includes exemplary operations, but the operations of at least method 400, method 500, method 800, method 1000, or method 1200 are not necessarily performed in the order shown. Operations of at least method 400, method 500, method 800, method 1000, or method 1200 may be added, substituted, reordered, and / or eliminated as appropriate, consistent with the spirit and scope of the disclosed embodiments. It should be understood that at least method 400, method 500, method 800, method 1000, or method 1200 utilizes features of one or more of system 100, wafer 200, carrier wafer 300, system 1400, or IC manufacturing system 1500.

[0091] In operation 402 of method 400, a simulation of heat distribution in the entire integrated circuit design is performed by a processor. In some embodiments, the simulation of operation 402 is performed by Figure 14 In some embodiments, the processor of method 400 includes Figure 14 Processor 1402.

[0092] In some embodiments, the integrated circuit design of method 400 includes at least Figure 7 Integrated Circuit Design 700, Figure 9A Integrated Circuit Design 900A, Figure 11A Integrated Circuit Design 1112, Figures 11B to 11C Integrated Circuit Design 1132, or Figure 11C The integrated circuit design of method 400 is 1162. In some embodiments, the integrated circuit design of method 400 is a design of an integrated circuit.

[0093] In some embodiments, the heat distribution of method 400 includes at least Figure 9C The heat distribution shown by the thermal signature 930 is Figure 11A The heat distribution shown by the thermal characteristics 1102 is Figure 11A The heat distribution shown by the thermal characteristics 1106 is Figures 11B to 11C The heat distribution shown by the thermal characteristics 1122 is Figure 11B The heat distribution shown by the thermal characteristics 1126, or by Figure 11C The thermal signature 1146 shows the heat distribution.

[0094] In operation 404 of method 400, an integrated circuit is manufactured according to the integrated circuit design. In some embodiments, the integrated circuit of method 400 includes at least wafer 102, wafer 200, multiple integrated circuits 201, or integrated circuit 203 ... Figure 15 The IC manufacturing system 1500 performs operation 404 .

[0095] In operation 406 of method 400, a burn-in test of the integrated circuit and an automated test of the integrated circuit are performed simultaneously. Figure 1 The system 100 performs operation 406. In some embodiments, the burn-in test of the method 400 includes: Figure 1 In some embodiments, the automated testing of method 400 includes the following steps: Figure 1 The system 100 performs an automatic test or ATE test, and similar detailed description is omitted.

[0096] Method 400 operates to implement the above description of at least Figure 1 System 100, Figure 2 Wafer 200 or Figure 3 The benefits of the carrier wafer 300 are discussed.

[0097] Figure 5 is a flow chart of a method 500 according to some embodiments.

[0098] In some embodiments, method 500 includes Figure 4 For example, in some embodiments, the method 500 includes: Figure 4 An embodiment of operations 402 and 404.

[0099] In some embodiments, method 500 is a method of performing simulation of thermal distribution throughout an integrated circuit design, and a method of fabricating an integrated circuit according to the integrated circuit design.

[0100] In some embodiments, a method for performing a simulation of thermal distribution throughout an integrated circuit design includes operations 502, 504, 506, 508, 510, 514, and 516. In some embodiments, operations 502, 504, 506, 508, 510, 514, and 516 are Figure 4 In some embodiments, one or more of operations 502, 504, 506, 508, 510, 514, and 516 are performed by Figure 14 Executed by system 110 or system 1400.

[0101] In some embodiments, a method of manufacturing an integrated circuit according to an integrated circuit design includes operation 512. In some embodiments, operation 512 is Figure 4 Operation 404, and similar detailed description is omitted. In some embodiments, by Figure 15 The IC manufacturing system 1500 performs operation 512 .

[0102] In operation 502 of method 500, a thermal range HR of an integrated circuit design is received from a user. In some embodiments, the user of method 500 includes at least Figure 14 In some embodiments, the heat range HR of method 500 includes Figure 1 In some embodiments, the heat range HR is defined as being between a minimum heat value Hmin and a maximum heat value Hmax.

[0103] In some embodiments, the heat values included in the heat range HR are considered to be a uniform heat distribution throughout the integrated circuit design. In some embodiments, the integrated circuit design of method 500 includes at least Figure 7 Integrated Circuit Design 700, Figure 9A Integrated Circuit Design 900A, Figure 11A Integrated Circuit Design 1112, Figures 11B to 11C Integrated Circuit Design 1132, or Figure 11C Integrated Circuit Design 1162.

[0104] In some embodiments, the integrated circuit design of method 500 is a design of an integrated circuit, such as at least wafer 102 , wafer 200 , plurality of integrated circuits 201 , or integrated circuit 203 .

[0105] In operation 504 of method 500 , configuration power information for the set of circuit blocks and the set of heaters in the integrated circuit design is obtained. In some embodiments, operation 504 of method 500 includes obtaining configuration power information for each circuit block in the set of circuit blocks and each heater in the set of heaters in the integrated circuit design.

[0106] In some embodiments, from a Figure 6 In some embodiments, table 600 is stored in a table such as table 600 of FIG. Figure 14 In some embodiments, the configuration power information of method 500 includes at least Figure 6 Maximum configured power information 604 or Figure 6 Configuration power information 606.

[0107] In some embodiments, the set of circuit blocks of the integrated circuit design of method 500 includes at least Figure 7 or Figures 11A to 11C In some embodiments, the circuit block set of the integrated circuit design of method 500 includes at least Figure 6 circuit blocks 602a, 602b or 602e.

[0108] In some embodiments, the heater set of the integrated circuit design of method 500 includes at least Figure 7 Heater assembly 706 or Figure 11C In some embodiments, the heater set of the integrated circuit design of method 500 includes at least Figure 6 heater 602c or 602d.

[0109] In operation 506 of method 500, location information for the set of circuit blocks and the set of heaters in the integrated circuit design is extracted from a design file (DEF). In some embodiments, operation 506 of method 500 includes extracting location information for each circuit block in the set of circuit blocks and each heater in the set of heaters in the integrated circuit design from the design file. In some embodiments, the design file of method 500 is stored in Figure 14 in the memory 1404.

[0110] In some embodiments, the location information of the circuit block set and the heater set in the integrated circuit design used in method 600 includes the location of each component in the integrated circuit design. In some embodiments, the design file of method 500 includes a Design Exchange Format (DEF) representing the physical layout of the integrated circuit design. In some embodiments, the DEF is in the American Standard Code for Information Interchange (ASCII) format and represents the netlist and circuit layout of the integrated circuit design.

[0111] In operation 508 of method 500 , thermal characteristics of the integrated circuit design are determined based on the configured power information and location information for the set of circuit blocks and the set of heaters included in the integrated circuit design.

[0112] In some embodiments, the thermal signature is a two-dimensional map of thermal values HV arranged throughout the integrated circuit design. In some embodiments, the thermal value HV is generated by each circuit block in the set of circuit blocks and each heater in the set of heaters included in the integrated circuit design.

[0113] In some embodiments, the heat value HV of the integrated circuit design is determined by Formula 2 (hereinafter referred to as Figure 8 and Figures 9A to 9C In some embodiments, Figure 8 Method 800 is an embodiment of operation 508 .

[0114] In some embodiments, operation 508 of method 500 includes determining a thermal signature of the integrated circuit design based on configured power information and location information for each circuit block in the set of circuit blocks and each heater in the set of heaters included in the integrated circuit design.

[0115] In some embodiments, the thermal characteristics of method 500 include at least Figure 9C Thermal characteristics of 930, Figure 11A Thermal characteristics 1102, Figure 11A Thermal characteristics 1106, Figures 11B to 11C Thermal characteristics 1122, Figure 11B Thermal characteristics 1126, or Figure 11C Thermal signature 1146.

[0116] In operation 510 of method 500 , it is determined whether a thermal value HV of a thermal signature of the integrated circuit design is within a user-specified thermal range HR.

[0117] In some embodiments, operation 510 includes determining whether a thermal value HV of a thermal signature of the integrated circuit design is equal to or greater than a minimum thermal value Hmin and equal to or less than a maximum thermal value Hmax.

[0118] In some embodiments, if the thermal value HV of the thermal signature of the integrated circuit design is within the user-specified thermal range HR, the result of operation 510 is “yes” and the method 500 proceeds to operation 512. In some embodiments, if the thermal value HV of the thermal signature of the integrated circuit design is within the user-specified thermal range HR, the thermal value HV of the thermal signature of the integrated circuit design is sufficient to enable the integrated circuit design to generate a uniform thermal distribution, thereby indicating that integrated circuits manufactured based on the integrated circuit design also generate a uniform thermal distribution, and the burn-in test of operation 406 performed by the system 100 is performed without activating the heater of the carrier wafer 106.

[0119] In some embodiments, if the thermal value HV of the thermal signature of the integrated circuit design is not within the user-specified thermal range HR, the result of operation 510 is “no” and the method 500 proceeds to operation 514 .

[0120] In operation 512 of method 500, an integrated circuit is manufactured according to the integrated circuit design. In some embodiments, the integrated circuit of method 500 includes at least wafer 102, wafer 200, multiple integrated circuits 201, or integrated circuit 203 ... Figure 15 The IC manufacturing system 1500 performs operation 512. In some embodiments, operation 512 is Figure 4 Operation 404 is performed, and similar detailed description is omitted.

[0121] In operation 514 of method 500, a determination is made as to whether the number of repetitions of operation 508, 510, or 516 exceeds a user-defined limit. In some embodiments, the user-defined limit of method 500 includes a maximum number of repetitions at which at least operation 508, 510, or 516 is performed. In operation 502 of method 500, the user-defined limit of method 500 is received from a user.

[0122] In some embodiments, if the number of repetitions of operations 508, 510, or 516 does not exceed the user-defined limit, the result of operation 514 is "No," and method 500 proceeds to operation 516. In some embodiments, if the number of repetitions of operations 508, 510, or 516 does not exceed the user-defined limit, the thermal value HV of the thermal signature of the integrated circuit design is insufficient to generate a uniform thermal distribution for the integrated circuit design, and method 500 attempts to modify the integrated circuit design via operation 516.

[0123] In some embodiments, if the number of repetitions of operations 508, 510, or 516 exceeds the user-defined limit, the result of operation 514 is "yes," and the method 500 proceeds to operation 512. In some embodiments, if the number of repetitions of operations 508, 510, or 516 exceeds the user-defined limit, the thermal value HV of the thermal signature of the integrated circuit design is insufficient to generate a uniform thermal distribution for the integrated circuit design, indicating that integrated circuits manufactured based on the integrated circuit design will not generate a uniform thermal distribution. Therefore, when the burn-in test of operation 406 performed by the system 100 is performed, the heater of the carrier wafer 106 is enabled to generate a supplemental thermal distribution, wherein the supplemental thermal distribution, when combined with the thermal distribution of the integrated circuits, is a uniform thermal distribution.

[0124] In operation 516 of method 500, the integrated circuit design is modified. In some embodiments, the integrated circuit design is modified in response to determining that the thermal value HV of the thermal characteristic of the integrated circuit design is not within the thermal range HR. In some embodiments, Figure 10 Method 1000 is an embodiment of operation 516 .

[0125] In some embodiments, operation 516 includes one or more of the following operations: adding a new circuit block to the circuit block set; adding a new heater to the heater set; removing the first heater from the heater set; moving the position of the first heater in the heater set; modifying the configured power of the first circuit block in the circuit block set; modifying the configured power of the first heater in the heater set, or modifying the size of the first heater in the heater set.

[0126] In some embodiments, the new circuit block or first circuit block in the set of circuit blocks of method 500 includes one or more circuit blocks similar to the set of circuit blocks 704 of the integrated circuit design. In some embodiments, the new heater or first heater in the set of heaters of method 500 includes one or more circuit blocks similar to the set of heaters 706 or 707 of the integrated circuit design. Figure 11C One or more heaters similar to heater 1164a.

[0127] In some embodiments, one or more of operations 508, 510, 514, or 516 are repeated to modify the integrated circuit design. In some embodiments, one or more of operations 508, 510, 514, or 516 are repeated until the thermal value HV of the thermal signature of the integrated circuit design is within a thermal range HR specified by the user, or the number of repetitions of operations 508, 510, or 516 exceeds a user-defined limit.

[0128] Method 500 operates to implement the above description of at least Figure 1 System 100, Figure 2 Wafer 200 or Figure 3 The benefits of the carrier wafer 300 are discussed.

[0129] surface

[0130] Figure 6 is table 600 according to some embodiments.

[0131] Table 600 is such as Figure 7 A lookup table of parameters of an integrated circuit design such as integrated circuit design 700 is provided.

[0132] Table 600 and Figure 5 In some embodiments, the method 500 is used with one or more operations of the method 500. In some embodiments, the method 500 is used with the lookup table 600. In some embodiments, one or more of operations 502, 504, 506, 508, or 516 of the method 500 utilizes a lookup table similar to Figure 6 In some embodiments, the table 600 is stored in Figure 14 In some embodiments, table 600 is composed of Figure 14 System 1400 generated.

[0133] Table 600 includes 6 rows and 3 columns. Column 1 includes a set of IC design elements 602. Column 2 includes a corresponding set of maximum configurable power entries 604 for the set of IC design elements 602. Column 3 includes a corresponding set of configurable power entries 606 for the set of IC design elements 602. Each entry in column 1 has a corresponding entry in column 2 and a corresponding entry in column 3.

[0134] Other numbers of columns or rows in table 600 are within the scope of the present disclosure.

[0135] IC design element set 602 includes at least IC design elements 602a, 602b, 602c, 602d, or 602e. IC design element set 602 corresponds to circuit block set 704 or heater set 706 of the integrated circuit design. IC design elements 602a, 602b, and 602e correspond to one or more circuit blocks in circuit block set 704 of integrated circuit design 700. IC design elements 602c and 602d correspond to one or more heaters in heater set 706 of integrated circuit design 700.

[0136] Other numbers of IC design elements in IC design element set 602 are within the scope of the present disclosure. Other numbers of circuit blocks or heaters in IC design element set 602 are within the scope of the present disclosure.

[0137] Column 2 includes a set of maximum configurable power entries 604 corresponding to the set of IC design elements 602. The set of maximum configurable power entries 604 includes at least a maximum configurable power entry 604a, 604b, 604c, 604d, or 604e. Each maximum configurable power entry 604a, 604b, 604c, 604d, or 604e in the set of maximum configurable power entries 604 is the maximum configurable power at which the corresponding IC design element 602a, 602b, 602c, 602d, or 602e in the set of IC design elements 602 can operate.

[0138] Other numbers or values of maximum configurable power entries in the set of maximum configurable power entries 604 are within the scope of the present disclosure.

[0139] Column 3 includes a set of configurable power entries 606 corresponding to the set of IC design elements 602 or the set of maximum configurable power entries 604 .

[0140] Configurable power entry set 606 includes at least configurable power entries 606a, 606b, 606c, 606d, or 606e. Each configurable power entry 606a, 606b, 606c, 606d, or 606e in configurable power entry set 606 is a configurable power at which a corresponding IC design element 602a, 602b, 602c, 602d, or 602e in IC design element set 602 can operate (excluding the maximum configurable power of column 2).

[0141] Other numbers or values of configurable power entries 606 in the set of configurable power entries 606 are within the scope of the present disclosure.

[0142] Configurable power entry 606a includes one or more configurable power entries that IC design element 602a can operate in. For example, configurable power entry 606a includes configurable power entries of 6 watts (W), 4 W, and 2 W that IC design element 602a can operate in.

[0143] Configurable power entry 606b includes one or more configurable power entries at which IC design element 602b can operate. For example, configurable power entry 606b includes configurable power entries 6W, 4W, and 2W at which IC design element 602b can operate.

[0144] Configurable power entry 606c includes one or more configurable power entries at which IC design element 602c can operate. For example, configurable power entry 606c includes configurable power entries 1W and 0.5W at which IC design element 602c can operate.

[0145] Configurable power entry 606d includes one or more configurable power entries at which IC design element 602d can operate. For example, configurable power entry 606d includes configurable power entries 2.5W and 1.25W at which IC design element 602d can operate.

[0146] Configurable power entry 606d includes one or more configurable power entries at which IC design element 602d can operate. For example, configurable power entry 606d includes configurable power entries 2.5W and 1.25W at which IC design element 602d can operate.

[0147] Configurable power entry 606e includes one or more configurable power entries at which IC design element 602e can operate. For example, configurable power entry 606e includes a configurable power entry of 0.25W at which IC design element 602e can operate.

[0148] In some embodiments, during operation 516 of method 500, the integrated circuit design is modified by adjusting (e.g., increasing or decreasing) the configured power of one or more circuit blocks in the set of circuit blocks or one or more heaters in the set of heaters according to the set of maximum configurable power entries 604 and the set of configurable power entries 606 of table 600. For example, in some embodiments, if a heat value HV generated by an IC design element 602a having a configurable power 606a of 2 W is less than a heat range HR, the configurable power 606a of the IC design element 602a may be increased from 2 W to 4 W, up to the maximum configurable power 604a in column 2.

[0149] integrated circuit design

[0150] Figure 7 is a block diagram of an integrated circuit design 700 according to some embodiments.

[0151] Integrated circuit design 700 corresponds to Figure 6 In some embodiments, the integrated circuit design 700 is associated with the table 600, and therefore similar detailed description is omitted. Figure 6 The IC design element set 602 , the maximum configurable power entry set 604 , and the configurable power entry set 606 of the table 600 correspond to the integrated circuit designs, and thus similar detailed descriptions are omitted.

[0152] In some embodiments, the integrated circuit design 700 is Figure 2 IC 203 or Figure 2 The integrated circuit design 700 may be used to manufacture one or more integrated circuits of the plurality of integrated circuits 201, and therefore similar detailed descriptions are omitted. Figure 2In some embodiments, the integrated circuit design 700 is stored in Figure 14 In some embodiments, the integrated circuit design 700 is composed of Figure 14 System 1400 generated.

[0153] The integrated circuit design 700 includes a circuit block set 704 and a heater set 706. In some embodiments, the circuit block set 704 of the integrated circuit design 700 may be used to manufacture Figure 2 The circuit block set 204 of the integrated circuit 203 is similarly described and thus a similar detailed description is omitted. In some embodiments, the heater set 706 of the integrated circuit design 700 can be used to manufacture Figure 2 In some embodiments, the operation of the elements of integrated circuit design 700 is similar to the corresponding elements of integrated circuit 203, and similar descriptions are omitted for brevity.

[0154] The circuit block set 704 includes at least a CPU 704a, a CPU 704b, a CPU 704c, a CPU 704d, a GPU 704e, or a PLL 704f. In some embodiments, at least the CPU 704a, the CPU 704b, the CPU 704c, the CPU 704d, the GPU 704e, or the PLL 704f of the integrated circuit design 700 may be used to manufacture Figure 2 The integrated circuit 203 includes at least the CPU 204a, the CPU 204b, the CPU 204c, the CPU 204d, the GPU 204e, or the PLL 204f, and thus similar detailed description is omitted.

[0155] In some embodiments, at least the CPU 704 a, CPU 704 b, CPU 704 c, CPU 704 d, GPU 704 e, or PLL 704 f in the set of circuit blocks 704 is configured to operate at one or more power levels according to the set of configurable power entries 606 of table 600 or the set of maximum configurable power entries 604 of table 600 , thereby generating thermal values and thermal characteristics of the integrated circuit design during execution of operation 402 of method 400 .

[0156] In some embodiments, Figure 2At least the CPU 204 a, CPU 204 b, CPU 204 c, CPU 204 d, GPU 204 e, or PLL 204 f in the set of circuit blocks 204 is configured to operate at one or more power levels according to the set of configurable power entries 606 of table 600 or the maximum set of configurable power entries 604 of table 600, thereby generating heat during burn-in testing and ATE testing of the integrated circuit 200 (e.g., operation 406 of method 400).

[0157] Other quantities of circuits in circuit block set 704 are within the scope of the present disclosure.

[0158] The heater set 706 includes at least one heater 706a or one heater 706b. In some embodiments, at least one heater 706a or one heater 706b in the integrated circuit design 700 may be used to manufacture Figure 2 At least the heater 206a or the heater 206b in the integrated circuit 203, so similar detailed description is omitted.

[0159] In some embodiments, at least heater 706a or heater 706b in heater set 706 is configured to operate at one or more power levels according to configurable power entry set 606 of table 600 or maximum configurable power entry set 604 of table 600, thereby generating thermal values and thermal characteristics of the integrated circuit design during execution of operation 402 of method 400.

[0160] In some embodiments, Figure 2 At least heater 206a or 206b in heater set 206 is configured to operate at one or more power levels according to configurable power entry set 606 of table 600 or maximum configurable power entry set 604 of table 600 to generate heat during burn-in testing and ATE testing of integrated circuit 200 (e.g., operation 406 of method 400).

[0161] Other numbers of heaters in heater set 706 are within the scope of the present disclosure.

[0162] In some embodiments, the set of circuit blocks 704 and the set of heaters 706 are configured as a set of heat sources to generate a thermal signature of the integrated circuit design 700 during performance of operation 402 of method 400 .

[0163] In some embodiments, the set of circuit blocks 704 and the set of heaters 706 are configured to generate a uniform heat distribution throughout the integrated circuit design 700. In some embodiments, the set of circuit blocks 704 and the set of heaters 706 are modified to generate a uniform heat distribution throughout the integrated circuit design 700. Figure 6The configured power levels contained in table 600 operate to generate a uniform thermal distribution throughout the integrated circuit design 700 .

[0164] In some embodiments, the thermal distribution throughout the integrated circuit design 700 is modified by changing at least the location, number of circuit elements, size, or configured power of the circuit element set 704 and the heater set 706. In some embodiments, the location, number of circuit elements, size, or configured power of at least the circuit element set 704 and the heater set 706 can be adjusted to generate a uniform thermal distribution throughout the integrated circuit design 700.

[0165] In some embodiments, if the integrated circuit design 700 has a uniform thermal distribution, the integrated circuit 201 manufactured based on the integrated circuit design 700 can be used with the system 100 during burn-in testing of the integrated circuit 201 or the wafer 102 while reducing Figure 1 In some embodiments, during burn-in testing of wafer 102 or integrated circuit 201 based on integrated circuit design 700, Figure 1 The number of active elements in the heater chip 108 is zero.

[0166] In some embodiments, if the integrated circuit design 700 does not have a uniform thermal distribution, during a burn-in test of the integrated circuit 201 or the wafer 102 performed by the system 100, the integrated circuit 201 manufactured based on the integrated circuit design 700 is exposed to a supplemental heat source (e.g., Figure 1 The heater chip 108 may be combined with multiple switched-on elements or supplemental heat sources generated by active elements.

[0167] Other configurations of the set of circuit blocks 704 and the set of heaters 706 are within the scope of the present disclosure.

[0168] Other configurations of integrated circuit design 700 are within the scope of this disclosure.

[0169] method

[0170] Figure 8 is a flow chart of a method 800 of determining thermal characteristics of an integrated circuit design, according to some embodiments.

[0171] In some embodiments, method 800 is an embodiment of operation 508 of method 500, and similar detailed description is omitted. In some embodiments, one or more of operations 802, 804, 806, and 808 are performed by Figure 14 Executed by system 110 or system 1400.

[0172] In some embodiments, the method 800 may be used to determine thermal characteristics of, for example, the following integrated circuit designs: Figure 9A Integrated Circuit Design 902, Figure 11A Integrated Circuit Design 1112, Figures 11B to 11C Integrated Circuit Design 1132, or Figure 11C Integrated Circuit Design 1162.

[0173] In some embodiments, method 800 may be used to determine thermal signatures, such as Figure 9C Thermal characteristics of 930, Figure 11A Thermal characteristics 1102 and 1106, Figure 11B Thermal characteristics 1122 and 1126, and Figure 11C Thermal characteristics 1122 and 1146.

[0174] In operation 802 of method 800, the integrated circuit design is divided into an array of windows. In some embodiments, the integrated circuit design is divided into the array of windows based on window size. In some embodiments, the window size is user-defined. In some embodiments, the windows of the array of windows have the same window size. In some embodiments, the window size is in a range of about 1 μm to about 20 μm. Other values of the window size are within the scope of the present disclosure.

[0175] In some embodiments, the integrated circuit design of method 800 includes at least Figure 7 Integrated Circuit Design 700, Figure 9A Integrated Circuit Design 902, Figure 11A Integrated Circuit Design 1112, Figures 11B to 11C Integrated Circuit Design 1132, or Figure 11C Integrated Circuit Design 1162.

[0176] In some embodiments, the window array of method 800 includes at least Figures 9A to 9B Array of windows 901. In some embodiments, Figure 9A Integrated circuit design 902 includes a window array 901 , which illustrates a non-limiting example of a window array after operation 802 is performed.

[0177] In some embodiments, each window in the window array has a square shape. In some embodiments, one or more windows in the window array are circular, triangular, rectangular, square, hexagonal, or other geometric shapes. In some embodiments, one or more windows in the window array are polygonal. Other shapes of window arrays are within the scope of the present disclosure.

[0178] In operation 804 of method 800, a power value for each window in the window array is determined based on the power information and position information of the circuit block set and the heater set. In some embodiments, operation 804 includes: generating a power value similar to Figure 9A In some embodiments, the power value of each window of method 800 corresponds to the power consumed by each circuit block or heater within the corresponding window.

[0179] In some embodiments, the power information of method 800 includes configured power information obtained for operation 504 of method 500. In some embodiments, the power information of method 800 includes configured power entry set 606 from table 600 or maximum configured power entry set 604 from table 600. In some embodiments, the location information of method 800 includes location information extracted for operation 506 of method 500.

[0180] In some embodiments, the set of circuit blocks of the integrated circuit design of method 800 includes at least Figure 7 or Figures 11A to 11C Circuit block set 704 or Figure 9A In some embodiments, the circuit block set of the integrated circuit design of method 800 includes at least Figure 6 circuit blocks 602a, 602b or 602e.

[0181] In some embodiments, the heater set of the integrated circuit design of method 800 includes at least Figure 7 Heater set 706, Figure 11C Heater 1164A or Figure 9A The heater set 906. In some embodiments, the heater set of the integrated circuit design of method 800 includes at least Figure 6 heater 602c or 602d.

[0182] In some embodiments, the power value P of each window of method 800 (e.g., also referred to as “power per window”) is determined according to Formula 1, where the power value P is expressed as:

[0183] P=NE / PE (1)

[0184] Wherein, NE is the number of elements covered by the first region of the integrated circuit design, and PE is the power consumed by the circuit blocks or heaters in the first region.

[0185] Non-limiting exemplary applications of Equation 1 include reference to 9A. For example, in some embodiments, Figure 9A Element 904a corresponds to circuit block 704A in layout design 700 and occupies Figure 9AThus, region 910 occupies or covers a total of 25 windows, and the power consumed for circuit block entry 606a according to table 600 is 2.5 W, applying equation 1 to these values results in 2.5 W divided by 25 windows, which equals 0.1 W per window. Figure 9A As shown, region 910 has a power value P (shown in keyword 920) equal to 0.1W.

[0186] In operation 806 of method 800, a total heat value H of each window is determined based on the power value P of each window. T .

[0187] In some embodiments, the total heat H of each window of method 800 is determined according to Equation 2. T , the total calorific value H T Expressed as:

[0188]

[0189] Where Pij is the power value of the i-th and j-th index, k is a constant based on the material of the circuit block or heater, Dij is the distance between the i-th and j-th windows, m is the number of rows in the window array, and n is the number of columns in the window array.

[0190] In some embodiments, the total calorific value H of each window of operation 806 is T The total heat value H for each window of operation 806 is the sum of the heat generated by the corresponding window and the heat generated by each other window in the integrated circuit design. T The value of k is the sum of the heat generated by the corresponding window and the heat generated by multiple other windows in the integrated circuit design within a defined distance of the current window. In some embodiments, the value of k is based on the semiconductor material within the heater or circuit block. In some embodiments, the value of k is equal to 1.

[0191] A non-limiting exemplary application of Equation 2 includes reference to 9B. For example, integrated circuit design 900B corresponds to Figure 9A The circuit block 904 of the integrated circuit design 900B is shown in FIG. 1 , but the integrated circuit design 900B further includes a region 950, and similar detailed description is omitted. The region 950 includes four windows (950a, 950B, 950c, and 950d), and the total calorific value H of the window 950a is determined. T11 Determining the heat value H generated by window 950a 11 and the heat value (H) generated by each of the other windows (950b, 950c, 950d) in region 950 of integrated circuit design 900B. 21 、H 12 、H 22). In this example, the region includes 4 windows, but it is within the scope of the present disclosure to include other numbers of windows in the region. Applying Equation 2 to the non-limiting example results in a total calorific value H for window 950a. T11 Equal to H T11 =k*(P 11 +(P 12 / D 12 )+(P 21 / D 21 )+(P 22 / D 22 ), where the power value P 11 、P 12 、P 21 and P 22 are the respective power values of the respective windows 502a, 502b, 502c, and 502d, which are determined in operation 804 and are shown as Figure 9A Integrated circuit power diagram 900A.

[0192] In some embodiments, operation 806 is performed for each circuit block in the set of circuit blocks and each heater in the set of heaters in the integrated circuit design to determine a total thermal value for the integrated circuit design.

[0193] In some embodiments, by partitioning the integrated circuit design into an array of windows, method 800 can accurately determine the heat generated at each window of the integrated circuit design by considering not only the heat generated by each window of the integrated circuit design, but also the impact of the heat generated by every other window in the integrated circuit design.

[0194] In operation 808 of method 800, a thermal map is populated based on the total thermal value of each window, thereby generating a thermal signature of the integrated circuit design. In some embodiments, operation 808 includes: generating a thermal map similar to Figure 9C Thermal diagram of 900C.

[0195] In some embodiments, operation 808 includes creating a heat map based on at least the position information of each window in the array of windows and the respective total heat value of each respective window.

[0196] In some embodiments, thermal features of method 800 include, for example, Figure 9C Thermal characteristics of 930, Figure 11A Thermal characteristics 1102 and 1106, Figure 11B Thermal characteristics 1122 and 1126, and Figure 11C Thermal characteristics 1122 and 1146.

[0197] Method 800 operates to implement the above description of at least Figure 1System 100, Figure 2 Wafer 200, Figure 3 Carrier wafer or Figure 4 The benefits of method 400 are discussed above.

[0198] Figure 9A is a diagram of a power graph 900A according to some embodiments.

[0199] Power diagram 900A corresponds to the power diagram of integrated circuit design 700, and thus similar detailed description is omitted. In some embodiments, power diagram 900A is generated by system 1400 when executing Figure 8 Generated during operation 804.

[0200] Power graph 900A includes integrated circuit design 902 and power keywords 920 that illustrate the configured power of each component in integrated circuit design 902. In some embodiments, power keywords 920 illustrate the configured power of each circuit block in set of circuit blocks 904 and each heater in set of heaters 906.

[0201] Integrated circuit design 902 corresponds to integrated circuit design 700, so similar detailed description is omitted. Integrated circuit design 902 is divided into window array 901. In some embodiments, the integrated circuit design 902 is divided into window array 901 corresponding to Figure 8 Operation 802.

[0202] Integrated circuit design 902 includes a set of circuit blocks 904 and a set of heaters 906. In some embodiments, the set of circuit blocks 904 is Figure 7 The corresponding circuit block set 704 and the heater set 906 are Figure 7 , and similar detailed description is omitted.

[0203] The circuit block set 904 includes at least a CPU 904a, a CPU 904b, a CPU 904c, a CPU 904d, a GPU 904e, or a PLL 904f. In some embodiments, the CPU 904a, the CPU 904b, the CPU 904c, the CPU 904d, the GPU 904e, or the PLL 904f is Figure 7 704a, CPU 704b, CPU 704c, CPU 704d, GPU 704e or PLL 704f, and similar detailed descriptions are omitted.

[0204] Other quantities of circuits in circuit block set 904 are within the scope of the present disclosure.

[0205] The heater assembly 906 includes at least one heater 906a or one heater 906b. In some embodiments, the heater 906a or the heater 906b is Figure 7 7. The corresponding heater 706a or heater 706b is shown in FIG. 1 and similar detailed description is omitted. Other numbers of heaters in heater set 906 are within the scope of the present disclosure.

[0206] Other configurations of the power diagram 900A are within the scope of the present disclosure.

[0207] Figure 9B is a block diagram of an integrated circuit design 900B according to some embodiments.

[0208] Integrated circuit design 900B corresponds to using power values P in corresponding windows 902a, 902b, 902c, and 902d. 11 、P 12 、P 21 and P 22 To fill Figure 9A The integrated circuit design 902 is shown in FIG. 1 , and similar detailed description is omitted.

[0209] In some embodiments, the system 1400 performs Figure 8 The power values P in the corresponding windows 902a, 902b, 902c and 902d are used in operation 804, 806 or 808. 11 、P 12 、P 21 and P 22 .

[0210] Other configurations of integrated circuit design 900B are within the scope of this disclosure.

[0211] Figure 9C is a diagram of a heat map 900C according to some embodiments.

[0212] Heat map 900A corresponds to power map 900A or the heat map of integrated circuit design 700 , and thus similar detailed description is omitted.

[0213] Heat map 900C corresponds to Figure 9A In some embodiments, the heat map 900C is generated by the system 1400 when executing the integrated circuit design 700 or the power map 900A, and thus similar detailed descriptions are described. Figure 8 Generated during operation 808.

[0214] Thermal map 900C includes thermal characteristics 930 of integrated circuit design 902 and thermal keywords 932 illustrating the thermal characteristics of each window in integrated circuit design 902. In some embodiments, thermal map 900C is a two-dimensional contour map of thermal characteristics 930 of integrated circuit design 902 according to thermal keywords 932.

[0215] Other configurations of the heat map 900C are within the scope of the present disclosure.

[0216] method

[0217] Figure 10 is a flow chart of a method 1000 of modifying an integrated circuit design according to some embodiments.

[0218] In some embodiments, method 1000 is an embodiment of operation 516 of method 500, and similar detailed description is omitted. In some embodiments, one or more of operations 1002, 1004, 1006, 1008, 1010, and 1012 are performed by Figure 14 Executed by system 110 or system 1400.

[0219] In some embodiments, method 1000 may be used to modify an integrated circuit design, such as integrated circuit design 700, Figure 9A Integrated Circuit Design 902, Figure 9B Integrated Circuit Design 900B, Figure 11A Integrated Circuit Design 1112, Figures 11B to 11C Integrated Circuit Design 1132, or Figure 11C Integrated Circuit Design 1162.

[0220] In operation 1002 of method 1000 , it is determined whether a maximum thermal value of a first portion of the integrated circuit design exceeds an upper limit of a user-defined thermal range HR.

[0221] In some embodiments, the upper limit of the caloric range HR of method 1000 includes a maximum caloric value Hmax.

[0222] In some embodiments, the maximum thermal values of the first portion of the integrated circuit design of method 1000 include the maximum thermal values generated by operation 808 that are in the thermal map generated by operation 810 .

[0223] In some embodiments, the integrated circuit design of method 1000 includes at least Figure 7 Integrated Circuit Design 700, Figure 9A Integrated Circuit Design 900A, Figure 11A Integrated Circuit Design 1112, Figures 11B to 11C Integrated Circuit Design 1132, or Figure 11CIntegrated Circuit Design 1162.

[0224] In some embodiments, the first portion of the integrated circuit design of method 1000 includes any portion of the integrated circuit design that satisfies the conditions of operation 1002. In some embodiments, the first portion of the integrated circuit design of method 1000 is also referred to as a "hot spot region."

[0225] In some embodiments, if the maximum thermal value of the first portion of the integrated circuit design exceeds the upper limit of the user-defined thermal range HR, thereby indicating that the thermal value HV of the thermal characteristic of the integrated circuit design exceeds the upper limit of the thermal range HR specified by the user, the result of operation 1002 is "yes" and method 1000 proceeds to operation 1004.

[0226] In some embodiments, if the maximum thermal value of the first portion of the integrated circuit design does not exceed the upper limit of the user-defined thermal range HR, and therefore the thermal value HV indicating the thermal characteristic of the integrated circuit design does not exceed the upper limit of the thermal range HR specified by the user, the result of operation 1002 is "no" and method 1000 proceeds to operation 1006.

[0227] In operation 1004 of method 1000 , power to a circuit block or heater in a first portion of the integrated circuit design is reduced.

[0228] In some embodiments, according to Figure 6 The power entry set 604 or the power entry set 606 included in the table 600 reduces the power of the circuit block or heater in the first portion of the integrated circuit design of operation 1004 .

[0229] In some embodiments, if more than one heater or circuit block is in the hot spot region, operation 1004 includes reducing at least the number of heaters or circuit blocks occupying or covering the hot spot region 1114b ( Figure 11A ) in a larger area of heater or circuit block. For example, Figure 11A In FIG. 1 , heater 706 b and circuit block 704 d are both in hot spot region 1114 b , and because circuit block 704 d occupies more area in hot spot region 1114 b than heater 706 b , power to circuit block 704 d is reduced through operation 1004 .

[0230] In some embodiments, if there are no heaters or circuit blocks in the hot spot region, operation 1004 includes reducing power to at least heaters or circuit blocks that are a minimum distance from the first hot spot region.

[0231] In operation 1006 of method 1000 , it is determined whether the minimum thermal value of the second portion of the integrated circuit design is less than a lower limit of the user thermal range.

[0232] In some embodiments, the lower limit of the thermal range HR of method 1000 includes a minimum thermal value Hmin.

[0233] In some embodiments, the minimum thermal values for the second portion of the integrated circuit design of method 1000 include minimum thermal values generated by operation 808 that are in the thermal map generated by operation 810 .

[0234] In some embodiments, the second portion of the integrated circuit design of method 1000 includes any portion of the integrated circuit design that satisfies the conditions of operation 1006. In some embodiments, the second portion of the integrated circuit design of method 1000 is also referred to as a "cold spot region."

[0235] In some embodiments, if the minimum thermal value of the second portion of the integrated circuit design is less than the lower limit of the user-defined thermal range HR, thereby indicating that the thermal value HV of the thermal characteristic of the integrated circuit design is less than the lower limit of the thermal range HR specified by the user, the result of operation 1006 is "yes" and method 1000 proceeds to operation 1008.

[0236] In some embodiments, if the minimum thermal value of the second portion of the integrated circuit design is not less than the lower limit of the user-defined thermal range HR, thereby indicating that the thermal value HV of the thermal characteristic of the integrated circuit design is not less than the lower limit of the thermal range HR specified by the user, the result of operation 1006 is "no" and method 1000 proceeds to operation 508.

[0237] In operation 1008 of method 1000 , it is determined whether power to a circuit block or heater in a second portion of the integrated circuit design is at maximum power.

[0238] In some embodiments, operation 1008 includes determining whether power to a circuit block or heater in a “cold spot region” of the integrated circuit design is at maximum power.

[0239] In some embodiments, if the power of the circuit block or heater in the second portion of the integrated circuit design is at maximum power, indicating that the power value of the circuit block or heater in the second portion of the integrated circuit design cannot be further increased, the result of operation 1008 is "yes" and method 1000 proceeds to operation 1010.

[0240] In some embodiments, if the power of the circuit block or heater in the second portion of the integrated circuit design is not at maximum power, thereby indicating that the power value of the circuit block or heater in the second portion of the integrated circuit design can be further increased, the result of operation 1008 is "no" and method 1000 proceeds to operation 1012.

[0241] In operation 1010 of method 1000, at least a heater is inserted into the second portion of the integrated circuit design. In some embodiments, the heater inserted in method 1000 includes Figure 11C Heater 1160.

[0242] In some embodiments, operation 1010 includes inserting at least a heater in a first cold spot region of the integrated circuit design.

[0243] In operation 1012 of method 1000, power is increased to a circuit block or heater in a second portion of the integrated circuit design. In some embodiments, the heater having increased power due to operation 1012 includes Figure 11B Heater 706a in.

[0244] Method 1000 operates to implement the above description of at least Figure 1 System 100, Figure 2 Wafer 200, Figure 3 Carrier wafer, Figure 4 or Figure 5 to Figure 1 1. The benefits discussed in method 400 of FIG. 1.

[0245] Figure 11A is a diagram 1100A of a power diagram and integrated circuit design according to some embodiments.

[0246] Diagram 1100A includes heat map 1102 , heat map 1106 , and integrated circuit design 1112 .

[0247] In some embodiments, integrated circuit design 1112 corresponds to integrated circuit design 700 and heat map 1102 corresponds to Figure 9C 900C, so similar detailed description is omitted.

[0248] Heat map 1102 corresponds to the heat map of integrated circuit design 1112, so similar detailed description is omitted. In some embodiments, heat maps 1102 and 1106 are generated by system 1400 when executing Figure 8 Generated during operation 804.

[0249] Heat map 1106 corresponds to executing Figure 10 The heat map of the integrated circuit design 1112 after operation 1004 is shown, and thus similar detailed description is omitted.

[0250] Heat map 1102 includes hot spot region 1104a and hot spot region 1104b. Hot spot region 1104a corresponds to region 1114a of integrated circuit design 1112, and hot spot region 1104b corresponds to region 1114b of integrated circuit design 1112.

[0251] Region 1114a of integrated circuit design 1112 covers circuit block 704c. Region 1114b of integrated circuit design 1112 covers circuit block 704d and a portion of heater 706b.

[0252] Heat map 1106 includes hot spot area 1108a and hot spot area 1108b. Hot spot area 1108a corresponds to hot spot area 1104a after operation 1004 is performed, while hot spot area 1108b corresponds to hot spot area 1104b after operation 1004 is performed.

[0253] For example, in some embodiments, during operation 1004 , circuit block 704 c is in region 1114 a corresponding to hot spot region 1104 a , and power to circuit block 704 c is reduced as a result of operation 1004 , thereby generating hot spot region 1108 a of thermal map 1106 .

[0254] For example, in some embodiments, during execution of operation 1004, both heater 706 b and circuit block 704 d are in region 1114 b corresponding to hot spot region 1104 b, and because circuit block 704 d occupies more area in region 1114 b than heater 706 b, the power of circuit block 704 d is reduced as a result of operation 1004, thereby generating hot spot region 1108 b of thermal map 1106.

[0255] Other configurations of FIG. 1100A are within the scope of the present disclosure.

[0256] Figure 11B is a diagram 1100B of a power diagram and integrated circuit design according to some embodiments.

[0257] Diagram 1100B includes thermal map 1122 , thermal map 1126 , and integrated circuit design 1132 .

[0258] In some embodiments, integrated circuit design 1132 corresponds to integrated circuit design 700 and heat map 1122 corresponds to Figure 9C 900C, so similar detailed description is omitted.

[0259] Heat map 1122 corresponds to the heat map of integrated circuit design 1132, so similar detailed description is omitted. In some embodiments, heat maps 1122 and 1126 are generated by system 1400 when executing Figure 8 Generated during operation 804.

[0260] Heat map 1126 corresponds to executing Figure 10 The heat map of the integrated circuit design 1132 after operation 1012 is shown, and thus similar detailed description is omitted.

[0261] Thermal map 1122 includes a cold spot region 1124 a , which corresponds to region 1134 a of integrated circuit design 1132 .

[0262] Region 1134a of integrated circuit design 1132 corresponds to circuit block 704c.

[0263] Heat map 1126 includes a cold spot region 1128a. Cold spot region 1128a corresponds to cold spot region 1124a after operation 1012 is performed. For example, in some embodiments, during operation 1012, heater 706a is in region 1134a corresponding to cold spot region 1124a, and the power of heater 704c is increased due to operation 1012, thereby generating cold spot region 1128a of heat map 1126.

[0264] Other configurations of FIG. 1100B are within the scope of the present disclosure.

[0265] Figure 11C is a diagram 1100C of a power diagram and integrated circuit design according to some embodiments.

[0266] Diagram 1100C includes thermal map 1122 , thermal map 1146 , integrated circuit design 1132 , and integrated circuit design 1162 .

[0267] In some embodiments, integrated circuit design 1132 corresponds to integrated circuit design 700 and heat map 1122 corresponds to Figure 9C 900C, so similar detailed description is omitted.

[0268] Heat map 1122 corresponds to the heat map of integrated circuit design 1132, so similar detailed description is omitted. In some embodiments, heat maps 1122 and 1146 are generated by system 1400 when executing Figure 8 Generated during operation 804.

[0269] Heat map 1146 corresponds to a heat map of integrated circuit design 1162 and is executed Figure 10 After operation 1010 , an integrated circuit design 1162 and a corresponding heat map 1146 are generated, and thus similar detailed descriptions are omitted.

[0270] Thermal map 1122 includes a cold spot region 1144 a . Cold spot region 1144 a corresponds to region 1154 a of integrated circuit design 1132 .

[0271] Region 1154 a of integrated circuit design 1132 does not include circuit blocks or heaters in integrated circuit design 1132 .

[0272] Thermal map 1146 includes a cold spot region 1148a. Cold spot region 1148a corresponds to cold spot region 1144a after performing operation 1010. For example, in some embodiments, during the performance of operation 1010, there was no heater in region 1154a of integrated circuit design 1132, so system 1400 inserts a new heater 1160 into region 1164a of integrated circuit design 1132, and region 1164a corresponds to cold spot region 1148a of thermal map 1146.

[0273] Other configurations of FIG. 1100C are within the scope of the present disclosure.

[0274] method

[0275] Figure 12 is a flow chart of a method 1200 of concurrently performing a burn-in test on an integrated circuit and an automated test on the integrated circuit, according to some embodiments.

[0276] In some embodiments, method 1200 is an embodiment of operation 408 of method 400, and similar detailed description is omitted. In some embodiments, one or more of operations 1202, 1204, and 1206 are performed by Figure 14 The method 1200 is performed by the system 100 or the system 1400. In some embodiments, the method 1200 can be used to simultaneously perform a burn-in test on an integrated circuit and an automated test on the integrated circuit.

[0277] In operation 1202 of method 1200 , a set of circuit blocks and a first set of heaters are configured as a first set of heat sources for burn-in testing of an integrated circuit, thereby generating a first thermal signature of the integrated circuit.

[0278] In some embodiments, operation 1202 includes turning on the set of circuit blocks and the first set of heaters according to a simulated design power level corresponding to the integrated circuit design, thereby generating a first thermal signature.

[0279] In some embodiments, the integrated circuit of method 1200 includes at least wafer 102 , wafer 200 , multiple integrated circuits 201 , or integrated circuit 203 .

[0280] In some embodiments, the integrated circuit design of method 1200 includes at least Figure 7 Integrated Circuit Design 700, Figure 9A Integrated Circuit Design 902, Figure 11A Integrated Circuit Design 1112, Figures 11B to 11C Integrated Circuit Design 1132, or Figure 11C Integrated Circuit Design 1162.

[0281] In some embodiments, the set of circuit blocks of the integrated circuit of method 1200 includes at least Figure 2 A circuit block set 204.

[0282] In some embodiments, the first heater set of the integrated circuit of method 1200 includes at least Figure 2 The heater assembly 206.

[0283] In some embodiments, the simulated design power level of method 1200 includes at least one or more power values 604 or 606 included in table 600 .

[0284] In operation 1204 of method 1200, an integrated circuit is placed on a carrier wafer. In some embodiments, the carrier wafer of method 1200 includes Figure 1 The carrier wafer 106 and Figure 3 The carrier wafer 300.

[0285] In operation 1206 of method 1200 , at least a portion of the carrier wafer is configured as a second set of heat sources for burn-in testing of the integrated circuit, thereby generating a second thermal signature of the integrated circuit.

[0286] In some embodiments, at least a portion of the carrier wafer of method 1200 includes Figure 3 at least a region 302 of the integrated circuit die 301 , one or more of the plurality of integrated circuit dies 301 , an integrated circuit die 303 , or at least one die in a circuit die set 304 .

[0287] In some embodiments, operation 1206 includes turning on a second set of heaters to generate a second thermal signature corresponding to a second set of heat sources used for burn-in testing of the integrated circuit.

[0288] In some embodiments, at least the second set of heaters of method 1200 includes Figure 1 The heater chip 108, at least one heater in the heater set 306, Figure 13 Heater 1300 or Figure 13 Interconnect 1302a or Figure 13 at least a portion of interconnect 1302b.

[0289] In some embodiments, the first thermal signature of the integrated circuit of method 1200 corresponds to an aged thermal profile of the integrated circuit, and heaters in the second set of heaters are turned off.

[0290] In some embodiments, the first thermal signature of the integrated circuit and the second thermal signature of method 1200 correspond to an aged thermal profile for the integrated circuit, and at least one heater in the second set of heaters is turned on.

[0291] Method 1200 operates to implement the above description of at least Figure 1 System 100, Figure 2 Wafer 200, Figure 3 Carrier wafer, Figure 4 or Figure 5 to Figure 1 1. The benefits discussed in method 400 of FIG. 1.

[0292] heater

[0293] Figure 13 is a cross-sectional view of a heater 1300 according to some embodiments. In some embodiments, the heater 1300 is Figure 1 An embodiment of the heater chip 108 or Figure 3 The heaters of the heater set 306 in FIG. 3 and similar detailed descriptions are omitted.

[0294] Heater 1300 can be used as Figure 1 The heater in the heater chip 108 or Figure 3 A heater in heater set 306 in .

[0295] Heater 1300 includes interconnects 1302a and 1302b in one or more layers of die 1304. In some embodiments, die 1304 corresponds to Figure 3 One or more dies in the die set 304 are described, and similar detailed descriptions are omitted.

[0296] Interconnects 1302 a and 1302 b each include one or more conductive features, such as conductive lines (not labeled), vias (not labeled), or conductive pads (not labeled), formed in insulating material 1310. In some embodiments, the one or more conductive features (e.g., conductive lines (not labeled), vias (not labeled), or conductive pads (not labeled)) formed in insulating material 1310 of interconnect structures 1302 a and 1302 b are referred to as one or more redistribution layers (RDLs) of die 1304. Figure 13 The routing of the conductive features shown in FIG is merely an example. Other configurations, arrangements, and materials of the conductive features of the interconnect structures 1302 a and 1302 b are within the contemplation of the present disclosure. Other configurations, arrangements, and materials of the conductive features of the interconnect structures 1302 a and 1302 b are within the contemplation of the present disclosure.

[0297] In some embodiments, interconnects 1302a and 1302b are configured to generate heat and serve as two different levels of heat sources when current passes through the respective interconnects 1302a and 1302b. In some embodiments, the amount of heat generated by interconnects 1302a and 1302b can be adjusted by varying the amount of current flowing through the respective interconnects 1302a and 1302b. In some embodiments, the amount of heat generated by interconnects 1302a and 1302b can be adjusted by selecting different levels of interconnects 1302a and 1302b.

[0298] In some embodiments, at least interconnect structure 1302a or 1302b is made of a conductive material, such as copper, a copper alloy, aluminum, an alloy, or a combination thereof. In some embodiments, other suitable materials are used. In some embodiments, at least interconnect structure 1302a or 1302b includes other conductive materials, such as tungsten (W), Cu, Al, or AlCu. In some embodiments, insulating material 1310 is made of silicon oxide. In some embodiments, insulating material 1310 includes multiple dielectric layers of dielectric material. One or more of the multiple dielectric layers is made of a low dielectric constant (low-k) material.

[0299] Figure 13 Two interconnects or two levels are shown, but other numbers of levels of interconnects 1302a and 1302b and corresponding current values through interconnects 1302a and 1302b are within the scope of the present disclosure.

[0300] Heater 1300 also includes an underbump metallurgy (UBM) layer 1312 on the surfaces of interconnect structures 1302a and 1302b. In some embodiments, the UBM layer includes one or more conductive portions 1312a, 1312b, ..., 1312f, where f is an integer corresponding to the number of conductive portions in UBM layer 1312. In some embodiments, UBM layer 1312 is formed on the surfaces of interconnect structures 1302a and 1302b. In some embodiments, UBM layer 1312 is formed on a metal liner (not shown). In some embodiments, UBM layer 1312 includes an adhesion layer and / or a wetting layer. In some embodiments, UBM layer 1312 includes at least a copper seed layer. In some embodiments, UBM layer 1312 includes titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), or tantalum (Ta). Other configurations, arrangements, and materials for UBM layer 1312 are within the contemplated scope of the present disclosure.

[0301] Integrated circuit 100 also includes a set of solder bumps 1314 on UBM layer 1312 .

[0302] Solder bump set 1314 includes one or more solder bumps 1314a, 1314b, ..., 1314f, where f is an integer corresponding to the number of solder bumps in solder bump set 1314. In some embodiments, solder bump set 1314 is formed on UBM layer 1312. In some embodiments, one or more solder bumps 1314a, 1314b, ..., 1314f in solder bump set 1314 include a conductive material having a low resistivity, such as solder or a solder alloy. In some embodiments, the solder alloy includes Sn, Pb, Ag, Cu, Ni, Bi, or a combination thereof. Other configurations, arrangements, and materials for solder bump set 1314 are within the contemplated scope of the present disclosure.

[0303] In some embodiments, solder bump sets 1314 are electrically connected to one or more other package structures (not shown) through bump sets 1314 .

[0304] Other configurations, arrangements, and materials for heater 1300 are within the contemplated scope of the present disclosure.

[0305] system

[0306] Figure 14 is a schematic diagram of a system 1400 for designing an IC layout design, simulating an IC design, and manufacturing an IC circuit according to some embodiments. In some embodiments, the system 1400 generates or places one or more IC layout designs described herein, tests one or more IC designs based on the IC layout designs, and manufactures ICs based on the layout designs. In some embodiments, the system 1400 is Figure 1 Therefore, similar detailed description is omitted.

[0307] System 1400 includes a hardware processor 1402 and a non-transitory computer-readable storage medium 1404 (e.g., memory 1404) encoded with (i.e., storing) computer program code 1406 (i.e., a set of executable instructions 1406). In some embodiments, computer-readable storage medium 1404 is configured to interface with a fabrication machine used to produce integrated circuits. In some embodiments, computer-readable storage medium 1404 is configured to interface with wafer 102, test circuit board 104, carrier wafer 106, and heater chip 108 for testing integrated circuits. In some embodiments, computer-readable storage medium 1404 is configured to generate and simulate integrated circuit designs.

[0308] The processor 1402 is electrically coupled to the computer-readable storage medium 1404 via a bus 1408. The processor 1402 is also electrically coupled to an I / O interface 1410 via the bus 1408. A network interface 1412 is also electrically connected to the processor 1402 via the bus 1408. The network interface 1412 is connected to a network 1414, enabling the processor 1402 and the computer-readable storage medium 1404 to connect to external components via the network 1414. The processor 1402 is configured to execute computer program code 1406 encoded in the computer-readable storage medium 1404 to enable the system 1400 to perform at least some or all of the operations described in the methods 400, 500, 800, 1000, or 1200.

[0309] In some embodiments, processor 1402 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0310] In some embodiments, computer-readable storage medium 1404 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, computer-readable storage medium 1404 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In some embodiments using optical disks, computer-readable storage medium 1404 includes compact disk read-only memory (CD-ROM), compact disk read / write (CD-R / W), and / or digital video disk (DVD).

[0311] In some embodiments, storage medium 1404 stores computer program code 1406 configured to cause system 1400 to perform at least method 400, 500, 800, 1000, or 1200. In some embodiments, storage medium 1404 also stores information required to perform at least method 400, 500, 800, 1000, or 1200 and information generated during performance of at least method 400, 500, 800, 1000, or 1200, such as IC design 1416, user interface 1418, IC design simulation 1422, simulation parameters 1424, test parameters 1426, lookup table 1428, and mapping 1430, and / or a set of executable instructions for performing at least the operations of method 400, 500, 800, 1000, or 1200. In some embodiments, IC design 1416 includes one or more layout patterns of layout designs 100 , 200 , 500 , 700 , 900A- 900C, 1000A- 1000E, or 1200B.

[0312] In some embodiments, IC design 1416 includes at least Figure 7Integrated Circuit Design 700, Figure 9A Integrated Circuit Design 902, Figure 11A Integrated Circuit Design 1112, Figures 11B to 11C Integrated Circuit Design 1132, or Figure 11C Integrated Circuit Design 1162.

[0313] In some embodiments, IC design simulation 1422 includes computer code configured to perform at least one or more portions of methods 400 , 500 , 800 , 1000 , or 1200 .

[0314] In some embodiments, simulation parameters 1424 include at least Figures 1 to 13 The number of repetitions of method 500 defined by one or more users, one or more thermal parameters, or one or more power parameters in one or more of the figures. In some embodiments, the one or more thermal parameters include at least Figures 1 to 13 In some embodiments, the one or more power parameters include at least power information from table 600, Figures 1 to 13 The power information or one or more power values of each window of the window array in one or more drawings.

[0315] In some embodiments, test parameters 1426 include at least Figures 1 to 13 The aging test parameters and ATE test parameters in one or more of the accompanying drawings.

[0316] In some embodiments, the lookup table 1428 includes at least Figures 1 to 13 In some embodiments, the lookup table 1428 includes design files for the method 500 .

[0317] In some embodiments, graph 1430 includes Figures 1 to 13 At least one or more heat maps, one or more power maps, one or more hot spots, one or more cold spots, or one or more window arrays in one or more of the drawings.

[0318] In some embodiments, storage medium 1404 stores instructions (e.g., computer program code 1406) for interfacing with a manufacturing machine. The instructions (e.g., computer program code 1406) enable processor 1402 to generate manufacturing instructions readable by the manufacturing machine to effectively implement at least method 400, 500, 800, 1000, or 1200 in a manufacturing process.

[0319] System 1400 includes an I / O interface 1410. I / O interface 1410 is coupled to external circuitry. In some embodiments, I / O interface 1410 includes a keyboard, keypad, mouse, trackball, trackpad, and / or cursor direction keys for transmitting information and commands to processor 1402.

[0320] System 1400 also includes a network interface 1412 coupled to processor 1402. Network interface 1412 allows system 1400 to communicate with a network 1414 to which one or more other computer systems are connected. Network interface 1412 includes a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA, or a wired network interface, such as Ethernet, USB, or IEEE-1494. In some embodiments, at least methods 400, 500, 800, 1000, or 1200 are implemented in two or more systems 1400, and information such as IC designs, user interfaces, IC design simulations, simulation parameters, test parameters, lookup tables, and graphs are exchanged between the different systems 1400 via network 1414.

[0321] System 1400 is configured to receive information related to an IC or layout design via I / O interface 1410 or network interface 1412. This information is transmitted to processor 1402 via bus 1408 to determine an IC design for producing at least wafer 102, wafer 200, multiple integrated circuits 201, or integrated circuit 203. The IC design is then stored in computer-readable medium 1404 as IC design 1416. System 1400 is also configured to receive information related to a user interface via I / O interface 1410 or network interface 1412. This information is stored in computer-readable medium 1404 as user interface 1418. System 1400 is also configured to receive information related to IC design simulation via I / O interface 1410 or network interface 1412. This information is stored in computer-readable medium 1404 as IC design simulation 1422. System 1400 is also configured to receive information related to simulation parameters via I / O interface 1410 or network interface 1412. This information is stored in computer-readable medium 1404 as simulation parameters 1424. System 1400 is configured to receive information related to test parameters via I / O interface 1410 or network interface 1412. This information is stored in computer-readable medium 1404 as test parameters 1426. System 1400 is configured to receive information related to lookup tables via I / O interface 1410 or network interface 1412. This information is stored in computer-readable medium 1404 as lookup tables 1428. System 1400 is configured to receive information related to graphs via I / O interface 1410 or network interface 1412. This information is stored in computer-readable medium 1404 as graphs 1430.

[0322] In some embodiments, at least some portions of one or more of methods 400, 500, 800, 1000, or 1200 are implemented as standalone software applications for execution by a processor. In some embodiments, at least some portions of one or more of methods 400, 500, 800, 1000, or 1200 are implemented as software applications that are part of an add-on software application. In some embodiments, at least some portions of one or more of methods 400, 500, 800, 1000, or 1200 are implemented as plug-ins to a software application. In some embodiments, at least some portions of one or more of methods 400, 500, 800, 1000, or 1200 are implemented as software applications that are part of an EDA tool. In some embodiments, at least some portions of one or more of methods 400, 500, 800, 1000, or 1200 are implemented as software applications used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout design for an integrated circuit device, generate and simulate an integrated circuit design for an IC device, or perform tests on the IC device. In some embodiments, the layout design, IC design, and simulation and test parameters are stored on a non-transitory computer readable medium. In some embodiments, the layout is generated using a computer program such as that available from CADENCEDESIGN SYSTEMS, Inc. , or another suitable layout generation tool. In some embodiments, the layout is generated based on a netlist created based on a schematic design. In some embodiments, at least some portions of one or more of methods 400, 500, 800, 1000, or 1200 are implemented by a fabrication facility to fabricate an integrated circuit using a mask set fabricated based on one or more layout designs generated by system 1400. In some embodiments, system 1400 is a fabrication facility that fabricates an integrated circuit using a mask set fabricated based on one or more layout designs disclosed herein.

[0323] In some embodiments, Figure 14 The system 1400 operates to implement at least the above Figure 1 System 100, Figure 2 Wafer 200, Figure 3 Carrier wafer 300, Figure 4 or Figures 5 to 13 The benefits of method 400 are discussed above.

[0324] Figure 151 is a block diagram of an integrated circuit (IC) fabrication system 1500 and an associated IC fabrication flow according to at least one embodiment of the present disclosure. In some embodiments, based on a layout diagram, fabrication system 1500 is used to fabricate at least one of the following: (A) one or more semiconductor masks, or (B) at least one component in a layer of a semiconductor integrated circuit.

[0325] exist Figure 15 In the present invention, IC manufacturing system 1500 (hereinafter referred to as "system 1500") includes entities that interact with each other during the design, development, and manufacturing cycles and / or services related to manufacturing IC devices 1560, such as design room 1520, mask room 1530, and IC manufacturer / fabricator ("fab") 1540. The entities in system 1500 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or more other entities. In some embodiments, one or more of design room 1520, mask room 1530, and IC fab 1540 are owned by a single larger company. In some embodiments, one or more of design room 1520, mask room 1530, and IC fab 1540 coexist in a common facility and use common resources.

[0326] The design office (or design team) 1520 generates an IC design layout 1522. The IC design layout 1522 includes various geometric patterns designed for the IC device 1560. The geometric patterns correspond to the patterns of the metal, oxide, or semiconductor layers that constitute the various components of the integrated circuit device 1560 to be manufactured. The various layers combine to form various IC features. For example, a portion of the IC design layout 1522 includes various IC features, such as active areas, gate electrodes, source electrodes and drain electrodes, metal lines or vias for interconnecting layers, and openings for bonding pads to be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. The design office 1520 implements an appropriate design program to form the IC design layout 1522. The design program includes one or more logical designs, physical designs, or location and routing. The IC design layout 1522 is presented in one or more data files having information about the geometric patterns. For example, the IC design layout 1522 can be represented in a GDSII file format or a DFII file format. In some embodiments, the IC design layout 1522 includes at least Figure 7 Integrated Circuit Design 700, Figure 9A Integrated Circuit Design 902, Figure 11A Integrated Circuit Design 1112, Figures 11B to 11C Integrated Circuit Design 1132, or Figure 11C Integrated Circuit Design 1162.

[0327] The mask chamber 1530 includes data preparation 1532 and mask fabrication 1534. The mask chamber 1530 uses the IC design layout 1522 to fabricate one or more masks 1545 for use in fabricating various layers of an IC device 1560 based on the IC design layout 1522. The mask chamber 1530 performs mask data preparation 1532, wherein the IC design layout 1522 is converted into a representative data file ("RDF"). The mask data preparation 1532 provides the RDF to the mask fabrication 1534. The mask fabrication 1534 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1545 or a semiconductor wafer 1542. The design layout 1522 is manipulated by the mask data preparation 1532 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 1540. In Figure 15 , mask data preparation 1532 and mask fabrication 1534 are shown as separate elements. In some embodiments, mask data preparation 1532 and mask fabrication 1534 may be collectively referred to as mask data preparation.

[0328] In some embodiments, mask data preparation 1532 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts IC design layout 1522. In some embodiments, mask data preparation 1532 also includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, etc., or a combination thereof. In some embodiments, inverse lithography techniques (ILT), which treat OPC as an inverse imaging problem, are also used.

[0329] In some embodiments, mask data preparation 1532 includes a mask rule checker (MRC) that checks an IC design layout that has been processed in OPC using a set of mask creation standard rules that include certain geometric and / or connectivity constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for the constraints during mask fabrication 1534, which may undo some of the modifications performed by OPC to satisfy the mask creation standard rules.

[0330] In some embodiments, mask data preparation 1532 includes a lithography process check (LPC) that simulates a process to be implemented by IC fab 1540 to manufacture IC device 1560. LPC simulates this process based on IC design layout 1522 to create a simulated manufactured device, such as IC device 1560. Process parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc., or a combination of the foregoing. In some embodiments, after the simulated manufactured device is created by LPC, if the shape of the simulated device is insufficient to meet the design rules, OPC and / or MRC are repeated to further improve the IC design layout 1522.

[0331] It should be understood that the above description of mask data preparation 1532 has been simplified for the sake of clarity. In some embodiments, mask data preparation 1532 includes additional features such as logic operations (LOPs) to modify the IC design layout according to manufacturing rules. Furthermore, the processes applied to IC design layout 1522 during mask data preparation 1532 can be performed in a variety of different orders.

[0332] After mask data preparation 1532 and during mask fabrication 1534, a mask 1545 or a set of masks 1545 are fabricated based on the modified IC design layout 1522. In some embodiments, mask fabrication 1534 includes performing one or more photolithographic exposures based on the IC design 1522. In some embodiments, an electron beam (e-beam) or multiple electron beams are used to form a pattern on a mask (photomask or reticle) 1545 based on the modified IC design layout 1522. Mask 1545 can be formed using various techniques. In some embodiments, mask 1545 is formed using binary techniques. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque regions and passes through the transparent regions. In one example, a binary version of mask 1545 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask 1545 is formed using phase shift technology. In a phase shift mask (PSM) version of mask 1545, various features in the pattern formed on the mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask(s) generated by mask manufacturing 1534 are used in various processes. For example, such mask(s) are used in an ion implantation process to form various doped regions in a semiconductor wafer, such mask(s) are used in an etching process to form various etched regions in a semiconductor wafer, and / or such mask(s) are used in other suitable processes.

[0333] IC fab 1540 is an IC manufacturing entity that includes one or more fabrication facilities for manufacturing a variety of different IC products. In some embodiments, IC fab 1540 is a semiconductor foundry. For example, one fabrication facility may provide front-end fabrication (front-end of line (FEOL) fabrication) for multiple IC products, while a second fabrication facility may provide back-end fabrication (back-end of line (BEOL) fabrication) for interconnect and packaging of the IC products. A third fabrication facility may provide other services for the foundry entity.

[0334] IC fab 1540 includes a wafer fabrication tool 1552 (hereinafter referred to as "fabrication tool 1552") configured to perform various fabrication operations on semiconductor wafer 1542 to fabricate IC device 1560 based on mask(s) (e.g., mask 1545). In various embodiments, fabrication tool 1552 includes one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or an LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes as discussed herein.

[0335] IC fab 1540 uses mask(s) 1545 manufactured by mask chamber 1530 to manufacture IC device 1560. Thus, IC fab 1540 at least indirectly uses IC design layout 1522 to manufacture IC device 1560. In some embodiments, semiconductor wafer 1542 is manufactured by IC fab 1540 using mask(s) 1545 to form IC device 1560. In some embodiments, IC fabrication includes performing one or more photolithographic exposures based at least indirectly on IC design 1522. Semiconductor wafer 1542 includes a silicon substrate or other suitable substrate having material layers formed thereon. Semiconductor wafer 1542 also includes one or more of various doped regions, dielectric features, multi-level interconnects, etc. (formed in subsequent fabrication steps).

[0336] In some embodiments, IC device 1560 includes at least wafer 102 , wafer 200 , multiple integrated circuits 201 , or integrated circuit 203 .

[0337] System 1500 is shown with design room 1520, mask room 1530, or IC fab 1540 as separate components or entities. However, it should be understood that one or more of design room 1520, mask room 1530, or IC fab 1540 are part of the same component or entity.

[0338] With respect to integrated circuit (IC) manufacturing systems (e.g., Figure 15 Details of the system 1500 and the IC manufacturing process associated therewith are found in, for example, U.S. Patent No. 9,256,709, issued on February 9, 2016; U.S. Pre-grant Publication No. 20150278429, published on October 1, 2015; U.S. Pre-grant Publication No. 20140040838, published on February 6, 2014; and U.S. Patent No. 7,260,442, issued on August 21, 2007, the entire contents of which are incorporated herein by reference.

[0339] It will be readily apparent to those skilled in the art that one or more of the disclosed embodiments achieve one or more of the advantages described above. After reading the foregoing description, those skilled in the art will be able to implement various variations, substitutions of equivalents, and various other embodiments as broadly disclosed herein. Accordingly, the protection granted herein is limited solely by the definitions contained in the appended claims and their equivalents.

[0340] One aspect of the present specification relates to a method for testing an integrated circuit on a test circuit board. In some embodiments, the method includes: performing, by a processor, a simulation of a first thermal distribution in an entire integrated circuit design; manufacturing the integrated circuit according to the integrated circuit design; and simultaneously performing a burn-in test on the integrated circuit and an automated test on the integrated circuit. In some embodiments, the integrated circuit design is configured to operate at a simulated design power level and generate a first thermal distribution. In some embodiments, the burn-in test has a minimum burn-in temperature of the integrated circuit and a burn-in thermal distribution over the entire integrated circuit. In some embodiments, the integrated circuit design corresponds to an integrated circuit. In some embodiments, the integrated circuit is configured to operate according to the simulated design power level, and the integrated circuit is coupled to the test circuit board. In some embodiments, the integrated circuit includes a set of circuit blocks and a first set of heaters.

[0341] Another aspect of the present specification relates to a method for testing an integrated circuit on a test circuit board. In some embodiments, the method includes: performing, by a processor, a simulation of a first thermal distribution in an entire integrated circuit design, and manufacturing an integrated circuit based on the integrated circuit design. In some embodiments, the integrated circuit design is configured to operate at a simulated design power level and generate a first thermal distribution. In some embodiments, the simulated design power level includes configuration power information. In some embodiments, the integrated circuit design includes a set of circuit blocks and a set of heaters. In some embodiments, performing the simulation includes: determining a thermal signature of the integrated circuit design based on the configuration power information and position information for each circuit block in the set of circuit blocks and each heater in the set of heaters included in the integrated circuit design. In some embodiments, the thermal signature including a thermal value is distributed throughout the integrated circuit design. In some embodiments, performing the simulation also includes: determining whether the thermal value of the thermal signature of the integrated circuit design is within a thermal range of the integrated circuit design, and modifying the integrated circuit design in response to determining that the thermal value of the integrated circuit design is not within the thermal range.

[0342] Another aspect of this specific embodiment relates to a test system. In some embodiments, the test system includes an integrated circuit, a test circuit board coupled to the integrated circuit, a carrier wafer coupled to at least the integrated circuit or the test circuit board, and a first system electrically coupled to the integrated circuit. In some embodiments, the first system includes a non-transitory computer-readable medium configured to store executable instructions, and a processor coupled to the non-transitory computer-readable medium. In some embodiments, the processor is configured to execute the executable instructions to perform a simulation of a first thermal distribution in the entire integrated circuit design. In some embodiments, the integrated circuit design is configured to operate at a simulated design power level and generate a first thermal distribution. In some embodiments, the integrated circuit design corresponds to an integrated circuit. In some embodiments, the integrated circuit is configured to operate according to the simulated design power level. In some embodiments, the test system is configured to simultaneously perform a burn-in test on the integrated circuit and an automated test on the integrated circuit. In some embodiments, the burn-in test has a minimum burn-in temperature of the integrated circuit and an burn-in thermal distribution over the entire integrated circuit.

[0343] The features of some embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. It should also be appreciated by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

[0344] Example

[0345] Example 1. A method for testing an integrated circuit on a test circuit board, the integrated circuit including a set of circuit blocks and a first set of heaters, the method comprising: performing, by a processor, a simulation of a first heat distribution in an entire integrated circuit design, the integrated circuit design being configured to operate at a simulated design power level and generate the first heat distribution, and the integrated circuit design corresponding to the integrated circuit; manufacturing the integrated circuit according to the integrated circuit design; and simultaneously performing an aging test on the integrated circuit and an automated test on the integrated circuit, the integrated circuit being configured to operate according to the simulated design power level, and the integrated circuit being coupled to the test circuit board, wherein the aging test has a minimum aging temperature of the integrated circuit and an aging heat distribution on the integrated circuit.

[0346] Example 2. A method according to Example 1, wherein simultaneously performing an aging test on the integrated circuit and an automated test on the integrated circuit includes: configuring the circuit block set and the first heater set as a first heat source set for the aging test on the integrated circuit, thereby generating a first thermal characteristic of the integrated circuit.

[0347] Example 3. A method according to Example 2, wherein the circuit block set and the first heater set are configured as the first heat source set for aging testing of the integrated circuit, thereby generating the first thermal characteristic of the integrated circuit, including: turning on the circuit block set and the first heater set according to a simulation design power level to generate the first thermal characteristic.

[0348] Example 4. The method of Example 2, wherein the first thermal characteristic of the integrated circuit corresponds to an aging thermal distribution on the integrated circuit.

[0349] Example 5. A method according to Example 2, wherein simultaneously performing an aging test on the integrated circuit and an automated test on the integrated circuit further includes: placing the integrated circuit on a carrier wafer; and configuring at least a portion of the carrier wafer as a second heat source set, the second heat source set being used for the aging test on the integrated circuit, thereby generating a second thermal signature of the integrated circuit, wherein the second heat source set corresponds to a second heater set located in a grid arrangement of an integrated circuit die, and the integrated circuit die is part of the carrier wafer.

[0350] Example 6. The method of Example 5, wherein the first thermal signature and the second thermal signature of the integrated circuit correspond to an aging thermal distribution on the integrated circuit.

[0351] Example 7. A method according to Example 5, wherein configuring at least a portion of the carrier wafer as the second heat source set for aging testing the integrated circuit includes: turning on the second heater set to generate the second heat characteristic corresponding to the second heat source set for aging testing the integrated circuit.

[0352] Example 8. The method of Example 1, wherein the first thermal distribution is uniform throughout the integrated circuit design.

[0353] Example 9. The method of Example 1, wherein the burn-in test on the integrated circuit and the automated test on the integrated circuit are performed simultaneously without using a burn-in board or an oven.

[0354] Example 10. The method of Example 1, wherein performing a simulation of the first thermal distribution throughout the integrated circuit design comprises modifying the integrated circuit design based on the first thermal distribution throughout the integrated circuit design.

[0355] Example 11. A method for testing an integrated circuit on a test circuit board, the method comprising: performing, by a processor, a simulation of a first thermal distribution in an entire integrated circuit design, the integrated circuit design comprising a set of circuit blocks and a set of heaters, the integrated circuit design being configured to operate at a simulated design power level and generate the first thermal distribution, the simulated design power level comprising configuration power information, and performing the simulation comprising: determining a thermal characteristic of the integrated circuit design based on the configuration power information and position information of each circuit block in the set of circuit blocks and each heater in the set of heaters included in the integrated circuit design, the thermal characteristic comprising a thermal value distributed throughout the integrated circuit design; determining whether the thermal value of the thermal characteristic of the integrated circuit design is within a thermal range of the integrated circuit design; and modifying the integrated circuit design in response to determining that the thermal value of the thermal characteristic of the integrated circuit design is not within the thermal range; and manufacturing an integrated circuit based on the integrated circuit design.

[0356] Example 12. The method of Example 11, further comprising: in response to determining that the thermal value of the thermal signature of the integrated circuit design is within the thermal range or determining that the number of iterations of the simulation exceeds a user-defined limit, not modifying the integrated circuit design.

[0357] Example 13. A method according to Example 11, wherein modifying the integrated circuit design includes: in response to determining that the thermal value of the thermal characteristic of the integrated circuit design is not within the thermal range of the integrated circuit design, modifying the configuration power of at least one element in the integrated circuit design, the element including at least the first circuit block of the circuit block set or the first heater of the heater set.

[0358] Example 14. The method of Example 13, wherein modifying the configured power of at least the element in the integrated circuit design comprises increasing the configured power of at least the first circuit block in the set of circuit blocks or the first heater in the set of heaters.

[0359] Example 15. The method of Example 13, wherein modifying the configured power of at least the element in the integrated circuit design comprises reducing the configured power of at least the first circuit block in the set of circuit blocks or the first heater in the set of heaters.

[0360] Example 16. The method of Example 11, wherein modifying the integrated circuit design comprises adding a new heater to the set of heaters in the integrated circuit design in response to determining that a thermal value of a thermal signature of the integrated circuit is not within the thermal range of the integrated circuit design.

[0361] Example 17. The method of Example 11, wherein modifying the integrated circuit design comprises removing a heater from the set of heaters in the integrated circuit design in response to determining that a thermal value of a thermal signature of the integrated circuit is not within the thermal range of the integrated circuit design.

[0362] Example 18. A method according to Example 11, wherein performing a simulation of the first thermal distribution in the entire integrated circuit design also includes: obtaining configuration power information for each circuit block in the circuit block set and each heater in the heater set in the integrated circuit design; and extracting position information for each circuit block in the circuit block set and each heater in the heater set in the integrated circuit design from a design file.

[0363] Example 19. A test system comprising: an integrated circuit; a test circuit board coupled to the integrated circuit; a carrier wafer coupled to at least the integrated circuit or the test circuit board; and a first system electrically coupled to the integrated circuit, the first system comprising: a non-transitory computer-readable medium configured to store executable instructions; and a processor coupled to the non-transitory computer-readable medium, wherein the processor is configured to execute the executable instructions to perform the following operations: perform a simulation of a first thermal distribution in an entire integrated circuit design, the integrated circuit design being configured to operate at a simulated design power and generate the first thermal distribution, and the integrated circuit design corresponding to the integrated circuit; wherein the test system is configured to simultaneously perform an aging test on the integrated circuit and an automated test on the integrated circuit, the integrated circuit being configured to operate according to the simulated design power level, wherein the aging test has a minimum aging temperature of the integrated circuit and an aging thermal distribution over the entire integrated circuit.

[0364] Example 20. A test system according to Example 19, wherein performing a simulation of the first thermal distribution in the entire integrated circuit design includes: obtaining configuration power information and position information for each circuit block in the circuit block set and each heater in the heater set used in the integrated circuit design; determining a thermal characteristic of the integrated circuit design based on the configuration power information and position information for each circuit block in the circuit block set and each heater in the heater set included in the integrated circuit design, the thermal characteristic including a thermal value distributed over the entire integrated circuit design; determining whether the thermal value of the thermal characteristic of the integrated circuit design is within the thermal range; and modifying the integrated circuit design in response to determining that the thermal value of the thermal characteristic of the integrated circuit design is not within the thermal range.

Claims

1. A method for testing an integrated circuit on a test circuit board, the integrated circuit comprising a circuit block set and a first heater set, the method comprising: performing, by a processor, a simulation of a first thermal distribution throughout an integrated circuit design, the integrated circuit design being configured to operate at a simulated design power level and generating the first thermal distribution, and the integrated circuit design corresponding to the integrated circuit; manufacturing the integrated circuit according to the integrated circuit design; as well as A burn-in test and an automated test of the integrated circuit are simultaneously performed, the integrated circuit being configured to operate according to the simulated design power level and coupled to the test circuit board, wherein the burn-in test has a minimum burn-in temperature of the integrated circuit and a burn-in heat distribution on the integrated circuit.

2. The method according to claim 1, wherein Simultaneously performing a burn-in test on the integrated circuit and an automated test on the integrated circuit includes: The set of circuit blocks and the first set of heaters are configured as a first set of heat sources for burn-in testing of the integrated circuit, thereby generating a first thermal signature of the integrated circuit.

3. The method according to claim 2, wherein: Configuring the set of circuit blocks and the first set of heaters as the first set of heat sources for burn-in testing of the integrated circuit to generate the first thermal signature of the integrated circuit includes: The set of circuit blocks and the first set of heaters are turned on according to a simulated design power level to generate the first thermal signature.

4. The method according to claim 2, wherein: The first thermal characteristic of the integrated circuit corresponds to an aging thermal distribution on the integrated circuit.

5. The method according to claim 2, wherein: Simultaneously performing an aging test on the integrated circuit and an automated test on the integrated circuit further includes: placing the integrated circuit on a carrier wafer; and configuring at least a portion of the carrier wafer as a second set of heat sources for burn-in testing of the integrated circuit to generate a second thermal signature of the integrated circuit, Wherein, the second set of heat sources corresponds to a second set of heaters located in a grid arrangement of integrated circuit dies, and the integrated circuit dies are part of the carrier wafer.

6. The method according to claim 5, wherein: The first thermal signature and the second thermal signature of the integrated circuit correspond to an aging thermal distribution on the integrated circuit.

7. The method according to claim 5, wherein: Configuring at least a portion of the carrier wafer as the second set of heat sources for burn-in testing of the integrated circuit includes: The second set of heaters is turned on to generate the second heat signature corresponding to the second set of heat sources used for burn-in testing of the integrated circuit.

8. The method according to claim 1, wherein The first heat distribution is uniform throughout the integrated circuit design.

9. The method according to claim 1, wherein Without using a burn-in board or an oven, a burn-in test on the integrated circuit and an automated test on the integrated circuit are performed simultaneously.

10. The method according to claim 1, wherein Performing a simulation of the first thermal distribution throughout the integrated circuit design includes: The integrated circuit design is modified based on the first thermal distribution throughout the integrated circuit design.

11. A method for testing an integrated circuit on a test circuit board, the method comprising: performing, by a processor, a simulation of a first thermal profile across an integrated circuit design, the integrated circuit design including a set of circuit blocks and a set of heaters, the integrated circuit design configured to operate at a simulated design power level and to generate the first thermal profile, the simulated design power level including configuration power information, and performing the simulation comprising: determining a thermal signature of the integrated circuit design based on configured power information and location information of each circuit block in a set of circuit blocks and each heater in a set of heaters included in the integrated circuit design, the thermal signature comprising a thermal value distributed throughout the integrated circuit design; determining whether a thermal value of a thermal signature of the integrated circuit design is within a thermal range for the integrated circuit design; and In response to determining that the thermal value of the thermal signature of the integrated circuit design is not within the thermal range, modifying the integrated circuit design; and An integrated circuit is manufactured according to the integrated circuit design.

12. The method according to claim 11, further comprising: In response to determining that the thermal value of the thermal signature of the integrated circuit design is within the thermal range or determining that the number of iterations of the simulation exceeds a user-defined limit, the integrated circuit design is not modified.

13. The method according to claim 11, wherein Modifying the integrated circuit design includes: In response to determining that the thermal value of the thermal characteristic of the integrated circuit design is not within the thermal range of the integrated circuit design, modifying the configuration power of at least one element in the integrated circuit design, the element including at least a first circuit block of the circuit block set or a first heater of the heater set.

14. The method according to claim 13, wherein Modifying the configuration power of at least the component in the integrated circuit design includes: The configured power of at least the first circuit block in the circuit block set or the first heater in the heater set is increased.

15. The method according to claim 13, wherein Modifying the configuration power of at least the component in the integrated circuit design includes: The configured power of at least the first circuit block in the circuit block set or the first heater in the heater set is reduced.

16. The method according to claim 11, wherein Modifying the integrated circuit design includes: In response to determining that the thermal value of the thermal signature of the integrated circuit is not within the thermal range of the integrated circuit design, a new heater is added to the set of heaters in the integrated circuit design.

17. The method according to claim 11, wherein Modifying the integrated circuit design includes: In response to determining that the thermal value of the thermal signature of the integrated circuit is not within the thermal range of the integrated circuit design, a heater is removed from the set of heaters in the integrated circuit design.

18. The method according to claim 11, wherein Performing a simulation of the first thermal distribution throughout the integrated circuit design further includes: obtaining configured power information for each circuit block in the set of circuit blocks and each heater in the set of heaters in the integrated circuit design; and Position information of each circuit block in the set of circuit blocks and each heater in the set of heaters in the integrated circuit design is extracted from a design file.

19. A testing system comprising: integrated circuit; a test circuit board coupled to the integrated circuit; a carrier wafer coupled to at least the integrated circuit or the test circuit board; as well as A first system electrically coupled to the integrated circuit, the first system comprising: a non-transitory computer-readable medium configured to store executable instructions; and a processor coupled to the non-transitory computer-readable medium, wherein the processor is configured to execute the executable instructions to: perform a simulation of a first thermal distribution throughout an integrated circuit design, the integrated circuit design being configured to operate at a simulated design power and to generate the first thermal distribution, and the integrated circuit design corresponding to the integrated circuit; The test system is configured to simultaneously perform an aging test on the integrated circuit and an automated test on the integrated circuit, wherein the integrated circuit is configured to operate according to the simulated design power level, wherein the aging test has a minimum aging temperature of the integrated circuit and an aging heat distribution across the integrated circuit.

20. The test system according to claim 19, wherein: Performing a simulation of the first thermal distribution throughout the integrated circuit design includes: Obtaining configuration power information and location information for each circuit block in the set of circuit blocks and each heater in the set of heaters in the integrated circuit design; determining a thermal signature of the integrated circuit design based on configured power information and position information for each circuit block in the set of circuit blocks and each heater in the set of heaters included in the integrated circuit design, the thermal signature comprising a thermal value distributed across the integrated circuit design; determining whether a thermal value of a thermal signature of the integrated circuit design is within a thermal range; and In response to determining that the thermal value of the thermal signature of the integrated circuit design is not within the thermal range, the integrated circuit design is modified.

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