Method for testing circuit system and related circuit system

Abstract

The circuit system includes a first circuit, a second circuit, and a comparator. The second circuit has a substantially identical structure to the first circuit. In a test mode, the circuit system causes the first and second circuits to synchronously perform substantially identical test operations. During the test operation, the comparator continuously compares a first intermediate signal generated within the first circuit with a second intermediate signal generated within the second circuit that corresponds to the first intermediate signal. When the first intermediate signal differs from the second intermediate signal, the circuit system causes the first and second circuits to stop performing the test operation and perform a scan dump operation on the first and second circuits to record the signals transmitted by the first and second circuits.

Description

Technical Field

[0001] The present invention relates to a method for testing a circuit system, and more particularly to a method for recording circuit signals when an error occurs in the circuit system and a related circuit system. Background Art

[0002] Generally speaking, to maintain chip quality, chips must be tested, both before shipment and upon customer return. If errors due to manufacturing defects are discovered, the cause of the error is analyzed to improve circuit design and / or chip manufacturing processes. Conventional technology often employs scan chains across all chip registers. When chip malfunctions are detected during testing, the scan chains are used to read the chip register values ​​for further analysis of the error's cause.

[0003] However, there is often a time lag between detecting a chip error and actually starting the scan chain to read the chip's register values. As a result, the scan chain often reads values ​​long after the chip error occurs, rather than the values ​​generated at the time of the error. This makes it difficult to effectively determine the cause of the error. In this situation, improving chip testing efficiency has become an urgent problem in the field. Summary of the Invention

[0004] One embodiment of the present invention relates to a circuit system. The circuit system includes a first circuit, a second circuit, and a comparator. The first circuit is used to perform at least one application operation. The second circuit has the same structure as the first circuit and is used to perform the at least one application operation. In a test mode, the first circuit and the second circuit synchronously perform the same test operation. During the process of the first circuit and the second circuit synchronously performing the test operation, the comparator is used to compare a first intermediate signal generated within the first circuit and a second intermediate signal generated within the second circuit corresponding to the first intermediate signal. When the comparator determines that the first intermediate signal is different from the second intermediate signal, the first circuit and the second circuit stop performing the test operation and perform a scan dump operation on the first circuit and the second circuit to obtain multiple first transmission signals currently generated by the first circuit and multiple second transmission signals currently generated by the second circuit.

[0005] Another embodiment of the present invention relates to a method for testing a circuit system, wherein the test circuit system includes a first circuit and a second circuit, the first circuit and the second circuit having identical structures. The method includes causing the first circuit and the second circuit to synchronously perform the same test operation, comparing a first intermediate signal generated within the first circuit with a second intermediate signal generated within the second circuit and corresponding to the first intermediate signal during the synchronous test operation, causing the first circuit and the second circuit to stop performing the test operation when the first intermediate signal differs from the second intermediate signal, and after the first circuit and the second circuit stop performing the test operation, causing the first circuit and the second circuit to perform a scan dump operation to obtain a plurality of first transmission signals currently generated by the first circuit and a plurality of second transmission signals currently generated by the second circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 FIG. 1 is a schematic diagram of a circuit system according to an embodiment of the present invention.

[0007] Figure 2 The present invention tests Figure 1 Flowchart of a method of a circuit system.

[0008] Figure 3 is a schematic diagram of a circuit system according to another embodiment of the present invention.

[0009] Figure 4 The present invention tests Figure 3 Flowchart of a method of a circuit system. DETAILED DESCRIPTION

[0010] Figure 1 is a schematic diagram of a circuit system 100 according to an embodiment of the present invention. The circuit system 100 may include a first circuit 110A, a second circuit 110B, and a comparator 120. The first circuit 110A may be used to perform at least one application operation of the circuit system 100, such as, but not limited to, reading or writing to a memory in the circuit system 100 and executing a program stored in the memory and performing corresponding operations and calculations. In addition, in this embodiment, the second circuit 110B has substantially the same structure as the first circuit 110A and can perform substantially the same at least one application operation. For example, the circuit system 100 may be a single chip including a plurality of circuits, and the first circuit 110A and the second circuit 110B may be substantially the same processor or computing unit, such as, but not limited to, a central processing unit, a graphics processing unit, and an Ethernet controller. In some embodiments, the second circuit 110B has exactly the same circuit layout as the first circuit 110A.

[0011] Figure 2 The present invention tests Figure 1 Flowchart of method 200 of circuit system 100. Method 200 includes steps S210-S240.

[0012] Step S210 : enabling the first circuit 110A and the second circuit 110B to synchronously perform substantially the same test operation;

[0013] Step S220: During the process of synchronously performing the test operation on the first circuit 110A and the second circuit 110B, the first intermediate signal SIG generated within the first circuit 110A is compared. M1 and the second intermediate signal SIG generated inside the second circuit 110B M2 ;

[0014] Step S230: On the first intermediate signal SIG M1 With the second intermediate signal SIG M2 At the same time, the first circuit 110A and the second circuit 110B stop performing the test operation; and

[0015] Step S240 : After the first circuit 110A and the second circuit 110B stop performing the test operation, the first circuit 110A and the second circuit 110B are enabled to perform a scan dump operation.

[0016] In step S210, the first circuit 110A and the second circuit 110B may synchronously execute the same test operation. In some embodiments, the tester may select one of the application operations that the first circuit 110A will execute in actual application as the test operation, or may provide additional instructions dedicated to the test as the test operation.

[0017] exist Figure 1In the embodiment, the circuit system 100 may further include a system bus 140, a main memory 150, and an input instruction multiplexer 160. The main memory 150 may store a plurality of instructions required for a test operation, and the system bus 140 may be coupled to the main memory 150 and the first circuit 110A. Therefore, the first circuit 110A may obtain data stored in the main memory 150 through the system bus 140 to perform corresponding operations. In addition, the first input instruction multiplexer 160 may have a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first input instruction multiplexer 160 may be coupled to the instruction input terminal of the first circuit 110A, the second input terminal of the first input instruction multiplexer 160 may be coupled to the system bus 140, and the output terminal of the first input instruction multiplexer 160 may be coupled to the instruction input terminal of the second circuit 110B. Under this setting, the first input instruction multiplexer 160 can enable the second circuit 110B to receive the same instruction signal as the first circuit 110A in the test mode, and can enable the second circuit 110B to receive multiple instruction signals required to perform application operations from the system bus 140 in the general application mode.

[0018] Since the first circuit 110A and the second circuit 110B execute the test operation synchronously according to the same instruction in step S210, the behaviors of the two circuits should be identical if neither of the first circuit 110A and the second circuit 110B has an error. In other words, the signals generated within the first circuit 110A and the second circuit 110B should be identical at the same time. However, if an error occurs in at least one of the first circuit 110A and the second circuit 110B, the signals generated therein may begin to differ.

[0019] In step S220, the comparator 120 may continuously compare the first intermediate signal SIG generated within the first circuit 110A with the first intermediate signal SIG. M1 and the second intermediate signal SIG generated inside the second circuit 110B M2 , to determine whether a possible error occurs. In this embodiment, the first intermediate signal SIG M1 With the second intermediate signal SIG M2 are signals corresponding to each other, that is, the first intermediate signal SIG M1 and the second intermediate signal SIG M2 It is a transmission signal generated by corresponding elements or units in the first circuit 110A and the second circuit 110B (as mentioned above, the two have substantially the same structure) at corresponding signal terminals. Figure 1 In the embodiment, the first circuit 110A may include first functional units 112A1-112AM, and the second circuit 110B may include second functional units 112B1-112BM. In this case, the first intermediate signal SIG M1It can be a data signal transmitted between the first functional units 112A1-112AM, and the second intermediate signal SIG M2 It may be a data signal transmitted between the second functional units 112B1 ˜ 112BM.

[0020] For example, the first functional unit 112A1 and the second functional unit 112B1 may be controllers, and the first functional unit 112A2 and the second functional unit 112B2 may be memories. In this case, the first intermediate signal SIG M1 It can be a data signal transmitted between the first controller 112A1 and the first memory 112A2, and the second intermediate signal SIG M2 It may be a data signal transmitted between the second controller 112B1 and the second memory 112B2, but is not limited thereto.

[0021] In addition, Figure 1 The circuit system 100 may further include a first multiplexer 130A and a second multiplexer 130B. The first multiplexer 130A may have multiple input terminals and output terminals. The multiple input terminals of the first multiplexer 130A may be respectively coupled to multiple specific signal terminals (not limited to those shown in the figure) of the first functional units 112A1-112AM, and the output terminal of the first multiplexer 130A may be coupled to the comparator 120. The first multiplexer 130A may transmit a transmission signal transmitted by a selected signal terminal among the multiple specific signal terminals of the first functional units 112A1-112AM to the comparator 120 as a first intermediate signal SIG. M1 Similarly, the second multiplexer 130B may have a plurality of input terminals and output terminals. The plurality of input terminals of the second multiplexer 130B may be respectively coupled to a plurality of specific signal terminals of the second functional units 112B1-112BM (the coupling method thereof may be substantially the same as the coupling method of the first multiplexer 130A and the first functional units 112A1-112AM), and the output terminal of the second multiplexer 130B may be coupled to the comparator 120. The second multiplexer 130B may transmit the transmission signal transmitted by the selected signal terminal among the plurality of specific signal terminals of the second functional units 112B1-112BM to the comparator 120 as the second intermediate signal SIG M2 .

[0022] That is, the circuit system 100 can select the signals transmitted from the corresponding signal terminals in the first circuit 110A and the second circuit 110B as the first intermediate signal SIG through the first multiplexer 130A and the second multiplexer 130B according to the requirements of the test operation. M1 and the second intermediate signal SIG M2, and then compared by the comparator 120. In this way, the test operation can be made more flexible, thereby helping to improve the efficiency of the test operation.

[0023] Generally speaking, when neither the first circuit 110A nor the second circuit 110B has an error, the first intermediate signal SIG M1 With the second intermediate signal SIG M2 On the contrary, if an error occurs in one of the first circuit 110A and the second circuit 110B, the first intermediate signal SIG M1 It may be combined with the second intermediate signal SIG M2 In step S230, when the first intermediate signal SIG M1 With the second intermediate signal SIG M2 If the first intermediate signal SIG is different from the first intermediate signal SIG, an error may occur. In this case, the first circuit 110A and the second circuit 110B may stop performing the test operation according to the comparison result of the comparator 120. In some embodiments, the comparator 120 may also be used to control a clock circuit (not shown) in the circuit system 100 and to determine the first intermediate signal SIG. M1 With the second intermediate signal SIG M2 At the same time, the clock signals required by the first circuit 110A and the second circuit 120B are interrupted to stop the operations of the first circuit 110A and the second circuit 120B.

[0024] Next, in step S240 , the first circuit 110A and the second circuit 110B perform a scan dump operation to obtain the transmission signal currently generated by the first circuit 110A and the transmission signal currently generated by the second circuit 110B.

[0025] In this embodiment, the transmission signals recorded by the scan dump operation may include the signals input and output by the first circuit 110A and the second circuit 110B, as well as the signals transmitted within the first circuit 110A and the second circuit 110B. In this case, the circuit system 100 can access the signals of the registers of the first circuit 110A and the registers of the second circuit 110B through the registers of the scan chain. For example, Figure 1 In the embodiment, the first circuit 110A may include a first scan chain register set 114A, and the second circuit 110B may include a second scan chain register set 114B.

[0026] The first scan chain register set 114A may include multiple serially connected registers, each of which may be coupled to the input and output terminals of the first circuit 110A and multiple signal terminals between the first functional units 112A1-112AM. Therefore, when the first circuit 110A transmits signals through its input and output terminals and the first signal terminals between the first functional units 112A1-112AM, the first scan chain register set 114A may synchronously record the current transmission signals generated by the first circuit 110A. In this way, the first scan chain register set 114A can continuously record the transmission signals generated by the first circuit 110A at these terminals. When the first circuit 110A performs a scan dump operation, the current transmission signals generated by the first circuit 110A can be read out, allowing researchers to further determine the cause of the error.

[0027] Similarly, the second scan chain register set 114B may also include a plurality of serially connected registers, each of which may be coupled to the input and output terminals of the second circuit 110B and to the plurality of signal terminals between the second functional units 112B1-112BM. In this way, the second scan chain register set 114B may continuously record the transmission signals generated by the second circuit 110B at these terminals and output the current transmission signals generated by the second circuit 110B when the second circuit 110B performs a scan dump operation.

[0028] However, the present invention is not limited to the first circuit 110A and the second circuit 110B recording and outputting the transmission signals transmitted by their input terminals, output terminals, and each functional unit via the scan chain register group. In some other embodiments, the first circuit 110A and the second circuit 110B may also use other types of interface signal storage circuits to store the signals transmitted internally or externally by the first circuit 110A and the second circuit 110B, depending on the requirements of the test operation. When performing a scan dump operation, the transmission signals generated when the error occurs can be read out through the interface signal storage circuits to enable researchers to further analyze the cause of the error.

[0029] Since the circuit system 100 can use the comparator 120 to instantly compare the first intermediate signal SIG generated by the first circuit 110A and the second circuit 110B M1 and the second intermediate signal SIG M2 , and judging the first intermediate signal SIG M1 and the second intermediate signal SIG M2 At the same time, the first circuit 110A and the second circuit 110B are immediately stopped from executing the test operation, and the first circuit 110A and the second circuit 110B are caused to execute a scan dump operation to read out the signals being transmitted. Therefore, more immediate data can be provided to researchers, allowing them to more efficiently find the cause of the error.

[0030] Figure 3 FIG is a schematic diagram of a circuit system 300 according to another embodiment of the present invention. The circuit system 300 may be a single chip including multiple circuits and has a similar structure to the circuit system 100 and may operate according to similar principles. Figure 3 In the embodiment, circuit system 300 may include a first circuit 310A, a second circuit 310B, and a third circuit 310C. The first circuit 310A, the second circuit 310B, and the third circuit 310C may have substantially the same structure and be capable of performing substantially the same operations. In some embodiments, the first circuit 310A, the second circuit 310B, and the third circuit 310C have identical circuit layouts. Circuit system 300 may perform testing operations using the first circuit 310A, the second circuit 310B, and the third circuit 310C, so that the first circuit 310A, the second circuit 310B, and the third circuit 310C serve as references for each other during testing operations. If the intermediate signals generated by the first circuit 310A, the second circuit 310B, and the third circuit 310C differ, it is possible to infer which of the first circuit 310A, the second circuit 310B, and the third circuit 310C is causing the error based on the different intermediate signals, thereby further improving the efficiency of the testing operation.

[0031] Figure 4 The present invention tests Figure 3 4. The method 400 of the circuit system 300 may include steps S410 to S470.

[0032] Step S410 : In the test mode, the third circuit 310C is caused to perform substantially the same test operation as the first circuit 310A and the second circuit 310B synchronously.

[0033] Step S420: When the first circuit 310A, the second circuit 310B and the third circuit 310C perform a test operation synchronously, compare the first intermediate signal SIG M1 , second intermediate signal SIG M2 and the third intermediate signal SIG generated within the third circuit 310C M3 ;

[0034] Step S430: On the first intermediate signal SIG M1 , second intermediate signal SIG M2 and the third intermediate signal SIG M3 When one of the two circuits is different from the other two, the first circuit 310A, the second circuit 310B and the third circuit 310C stop performing the test operation;

[0035] Step S440: causing the two circuits that output different intermediate signals to synchronously perform a test operation again, and causing the remaining circuit to perform the same test operation after a predetermined delay;

[0036] Step S450: comparing intermediate signals generated within two circuits that synchronously perform a test operation;

[0037] Step S460 : When the intermediate signals generated by the two circuits that synchronously perform the test operation are different, stop the first circuit 310A, the second circuit 310B, and the third circuit 310C from performing the test operation; and

[0038] Step S470 : After the first circuit 310A, the second circuit 310B, and the third circuit 310C stop performing the test operation, the circuits performing the test operation are delayed for a predetermined time before performing the scan dump operation.

[0039] In step S410, the first circuit 310A, the second circuit 310B and the third circuit 310C may synchronously perform substantially the same test operation, and in step S420, the comparator 320 may continuously compare the intermediate signals SIG generated by the first circuit 310A, the second circuit 310B and the third circuit 310C. M1 , SIG M2 and SIG M3 In this embodiment, the first intermediate signal SIG M1 It can be a signal transmitted between the functional units 312A1 to 312AM in the first circuit 310A, and the second intermediate signal SIG M2 It can be a signal transmitted between the functional units 312B1-312BM in the second circuit 310B, and the third intermediate signal SIG M3 It may be a signal transmitted between the functional units 312C1 - 312CM in the third circuit 310C.

[0040] Furthermore, the circuit system 300 may include a first multiplexer 330A, a second multiplexer 330B, and a third multiplexer 330C. The first multiplexer 330A, the second multiplexer 330B, and the third multiplexer 330C may transmit signals transmitted from selected signal terminals of the functional units 312A1-312AM, 312B1-312BM, and 312C1-312CM to the comparator 320 as the first intermediate signal SIGM1 and the second intermediate signal SIG M2 and the third intermediate signal SIG M3 In this way, the circuit system 300 can select the signal transmitted by the first signal terminal to be tested from the multiple first signal terminals of the first functional units 312A1 to 312AM as the first intermediate signal SIG M1, a signal transmitted by a second signal terminal to be tested can be selected from a plurality of second signal terminals of the second functional units 312B1 to 312BM as a second intermediate signal SIG M2 , and can select the signal transmitted by the third signal terminal to be tested from the plurality of third signal terminals of the third functional units 312C1-312CM as the third intermediate signal SIG M3 This makes the test operation more flexible and helps improve the efficiency of the test operation.

[0041] In step S430, when the comparator 320 determines the first intermediate signal SIG M1 , second intermediate signal SIG M2 and the third intermediate signal SIG M3 If one of the three is different from the other two, it indicates that an error may have occurred. In this case, the first circuit 310A, the second circuit 310B, and the third circuit 310C may stop performing the test operation. Generally speaking, since the probability of an error occurring in the first circuit 310A, the second circuit 310B, and the third circuit 310C is lower than the probability of normal operation, when the first intermediate signal SIG M1 , second intermediate signal SIG M2 and the third intermediate signal SIG M3 When one of the three is different from the other two, it can be reasonably inferred that the circuit that generates the intermediate signal and is different from the other two has a higher probability of being an erroneous circuit.

[0042] For example, if the comparator 320 determines that the second intermediate signal SIG M2 With the first intermediate signal SIG M1 Different, the second intermediate signal SIG M2 With the third intermediate signal SIG M3 different, and the first intermediate signal SIG M1 With the third intermediate signal SIG M3 The same test results are obtained, so it is reasonable to infer that an error may have occurred in the second circuit 310B. In this case, in step S440, after resetting the first circuit 310A and the second circuit 310B, substantially the same test operation can be performed again synchronously. After the reset, the third circuit 310C will perform the same test operation as the first circuit 310A and the second circuit 310B after a predetermined delay time after the first circuit 310A and the second circuit 310B start performing the test operation.

[0043] Next, in step S450, the comparator 320 continuously compares the first intermediate signal SIG M1 and the second intermediate signal SIG M2 , and when the comparator 320 determines that the first intermediate signal SIGM1 With the second intermediate signal SIG M2 If not, the first circuit 310A, the second circuit 310B and the third circuit 310C may stop performing the test operation again in step S460 , and the third circuit 310C may perform a scan dump operation in step S470 to obtain the transmission signal currently generated by the third circuit 310C.

[0044] Since the third circuit 310C starts to perform the test operation after a predetermined delay, when the comparator 320 determines that the first intermediate signal SIGM1 is different from the second intermediate signal SIGM2, the third circuit 310C may still be in the stage where an error is about to occur or is occurring. Therefore, by performing a scan dump operation on the third circuit 310C, the transmission signal generated by the third circuit 310C when the error is about to occur or is occurring can be obtained, allowing researchers to more efficiently grasp the error occurrence and thus understand the cause of the error. In some embodiments, when the comparator 320 determines that the first intermediate signal SIG M1 With the second intermediate signal SIG M2 At the same time, the first circuit 310A and the second circuit 310B may also perform a scan dump operation to obtain the signals currently generated by the first circuit 310A and the second circuit 310B.

[0045] Because first circuit 310A and second circuit 310B may operate at a high-frequency clock, when an error is determined based on the comparison result of comparator 320, even if first circuit 310A and second circuit 310B are immediately stopped and a scan dump operation is performed, the signals read may be signals generated by first circuit 310A and second circuit 310B several clock cycles after the error occurred. In this case, the signals read by third circuit 310C performing a scan dump operation (based on the same test operation but delayed by a predetermined time) may be closer to the state when the error is about to occur or is actually occurring, allowing researchers to more efficiently infer the possible cause of the error.

[0046] exist Figure 3 In the embodiment, the first circuit 310A, the second circuit 310B, and the third circuit 310C may include a first scan chain register set 314A, a second scan chain register set 314B, and a third scan chain register set 314C, respectively, to obtain the transmission signals transmitted by the first circuit 310A, the second circuit 310B, and the third circuit 310C during the scan dump operation. However, in some other embodiments, the first circuit 310A, the second circuit 310B, and the third circuit 310C may also include other types of interface signal storage circuits.

[0047] In addition, Figure 3 In the embodiment, the circuit system 300 may further include a system bus 340, a main memory 350, a first input instruction multiplexer 360A, a second input instruction multiplexer 360B, a first delay unit 370A and a second delay unit 370B. In this embodiment, the first delay unit 370A may be coupled to the instruction input terminal of the first circuit 310A. The first delay unit 370A may receive a plurality of instruction signals received by the first circuit 310A and output these instruction signals after a first delay time, wherein the length of the first delay time is greater than or equal to 0. In addition, in some embodiments, the first delay unit 370A may adjust the length of the first delay time as needed. For example, the first delay unit 370A may include a plurality of registers connected in series (for example, implemented as flip-flops), and the first delay unit 370A may select the number of registers that the instruction signal should pass through, thereby adjusting the first delay time of the instruction signal output.

[0048] A first input terminal of the first input instruction multiplexer 360A can be coupled to the first delay unit 370A, a second input terminal of the first input instruction multiplexer 360A can be coupled to the system bus 340, and an output terminal of the first input instruction multiplexer 360A can be coupled to the instruction input terminal of the third circuit 310C. In this way, the first input instruction multiplexer 360A can be used to enable the third circuit 310C to receive the same instruction signal as the first circuit 310A in the test mode, and to enable the third circuit 310C to receive the instruction signal required for the application operation it executes from the system bus 340 in the application mode.

[0049] Similarly, in Figure 3 In the embodiment of the present invention, the second delay unit 370B can be coupled to the instruction input terminal of the first circuit 310A, the first input terminal of the second input instruction multiplexer 360B can be coupled to the second delay unit 370B, the second input terminal of the second input instruction multiplexer 360B can be coupled to the system bus 340, and the output terminal of the second input instruction multiplexer 360B can be coupled to the instruction input terminal of the second circuit 310B. In this way, the second input instruction multiplexer 360B can be used to enable the second circuit 310B to receive the same instruction signal as the first circuit 310A in the test mode, and to enable the second circuit 310B to receive the instruction signal required for the application operation it executes from the system bus 340 in the application mode.

[0050] Since it is impossible to predict whether the error will occur in the first circuit 310A, the second circuit 310B, or the third circuit 310C during the manufacture of the circuit system 300, the first input instruction multiplexer 360A, the second input instruction multiplexer 360B, the first delay unit 370A, and the second delay unit 370B can flexibly control the timing of the second circuit 310B and the third circuit 310C performing test operations, making it easier for researchers to conduct tests under different circumstances. In addition, in some embodiments, the circuit system 300 may further include more input instruction multiplexers and / or delay units, so that the first circuit 310A can receive the instruction signals received by the second circuit 310B and / or the third circuit 310C synchronously or with a delay.

[0051] Furthermore, in Figure 4 In the embodiment, method 400 performs a test operation on the first circuit 310A, the second circuit 310B, and the third circuit 310C synchronously through steps S410-S430. The method then infers which of the first circuit 310A, the second circuit 310B, and the third circuit 310C is faulty based on the first intermediate signal SIGM1, the second intermediate signal SIGM2, and the third intermediate signal SIGM3. Steps S440-S470 are then performed accordingly. However, in other embodiments, if researchers have already determined which of the first circuit 310A, the second circuit 310B, and the third circuit 310C is faulty through other comparison methods, steps S410-S430 of method 400 may be omitted, and steps S440-S470 may be performed directly.

[0052] For example, if it is known that the second circuit 310B will fail, then in step S440, the third circuit 310C can be made to perform substantially the same test operation as the first circuit 310A and the second circuit 310B after a predetermined delay, and in step S450, the first intermediate signal SIG can be compared by the comparator 320. M1 and the second intermediate signal SIG M2 When the comparator 320 determines the first intermediate signal SIG in step S460 M1 and the second intermediate signal SIG M2 If the second circuit 310B is not faulty, the third circuit 310C can be caused to stop executing the test operation and, in step S470, to execute a scan dump operation. In this way, when the second circuit 310B is about to or is experiencing an error, the third circuit 310C can record the signal that should theoretically be received or generated at that time, allowing researchers to more efficiently determine the cause of the error.

[0053] In summary, the circuit system and method for testing the circuit system according to the embodiments of the present invention enable synchronous testing of identical circuits within the circuit system and, through a comparator, instantaneously compare the intermediate signals generated within the identical circuits. Therefore, when an error occurs, a scan dump operation can be immediately performed to record the signals generated by each circuit at the time the error occurred, enabling researchers to efficiently understand the circumstances under which the error occurred. Furthermore, the circuit system can compare the intermediate signals generated by three or more circuits to infer the circuit in which the error may have occurred, and by delaying the execution of the test operation to record the transmission signals generated by the circuit at the time the error occurred, enabling researchers to more quickly understand the circumstances under which the error occurred and further deduce the cause of the error.

[0054] Description of reference numerals:

[0055] 100: Circuit System

[0056] 110A: First circuit

[0057] 110B: Second Circuit

[0058] 112A1: First functional unit

[0059] 112A2: First functional unit

[0060] 112AM: First Functional Unit

[0061] 112B1: Second functional unit

[0062] 112B2: Second functional unit

[0063] 112BM: Second functional unit

[0064] 114A: First scan chain register group

[0065] 114B: Second scan chain register group

[0066] 120: Comparator

[0067] 130A: First multiplexer

[0068] 130B: Second multiplexer

[0069] 140: System bus

[0070] 150: Main memory

[0071] 160: Input instruction multiplexer

[0072] 200: Method

[0073] 300: Circuit System

[0074] 310A: First Circuit

[0075] 310B: Second Circuit

[0076] 312A1: First functional unit

[0077] 312A2: First functional unit

[0078] 312AM: First functional unit

[0079] 312B1: Second functional unit

[0080] 312B2: Second functional unit

[0081] 312BM: Second functional unit

[0082] 312C1: Third functional unit

[0083] 312C2: Third functional unit

[0084] 312CM: The third functional unit

[0085] 314A: First scan chain register group

[0086] 314B: Second scan chain register group

[0087] 314C: Third scan chain register group

[0088] 320: Comparator

[0089] 330A: First Multiplexer

[0090] 330B: Second multiplexer

[0091] 330C: Third multiplexer

[0092] 340: System bus

[0093] 350: Main memory

[0094] 360A: First input instruction multiplexer

[0095] 360B: Second input instruction multiplexer

[0096] 370A: First delay unit

[0097] 370B: Second delay unit

[0098] 400: Method

[0099] S210: Steps

[0100] S220: Steps

[0101] S230: Steps

[0102] S240: Steps

[0103] S410: Step

[0104] S420: Steps

[0105] S430: Steps

[0106] S440: Steps

[0107] S450: Steps

[0108] S460: Steps

[0109] S470: Steps

[0110] SIGM1: First intermediate signal

[0111] SIGM2: Second intermediate signal

[0112] SIGM3: Third intermediate signal

Claims

1. A circuit system comprising: a first circuit for executing at least one application operation; a second circuit having substantially the same structure as the first circuit, and configured to execute the at least one application operation; and a comparator; in: In a test mode, the first circuit and the second circuit synchronously perform a substantially identical test operation; while the first circuit and the second circuit synchronously perform the test operation, the comparator is configured to compare a first intermediate signal generated within the first circuit with a second intermediate signal generated within the second circuit and corresponding to the first intermediate signal; and When the comparator determines that the first intermediate signal is different from the second intermediate signal, the first circuit and the second circuit stop performing the test operation and perform a scan dump operation to obtain multiple first transmission signals currently generated by the first circuit and multiple second transmission signals currently generated by the second circuit.

2. The circuit system according to claim 1, wherein: Also includes: a third circuit having substantially the same structure as the first circuit, and configured to execute the at least one application operation; in: In the test mode, the third circuit performs substantially the same test operation as the first circuit and the second circuit synchronously; When the first circuit, the second circuit, and the third circuit synchronously perform the test operation, the comparator compares the first intermediate signal, the second intermediate signal, and a third intermediate signal generated within the third circuit and corresponding to the first intermediate signal; and When the comparator determines that one of the first intermediate signal, the second intermediate signal, and the third intermediate signal is different from the other two, the first circuit, the second circuit, and the third circuit stop performing the test operation.

3. The circuit system according to claim 2, wherein: After the first circuit, the second circuit, and the third circuit stop performing the test operation, the third circuit performs the scan dump operation to acquire a plurality of third transmission signals currently generated by the third circuit.

4. The circuit system according to claim 2, wherein: In the test mode, when the comparator determines that the second intermediate signal is different from the first intermediate signal and the third intermediate signal and the first intermediate signal is the same as the third intermediate signal, the first circuit and the second circuit synchronously perform the same test operation again, and the third circuit performs substantially the same test operation as the first circuit and the second circuit after a predetermined delay. When the first circuit and the second circuit synchronously perform the test operation again, the comparator compares the first intermediate signal and the second intermediate signal; and When the comparator determines that the first intermediate signal and the second intermediate signal are different, the first circuit, the second circuit, and the third circuit stop performing the test operation again, and the third circuit performs the scan dump operation to obtain a plurality of third transmission signals currently generated by the third circuit.

5. The circuit system according to claim 4, wherein: After the first circuit, the second circuit, and the third circuit stop performing the test operation again, the first circuit and the second circuit perform the scan dump operation.

6. The circuit system according to claim 1, wherein: Also includes: a third circuit having substantially the same structure as the first circuit, and configured to execute the at least one application operation; in: In the test mode, the third circuit performs substantially the same test operation as the first circuit and the second circuit after a predetermined delay; and When the first intermediate signal and the second intermediate signal are different, the third circuit stops performing the test operation and performs the scan dump operation to obtain a plurality of third transmission signals currently generated by the third circuit.

7. A method for testing a circuit system, the test circuit system comprising a first circuit and a second circuit, the first circuit and the second circuit having the same structure, the method comprising: enabling the first circuit and the second circuit to synchronously perform the same test operation in a test mode; During the process in which the first circuit and the second circuit synchronously perform the test operation, comparing a first intermediate signal generated within the first circuit and a second intermediate signal generated within the second circuit and corresponding to the first intermediate signal; When the first intermediate signal is different from the second intermediate signal, stopping the first circuit and the second circuit from performing the test operation; and After the first circuit and the second circuit stop performing the test operation, the first circuit and the second circuit are enabled to perform a scan dump operation to obtain a plurality of first transmission signals currently generated by the first circuit and a plurality of second transmission signals currently generated by the second circuit.

8. The method for testing a circuit system according to claim 7, wherein: The circuit system further includes a third circuit having the same structure as the first circuit, and the method further includes: In the test mode, the third circuit is caused to perform substantially the same test operation as the first circuit and the second circuit synchronously; When the first circuit, the second circuit, and the third circuit synchronously perform the test operation, comparing the first intermediate signal, the second intermediate signal, and a third intermediate signal generated within the third circuit and corresponding to the first intermediate signal; and When one of the first intermediate signal, the second intermediate signal, and the third intermediate signal is different from the other two, the third circuit is stopped from performing the test operation.

9. The method for testing a circuit system according to claim 8, wherein: Also includes: In the test mode, when the second intermediate signal is different from the first intermediate signal and the third intermediate signal and the first intermediate signal is the same as the third intermediate signal, the first circuit and the second circuit are synchronously executed again with each other to perform the same test operation, and the third circuit is delayed for a predetermined time and then executed with the first circuit and the second circuit to perform the same test operation; When the first circuit and the second circuit synchronously perform the test operation again, comparing the first intermediate signal and the second intermediate signal; When the first intermediate signal and the second intermediate signal are different, stopping the first circuit, the second circuit, and the third circuit from performing the test operation; and After the first circuit, the second circuit, and the third circuit stop performing the test operation, the third circuit is enabled to perform the scan dump operation to acquire a plurality of third transmission signals currently generated by the third circuit.

10. The method for testing a circuit system according to claim 7, wherein: The circuit system further includes a third circuit having the same structure as the first circuit, and the method further includes: In the test mode, the third circuit is caused to perform the same test operation as the first circuit and the second circuit after a predetermined delay; When the first intermediate signal and the second intermediate signal are different, causing the third circuit to stop performing the test operation; and After the third circuit stops performing the test operation, the third circuit is enabled to perform the scan dump operation to acquire a plurality of third transmission signals currently generated by the third circuit.

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