Joint body and insulating circuit substrate

Abstract

The joint body of the present invention has a structure formed by joining an insulating resin part made of insulating resin and a metal part made of metal, wherein the joining interface between the insulating resin part and the metal part is in a concave-convex shape with convex portions and concave portions, wherein the convex portion is formed by the metal part protruding toward the insulating resin part side, and the concave portion is formed by the metal part retreating from the insulating resin part side, at least one of the kurtosis Rku of the contour curve at the joining interface of the metal part and the kurtosis Sku of the contour surface at the joining interface of the metal part is within the range of greater than 2.75 and less than 6.00, and the overhang rate of the metal part is greater than 7%, and the overhang rate represents the length ratio of the area overlapping the stacking direction in the direction along the joining interface.

Description

Technical Field

[0001] The present invention relates to a joined body having a structure in which an insulating resin member made of insulating resin and a metal member are joined together, and an insulating circuit substrate.

[0002] This application claims priority based on Patent Application No. 2020-060041 filed in Japan on March 30, 2020 and Patent Application No. 2020-161017 filed in Japan on September 25, 2020, and the contents of which are incorporated herein by reference. Background Art

[0003] The power module, LED module and thermoelectric module have the following structure: a power semiconductor element, LED element and thermoelectric element are bonded to an insulating circuit substrate having a circuit layer made of a conductive material formed on one side of an insulating layer. In addition, as the insulating layer, an insulating layer made of ceramic or an insulating layer made of insulating resin is proposed.

[0004] Here, as an insulating circuit substrate having an insulating resin layer, for example, a metal base circuit substrate is proposed in Patent Document 1. Furthermore, a multilayer wiring substrate is proposed in Patent Document 2.

[0005] In the metal base circuit board described in Patent Document 1, an insulating resin layer is formed on a metal substrate, and a circuit layer having a circuit pattern is formed on the insulating resin layer. Here, the insulating resin layer is composed of epoxy resin as a thermosetting resin, and the circuit layer is composed of copper foil.

[0006] The metal base circuit board has a structure in which a semiconductor element is bonded to a circuit layer, a heat sink is disposed on the surface of the metal substrate opposite to the insulating resin layer, and heat generated by the semiconductor element is transferred to the heat sink for dissipation.

[0007] Furthermore, in the multilayer wiring substrate described in Patent Document 2, a metal foil bonded to a resin film is etched so that the surface roughness (Ra) of the metal foil reaches 0.2 μm or more, and is further etched into a circuit pattern to form a wiring circuit layer. The wiring circuit layer formed on the surface of the resin film is buried in the insulating sheet while applying pressure to the surface of the soft insulating sheet, thereby transferring the wiring circuit layer to the surface of the insulating sheet. The plurality of insulating sheets thus obtained are stacked and heated and cured together to manufacture a multilayer wiring substrate.

[0008] Patent Document 1: Japanese Patent Application Publication No. 2015-207666

[0009] Patent Document 2: Japanese Patent Application Publication No. 2000-077850

[0010] In an insulating circuit substrate having a structure in which a metal plate or the like is bonded to an insulating resin layer to form a circuit layer, it is necessary to ensure the close contact between the insulating resin layer and the circuit layer (metal plate) to avoid peeling of the insulating resin layer and the circuit layer (metal plate) during use.

[0011] Here, in the metal base circuit board described in Patent Document 1, no consideration is given to improving the adhesion between the insulating resin layer and the circuit layer, so that the insulating resin layer and the circuit layer (metal plate) may peel off during use.

[0012] On the other hand, in the multilayer wiring board described in Patent Document 2, the wiring circuit layer is embedded in the insulating sheet with a surface roughness (Ra) of 0.2 μm or more, thereby improving the adhesion between the insulating sheet and the wiring circuit layer.

[0013] However, if the surface roughness (Ra) of the metal plate (wiring circuit layer) is too large, electric charges may be concentrated in the portion where the metal plate surface enters, causing the insulation (insulation withstand voltage) of the insulating resin layer to decrease, making it impossible to use it as an insulating circuit substrate. Summary of the invention

[0014] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a bonded body and an insulating circuit board which are excellent in adhesion between an insulating resin member and a metal member and excellent in insulation properties of the insulating resin member and can be used stably.

[0015] In order to solve the above-mentioned problems, the joint body of the present invention has a structure formed by joining an insulating resin part made of insulating resin and a metal part made of metal, and the joint body is characterized in that the joining interface between the insulating resin part and the metal part is a concave-convex shape with convex parts and concave parts, the convex part is formed by the metal part protruding toward the insulating resin part side, and the concave part is formed by the metal part retreating from the insulating resin part side, at least one of the kurtosis Rku of the contour curve at the joining interface of the metal part and the kurtosis Sku of the contour surface at the joining interface of the metal part is within the range of greater than 2.75 and less than 6.00, and the overhang ratio of the metal part is greater than 7%, and the overhang ratio represents the length ratio of the area overlapping the stacking direction in the direction along the joining interface.

[0016] According to the joint body of this structure, since the joining interface between the insulating resin part and the metal part is a concave-convex shape with a convex portion and a concave portion, the convex portion is formed by the metal part protruding toward the insulating resin part side, and the concave portion is formed by the metal part retreating from the insulating resin part side, at least one of the kurtosis Rku of the contour curve at the joining interface of the metal part and the kurtosis Sku of the contour surface at the joining interface of the metal part is within the range of greater than 2.75 and less than 6.00, and therefore the front end of the convex portion is not excessively sharp, and the insulation (insulation withstand voltage) of the insulating resin part can be fully ensured.

[0017] Furthermore, since the overhang ratio indicating the length ratio of the region overlapping the lamination direction in the direction along the bonding interface is 7% or more, the metal component and the insulating resin component can be sufficiently engaged, thereby improving the adhesion between the insulating resin component and the metal component.

[0018] Here, in the bonded body of the present invention, at least one of a root mean square height Rq of a profile curve at the bonding interface of the metal parts and a root mean square height Sq of a profile surface at the bonding interface of the metal parts is preferably within a range of 0.20 μm to 0.90 μm.

[0019] In this case, since at least one of the root mean square height Rq of the contour curve at the joining interface of the metal part and the root mean square height Sq of the contour surface at the joining interface of the metal part is within the range of greater than 0.20 μm and less than 0.90 μm, the electric field concentration at the front end of the protrusion can be suppressed, thereby reliably ensuring insulation and reliably improving the adhesion between the insulating resin part and the metal part.

[0020] The insulating circuit substrate of the present invention comprises an insulating resin layer and a circuit layer formed by joining a metal plate to one side of the insulating resin layer. The insulating circuit substrate is characterized in that the joining interface between the insulating resin layer and the circuit layer is in a concave-convex shape with convex portions and concave portions, the convex portion is formed by the circuit layer protruding toward the insulating resin layer side, and the concave portion is formed by the circuit layer retreating from the insulating resin layer side, at least one of the kurtosis Rku of the contour curve at the joining interface of the circuit layer and the kurtosis Sku of the contour surface at the joining interface of the circuit layer is within the range of greater than 2.75 and less than 6.00, the overhang rate of the circuit layer is greater than 7%, and the overhang rate represents the length ratio of the area overlapping the stacking direction in the direction along the joining interface.

[0021] According to the insulating circuit substrate of this structure, since the bonding interface between the insulating resin layer and the circuit layer is in a concave-convex shape with convex portions and concave portions, the convex portion is formed by the circuit layer protruding toward the insulating resin layer side, and the concave portion is formed by the circuit layer retreating from the insulating resin layer side, and at least one of the kurtosis Rku of the contour curve at the bonding interface of the circuit layer and the kurtosis Sku of the contour surface at the bonding interface of the circuit layer is within the range of greater than 2.75 and less than 6.00, the front end of the convex portion will not be excessively sharp, and the insulation (insulation withstand voltage) of the insulating resin layer can be fully ensured.

[0022] Moreover, since the overhang rate is greater than 7%, which represents the length ratio of the region overlapping the stacking direction along the bonding interface, the circuit layer and the insulating resin layer can be fully engaged, thereby improving the adhesion between the circuit layer and the insulating resin layer.

[0023] Here, in the insulating circuit substrate of the present invention, at least one of the root mean square height Rq of the contour curve at the bonding interface of the circuit layer and the root mean square height Sq of the contour surface at the bonding interface of the circuit layer is preferably within the range of 0.20 μm to 0.90 μm.

[0024] In this case, since at least one of the root mean square height Rq of the contour curve at the bonding interface of the circuit layer and the root mean square height Sq of the contour surface at the bonding interface of the circuit layer is within the range of greater than 0.20 μm and less than 0.90 μm, the electric field concentration at the front end of the protrusion can be suppressed, thereby reliably ensuring insulation and reliably improving the adhesion between the insulating resin layer and the circuit layer.

[0025] According to the present invention, it is possible to provide a bonded body and an insulating circuit board which are excellent in adhesion between an insulating resin member and a metal member, and excellent in insulation properties of the insulating resin member and can be stably used. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic explanatory diagram of a power module including an insulating circuit substrate according to an embodiment of the present invention.

[0027] Figure 2 This is a flowchart for explaining a method for manufacturing an insulating circuit board according to an embodiment of the present invention.

[0028] Figure 3The following are cross-sectional observation photographs of a metal plate (metal substrate) before and after the surface roughening step S01 in the method for manufacturing an insulating circuit substrate according to an embodiment of the present invention. (a) is a photograph before the surface roughening step S01 is performed, and (b) is a photograph after the surface roughening step S01 is performed.

[0029] Figure 4 yes Figure 2 A schematic diagram for explaining a method for manufacturing an insulating circuit substrate shown in FIG.

[0030] Figure 5 It is an explanatory diagram showing a measurement example of the overhang rate in the examples.

[0031] Figure 6 This is a schematic explanatory diagram of a test device for evaluating the insulation properties (insulation withstand voltage) of an insulating circuit board in Examples. DETAILED DESCRIPTION

[0032] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0033] The bonded body according to the present embodiment is an insulating circuit substrate 10 formed by bonding an insulating resin layer 12 as an insulating resin member, a metal plate 23 (circuit layer 13 ) as a metal member, and a metal substrate 11 .

[0034] Figure 1 An insulating circuit substrate 10 according to an embodiment of the present invention and a power module 1 using the insulating circuit substrate 10 are shown.

[0035] Figure 1 The power module 1 shown in the figure comprises: an insulating circuit substrate 10; a first solder layer 2 and a surface of the insulating circuit substrate 10 (in Figure 1 and the other side of the insulating circuit substrate 10 (in the solder layer 32) is connected to the semiconductor element 3; and the other side of the insulating circuit substrate 10 (in the solder layer 32) is connected to the semiconductor element 3; Figure 1 The heat sink 31 is connected to the heat sink 31 (the lower side in the middle).

[0036] The semiconductor element 3 is made of a semiconductor material such as Si. The first solder layer 2 joining the insulating circuit board 10 and the semiconductor element 3 is, for example, Sn-Ag, Sn-Cu, Sn-In, or Sn-Ag-Cu solder (so-called lead-free solder).

[0037] The heat sink 31 is used to dissipate the heat on the insulating circuit substrate 10 side. The heat sink 31 is made of copper or copper alloy, aluminum or aluminum alloy, etc., which have good thermal conductivity. In this embodiment, the heat sink is a heat sink made of oxygen-free copper. In addition, the thickness of the heat sink 31 is set in the range of 3 mm or more and 10 mm or less.

[0038] Here, the insulating circuit substrate 10 and the heat sink 31 are bonded to each other via a solder layer 32. The solder layer 32 may have the same structure as the solder layer 2 described above.

[0039] Moreover, if Figure 1 As shown, the insulating circuit substrate 10 of this embodiment includes: a metal substrate 11; a Figure 1 and formed on one side of the insulating resin layer 12 (in Figure 1 The circuit layer 13 is shown as the upper side.

[0040] The metal substrate 11 has the following function: the heat dissipation characteristics are improved by diffusing the heat generated in the semiconductor element 3 mounted on the insulating circuit substrate 10 in the surface direction. Therefore, the metal substrate 11 is composed of a metal with excellent thermal conductivity (such as copper or copper alloy, aluminum or aluminum alloy). In the present embodiment, the metal substrate is composed of a rolled plate of oxygen-free copper. In addition, the thickness of the metal substrate 11 is set within the range of more than 0.05 mm and less than 3 mm, and in the present embodiment, it is set to 2.0 mm.

[0041] The insulating resin layer 12 is a layer for preventing electrical connection between the circuit layer 13 and the metal substrate 11 , and is made of a thermosetting resin having insulating properties.

[0042] In this embodiment, in order to ensure the strength of the insulating resin layer 12 and to ensure thermal conductivity, a thermosetting resin containing a filler is used. Here, as the filler, for example, aluminum oxide, boron nitride, aluminum nitride, etc. can be used. In addition, as the thermosetting resin, epoxy resin or polyimide resin can be used. In this embodiment, the insulating resin layer 12 is composed of an epoxy resin containing aluminum oxide as a filler. In addition, the thickness of the insulating resin layer 12 is in the range of 20 μm or more and 250 μm or less, and is 150 μm in this embodiment.

[0043] like Figure 4 As shown, the circuit layer 13 is formed by bonding a metal plate 23 made of a metal having excellent conductivity to one side of the insulating resin layer 12 (at Figure 4 As the metal plate 23, a rolled plate of copper or copper alloy, aluminum or aluminum alloy, etc. can be used. In the present embodiment, as the metal plate 23 constituting the circuit layer 13, a rolled plate of oxygen-free copper is used.

[0044] A circuit pattern is formed in the circuit layer 13, one side of which (on Figure 1 The upper surface in the middle is the mounting surface on which the semiconductor element 3 is mounted. Here, the thickness of the circuit layer 13 (metal plate 23) is set within a range of 0.3 mm to 3 mm, and is set to 0.5 mm in the present embodiment.

[0045] Moreover, in the insulating circuit substrate 10 of the present embodiment, the bonding interface between the insulating resin layer 12 and the circuit layer 13 (metal substrate 11) presents a concave-convex shape having a convex portion 18 and a concave portion 19, wherein the convex portion 18 is formed by the circuit layer 13 (metal substrate 11) protruding toward the insulating resin layer 12 side, and the concave portion 19 is formed by the circuit layer 13 (metal substrate 11) retreating from the insulating resin layer 12 side.

[0046] That is, in the present embodiment, the circuit layer 13 (metal substrate 11 ) has a structure in which the insulating resin layer 12 is embedded.

[0047] Here, in this embodiment, at least one of the kurtosis Rku of the contour curve at the bonding interface of the circuit layer 13 (metal substrate 11) and the kurtosis Sku of the contour surface at the bonding interface of the circuit layer 13 (metal substrate 11) is within the range of greater than 2.75 and less than 6.00.

[0048] Furthermore, the overhang ratio indicating the length ratio of the region overlapping the lamination direction in the direction along the bonding interface is 7% or more.

[0049] In addition, in the present embodiment, at least one of the root mean square height Rq of the contour curve at the bonding interface of the circuit layer 13 (metal substrate 11) and the root mean square height Sq of the contour surface at the bonding interface of the circuit layer 13 (metal substrate 11) is preferably within the range of greater than 0.20 μm and less than 0.90 μm.

[0050] Hereinafter, the reasons for specifying the kurtosis Rku of the contour curve at the bonding interface of the circuit layer 13 (metal substrate 11) and the kurtosis Sku of the contour surface at the bonding interface of the circuit layer 13 (metal substrate 11), the overhang rate representing the length ratio of the area overlapping with the stacking direction in the direction along the bonding interface, the root mean square height Rq of the contour curve at the bonding interface of the circuit layer 13 (metal substrate 11), and the root mean square height Sq of the contour surface at the bonding interface of the circuit layer 13 (metal substrate 11) as described above in the insulating circuit substrate 10 of the present embodiment will be explained.

[0051] (Kurtosis Rku of the profile curve and kurtosis Sku of the profile surface at the bonding interface)

[0052] The kurtosis Rku of the profile curve is a parameter specified in JIS B 0601:2001, and the kurtosis Sku of the profile surface is a parameter specified in JIS B 0681-2:2018, and is a value for evaluating the kurtosis which is a measure of the surface sharpness.

[0053] The kurtosis Rku of the profile curve is Rku=3 in the shape of a normal distribution, Rku>3 when the height distribution is sharper than the normal distribution, and Rku<3 when the height distribution is flatter than the normal distribution.

[0054] Furthermore, the kurtosis Sku of the contour surface is a parameter obtained by expanding the kurtosis Rku of the contour curve into three dimensions.

[0055] Here, if the peak Rku of the contour curve and the peak Sku of the contour surface at the bonding interface of the circuit layer 13 (metal substrate 11) are both less than 2.75, the surface of the circuit layer 13 (the front end of the protrusion 18) will become a collapsed shape, and it is possible that the circuit layer 13 (metal substrate 11) cannot fully enter the insulating resin layer 12 side, thereby failing to improve the close contact between the insulating resin layer 12 and the circuit layer 13 (metal substrate 11). On the other hand, if the peak Rku of the contour curve and the peak Sku of the contour surface at the bonding interface of the circuit layer 13 (metal substrate 11) are both greater than 6.00, the surface of the circuit layer 13 (the front end of the protrusion 18) will be too sharp, and it is possible that electric field concentration will occur at the front end of the protrusion 18, and the insulation (insulation withstand voltage) of the insulating resin layer 12 cannot be ensured.

[0056] Therefore, in the present embodiment, at least one of the kurtosis Rku of the contour curve and the kurtosis Sku of the contour surface at the bonding interface of the circuit layer 13 (metal substrate 11 ) is set within a range of 2.75 to 6.00.

[0057] In addition, at least one of the kurtosis Rku of the contour curve and the kurtosis Sku of the contour surface at the bonding interface of the circuit layer 13 (metal substrate 11) is preferably 2.75 or more, and more preferably 3.00 or more. On the other hand, at least one of the kurtosis Rku of the contour curve and the kurtosis Sku of the contour surface at the bonding interface of the circuit layer 13 (metal substrate 11) is preferably 6.00 or less, and more preferably 3.75 or less.

[0058] (Overhang rate)

[0059] The overhang rate in this embodiment is the following value: when the cross-sectional shape of the bonding interface is image analyzed using image processing software, for the obtained cross-sectional curve, the area overlapping with the stacking direction (height direction: Y direction) in the direction along the bonding interface (horizontal direction: X direction) is taken as the overhang portion, the ratio of the length of the overhang portion in the X direction to the total length of the obtained cross-sectional curve in the X direction.

[0060] In addition, when the length of the overhang portion is calculated in the X direction, for example, when there is no overhang portion in the Y direction, it is 0, when there is one overhang portion in the Y direction, it is 1, when there are two overhang portions in the Y direction, it is 2, and when there are multiple overhang portions in the Y direction, it is calculated as multiple. Therefore, the overhang ratio can be 100% or more.

[0061] Here, when the overhang rate, which represents the length ratio of the area overlapping with the stacking direction in the direction along the bonding interface, is less than 7%, it may be impossible to fully engage the circuit layer 13 (metal substrate 11) and the insulating resin layer 12, thereby failing to improve the adhesion between the insulating resin layer 12 and the circuit layer 13 (metal substrate 11).

[0062] Therefore, in the present embodiment, the overhang ratio indicating the length ratio of the region overlapping the lamination direction in the direction along the bonding interface is set to 7% or more.

[0063] The overhang rate is preferably 7% or more, and more preferably 15% or more. On the other hand, the overhang rate is not particularly limited, but is preferably 100% or less.

[0064] (Root mean square height Rq of the profile curve at the bonding interface and root mean square height Sq of the profile surface)

[0065] The root mean square height Rq of the profile curve is a parameter specified in JIS B 0601:2001, and the root mean square height Sq of the profile surface is a parameter specified in JIS B 0681-2:2018, which is a value indicating the standard deviation of the surface roughness.

[0066] In the insulating circuit substrate 10 of the present embodiment, by making at least one of the root mean square height Rq of the contour curve and the root mean square height Sq of the contour surface at the bonding interface of the circuit layer 13 (metal substrate 11) to be 0.20 μm or more, the circuit layer 13 (metal substrate 11) is sufficiently inserted into the insulating resin layer 12 side, thereby reliably improving the adhesion between the insulating resin layer 12 and the circuit layer 13 (metal substrate 11). On the other hand, by making at least one of the root mean square height Rq of the contour curve and the root mean square height Sq of the contour surface at the bonding interface of the circuit layer 13 (metal substrate 11) to be 0.90 μm or less, it is possible to suppress the electric field concentration at the tip of the protrusion 18 formed by the circuit layer 13 (metal substrate 11) that enters the inside of the insulating resin layer 12, thereby reliably ensuring the insulation of the insulating resin layer 12.

[0067] Therefore, in the insulating circuit substrate 10 of this embodiment, it is preferred that at least one of the root mean square height Rq of the contour curve and the root mean square height Sq of the contour surface at the bonding interface of the circuit layer 13 (metal substrate 11) be within the range of 0.20 μm to 0.90 μm.

[0068] In addition, at least one of the root mean square height Rq of the contour curve at the bonding interface of the circuit layer 13 (metal substrate 11) and the root mean square height Sq of the contour surface is preferably 0.20 μm or more, and more preferably 0.30 μm or more. On the other hand, at least one of the root mean square height Rq of the contour curve at the bonding interface of the circuit layer 13 (metal substrate 11) and the root mean square height Sq of the contour surface is preferably 0.90 μm or less, and more preferably 0.80 μm or less.

[0069] Next, refer to Figures 2 to 4 A method for manufacturing the insulating circuit board 10 according to the present embodiment will be described.

[0070] (Surface Roughening Process S01)

[0071] First, the roughened plating layer 23a is formed on the joint surface between the metal plate 23 and the insulating resin layer 12, which will become the circuit layer 13, and the roughened plating layer 11a is formed on the joint surface between the metal substrate 11 and the insulating resin layer 12. Thus, concavo-convex portions are formed on the joint surface between the metal plate 23 and the insulating resin layer 12, which will become the circuit layer 13, and on the joint surface between the metal substrate 11 and the insulating resin layer 12. In addition, the roughened plating layers 23a and 11a are formed as follows.

[0072] Electroplating is performed on the joint surface of the metal plate 23 and the metal substrate 11. In the present embodiment, as the electroplating solution, an electrolyte composed of an aqueous solution is preferably used: the aqueous solution is formed by adding disodium 3,3'-dithiobis(1-propanesulfonic acid) to a copper sulfate bath containing copper sulfate (CuSO4) and sulfuric acid (H2SO4) as main components. In addition, the temperature of the plating bath is preferably within a range of, for example, 25°C or more and 35°C or less.

[0073] As the electroplating process, a PR (Periodic Reverse) pulse plating process is used. The PR pulse plating process is a method of performing electroplating while passing current while periodically reversing the direction of the current. For example, 1A / dm 2 Above and 30A / dm 2 The positive electrolysis (anodic electrolysis using the metal plate 23 and the metal substrate 11 as anodes) is set to 1 ms to 1000 ms, and the current is set to 1 A / dm 2 Above and 30A / dm 2 The following negative electrolysis (cathode electrolysis using the metal plate 23 and the metal substrate 11 as cathodes) is performed for a period of 1 ms to 1000 ms, and this operation is repeated.

[0074] Thus, the dissolution of the surfaces of the metal plate 23 and the metal substrate 11 and the precipitation of copper are repeated, thereby forming the roughened plating layers 23 a and 11 a .

[0075] Here, according to the surface properties of the metal plate 23 and the metal substrate 11 before forming the roughened plating layers 23a and 11a and various plating conditions (pulse application time, pulse waveform (ratio of precipitation amount / solubility), pulse frequency), the kurtosis Rku of the contour curve and the kurtosis Sku of the contour surface at the joining surface of the metal plate 23 and the metal substrate 11, the overhang rate, the root mean square height Rq of the contour curve and the root mean square height Sq of the contour surface can be adjusted.

[0076] For example, if the pulse application time is prolonged, the kurtosis Rku of the profile curve and the kurtosis Sku of the profile surface approach 3, the overhang rate increases, and the root mean square height Rq of the profile curve and the root mean square height Sq of the profile surface increase.

[0077] Furthermore, when the ratio of precipitation amount / solubility as the pulse waveform is increased, the kurtosis Rku of the profile curve and the kurtosis Sku of the profile surface increase, the overhang rate decreases, and the root mean square height Rq of the profile curve and the root mean square height Sq of the profile surface decrease.

[0078] In addition, if the pulse frequency increases, the kurtosis Rku of the contour curve and the kurtosis Sku of the contour surface approach 3, the overhang rate decreases, and the root mean square height Rq of the contour curve and the root mean square height Sq of the contour surface decrease.

[0079] Here, in Figure 3 (a) shows a cross-sectional photograph of the metal plate 23 (metal substrate 11) before the surface roughening step S01 is performed. Figure 3 (b) shows a cross-sectional photograph of the metal plate 23 (metal substrate 11 ) after the surface roughening step S01 has been performed.

[0080] By performing the surface roughening step S01 of the present embodiment, it was confirmed that concavo-convex portions were formed on the bonding surface of the metal plate 23 (metal substrate 11 ) and an overhang portion was formed.

[0081] (Lamination Step S02)

[0082] Next, a resin composition 22 containing alumina as a filler, epoxy resin as a thermosetting resin, and a curing agent is disposed on one side (at the bottom) of the metal substrate 11. Figure 4 In the present embodiment, the resin composition 22 is formed into a sheet shape.

[0083] Furthermore, on one side of the resin composition 22 (on Figure 4 A metal plate 23 serving as the circuit layer 13 is provided (the upper side in the middle).

[0084] (Thermocompression bonding process S03)

[0085] Next, the stacked metal substrate 11, resin composition 22, and metal plate 23 are pressurized and heated in the stacking direction to cure the resin composition 22 to form an insulating resin layer 12, and the metal substrate 11 and the insulating resin layer 12 are bonded, and the insulating resin layer 12 and the metal plate 23 are bonded.

[0086] The conditions of the thermocompression bonding step S03 are preferably: a heating temperature in the range of 150° C. to 400° C., a holding time at the heating temperature in the range of 30 minutes to 90 minutes, and a pressurization pressure in the lamination direction in the range of 1 MPa to 100 MPa.

[0087] (Circuit Pattern Forming Step S04)

[0088] Next, the metal plate 23 bonded to the insulating resin layer 12 is etched to form a circuit pattern, thereby forming the circuit layer 13 .

[0089] As described above, the insulating circuit board 10 of the present embodiment is manufactured.

[0090] (Heat sink bonding process S05)

[0091] Next, the heat sink 31 is bonded to the other surface of the metal substrate 11 of the insulating circuit substrate 10. In the present embodiment, the metal substrate 11 and the heat sink 31 are bonded by solder.

[0092] (Semiconductor element bonding step S06)

[0093] Then, the semiconductor element 3 is bonded to the circuit layer 13 of the insulating circuit substrate 10. In the present embodiment, the circuit layer 13 and the semiconductor element 3 are bonded by solder.

[0094] Through the above process, the Figure 1 The power module 1 is shown.

[0095] According to the insulating circuit substrate 10 (joint body) involved in the present embodiment constructed as above, since the bonding interface between the insulating resin layer 12 and the circuit layer 13 (metal substrate 11) presents a concave-convex shape with a convex portion 18 and a concave portion 19, the convex portion 18 is formed by the circuit layer 13 (metal substrate 11) protruding toward the insulating resin layer 12 side, and the concave portion 19 is formed by the circuit layer 13 (metal substrate 11) retreating from the insulating resin layer 12 side, and at least one of the peak Rku of the contour curve and the peak Sku of the contour surface at the bonding interface of the circuit layer 13 (metal substrate 11) is greater than 2.75, the circuit layer 13 (metal substrate 11) can fully enter the insulating resin layer 12 side, thereby improving the close contact between the insulating resin layer 12 and the circuit layer 13 (metal substrate 11). Furthermore, since at least one of the peaks Rku of the contour curve and the peaks Sku of the contour surface at the bonding interface of the circuit layer 13 (metal substrate 11) is less than 6.00, the front end of the protrusion 18 is not overly sharp, thereby fully ensuring the insulation (insulation withstand voltage) of the insulating resin layer.

[0096] Moreover, since the overhang rate, which represents the length ratio of the area overlapping the stacking direction in the direction along the bonding interface, is greater than 7%, the circuit layer 13 (metal substrate 11) and the insulating resin layer 12 can be fully engaged, thereby improving the adhesion between the circuit layer 13 (metal substrate 11) and the insulating resin layer 12.

[0097] Here, in the insulating circuit substrate 10 (joint) of the present embodiment, when at least one of the root mean square height Rq of the contour curve and the root mean square height Sq of the contour surface at the bonding interface of the circuit layer 13 (metal substrate 11) is within the range of greater than 0.20 μm and less than 0.90 μm, the electric field concentration at the front end of the protrusion 18 can be suppressed, the insulation of the insulating resin layer 12 can be reliably ensured, and the adhesion between the circuit layer 13 (metal substrate 11) and the insulating resin layer 12 can be reliably improved.

[0098] As mentioned above, although embodiment of this invention was described, this invention is not limited to this, It can change suitably within the range which does not deviate from the technical idea of ​​this invention.

[0099] In this embodiment, Figures 2 to 4 The method for manufacturing the insulating circuit substrate shown is explained in terms of a method for manufacturing the insulating circuit substrate, but is not limited thereto.

[0100] Furthermore, in the present embodiment, a plate made of oxygen-free copper is described as a metal substrate and a metal plate forming a circuit layer, but it is not limited thereto and can be made of other copper or copper alloys, or other metals such as aluminum or aluminum alloys. In addition, it can also be a structure formed by stacking multiple metals.

[0101] In addition, in this embodiment, a structure in which a semiconductor element is mounted on an insulating circuit substrate to form a power module is described, but the present invention is not limited thereto. For example, an LED element may be mounted on a circuit layer of an insulating circuit substrate to form an LED module, or a thermoelectric element may be mounted on a circuit layer of an insulating circuit substrate to form a thermoelectric module.

[0102] Example

[0103] Hereinafter, the results of confirmation experiments conducted to confirm the effects of the present invention will be described.

[0104] A metal substrate (40mm×40mm×thickness 2mm) made of a rolled plate of oxygen-free copper and a metal plate (40mm×40mm×thickness 0.5mm) serving as a circuit layer are prepared, and a roughened plating layer is formed on the joining surfaces of these metal substrates and metal plates with the insulating resin layer by the PR pulse electrolysis method described in the above embodiment.

[0105] Then, a sheet (40 mm×40 mm×0.15 mm thick) of a resin composition containing Al 2 O 3 as a filler and an epoxy resin was placed on the surface of the metal substrate on which the roughened plated layer was formed.

[0106] Then, the metal plate to be the circuit layer was laminated on one surface of the resin composition sheet so that the surface on which the roughened plated layer was formed faced the resin composition sheet side.

[0107] The metal substrate, the resin composition sheet and the metal plate stacked as described above are heated while being pressed in the stacking direction, so that the resin composition is cured to form an insulating resin layer, and the metal substrate and the insulating resin layer are bonded, and the insulating resin layer and the metal plate are bonded, thereby obtaining an insulating circuit substrate. In addition, the pressing pressure in the stacking direction is 10 MPa, the heating temperature is 180° C., and the holding time at the heating temperature is 60 minutes.

[0108] The insulating circuit substrates obtained as described above were evaluated for the following items.

[0109] (Kurtosis and RMS height)

[0110] The bonding interface between the circuit layer and the insulating resin layer was observed using a laser microscope OLS5000 with a 100x objective lens within a measuring range of 129μm×129μm. The sample was processed to remove the tilt and noise, and the kurtosis Sku of the contour surface at the bonding interface and the root mean square height Sq of the contour surface were calculated.

[0111] Next, the kurtosis Rku of the profile curve and the root mean square height Rq of the profile curve at the bonding interface were calculated in the direction where the roughness was considered to be the greatest. In addition, at least three points were measured within the measurement range, and the average values ​​were recorded in the table.

[0112] (Overhang rate)

[0113] The insulating circuit substrate was cut in the diagonal direction and along the stacking direction, and the cross section of the bonding interface between the circuit layer and the insulating resin layer was observed to obtain a SIM (Structure Illumination Microscopy) image (512 pixels = 11 μm) with a magnification of 10,000 times. The SIM image was binarized using the image analysis software Image J, and the outline was extracted after manually removing the noise.

[0114] The cross-sectional curve coordinates from which the contours were extracted were output in csv format, and the number of metal regions overlapping in the Y direction was counted for an X-direction length of 512 pixels. In addition, in order to avoid repeated counting of vertical lines, pixels extending in the Y direction (adjacent pixels in the Y direction) were excluded. Then, the overhang ratio was calculated by dividing the number of overlapping regions at each X-axis position by the overall X-coordinate length.

[0115] [Overhang ratio] = [Total number of overhang areas at each X-axis position] / [Number of pixels in the X direction] × 100 (%)

[0116] The measurement example is shown in Figure 5 .exist Figure 5 In the cross-sectional curve shown, the number of overlapping areas in the Y direction at each X-axis position is 0, 1, 1, 0, 0, 0, 0, 0, 1, 1, 2, 2, 1, 1, 0 from the left, and their total is 10. The number of pixels in the X direction is 15, so the overhang rate is 10 / 15×100, which is 67%.

[0117] (Reflow treatment after moisture absorption treatment)

[0118] The insulating circuit board was placed in a constant temperature and humidity chamber (temperature 85°C, humidity 85%) for 3 days, and then placed in a heating furnace and subjected to a reflow treatment at 290°C for 10 minutes.

[0119] In the insulating circuit board after the reflow process, the bonding rate between the circuit layer and the insulating resin layer and the breakdown voltage were evaluated as follows.

[0120] (Joining rate)

[0121] The bonding rate between the circuit layer and the insulating resin layer was evaluated using an ultrasonic flaw detector (FineSAT200 manufactured by Hitachi Power Solutions Co., Ltd.) and calculated by the following formula. Here, the initial bonding area is the area to be bonded before bonding. In the image of the ultrasonic flaw detection image that has been binarized, the peeling is represented by the white part in the bonding part, so the area of ​​the white part is taken as the peeling area.

[0122] (Joining rate) = {(initial joining area) - (peeling area)} / (initial joining area) × 100

[0123] (breakdown voltage)

[0124] like Figure 6 As shown, the metal substrate 11 was placed on the base plate 61, and the probe 62 was brought into contact with the circuit layer 13 to evaluate partial discharge. As a measuring device, a partial discharge tester manufactured by MITSUBISHI CABLE INDUSTRIES, LTD. was used. In addition, as a test atmosphere, the test was carried out in Fluorinert (trademark) FC-770 manufactured by 3M Company.

[0125] Then, the voltage was increased in steps of 0.5 kV (holding time 30 seconds), and the voltage at which breakdown occurred (voltage at which the leakage current was 10 mA or more) was defined as the breakdown voltage.

[0126] Table 1 shows the evaluation results.

[0127] [Table 1]

[0128]

[0129] In Comparative Example 1, where the kurtosis Rku of the profile curve at the bonding interface of the circuit layer was 2.70 and the kurtosis Sku of the profile surface was 2.50, the bonding rate after moisture absorption reflow was as low as 80%, and the adhesion between the circuit layer and the insulating resin layer was insufficient.

[0130] In Comparative Example 2, in which the kurtosis Rku of the profile curve at the bonding interface of the circuit layer was 10.30 and the kurtosis Sku of the profile surface was 9.40, the breakdown voltage after moisture absorption reflow was as low as 5.1 V, indicating insufficient insulation.

[0131] In Comparative Example 3 in which the overhang rate was 4.2%, the bonding rate after moisture absorption reflow was as low as 82%, and the adhesion between the circuit layer and the insulating resin layer was insufficient.

[0132] In contrast, in Examples 1 to 8 of the present invention, in which at least one of the kurtosis Rku of the contour curve and the kurtosis Sku of the contour surface at the bonding interface of the circuit layer is within the range of 2.75 to 6.00 and the overhang rate is 7% or more, the bonding rate after moisture absorption reflow is 84% ​​or more, and the circuit layer and the insulating resin layer have excellent adhesion. In addition, the breakdown voltage after moisture absorption reflow is 5.8V or more, and the insulating resin layer has excellent insulation. In addition, in Examples 1 to 8 of the present invention, at least one of the root mean square height Rq of the contour curve and the root mean square height Sq of the contour surface at the bonding interface of the circuit layer is within the range of 0.20μm to 0.90μm. In addition, in Examples 1 to 8 of the present invention, both the kurtosis Rku of the contour curve and the kurtosis Sku of the contour surface at the bonding interface of the circuit layer are within the range of 2.75 to 6.00, so the adhesion between the circuit layer and the insulating resin layer is particularly excellent.

[0133] Furthermore, in Examples 1 to 6 and 8 of the present invention, in which the root mean square height Rq of the contour curve and the root mean square height Sq of the contour surface at the bonding interface of the circuit layer are both within the range of greater than 0.20 μm and less than 0.90 μm, the bonding rate after moisture absorption reflow is greater than 85%, and the adhesion between the circuit layer and the insulating resin layer is particularly excellent.

[0134] From the above experimental results, it can be seen that according to the present example, an insulating circuit substrate (joint body) can be provided which has excellent adhesion between the insulating resin layer (insulating resin part) and the circuit layer (metal part) and excellent insulation of the insulating resin layer (insulating resin part) and can be used stably.

[0135] Explanation of symbols

[0136] 10 - insulating circuit substrate (joined body), 11 - metal substrate (metal component), 12 - insulating resin layer (insulating resin component), 13 - circuit layer (metal component), 18 - convex portion, 19 - concave portion.

Claims

1. A joined body having a structure formed by joining an insulating resin component made of insulating resin and a metal component made of metal, characterized in that: The bonding interface between the insulating resin component and the metal component is in a concave-convex shape having a convex portion and a concave portion, wherein the convex portion is formed by the metal component protruding toward the insulating resin component side, and the concave portion is formed by the metal component retreating from the insulating resin component side. At least one of the kurtosis Rku of the contour curve at the bonding interface of the metal component and the kurtosis Sku of the contour surface at the bonding interface of the metal component is within a range of 2.75 or more and 6.00 or less, The overhang rate of the metal member is 7% or more, where the overhang rate indicates a ratio of a length of a region overlapping in a lamination direction in a direction along the bonding interface.

2. The joint body according to claim 1, characterized in that: At least one of a root mean square height Rq of a contour curve at the bonding interface of the metal component and a root mean square height Sq of a contour surface at the bonding interface of the metal component is within a range of 0.20 μm to 0.90 μm.

3. An insulating circuit substrate comprising: an insulating resin layer; and a circuit layer formed by bonding a metal plate to one side of the insulating resin layer, characterized in that: The bonding interface between the insulating resin layer and the circuit layer is in a concave-convex shape with convex parts and concave parts, wherein the convex part is formed by the circuit layer protruding toward the insulating resin layer side, and the concave part is formed by the circuit layer retreating from the insulating resin layer side. At least one of the kurtosis Rku of the contour curve at the bonding interface of the circuit layer and the kurtosis Sku of the contour surface at the bonding interface of the circuit layer is within a range of 2.75 or more and 6.00 or less, The overhang rate of the circuit layer is 7% or more, where the overhang rate indicates a length ratio of a region overlapping in a stacking direction in a direction along the bonding interface.

4. The insulating circuit substrate according to claim 3, characterized in that: At least one of a root mean square height Rq of a contour curve at the bonding interface of the circuit layer and a root mean square height Sq of a contour surface at the bonding interface of the circuit layer is within a range of 0.20 μm to 0.90 μm.

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