A voltage-regulated communication circuit and its system

Abstract

This invention discloses a voltage-regulated communication circuit, comprising: an output circuit for outputting a stable voltage to the negative input terminal of a comparator circuit; a comparator circuit for outputting a wake-up signal to an FPGA system, with a positive input terminal corresponding to the negative input terminal for receiving the comparison voltage; and a voltage-regulating circuit for receiving an identification signal sent by the FPGA system and receiving an external input voltage, and performing voltage reduction and regulation based on the identification signal to obtain a safe voltage. Through this method, this invention can wake up the FPGA system through an I / O port and realize communication between the detection module for input detection voltage and the FPGA system, while ensuring the stability of the voltage at the FPGA's I / O port.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of voltage regulator circuits, and in particular to a voltage regulator communication circuit and system thereof. Background Technology

[0002] With the rapid development of the internet industry, more and more devices are being connected to the internet, leading to an explosive growth in data volume. However, not all devices can connect to the internet for communication; most devices are still at the stage of being activated and controlled by mechanical circuits. Furthermore, existing communication networks are insufficient to support such large volumes of data. Therefore, researching communication methods with higher transmission rates is extremely important.

[0003] Due to its advantages such as large communication capacity, long transmission distance, low signal interference, and excellent transmission quality, optical fiber plays an increasingly important role in the field of communications. As industrial systems demand ever-increasing hardware speeds, the requirements for data communication rates between hardware components are also rising. Therefore, optical fiber is widely used for data exchange between hardware devices.

[0004] FPGA, or Field Programmable Gate Array, is a further development based on programmable devices such as PAL, GAL, and CPLD. It emerged as a semi-custom circuit in the field of Application-Specific Integrated Circuits (ASICs), offering low latency and high connectivity. It addresses the shortcomings of custom circuits while overcoming the limited gate count of traditional programmable devices. Therefore, FPGA has become one of the best platforms for achieving high-speed data transmission. Summary of the Invention

[0005] The main technical problem solved by the embodiments of the present invention is to provide a voltage-stabilized communication circuit and system that can wake up the FPGA system through an IO port and realize communication between the module for input detection voltage and the FPGA system, while ensuring the stability of the voltage of the FPGA's IO.

[0006] To solve the above-mentioned technical problems, one technical solution adopted in this embodiment of the invention is: providing a voltage-regulated communication circuit, comprising: an output circuit for outputting a stable voltage to the negative input terminal of the comparator circuit; a comparator circuit for outputting a wake-up signal to the FPGA system, wherein a positive input terminal corresponding to the negative input terminal is used to receive the comparison voltage; and a voltage-regulating circuit for receiving an identification signal and a detection voltage sent by the FPGA system, and for stepping down and regulating the detection voltage according to the identification signal to obtain a safe voltage.

[0007] In some embodiments, a voltage divider circuit is further included, which is used to receive the detected voltage and output the comparison voltage.

[0008] In some embodiments, the output circuit includes a power management chip, a second resistor, a fourth resistor, a fifth resistor, a first capacitor, and a third capacitor. The output terminal of the power management chip is connected to a first terminal of the third capacitor and a first terminal of the second resistor, the first terminal of the second resistor being used to receive a second input voltage. The noise reduction terminal of the power management chip is connected to the first terminal of the first capacitor. The second terminal of the first capacitor is connected to a second terminal of the third capacitor and a second terminal of the fourth resistor, the first terminal of the first capacitor being grounded. The second terminal of the second resistor is connected to a first terminal of the fourth resistor and a first terminal of the fifth resistor, the second terminal of the fifth resistor being used to output a stable voltage.

[0009] In some embodiments, the output circuit further includes a first resistor, a third resistor, and a second capacitor, wherein the output terminal of the power management chip is connected to a first terminal of the first resistor and a first terminal of the second capacitor; the feedback terminal of the power management chip is connected to a second terminal of the first resistor, a first terminal of the second capacitor, and a first terminal of the third resistor; and the second terminal of the third resistor is connected to a second terminal of the first capacitor.

[0010] In some embodiments, the output circuit further includes a fourth capacitor and a fifth capacitor, wherein the input terminal and the enable terminal of the power management chip are both connected to the first terminal of the fourth capacitor and the first terminal of the fifth capacitor, the first terminal of the fourth capacitor being used to receive a first input voltage; the ground terminal of the power management chip is connected to the second terminal of the fourth capacitor and the second terminal of the fifth capacitor, the second terminal of the fourth capacitor being grounded.

[0011] In some embodiments, the comparison circuit includes a comparator and a sixth capacitor, wherein the output terminal of the comparator is used to output a wake-up signal; the negative input terminal of the comparator is used to receive the stable voltage, and the positive input terminal corresponding to the negative input terminal is used to receive the comparison voltage; the voltage input terminal of the comparator is connected to the first terminal of the sixth capacitor, the second terminal of the sixth capacitor is grounded, and the first terminal of the sixth capacitor is used to receive the first input voltage.

[0012] In some embodiments, the voltage regulator circuit includes a voltage regulator chip, a sixth resistor, a tenth resistor, and an eleventh resistor, wherein the reference input terminal of the voltage regulator chip is connected to a first terminal of the sixth resistor and a second terminal of the eleventh resistor, and the second terminal of the sixth resistor is grounded; the first terminal of the eleventh resistor is connected to the second terminal of the tenth resistor and the cathode terminal of the voltage regulator chip, and the cathode terminal of the voltage regulator chip is used to receive the identification signal; the first terminal of the tenth resistor is used to receive a reference voltage.

[0013] In some embodiments, the voltage regulator circuit further includes a twelfth resistor and a seventh capacitor, wherein a first terminal of the seventh capacitor is connected to the cathode of the voltage regulator chip, and a second terminal of the seventh capacitor is grounded; a second terminal of the twelfth resistor is connected to the cathode of the voltage regulator chip, and a first terminal of the twelfth resistor is used to receive the detected voltage.

[0014] In some embodiments, the voltage divider circuit includes a seventh resistor, an eighth resistor, and a ninth resistor, wherein the second terminal of the seventh resistor is connected to the first terminal of the eighth resistor and the first terminal of the ninth resistor, the first terminal of the seventh resistor is used to receive the detection voltage; the second terminal of the eighth resistor is grounded, and the second terminal of the ninth resistor is used to output the comparison voltage.

[0015] To solve the above-mentioned technical problems, another technical solution adopted in the embodiments of the present invention is: to provide a voltage-regulated communication system, including: a detection power supply for inputting a detection voltage to a voltage-regulated communication circuit; an FPGA system for receiving a wake-up signal sent by the voltage-regulated communication circuit and sending an identification signal to the voltage-regulated communication circuit; and the voltage-regulated communication circuit as described above.

[0016] The beneficial effects of the embodiments of the present invention are as follows: Unlike the prior art, the embodiments of the present invention can wake up the FPGA system through an IO port and realize communication between the module for input detection voltage and the FPGA system, and ensure the stability of the voltage of the FPGA's IO. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a voltage-regulated communication circuit provided in an embodiment of the present invention;

[0018] Figure 2 This is a hardware structure diagram of the first output circuit provided in the embodiments of the present invention;

[0019] Figure 3 This is a hardware schematic diagram of the second output circuit provided in an embodiment of the present invention;

[0020] Figure 4 This is a hardware schematic diagram of the third output circuit provided in the embodiments of the present invention;

[0021] Figure 5 This is a hardware schematic diagram of a comparison circuit provided in an embodiment of the present invention;

[0022] Figure 6 This is a hardware schematic diagram of the first voltage regulator circuit provided in the embodiments of the present invention;

[0023] Figure 7 This is a hardware schematic diagram of the second voltage regulator circuit provided in an embodiment of the present invention;

[0024] Figure 8 This is a hardware schematic diagram of a voltage divider circuit provided in an embodiment of the present invention;

[0025] Figure 9 This is a hardware schematic diagram of a voltage-regulated communication circuit provided in an embodiment of the present invention;

[0026] Figure 10 This is a hardware schematic diagram of a pressure communication system provided by an embodiment of the present invention. Detailed Implementation

[0027] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0029] To enable communication between the detection module (which detects the input voltage) and the FPGA system via a single I / O port, and to ensure the stability of the FPGA's I / O voltage, this invention provides a voltage-regulated communication circuit, the schematic of which is shown below. Figure 1 As shown:

[0030] The voltage-regulated communication circuit includes an output circuit 100, a voltage divider circuit 200, a comparator circuit 300, and a voltage regulator circuit 400, wherein...

[0031] The output terminal of the output circuit 100 is connected to the negative input terminal of the comparator circuit 300 to output a stable voltage to the negative input terminal of the comparator circuit 300.

[0032] The output of the voltage divider circuit 200 is connected to the positive input of the comparator circuit 300 to receive the detection voltage input from the external detection module and output a comparison voltage to the positive input of the comparator circuit 300.

[0033] The output of the comparator circuit 300 is connected to an external FPGA system to output a wake-up signal to the FPGA system, and the positive input terminal corresponding to the negative input terminal is used to receive the comparison voltage.

[0034] The input of the voltage regulator circuit 400 is connected to the output of the FPGA system to receive the identification signal sent by the FPGA system, and to step down and regulate the detection voltage according to the identification signal to obtain a safe voltage.

[0035] In some embodiments, when the detected voltage is greater than the stable voltage, the comparator circuit 300 outputs a high-level wake-up signal to the FPGA system. Upon receiving the wake-up signal, the FPGA system sends an identification signal to the voltage regulator circuit 400, causing the voltage regulator circuit 400 to step down and regulate the detected voltage to obtain a safe voltage.

[0036] In some embodiments, the hardware structure diagram of the output circuit 100 is as follows: Figure 2 As shown, the output circuit 100 includes: a power management chip U1, a second resistor R2, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, and a third capacitor C3, wherein...

[0037] The output terminal of the power management chip U1 is connected to the first terminal of the third capacitor C3 and the first terminal of the second resistor R2. The first terminal of the second resistor R2 is used to receive the second input voltage.

[0038] The noise reduction terminal of the power management chip U1 is connected to the first terminal of the first capacitor C1; the second terminal of the first capacitor C1 is connected to the second terminal of the third capacitor C3 and the second terminal of the fourth resistor R4, and the first terminal of the first capacitor C1 is grounded; the second terminal of the second resistor R2 is connected to the first terminal of the fourth resistor R4 and the first terminal of the fifth resistor R5, and the second terminal of the fifth resistor R5 is used to output a stable voltage INA-.

[0039] Preferably, the power management chip U1 is a TPS79301. It should be noted that those skilled in the art can select other power management chips according to actual needs to achieve the beneficial effects of this invention, and the resulting embodiments are also within the scope of protection of this application.

[0040] Preferably, the second input voltage is 4.1V. It should be noted that those skilled in the art can also select different voltage values ​​according to actual needs to achieve the beneficial effects of the present invention, and the embodiments obtained therefrom are also within the protection scope of this application.

[0041] Preferably, the second resistor R2 has a resistance of 10 kΩ, the fourth resistor R4 has a resistance of 10 kΩ, the fifth resistor R5 has a resistance of 1 kΩ, the first capacitor C1 has a capacitance of 0.01 μF, and the third capacitor C3 has a capacitance of 2.2 μF. Those skilled in the art can also select resistors and capacitors with other resistance values ​​and capacitance values ​​according to actual needs to achieve the beneficial effects of the present invention, and the resulting embodiments are also within the scope of protection of this application.

[0042] In other embodiments, the hardware structure diagram of the output circuit 100 is as follows: Figure 3 As shown, the output circuit 100 includes: a power management chip U1, a first resistor R1, a third resistor R3, a second capacitor C2, a second resistor R2, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, and a third capacitor C3, wherein...

[0043] The power management chip U1, the second resistor R2, the fourth resistor R4, the fifth resistor R5, the first capacitor C1, and the third capacitor C3, wherein,

[0044] The output terminal of the power management chip U1 is connected to the first terminal of the third capacitor C3, the first terminal of the second resistor R2, the first terminal of the first resistor R1, and the first terminal of the second capacitor C2. The first terminal of the second resistor R2 is used to receive the second input voltage.

[0045] The feedback terminal of the power management chip U1 is connected to the second terminal of the first resistor R1, the second terminal of the second capacitor C2, and the first terminal of the third resistor R3. The second terminal of the third resistor R3 is grounded.

[0046] The noise reduction terminal of the power management chip U1 is connected to the first terminal of the first capacitor C1; the second terminal of the first capacitor C1 is connected to the second terminal of the third capacitor C3 and the second terminal of the fourth resistor R4, and the first terminal of the first capacitor C1 is grounded; the second terminal of the second resistor R2 is connected to the first terminal of the fourth resistor R4 and the first terminal of the fifth resistor R5, and the second terminal of the fifth resistor R5 is used to output a stable voltage INA-.

[0047] Preferably, the power management chip U1 is a TPS79301. It should be noted that those skilled in the art can select other power management chips according to actual needs to achieve the beneficial effects of this invention, and the resulting embodiments are also within the scope of protection of this application.

[0048] Preferably, the second input voltage is 4.1V. It should be noted that those skilled in the art can also select different voltage values ​​according to actual needs to achieve the beneficial effects of the present invention, and the embodiments obtained therefrom are also within the protection scope of this application.

[0049] Preferably, the resistance of the first resistor R1 is 36 kΩ, the resistance of the second resistor R2 is 10 kΩ, the resistance of the third resistor R3 is 15 kΩ, the resistance of the fourth resistor R4 is 10 kΩ, the resistance of the fifth resistor R5 is 1 kΩ, the capacitance of the first capacitor C1 is 0.01 μF, the capacitance of the second capacitor C2 is 15 pF, and the capacitance of the third capacitor C3 is 2.2 μF. Those skilled in the art can also select resistors and capacitors with other resistance values ​​and capacitance values ​​according to actual needs to achieve the beneficial effects of the present invention, and the embodiments obtained thereby are also within the scope of protection of this application.

[0050] In other embodiments, the hardware structure diagram of the output circuit 100 is as follows: Figure 4 As shown, the output circuit 100 includes: a power management chip U1, a first resistor R1, a third resistor R3, a second capacitor C2, a second resistor R2, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, a third capacitor C3, a fourth capacitor C4, and a fifth capacitor C5, wherein...

[0051] The power management chip U1, the second resistor R2, the fourth resistor R4, the fifth resistor R5, the first capacitor C1, and the third capacitor C3, wherein,

[0052] The output terminal of the power management chip U1 is connected to the first terminal of the third capacitor C3, the first terminal of the second resistor R2, the first terminal of the first resistor R1, and the first terminal of the second capacitor C2. The first terminal of the second resistor R2 is used to receive the second input voltage.

[0053] The feedback terminal of the power management chip U1 is connected to the second terminal of the first resistor R1, the second terminal of the second capacitor C2, and the first terminal of the third resistor R3. The second terminal of the third resistor R3 is grounded.

[0054] The noise reduction terminal of the power management chip U1 is connected to the first terminal of the first capacitor C1; the second terminal of the first capacitor C1 is connected to the second terminal of the third capacitor C3 and the second terminal of the fourth resistor R4, and the first terminal of the first capacitor C1 is grounded; the second terminal of the second resistor R2 is connected to the first terminal of the fourth resistor R4 and the first terminal of the fifth resistor R5, and the second terminal of the fifth resistor R5 is used to output a stable voltage INA-.

[0055] The input and enable terminals of the power management chip U1 are both connected to the first terminal of the fourth capacitor C4 and the first terminal of the fifth capacitor C5. The first terminal of the fourth capacitor C4 is used to receive the first input voltage.

[0056] The ground terminal of the power management chip is connected to the second terminal of the fourth capacitor C4 and the second terminal of the fifth capacitor C5, and the second terminal of the fourth capacitor C4 is grounded.

[0057] Preferably, the power management chip U1 is a TPS79301. It should be noted that those skilled in the art can select other power management chips according to actual needs to achieve the beneficial effects of this invention, and the resulting embodiments are also within the scope of protection of this application.

[0058] Preferably, the first input voltage is 5V. It should be noted that those skilled in the art can also select different voltage values ​​according to actual needs to achieve the beneficial effects of the present invention, and the embodiments obtained therefrom are also within the protection scope of this application.

[0059] Preferably, the second input voltage is 4.1V. It should be noted that those skilled in the art can also select different voltage values ​​according to actual needs to achieve the beneficial effects of the present invention, and the embodiments obtained therefrom are also within the protection scope of this application.

[0060] Preferably, the resistance of the first resistor R1 is 36 kΩ, the resistance of the second resistor R2 is 10 kΩ, the resistance of the third resistor R3 is 15 kΩ, the resistance of the fourth resistor R4 is 10 kΩ, and the resistance of the fifth resistor R5 is 1 kΩ. The capacitance of the first capacitor C1 is 0.01 μF, the capacitance of the second capacitor C2 is 15 pF, the capacitance of the third capacitor C3 is 2.2 μF, the capacitance of the fourth capacitor C4 is 0.1 μF, and the capacitance of the fifth capacitor C5 is 10 μF. Those skilled in the art can also select resistors and capacitors with other resistance values ​​and capacitance values ​​according to actual needs to achieve the beneficial effects of the present invention, and the embodiments obtained thereby are also within the scope of protection of this application.

[0061] In some embodiments, the hardware structure diagram of the comparator circuit 300 is as follows: Figure 5 As shown, the output circuit 100 includes a comparator U2 and a sixth capacitor C6, wherein,

[0062] The output of comparator U2 is used to output the wake-up signal OUT_FPGA_A.

[0063] The negative input terminal of comparator U2 is used to receive the stable voltage INA-, and the positive input terminal corresponding to the negative input terminal is used to receive the comparison voltage INA+.

[0064] The voltage input terminal of comparator U2 is connected to the first terminal of the sixth capacitor C6, the second terminal of the sixth capacitor C6 is grounded, and the first terminal of the sixth capacitor C6 is used to receive the first input voltage.

[0065] In some embodiments, the comparator U2 is of models including LM393 / NE5532 / TLV272. It should be noted that those skilled in the art can select other comparator models according to actual needs to achieve the beneficial effects of the present invention, and the resulting embodiments are also within the scope of protection of this application.

[0066] Preferably, the capacitance of the sixth capacitor C6 is 0.1uF. Those skilled in the art can also select capacitors with other capacitance values ​​according to actual needs to achieve the beneficial effects of the present invention, and the resulting embodiments are also within the scope of protection of this application.

[0067] In some embodiments, the hardware structure diagram of the voltage regulator circuit 400 is as follows: Figure 6 As shown, the voltage regulator circuit 400 includes a voltage regulator chip U3, a sixth resistor R6, a tenth resistor R10, and an eleventh resistor R11, wherein...

[0068] The reference input terminal of the voltage regulator chip U3 is connected to the first terminal of the sixth resistor R6 and the second terminal of the eleventh resistor R11, and the second terminal of the sixth resistor R6 is grounded.

[0069] The first end of the eleventh resistor R11 is connected to the second end of the tenth resistor R10 and the cathode of the voltage regulator chip U3. The cathode of the voltage regulator chip U3 is used to receive the identification signal VOUT_FPGA1.

[0070] The first terminal of the tenth resistor R10 is used to receive the reference voltage.

[0071] Preferably, the voltage regulator chip U3 is model TL431ADCR. It should be noted that those skilled in the art can select other models of voltage regulator chips according to actual needs to achieve the beneficial effects of the present invention, and the resulting embodiments are also within the scope of protection of this application.

[0072] Preferably, the reference voltage is 3.3V. It should be noted that those skilled in the art can also select different reference voltage values ​​according to actual needs to achieve the beneficial effects of the present invention, and the embodiments obtained therefrom are also within the protection scope of this application.

[0073] Preferably, the resistance of the sixth resistor R6 is 62 kΩ, the resistance of the tenth resistor R10 is 510 Ω, and the resistance of the eleventh resistor R11 is 18 kΩ. Those skilled in the art can also select resistors with other resistance values ​​according to actual needs to achieve the beneficial effects of the present invention, and the resulting embodiments are also within the scope of protection of this application.

[0074] In other embodiments, the hardware structure diagram of the voltage regulator circuit 400 is as follows: Figure 7 As shown, the voltage regulator circuit 400 includes a voltage regulator chip U3, a sixth resistor R6, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, and a seventh capacitor C7.

[0075] The reference input terminal of the voltage regulator chip U3 is connected to the first terminal of the sixth resistor R6 and the second terminal of the eleventh resistor R11, and the second terminal of the sixth resistor R6 is grounded.

[0076] The first end of the eleventh resistor R11 is connected to the second end of the tenth resistor R10 and the cathode of the voltage regulator chip U3. The cathode of the voltage regulator chip U3 is used to receive the identification signal VOUT_FPGA1.

[0077] The first terminal of the tenth resistor R10 is used to receive the reference voltage.

[0078] The first terminal of the seventh capacitor C7 is connected to the cathode of the voltage regulator chip U3, and the second terminal of the seventh capacitor C7 is grounded.

[0079] The second terminal of the twelfth resistor R12 is connected to the cathode of the voltage regulator chip U3, and the first terminal of the twelfth resistor R12 is used to receive the detection voltage VUSB1.

[0080] In some embodiments, the detection voltage VUSB1 is 5V.

[0081] Preferably, the voltage regulator chip U3 is model TL431ADCR. It should be noted that those skilled in the art can select other models of voltage regulator chips according to actual needs to achieve the beneficial effects of the present invention, and the resulting embodiments are also within the scope of protection of this application.

[0082] Preferably, the reference voltage is 3.3V. It should be noted that those skilled in the art can also select different reference voltage values ​​according to actual needs to achieve the beneficial effects of the present invention, and the embodiments obtained therefrom are also within the protection scope of this application.

[0083] Preferably, the seventh capacitor has a capacitance of 0, the sixth resistor R6 has a resistance of 62 kΩ, the tenth resistor R10 has a resistance of 510 Ω, the eleventh resistor R11 has a resistance of 18 kΩ, and the twelfth resistor R12 has a resistance of 51 Ω. Those skilled in the art can also select resistors with other resistance values ​​according to actual needs to achieve the beneficial effects of the present invention, and the resulting embodiments are also within the scope of protection of this application.

[0084] In some embodiments, the hardware structure diagram of the voltage divider circuit 200 is as follows: Figure 8 As shown, the voltage divider circuit 200 includes a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9, wherein...

[0085] The second end of the seventh resistor R7 is connected to the first end of the eighth resistor R8 and the first end of the ninth resistor R9. The first end of the seventh resistor R7 is used to receive the detection voltage VUSB1.

[0086] The second terminal of the eighth resistor R8 is grounded, and the second terminal of the ninth resistor R9 is used to output the comparison voltage INA+.

[0087] In some embodiments, the detection voltage VUSB1 is 5V.

[0088] Preferably, the resistance of the seventh resistor R7 is 10 kΩ, the resistance of the eighth resistor R8 is 10 kΩ, and the resistance of the ninth resistor R9 is 1 kΩ. Those skilled in the art can also select resistors with other resistance values ​​according to actual needs to achieve the beneficial effects of the present invention, and the resulting embodiments are also within the scope of protection of this application.

[0089] In some embodiments, the hardware structure diagram of the voltage-regulated communication circuit is as follows: Figure 9As shown, the voltage-regulated communication circuit includes a power management chip U1, a first resistor R1, a third resistor R3, a second capacitor C2, a second resistor R2, a fourth resistor R4, a fifth resistor R5, a comparator U2, a sixth capacitor C6, a voltage regulator chip U3, a sixth resistor R6, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a seventh capacitor C7, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9.

[0090] The output terminal of the power management chip U1 is connected to the first terminal of the third capacitor C3, the first terminal of the second resistor R2, the first terminal of the first resistor R1, and the first terminal of the second capacitor C2. The first terminal of the second resistor R2 is used to receive the second input voltage.

[0091] The feedback terminal of the power management chip U1 is connected to the second terminal of the first resistor R1, the second terminal of the second capacitor C2, and the first terminal of the third resistor R3. The second terminal of the third resistor R3 is grounded.

[0092] The noise reduction terminal of the power management chip U1 is connected to the first terminal of the first capacitor C1; the second terminal of the first capacitor C1 is connected to the second terminal of the third capacitor C3 and the second terminal of the fourth resistor R4, and the first terminal of the first capacitor C1 is grounded; the second terminal of the second resistor R2 is connected to the first terminal of the fourth resistor R4 and the first terminal of the fifth resistor R5, and the second terminal of the fifth resistor R5 is used to output a stable voltage INA-.

[0093] The input and enable terminals of the power management chip U1 are both connected to the first terminal of the fourth capacitor C4 and the first terminal of the fifth capacitor C5. The first terminal of the fourth capacitor C4 is used to receive the first input voltage.

[0094] The ground terminal of the power management chip is connected to the second terminal of the fourth capacitor C4 and the second terminal of the fifth capacitor C5, and the second terminal of the fourth capacitor C4 is grounded.

[0095] The output of comparator U2 is used to output the wake-up signal OUT_FPGA_A.

[0096] The negative input terminal of comparator U2 is used to receive the stable voltage INA-, and the positive input terminal corresponding to the negative input terminal is used to receive the comparison voltage INA+.

[0097] The voltage input terminal of comparator U2 is connected to the first terminal of the sixth capacitor C6, the second terminal of the sixth capacitor C6 is grounded, and the first terminal of the sixth capacitor C6 is used to receive the first input voltage.

[0098] The reference input terminal of the voltage regulator chip U3 is connected to the first terminal of the sixth resistor R6 and the second terminal of the eleventh resistor R11, and the second terminal of the sixth resistor R6 is grounded.

[0099] The first end of the eleventh resistor R11 is connected to the second end of the tenth resistor R10 and the cathode of the voltage regulator chip U3. The cathode of the voltage regulator chip U3 is used to receive the identification signal VOUT_FPGA1.

[0100] The first terminal of the tenth resistor R10 is used to receive the reference voltage.

[0101] The first terminal of the seventh capacitor C7 is connected to the cathode of the voltage regulator chip U3, and the second terminal of the seventh capacitor C7 is grounded.

[0102] The second terminal of the twelfth resistor R12 is connected to the cathode of the voltage regulator chip U3, and the first terminal of the twelfth resistor R12 is used to receive the detection voltage VUSB1.

[0103] The second end of the seventh resistor R7 is connected to the first end of the eighth resistor R8 and the first end of the ninth resistor R9. The first end of the seventh resistor R7 is used to receive the detection voltage VUSB1.

[0104] The second terminal of the eighth resistor R8 is grounded, and the second terminal of the ninth resistor R9 is used to output the comparison voltage INA+.

[0105] In some embodiments, the detection voltage VUSB1 is 5V.

[0106] Preferably, the power management chip U1 is a TPS79301. It should be noted that those skilled in the art can select other power management chips according to actual needs to achieve the beneficial effects of this invention, and the resulting embodiments are also within the scope of protection of this application.

[0107] In some embodiments, the comparator U2 is of models including LM393 / NE5532 / TLV272. It should be noted that those skilled in the art can select other comparator models according to actual needs to achieve the beneficial effects of the present invention, and the resulting embodiments are also within the scope of protection of this application.

[0108] Preferably, the voltage regulator chip U3 is model TL431ADCR. It should be noted that those skilled in the art can select other models of voltage regulator chips according to actual needs to achieve the beneficial effects of the present invention, and the resulting embodiments are also within the scope of protection of this application.

[0109] Preferably, the first input voltage is 5V. It should be noted that those skilled in the art can also select different voltage values ​​according to actual needs to achieve the beneficial effects of the present invention, and the embodiments obtained therefrom are also within the protection scope of this application.

[0110] Preferably, the second input voltage is 4.1V. It should be noted that those skilled in the art can also select different voltage values ​​according to actual needs to achieve the beneficial effects of the present invention, and the embodiments obtained therefrom are also within the protection scope of this application.

[0111] Preferably, the reference voltage is 3.3V. It should be noted that those skilled in the art can also select different reference voltage values ​​according to actual needs to achieve the beneficial effects of the present invention, and the embodiments obtained therefrom are also within the protection scope of this application.

[0112] Preferably, the resistance of the first resistor R1 is 36 kΩ, the resistance of the second resistor R2 is 10 kΩ, the resistance of the third resistor R3 is 15 kΩ, the resistance of the fourth resistor R4 is 10 kΩ, the resistance of the fifth resistor R5 is 1 kΩ, the capacitance of the first capacitor C1 is 0.01 uF, the capacitance of the second capacitor C2 is 15 pF, the capacitance of the third capacitor C3 is 2.2 uF, the capacitance of the fourth capacitor C4 is 0.1 uF, the capacitance of the fifth capacitor C5 is 10 uF, the capacitance of the sixth capacitor C6 is 0.1 uF, the capacitance of the seventh capacitor is 0, the resistance of the sixth resistor R6 is 62 kΩ, the resistance of the tenth resistor R10 is 510 Ω, the resistance of the eleventh resistor R11 is 18 kΩ, the resistance of the twelfth resistor R12 is 51 Ω, the resistance of the seventh resistor R7 is 10 kΩ, the resistance of the eighth resistor R8 is 10 kΩ, and the resistance of the ninth resistor R9 is 1 kΩ. Those skilled in the art can also select resistors with other resistance values ​​and capacitors with other capacitance values ​​according to actual needs to achieve the beneficial effects of the present invention, and the resulting embodiments are also within the protection scope of this application.

[0113] Unlike existing technologies, the embodiments of the present invention can wake up the FPGA system through an IO port and realize communication between the module for input detection voltage and the FPGA system, while ensuring the stability of the voltage of the FPGA's IO.

[0114] Based on the above-described voltage-regulated communication circuit, this invention also provides a voltage-regulated communication system, the schematic diagram of which is shown below. Figure 10 The system includes a detection module 10, an FPGA system 20, and the aforementioned voltage-regulated communication circuit 30.

[0115] The detection module 10 inputs the detection voltage VUSB1 to the voltage regulator communication circuit 30.

[0116] The FPGA system 20 is used to receive the wake-up signal OUT_FPGA_A sent by the voltage regulator communication circuit 20 and send the identification signal VOUT_FPGA1 to the voltage regulator communication circuit 20, so that the voltage regulator communication circuit 20 steps down and regulates the detection voltage VUSB1.

[0117] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A voltage-regulated communication circuit, characterized in that, include: The output circuit is used to output a stable voltage to the negative input terminal of the comparator circuit. The comparator circuit is used to output a wake-up signal to the FPGA system, and the positive input terminal corresponding to the negative input terminal is used to receive the comparison voltage. A voltage regulator circuit is used to receive the identification signal and detection voltage sent by the FPGA system, and to step down and regulate the detection voltage according to the identification signal to obtain a safe voltage. A voltage divider circuit is used to receive the detected voltage and output the comparison voltage; The voltage regulator circuit includes a voltage regulator chip, a sixth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, and a seventh capacitor. The reference input terminal of the voltage regulator chip is connected to the first terminal of the sixth resistor and the second terminal of the eleventh resistor, and the second terminal of the sixth resistor is grounded; The first end of the eleventh resistor is connected to the second end of the tenth resistor and the cathode of the voltage regulator chip, and the cathode of the voltage regulator chip is used to receive the identification signal; The first terminal of the tenth resistor is used to receive a reference voltage; The first terminal of the seventh capacitor is connected to the cathode of the voltage regulator chip, and the second terminal of the seventh capacitor is grounded. The second end of the twelfth resistor is connected to the cathode of the voltage regulator chip, and the first end of the twelfth resistor is used to receive the detection voltage.

2. The voltage-regulated communication circuit according to claim 1, characterized in that, The output circuit includes a power management chip, a second resistor, a fourth resistor, a fifth resistor, a first capacitor, and a third capacitor, wherein... The output terminal of the power management chip is connected to the first terminal of the third capacitor and the first terminal of the second resistor, and the first terminal of the second resistor is used to receive the second input voltage. The noise reduction terminal of the power management chip is connected to the first terminal of the first capacitor; The second terminal of the first capacitor is connected to the second terminal of the third capacitor and the second terminal of the fourth resistor, and the first terminal of the first capacitor is grounded. The second end of the second resistor is connected to the first end of the fourth resistor and the first end of the fifth resistor, and the second end of the fifth resistor is used to output a stable voltage.

3. The voltage-regulated communication circuit according to claim 2, characterized in that, The output circuit further includes a first resistor, a third resistor, and a second capacitor, wherein, The output terminal of the power management chip is connected to the first terminal of the first resistor and the first terminal of the second capacitor; The feedback terminal of the power management chip is connected to the second terminal of the first resistor, the first terminal of the second capacitor, and the first terminal of the third resistor; The second end of the third resistor is connected to the second end of the first capacitor.

4. The voltage-regulated communication circuit according to claim 3, characterized in that, The output circuit also includes a fourth capacitor and a fifth capacitor, wherein, The input terminal and the enable terminal of the power management chip are both connected to the first terminal of the fourth capacitor and the first terminal of the fifth capacitor. The first terminal of the fourth capacitor is used to receive the first input voltage. The ground terminal of the power management chip is connected to the second terminal of the fourth capacitor and the second terminal of the fifth capacitor, and the second terminal of the fourth capacitor is grounded.

5. The voltage-regulated communication circuit according to claim 4, characterized in that, The comparison circuit includes a comparator and a sixth capacitor, wherein, The output of the comparator is used to output a wake-up signal; The negative input terminal of the comparator is used to receive the stable voltage, and the positive input terminal corresponding to the negative input terminal is used to receive the comparison voltage; The voltage input terminal of the comparator is connected to the first terminal of the sixth capacitor, the second terminal of the sixth capacitor is grounded, and the first terminal of the sixth capacitor is used to receive the first input voltage.

6. The voltage-regulated communication circuit according to claim 1, characterized in that, The voltage divider circuit includes a seventh resistor, an eighth resistor, and a ninth resistor, wherein, The second end of the seventh resistor is connected to the first end of the eighth resistor and the first end of the ninth resistor, and the first end of the seventh resistor is used to receive the detection voltage; The second terminal of the eighth resistor is grounded, and the second terminal of the ninth resistor is used to output the comparison voltage.

7. A voltage-regulated communication system, characterized in that, include: The detection module is used to input the detection voltage to the voltage regulation communication circuit; The FPGA system is used to receive the wake-up signal sent by the voltage-regulated communication circuit and to send an identification signal to the voltage-regulated communication circuit. And the voltage-regulated communication circuit as described in any one of claims 1-6.

Images