A process migration method, a computing device and a readable storage medium

Abstract

The application discloses a process migration method, which is executed in a computing device and comprises the following steps: when a first process wakes up a second process, it is determined whether a CPU where the first process is located is in an idle state, the first process is a process for executing a wake-up flow, and the second process is a process woken up by the first process; if the CPU where the first process is located is not in the idle state, the second process is migrated into a target CPU of the computing device based on affinity between the first process and the second process. The process migration method improves the performance of program running.

Description

[0001] This application is a divisional application of the invention patent application No. 2022103365346 filed on April 1, 2022. Technical Field

[0002] This invention relates to the field of computer technology, and in particular to a process migration method, a computing device, and a readable storage medium. Background Technology

[0003] When two processes share variables, memory, and instruction segments, and frequently compete for the same lock, then these two processes exhibit process affinity. The shared content refers to their common resources. For processes whose common resources are memory, variables, or instruction segments, if they run on the same CPU, they can share the CPU's private cache, requiring only one load. If they run on different CPUs, the cache needs to be loaded an additional time. Furthermore, after one CPU modifies a shared variable or memory, the other CPU needs to synchronize the cache state via the bus, incurring a significant cost.

[0004] In existing process migration methods, the kernel prioritizes CPUs with lower loads and migrates the wakee process to one of these CPUs. This prevents the wakeer and wakee processes, which have affinity, from running on the same CPU, resulting in low efficiency. Furthermore, after migrating the wakee process to the CPU where the wakeer process resides, the existing solution immediately migrates the wakeer and wakee processes to different CPUs during load balancing, leading to a significant performance drop.

[0005] Therefore, a process migration method is needed to solve the problems existing in the current technical solutions. Summary of the Invention

[0006] Therefore, the present invention provides a process migration method, system, computing device, and readable storage medium to solve or at least alleviate the problems mentioned above.

[0007] According to one aspect of the present invention, a process migration method is provided, which is executed in a computing device. The method includes: when a first process wakes up a second process, determining whether the CPU where the first process is located is in an idle state, wherein the first process is the process executing the wake-up process and the second process is the process woken up by the first process; if the CPU where the first process is located is not in an idle state, then migrating the second process to a target CPU of the computing device based on the affinity between the first process and the second process.

[0008] Optionally, in the process migration method according to the present invention, the step of migrating the second process to the target CPU based on the affinity between the first process and the second process includes: determining whether the first process and the second process have affinity; if the first process and the second process have affinity, determining whether the number of processes in the CPU where the first process is located is less than or equal to 1; if the number of processes in the CPU where the first process is located is less than or equal to 1, migrating the second process to the CPU where the first process is located; otherwise, migrating the second process to the target CPU based on whether the CPU where the second process was last run shares the last-level cache with the CPU where the first process is located.

[0009] Optionally, in the process migration method according to the present invention, after the step of determining whether the first process and the second process have affinity, the method further includes: if the first process and the second process do not have affinity, then based on whether the CPU where the second process was last run shares the last-level cache with the CPU where the first process is run, the second process is migrated to the target CPU.

[0010] Optionally, in the process migration method according to the present invention, the step of migrating the second process to the target CPU based on whether the CPU where the second process last ran shares the last level cache with the CPU where the first process ran includes: determining whether the CPU where the second process last ran shares the last level cache with the CPU where the first process ran; if so, migrating the second process to the target CPU based on whether the CPU where the second process last ran is in an idle state; otherwise, traversing the scheduling domain of the computing device from bottom to top, selecting the CPU with the least load as the target CPU, and migrating the second process to the target CPU.

[0011] Optionally, in the process migration method according to the present invention, the step of migrating the second process to the target CPU based on whether the CPU where the second process was last executed is in an idle state includes: determining whether the CPU where the second process was last executed is in an idle state; if so, migrating the second process to the CPU where it was last executed; otherwise, determining whether there is an idle CPU in the domain where the CPU where the second process was last executed and the CPU where the first process is executed share the last-level cache; if so, selecting an idle CPU as the target CPU and migrating the second process to the target CPU; otherwise, traversing the scheduling domain of the computing device from bottom to top, selecting the CPU with the least load as the target CPU, and migrating the second process to the target CPU.

[0012] Optionally, the process migration method according to the present invention further includes: if the CPU where the first process is located is in an idle state, then traversing the scheduling domain of the computing device from bottom to top, selecting the CPU with the least load as the target CPU, and migrating the second process to the target CPU.

[0013] Optionally, the process migration method according to the present invention further includes: if the target CPU is the CPU where the first process is located, then marking the process descriptor of the second process so that, when performing load balancing, the unmarked process is preferentially selected for migration.

[0014] Optionally, the process migration method according to the present invention further includes: when performing load balancing, selecting unmarked processes for migration; if load balancing is not achieved after a predetermined number of load balancing operations, then marking and clearing the marked processes and migrating them.

[0015] According to another aspect of the present invention, a computing device is provided, comprising: at least one processor; and a memory storing program instructions, wherein the program instructions are configured to be executed by the at least one processor, the program instructions including instructions for performing the methods described above.

[0016] According to another aspect of the present invention, a readable storage medium storing program instructions is provided, which, when read and executed by a computing device, causes the computing device to perform the method described above.

[0017] According to the process migration method of the present invention, whenever the first process wakes up the second process, the affinity relationship between the two processes is determined. Based on the affinity between the first process and the second process, a target CPU is determined for the second process to improve the performance of program execution.

[0018] Furthermore, by migrating second processes with affinity to the first process to the same or adjacent CPUs as much as possible, the performance of the programs corresponding to the second processes is maximized. Minor load differences that may arise are adjusted by load balancing. Additionally, by marking second processes migrating to the CPU where the first process resides, unmarked processes are prioritized for migration during load balancing, avoiding significant performance degradation caused by migrating affinity processes. This also prevents ping-pong issues during process migration after wake-up and other load balancing operations.

[0019] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0020] To achieve the foregoing and related objectives, certain illustrative aspects are described herein in conjunction with the following description and accompanying drawings. These aspects indicate various ways in which the principles disclosed herein may be practiced, and all aspects and their equivalents are intended to fall within the scope of the claimed subject matter. The foregoing and other objectives, features, and advantages of this disclosure will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings. Throughout this disclosure, the same reference numerals generally refer to the same parts or elements.

[0021] Figure 1 A schematic diagram of a computing device 100 according to an embodiment of the present invention is shown;

[0022] Figure 2 A flowchart of a process migration method 200 according to an embodiment of the present invention is shown; and

[0023] Figure 3 A flowchart of a process migration method 300 according to another embodiment of the present invention is shown. Detailed Implementation

[0024] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0025] The process migration method of the present invention is executed in a computing device. The computing device can be any device with storage and computing capabilities, such as a server, workstation, or a personal computer such as a desktop computer or laptop computer, or a terminal device such as a mobile phone, tablet computer, smart wearable device, or Internet of Things device, but is not limited thereto.

[0026] Figure 1 A schematic diagram of a computing device 100 according to an embodiment of the present invention is shown. It should be noted that... Figure 1 The computing device 100 shown is merely an example. In practice, the computing device used to implement the process migration method of the present invention can be any type of device, and its hardware configuration can be similar to... Figure 1 The computing device 100 shown is the same as, and can also be the same as, the computing device 100 shown. Figure 1 The computing device 100 shown is different. In practice, the computing device used to implement the process migration method of the present invention can be... Figure 1 The hardware components of the computing device 100 shown may be added or removed. This invention does not limit the specific hardware configuration of the computing device.

[0027] like Figure 1 As shown, in the basic configuration 102, the computing device 100 typically includes system memory 106 and one or more processors 104. Memory bus 108 can be used for communication between processor 104 and system memory 106.

[0028] Depending on the desired configuration, processor 104 can be any type of processor, including but not limited to: microprocessor (μP), microcontroller (μC), digital information processor (DSP), or any combination thereof. Processor 104 may include one or more levels of cache such as L1 cache 110 and L2 cache 112, processor core 114, and registers 116. Example processor core 114 may include an arithmetic logic unit (ALU), floating-point unit (FPU), digital signal processing core (DSP core), or any combination thereof. Example memory controller 118 may be used with processor 104, or in some implementations, memory controller 118 may be an internal part of processor 104.

[0029] Depending on the desired configuration, system memory 106 can be any type of memory, including but not limited to: volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, etc.), or any combination thereof. Physical memory in a computing device typically refers to volatile RAM, and data on a disk needs to be loaded into physical memory before it can be read by processor 104. System memory 106 may include operating system 120, one or more applications 122, and program data 124. In some embodiments, application 122 may be configured to execute instructions on the operating system using program data 124 by one or more processors 104. Operating system 120 may be, for example, Linux, Windows, etc., and includes program instructions for handling basic system services and performing hardware-dependent tasks. Application 122 includes program instructions for implementing various user-desired functions, and application 122 may be, for example, a browser, instant messaging software, software development tools (such as integrated development environments IDEs, compilers, etc.), but is not limited to these. When application 122 is installed in computing device 100, driver modules may be added to operating system 120.

[0030] When computing device 100 starts up, processor 104 reads and executes program instructions from memory 106 of operating system 120. Application 122 runs on operating system 120, utilizing interfaces provided by operating system 120 and underlying hardware to implement various user-expected functions. When user starts application 122, application 122 is loaded into memory 106, and processor 104 reads and executes program instructions from memory 106 of application 122.

[0031] The computing device 100 also includes a storage device 132, which includes a removable storage device 136 and a non-removable storage device 138, both of which are connected to a storage interface bus 134.

[0032] The computing device 100 may also include an interface bus 140 that facilitates communication from various interface devices (e.g., output devices 142, peripheral interfaces 144, and communication devices 146) to the basic configuration 102 via a bus / interface controller 130. Example output devices 142 include a graphics processing unit 148 and an audio processing unit 150. They may be configured to facilitate communication with various external devices such as displays or speakers via one or more A / V ports 152. Example peripheral interfaces 144 may include a serial interface controller 154 and a parallel interface controller 156, which may be configured to facilitate communication with external devices such as input devices (e.g., keyboards, mice, pens, voice input devices, touch input devices) or other peripherals (e.g., printers, scanners, etc.) via one or more I / O ports 158. Example communication devices 146 may include a network controller 160, which may be arranged to facilitate communication with one or more other computing devices 162 via a network communication link through one or more communication ports 164.

[0033] A network communication link can be an example of a communication medium. A communication medium can typically be embodied in a modulated data signal, such as a carrier wave or other transmission mechanism, and can include any information delivery medium. A “modulated data signal” can be a signal whose data set, or whose modifications, can be encoded with information within the signal. As a non-limiting example, a communication medium can include wired media such as wired networks or leased lines, and various wireless media including sound, radio frequency (RF), microwave, infrared (IR), or other wireless media. The term “computer-readable medium” as used herein can include both storage media and communication media.

[0034] In the computing device 100 according to the present invention, the operating system 120 includes instructions for executing the process migration method of the present invention, which can instruct the processor 104 to execute the process migration method of the present invention. It should be noted that the operating system targeted by the method of the present invention can be any operating system, such as Linux or Windows; the process migration method of the present invention is not limited to the specific type of operating system.

[0035] Figure 2 A flowchart of a process migration method 200 according to an embodiment of the present invention is shown. Method 200 involves a first process and a second process. The first process is the process executing the wake-up process, i.e., the process initiating the wake-up, and is typically referred to as the wakeer process. The second process is the process woken up by the first process and is typically referred to as the wakee process.

[0036] like Figure 2 As shown, method 200 begins with step S210.

[0037] In step S210, when the first process wakes up the second process, it is determined whether the CPU where the first process is located is in an idle state.

[0038] Subsequently, in step S220, if the CPU where the first process is located is not in an idle state, the second process is migrated to the target CPU based on the affinity between the first process and the second process.

[0039] According to an embodiment of the present invention, it is determined whether the first process and the second process have affinity. If the first process and the second process have affinity, it is determined whether the number of processes in the CPU where the first process is located is less than or equal to 1. If the number of processes in the CPU where the first process is located is less than or equal to 1, the second process is migrated to the CPU where the first process is located; otherwise, based on whether the CPU where the second process last ran shares the last level cache with the CPU where the first process is located, the second process is migrated to the target CPU. If the first process and the second process do not have affinity, based on whether the CPU where the second process last ran shares the last level cache with the CPU where the first process is located, the second process is migrated to the target CPU.

[0040] To better illustrate the complete implementation process of the present invention, the process migration method of the present invention will be described in detail below. Figure 3 A flowchart of a process migration method 300 according to another embodiment of the present invention is shown. Method 300 is adapted to be used in a computing device (e.g., Figure 1 Executed in the computing device 100 shown. Figure 3 As shown, method 300 begins with step S301.

[0041] Figure 3A flowchart of a process migration method 300 according to an embodiment of the present invention is shown. Method 300 involves a first process and a second process. The first process is the process executing the wake-up process, i.e., the process initiating the wake-up, and is commonly referred to as the wakeer process. The second process is the process woken up by the first process and is commonly referred to as the wakee process.

[0042] like Figure 3 As shown, method 300 begins with step S301.

[0043] In step S301, when the first process wakes up the second process, it is determined whether the CPU where the first process is located is in an idle state.

[0044] If the CPU where the first process is located is idle, then step S302 is executed, which involves traversing the scheduling domain of the computing device from bottom to top, selecting the CPU with the least load as the target CPU, and migrating the second process to the target CPU.

[0045] Normally, when the first process wakes up the second process, the first process is still running, meaning its state is not idle. However, if an interrupt or software interrupt occurs during the wake-up process, the CPU on which the first process resides is not running, resulting in the CPU being idle.

[0046] According to one embodiment of the present invention, if the CPU containing the first process is idle, it indicates that the first process is in a non-process context, that is, the first process is not in a process execution environment. Therefore, the scheduling domain of the computing device is traversed from bottom to top to determine if there is an idle CPU. If so, an idle CPU is selected as the target CPU, and the second process is migrated to the target CPU. Otherwise, the CPU with the fewest processes in the scheduling domain is selected as the target CPU, and the second process is migrated to the target CPU. Since there are multiple levels of domains in the scheduling domain, and the same CPU can belong to multiple different domains, the lower the domain level, the more resources are shared between CPUs, and the lower the cost of migrating processes within a domain. Therefore, by traversing the scheduling domain from bottom to top, CPUs are preferentially searched in domains with lower migration costs.

[0047] If the CPU where the first process is located is not idle, then step S303 is executed, and the second process is migrated to the target CPU based on the affinity between the first process and the second process.

[0048] Specifically, in step S303, it is determined whether the first process and the second process have an affinity relationship. According to one embodiment of the present invention, the wake_wide() function can be used to determine whether the first process and the second process satisfy an affinity relationship. This function determines whether the waker process has recently frequently woken up many different processes and returns true or false. If the wake_wide() function returns false, it means that the first process has not recently frequently woken up different processes, but the first process woke up the second process, indicating that the first process and the second process have a certain affinity relationship. If the function returns true, it means that the first process and the second process do not have an affinity relationship.

[0049] According to another embodiment of the present invention, process affinity can be determined by `wakee_flips`. The operating system kernel records the number of times a wakeer process wakes up different wakeer processes in `wakee_flips`. The larger the value, the more frequently the wakeer process wakes up different processes. Affinity between the first process and the second process is determined by whether the `wakee_flips` of the first process is greater than a first threshold. The first threshold can be selected as the number of CPUs sharing the Last Level Cache (LLC) in the operating system kernel. If the `wakee_flips` of the first process is greater than the first threshold, it indicates that there is no affinity between the first process and the second process; if the `wakee_flips` of the first process is less than or equal to the first threshold, it indicates that there is affinity between the first process and the second process.

[0050] If the first process and the second process have affinity, then proceed to step S304; if the first process and the second process do not have affinity, then proceed to step S305.

[0051] In step S304, it is determined whether the number of processes running on the CPU where the first process resides is less than or equal to 1. If the number of processes running on the CPU where the first process resides is less than or equal to 1, then step S306 is executed; otherwise, step S305 is executed.

[0052] In step S305, based on whether the CPU where the second process was last run shared the last-level cache with the CPU where the first process was run, the second process is migrated to the target CPU.

[0053] According to an embodiment of the present invention, the CPU where the second process last ran can be obtained through prev_cpu, and then it can be determined whether the CPU where the second process last ran shares the last level cache with the CPU where the first process ran. If the CPU where the second process last ran shares the last level cache with the CPU where the first process ran, then step S307 is executed; otherwise, step S308 is executed.

[0054] In step S306, the second process is migrated to the CPU where the first process resides.

[0055] In step S307, it is determined whether the CPU where the second process was last run was in an idle state. If the CPU where the second process was last run was in an idle state, then step S309 is executed; otherwise, step S310 is executed.

[0056] In step S309, the second process is migrated to the CPU where it was previously executed.

[0057] In step S310, it is determined whether there is an idle CPU in the domain of the last-level cache shared by the CPU where the second process last ran and the CPU where the first process ran. If there is an idle CPU in the domain of the last-level cache shared by the CPU where the second process last ran and the CPU where the first process ran, then step S311 is executed; otherwise, step S308 is executed.

[0058] In step S311, an idle CPU is selected as the target CPU, and the second process is migrated to the target CPU.

[0059] In step S308, the scheduling domain of the computing device is traversed from bottom to top, and the CPU with the least load is selected as the target CPU, and the second process is migrated to the target CPU.

[0060] According to an embodiment of the present invention, the scheduling domain of the computing device is traversed from bottom to top to determine whether there is an idle CPU. If so, step S312 is executed, selecting an idle CPU as the target CPU and migrating the second process to the target CPU. Otherwise, step S313 is executed, determining the CPU with the fewest processes from the scheduling domain as the target CPU and migrating the second process to the target CPU. Since there are multiple levels of domains in the scheduling domain, the same CPU can belong to multiple different domains. The lower the domain level, the more resources are shared between CPUs, and the lower the cost of migrating processes within a domain. Therefore, by traversing the scheduling domain from bottom to top, CPUs are preferentially searched in domains with lower migration costs.

[0061] According to the process migration method of the present invention, priority is given to whether the first process and the second process have affinity, and the second process with affinity is migrated to the CPU where the first process is located as much as possible to maximize the running efficiency of the program corresponding to the second process. Even if the second process cannot be migrated to the CPU where the first process is located, the scheduling domain is traversed to find a CPU that is close to the CPU where the first process is located and has a low load, and the second process is migrated to the CPU with a low load and close proximity to maximize the running efficiency of the program corresponding to the second process. According to one embodiment of the present invention, after the second process is migrated to the target CPU, if the target CPU is the CPU where the first process is located, it is marked in the process descriptor (i.e., the task_struct structure) of the second process so that the unmarked process is preferentially selected for migration during load balancing. Optionally, a wake affine flag is recorded in the task_struct structure of the second process. If the execution of the process migration method according to the present invention results in a slight load difference or the proportion of CPU load does not exceed a threshold, the second process is allowed to run on the CPU where the first process is located, and the affinity relationship is recorded. The imbalance caused by wake-up will be restored to balance during load balancing.

[0062] According to embodiments of the present invention, during load balancing, such as periodic load balancing, idle load balancing, and NUMA balancing (Non-Uniform Memory Access Balancing), processes without affinity are migrated first. If imbalance persists after several attempts to migrate other processes, then affinity processes are migrated, thus ensuring performance stability as much as possible. Specifically, during load balancing, unmarked processes are migrated first. If balance is not achieved after load balancing, the process continues. When the number of load balancing attempts reaches a predetermined value and load balance is still not achieved, affinity processes, i.e., marked processes, are migrated. For affinity processes that need to be migrated, their markings are cleared before migration. Prioritizing the migration of unmarked processes during load balancing avoids a significant performance drop caused by migrating affinity processes, and also prevents ping-pong phenomena during process migration after wake-up and load balancing at other times.

[0063] According to one embodiment of the present invention, a red-black tree recording affinity can also be constructed for each CPU in the computing device, and processes on each CPU can be sorted according to the strength of affinity. Constructing a red-black tree can increase the accuracy of affinity determination during process migration.

[0064] According to the process migration method of the present invention, whenever the first process wakes up the second process, the affinity relationship between the two processes is determined. Based on the affinity between the first process and the second process, a target CPU is determined for the second process to improve the running performance of the program corresponding to the second process.

[0065] Furthermore, by migrating second processes with affinity to the first process to the same or adjacent CPUs as much as possible, the performance of the programs corresponding to the second processes is maximized. Minor load differences that may arise are adjusted by load balancing. Additionally, by marking second processes migrating to the CPU where the first process resides, unmarked processes are prioritized for migration during load balancing, avoiding significant performance degradation caused by migrating affinity processes. This also prevents ping-pong issues during process migration after wake-up and other load balancing operations.

[0066] The various techniques described herein can be implemented in combination with hardware or software, or a combination thereof. Thus, the methods and apparatus of the present invention, or certain aspects or portions thereof, can take the form of program code (i.e., instructions) embedded in a tangible medium, such as a removable hard disk, USB flash drive, floppy disk, CD-ROM, or any other machine-readable storage medium, wherein when the program is loaded into and executed by a machine such as a computer, the machine becomes an apparatus for practicing the present invention.

[0067] When the program code is executed on a programmable computer, the mobile terminal generally includes a processor, a processor-readable storage medium (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device. The memory is configured to store program code; the processor is configured to execute the process migration method of the present invention according to instructions in the program code stored in the memory.

[0068] By way of example, and not limitation, readable media include readable storage media and communication media. Readable storage media stores information such as computer-readable instructions, data structures, program modules, or other data. Communication media generally embodies computer-readable instructions, data structures, program modules, or other data in the form of modulated data signals such as carrier waves or other transmission mechanisms, and includes any information delivery medium. Any combination of the above is also included within the scope of readable media.

[0069] In the specification provided herein, the algorithms and displays are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used with the examples of this invention. The required structure for constructing such systems is apparent from the above description. Furthermore, this invention is not directed to any particular programming language. It should be understood that the contents of the invention described herein can be implemented using various programming languages, and the above description of specific languages ​​is for the purpose of disclosing the best mode of implementation of the invention.

[0070] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0071] Similarly, it should be understood that, in order to streamline this disclosure and aid in understanding one or more of the various aspects of the invention, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof. However, this method of disclosure should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into this detailed description, wherein each claim itself is a separate embodiment of the invention.

[0072] Those skilled in the art will understand that modules, units, or components of the devices disclosed in the examples herein can be arranged in the devices described in this embodiment, or alternatively, can be located in one or more devices different from the devices in this example. The modules in the foregoing examples can be combined into a single module or, in addition, can be divided into multiple sub-modules.

[0073] Those skilled in the art will understand that modules in the device of the embodiments can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or device so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0074] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination.

[0075] Furthermore, some of the embodiments described herein are methods or combinations of method elements that can be implemented by a processor of a computer system or by other means of performing the functions. Therefore, a processor having the necessary instructions for implementing the methods or method elements forms means for implementing the methods or method elements. Furthermore, the elements described herein in the apparatus embodiments are examples of means for implementing the functions performed by elements for the purposes of carrying out the invention.

[0076] As used herein, unless otherwise specified, the use of ordinal numbers such as “first,” “second,” “third,” etc., to describe ordinary objects merely indicates different instances of similar objects and is not intended to imply that the objects being described must have a given order in time, space, ordering, or any other manner.

[0077] Although the invention has been described with respect to a limited number of embodiments, those skilled in the art will understand from the foregoing description that other embodiments are conceivable within the scope of the invention described herein. Furthermore, it should be noted that the language used in this specification has been chosen primarily for readability and edibility purposes, and not for the purpose of interpreting or limiting the subject matter of the invention. Therefore, many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the appended claims. The disclosure of the invention is illustrative rather than restrictive, and the scope of the invention is defined by the appended claims.

Claims

1. A process migration method, executed in a computing device, the method comprising: When the first process wakes up the second process, it is determined whether the CPU where the first process is located is in an idle state; If the CPU where the first process resides is not idle, then based on the affinity between the first process and the second process, the second process is migrated to the target CPU of the computing device. If the CPU where the first process is located is idle, the scheduling domain of the computing device is traversed from bottom to top, and the CPU with the least load is selected as the target CPU, and the second process is migrated to the target CPU. The step of migrating the second process to the target CPU based on the affinity between the first process and the second process includes: Determine whether the first process and the second process have affinity; If the first process and the second process have affinity, then determine whether the number of processes in the CPU where the first process is located is less than or equal to 1; If the number of processes in the CPU where the first process is located is less than or equal to 1, then the second process will be migrated to the CPU where the first process is located. Otherwise, based on whether the CPU where the second process last ran shares the last-level cache with the CPU where the first process ran, the second process is migrated to the target CPU; The method further includes: if the target CPU is the CPU where the first process is located, then marking the process descriptor of the second process so that, when performing load balancing, the unmarked process is preferentially selected for migration.

2. The method according to claim 1, wherein, After the step of determining whether the first process and the second process have affinity, the method further includes: If the first process and the second process do not have affinity, then based on whether the CPU where the second process was last run shares the last-level cache with the CPU where the first process was run, the second process will be migrated to the target CPU.

3. The method according to claim 1 or 2, wherein, The step of migrating the second process to the target CPU based on whether the CPU where the second process last ran shares the final cache with the CPU where the first process ran includes: Determine whether the CPU where the second process was last executed shares the last-level cache with the CPU where the first process is executed. If so, the second process will be migrated to the target CPU based on whether the CPU where the second process was last executed is in an idle state. Otherwise, the scheduling domain of the computing device is traversed from bottom to top, and the CPU with the least load is selected as the target CPU, and the second process is migrated to the target CPU.

4. The method according to claim 3, wherein, The step of migrating the second process to the target CPU based on whether the CPU where the second process last ran was in an idle state includes: Determine whether the CPU where the second process was last executed was in an idle state; If so, the second process will be migrated to the CPU where it last ran; Otherwise, determine whether there is an idle CPU in the domain of the last-level cache shared by the CPU where the second process last ran and the CPU where the first process ran; If it exists, select an idle CPU as the target CPU and migrate the second process to the target CPU; Otherwise, the scheduling domain of the computing device is traversed from bottom to top, and the CPU with the least load is selected as the target CPU, and the second process is migrated to the target CPU.

5. The method according to claim 1 or 2, further comprising: When performing load balancing, select untagged processes for migration; If load balancing is not achieved after a predetermined number of attempts, the marked processes will be cleared and migrated.

6. A computing device, comprising: At least one processor; as well as A memory storing program instructions, wherein the program instructions are configured to be executed by the at least one processor, the program instructions including instructions for performing the method as claimed in any one of claims 1 to 5.

7. A readable storage medium storing program instructions that, when read and executed by a computing device, cause the computing device to perform the method as described in any one of claims 1 to 5.

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