Memory interface circuit, memory control method, and electronic device

Abstract

The present disclosure relates to a memory interface circuit, a memory control method and an electronic device, and belongs to the technical field of integrated circuits. The memory interface circuit comprises: a memory interface circuit connected with a processor interface circuit; and a signal connection line connected with a power supply end of the memory interface circuit and a power supply end of the processor interface circuit, used for applying a voltage of the power supply end of the processor interface circuit to the power supply end of the memory interface circuit after the processor is powered on and before the memory is powered on. The present disclosure can avoid the occurrence of latch-up effect before the memory is powered on.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to a memory interface circuit, a memory control method and an electronic device. BACKGROUND

[0002] DDR5 SDRAM(Double Data Rate Fourth Synchronous Dynamic Random Access Memory, double data rate fifth synchronous dynamic random access memory) is a synchronous DRAM memory. For a DDR5 DIMM(Dual-Inline-Memory-Modules, dual in-line memory module), the power management module is transferred from the mainboard to the DIMM.

[0003] Generally, after the CPU(Central Processing Unit, central processing unit) is powered on, the power management module on the DIMM is controlled to power on the DIMM.

[0004] However, after the CPU is powered on, the voltage from the input and output interface of the CPU drives the DDR5 on the DIMM, and the latch effect occurs. If this state lasts for too long, it will cause permanent damage to the DDR5.

[0005] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0006] The purpose of the present disclosure is to provide a memory interface circuit, a memory control method and an electronic device to avoid the latch effect before the memory is powered on.

[0007] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description, or will be learned by practice of the present disclosure.

[0008] According to a first aspect of the present disclosure, a memory interface circuit is provided, comprising: the memory interface circuit is connected to a processor interface circuit; a signal connection line connects a power supply end of the memory interface circuit and a power supply end of the processor interface circuit, and is used to apply a voltage of the power supply end of the processor interface circuit to the power supply end of the memory interface circuit before the memory is powered on after the processor is powered on.

[0009] In an example embodiment of the present disclosure, the signal connection line is connected to the memory interface circuit through a signal connection line, and the signal connection line is connected to the processor interface circuit through a signal connection line.

[0010] In an example embodiment of the present disclosure, the memory interface circuit comprises a first switch module, wherein the first switch module comprises a memory input / output terminal, a ground terminal and a power terminal of the memory interface circuit, and the memory input / output terminal is connected to the processor interface circuit.

[0011] In an example embodiment of the present disclosure, the memory interface circuit further comprises a first diode and a second diode, wherein the anode of the first diode is connected to the memory input / output terminal, the cathode of the first diode is connected to the power terminal of the memory interface circuit, the cathode of the second diode is connected to the memory input / output terminal, and the anode of the second diode is connected to the ground terminal.

[0012] In an example embodiment of the present disclosure, the first switch module comprises a first switch tube and a second switch tube, wherein the gate of the first switch tube is connected to the memory input / output terminal, the source of the first switch tube is connected to the power terminal of the memory interface circuit, the drain of the first switch tube is connected to the drain of the second switch tube, the gate of the second switch tube is connected to the memory input / output terminal, and the source of the second switch tube is grounded.

[0013] In an example embodiment of the present disclosure, the processor interface circuit comprises a second switch module and a third switch module, wherein the first end of the second switch module is connected to the power terminal of the processor interface circuit, the second end of the second switch module is grounded, the third end of the second switch module is a processor input / output terminal, the processor input / output terminal is connected to the memory input / output terminal, the first end of the third switch module is connected to the power terminal of the processor interface circuit, the second end of the third switch module is grounded, and the third end of the third switch module is connected to the power terminal of the memory interface circuit through the signal connection line.

[0014] In an example embodiment of the present disclosure, the second switch module comprises a third switch tube and a fourth switch tube, wherein the source of the third switch tube is connected to the power terminal of the processor interface circuit, the drain of the third switch tube is connected to the processor input / output terminal, the drain of the fourth switch tube is connected to the drain of the third switch tube, and the source of the fourth switch tube is grounded.

[0015] In an example embodiment of the present disclosure, the third switch module includes a fifth switch tube and a sixth switch tube; a source of the fifth switch tube is connected to a power supply end of the processor interface circuit, a drain of the fifth switch tube is connected to a power supply end of the memory interface circuit through the signal connection line; a drain of the sixth switch tube is connected to a drain of the fifth switch tube, and a source of the sixth switch tube is grounded.

[0016] In an example embodiment of the present disclosure, the memory interface circuit further includes a first PMIC connected to the power supply end of the memory interface circuit, configured to provide power supply for the memory.

[0017] In an example embodiment of the present disclosure, the memory interface circuit further includes a second PMIC connected to the power supply end of the processor interface circuit, configured to provide power supply for the processor.

[0018] According to a second aspect of the present disclosure, a memory control method is provided, configured to the memory interface circuit, including: after the system is started, supplying power to a power supply end of the processor interface circuit to power on the processor, applying a voltage of the power supply end of the processor interface circuit on a power supply end of the memory interface circuit through the signal connection line; and supplying power to the power supply end of the memory interface circuit to power on the memory.

[0019] In an example embodiment of the present disclosure, the memory control method further includes: after the processor is powered on, opening a switch unit to connect the signal connection line; and after the memory is powered on, closing the switch unit to disconnect the signal connection line.

[0020] In an example embodiment of the present disclosure, the memory control method further includes: after the memory is powered on, initializing the memory and performing read-write operation by the processor.

[0021] In an example embodiment of the present disclosure, the memory control method further includes: supplying power to the power supply end of the processor interface circuit by the first PMIC, and supplying power to the power supply end of the memory interface circuit by the second PMIC.

[0022] According to a third aspect of the present disclosure, an electronic device is provided, including the memory interface circuit.

[0023] The technical solution provided by the present disclosure can include the following beneficial effects:

[0024] The memory interface circuit provided by the exemplary embodiments of the present disclosure sets a signal connection line in the memory interface circuit, and connects the power supply end of the memory interface circuit and the power supply end of the processor interface circuit through the signal connection line. After the processor is powered on, that is, after the power supply end of the processor interface circuit is connected to the power supply to generate voltage, the signal connection line can directly apply the voltage of the power supply end of the processor interface circuit to the power supply end of the memory interface circuit, thereby avoiding the phenomenon that the voltage at the memory input and output end of the memory interface circuit is higher than the voltage of the power supply end, thereby avoiding the latch-up effect before the memory is powered on, and reducing the probability of damage to the memory.

[0025] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0026] The accompanying drawings incorporated in and forming a part of the specification illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure. It is apparent that the accompanying drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those of ordinary skill in the art without creative labor based on these drawings. In the drawings:

[0027] Figure 1 The structure of a memory interface circuit according to an exemplary embodiment of the present disclosure is schematically shown;

[0028] Figure 2 A pin diagram of a DDR5 DIMM memory according to an exemplary embodiment of the present disclosure is schematically shown;

[0029] Figure 3 The structure of another memory interface circuit according to an exemplary embodiment of the present disclosure is schematically shown;

[0030] Figure 4 The structure of another memory interface circuit according to an exemplary embodiment of the present disclosure is schematically shown;

[0031] Figure 5 A flowchart of a memory control method according to an exemplary embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0032] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the several views and, thus, description of the same elements will not be repeated.

[0033] Moreover, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the disclosure.

[0034] The block diagrams in the drawings show only the functionality of the features and can not imply a physical or architectural arrangement of the devices. That is, the functionality can be implemented in software, hardware, or a combination thereof. The functionality can be implemented in one or more modules, which can be implemented in software or hardware.

[0035] With the development of memory technology, DDR4 SDRAM (Double Data Rate Fourth Synchronous Dynamic Random Access Memory) and DDR5 SDRAM have emerged. Both DDR4 SDRAM and DDR5 SDRAM have a lower supply voltage and a higher transmission rate. The bank group on the memory has the characteristics of independent start operation reading, writing, and the like. In addition, compared with, for example, DDR3 and DDR2 memories, DDR4 and DDR5 have the characteristics of fast and power saving, and can also enhance the integrity of the signal, improve the reliability of data transmission and storage.

[0036] Compared with DDR4 memory particles, the power management module of the DDR5 memory particle is externally arranged on the dual in-line memory module (DIMM). However, whether it is a DDR3 memory particle, a DDR2 memory particle, a DDR4 memory particle, or a DDR5 memory particle, the processor CPU is powered on first after the system is started, and then the memory particle on the DIMM is powered on through the processor CPU.

[0037] However, generally after the processor CPU is powered on, the voltage on the processor CPU is applied to the input / output interface of the memory particle, so that the voltage at the input / output interface of the memory particle is higher than the voltage at the power supply end of the memory particle, thereby causing a latch-up effect. The latch-up effect is an important problem in a CMOS (Metal-Oxide-Semiconductor) integrated circuit, which can cause confusion of chip functions or direct failure of the circuit to work or even burn out. The latch-up effect is also a reverse bias state.

[0038] The latch-up effect is generated by an n-p-n-p structure composed of an active region of an NMOS (N-Metal-Oxide-Semiconductor), a P substrate, an N well, and an active region of a PMOS (P-Metal-Oxide-Semiconductor), and when one of the three transistors is positively biased, a positive feedback is formed to cause the latch-up. A method for avoiding the latch-up is to reduce the parasitic resistance of the substrate and the N well, so that the parasitic transistor is not in a positive bias state. Voltage transients can cause the latch-up effect, which is one of the main reasons for failure of semiconductor devices. If a strong electric field is applied to the oxide film in the device structure, the oxide film can be damaged due to dielectric breakdown. Very thin metalized traces can be damaged due to a large current, and can form an open circuit due to overheating caused by inrush current. This is called the "latch-up effect". In the latch-up case, the device forms a short circuit between the power supply and the ground, causing a large current and damage to the device.

[0039] That is, in the prior art, after the system is powered on, the voltage applied to the processor CPU directly acts on the input / output interface of the memory particle, so that the memory particle that has not been powered on can be permanently damaged due to the latch-up effect.

[0040] Based on this, the example embodiment of the present disclosure provides a memory interface circuit, which can be used in any memory circuit such as a DRAM connected to a processor CPU, and the example embodiment of the present disclosure is not specially limited to a specific DRAM.

[0041] Referring to Figure 1 , a structure schematic diagram of a memory interface circuit provided by the example embodiment of the present disclosure is shown. As Figure 1As shown, the memory interface circuit 100 is connected with the processor interface circuit 200, the processor CPU is connected with the memory interface circuit 100 through the processor interface circuit 200, and the memory is controlled and managed through the memory interface circuit 100. The memory can be a semiconductor memory such as DDR5, DDR4, DDR3 or DDR2, and can also be a random access memory (RAM), that is, a main memory, which is a memory storage directly exchanging data with the processor CPU, can be read and written at any time, has a very fast speed, and is usually used as a temporary data storage medium for an operating system or other programs running.

[0042] In the memory interface circuit 100 provided by the exemplary embodiments of the present disclosure, a signal connection line 110 is additionally arranged, which connects the power supply end 120 of the memory interface circuit 100 and the power supply end 210 of the processor interface circuit 200, and is used to apply the voltage of the power supply end 210 of the processor interface circuit 200 to the power supply end 120 of the memory interface circuit 100 before the memory is powered on after the processor CPU is powered on.

[0043] In the exemplary embodiments of the present disclosure, by arranging the signal connection line 110 in the memory interface circuit 100 and connecting the power supply end 120 of the memory interface circuit 100 and the power supply end 210 of the processor interface circuit 200 through the signal connection line 110, after the processor CPU is powered on, that is, after the power supply end 210 of the processor interface circuit 200 is connected to the power supply to generate voltage, the signal connection line 110 can directly apply the voltage of the power supply end 210 of the processor interface circuit 200 to the power supply end 120 of the memory interface circuit 100, thereby avoiding the phenomenon that the voltage at the input and output end of the memory in the memory interface circuit 100 is higher than the voltage of the power supply end 120, thereby avoiding the generation of latch-up effect and reducing the probability of damage to the memory.

[0044] In actual application, the signal connection line 110 can be realized through corresponding pins on the memory and the processor, for example, the signal connection line 110 mentioned in the exemplary embodiments of the present disclosure can be formed by using the reserved RFU (Reserved for future use) pin on the memory and the corresponding pin on the processor.

[0045] Reference Figure 2 shows a schematic diagram of a DDR5 DIMM memory stick pin. Figure 2In the embodiment, the reserved RFU pins on the DDR5 memory bar are six, namely, RFU0 pin-RFU5 pin. In actual use, any one of the six RFU pins can be connected with the corresponding pin on the processor to form the signal connection line 110. For example, the RFU5 pin is connected with the corresponding pin on the processor. As shown in the figure, the number of the RFU5 pin is 232. Therefore, the pin numbered 232 on the processor can be connected with the RFU5 pin, and the RFU5 pin is connected with the power supply end 120 of the memory interface circuit 100, and the pin numbered 232 on the processor is connected with the power supply end 210 of the processor interface circuit 200, so as to form the signal connection line 110 in the embodiment.

[0046] In the memory interface circuit 100 provided by the embodiment, in addition to the signal connection line 110, a switch unit 220 is further included. Figure 3 The structure of another memory interface circuit provided by the embodiment is shown in FIG. 2B. As shown in FIG. 2B, the switch unit 220 is arranged on the signal connection line 110, and the switch unit 220 is used to connect the signal connection line 110 before the processor is powered on and the memory is powered on, and cut off the signal connection line 110 after the memory is powered on. Figure 3

[0047] This is because the power supply end 210 of the processor interface circuit 200 and the power supply end 120 of the memory interface circuit 100 are powered by different power supplies. After the processor and the memory are powered on, if the signal connection line 110 is not cut off, the power supply end 210 of the processor interface circuit 200 and the power supply end 120 of the memory interface circuit 100 will generate current on the signal connection line 110 due to the pressure difference, thereby increasing the additional power consumption of the system. In the embodiment, the switch unit 220 is arranged on the signal connection line 110, and the switch unit 220 is used to cut off the signal connection line 110 after the memory is powered on, thereby reducing the additional power consumption of the system and achieving the purpose of energy saving.

[0048] In actual application, the switch unit 220 arranged on the signal connection line 110 can be arranged on the circuit board corresponding to the processor or the circuit board corresponding to the memory, and the embodiment does not specially limit this.

[0049] In the embodiment, the switch unit 220 can be a triode switch unit, a single-blade switch unit, or other switch units that can be automatically switched under signal control, so as to automatically turn on / off the signal connection line 110 under signal control. The embodiment does not specially limit the specific form of the switch unit 220. ​

[0050] As shown in Figure 1 and Figure 3 The memory interface circuit 100 can include a first switch module 130, the processor interface circuit 200 can include a second switch module 230 and a third switch module 240, and the first switch module 130 is connected to the second switch module 230. After the processor and the memory are powered on, the processor can control the memory to initialize, reset, or read and write the memory through the connected first switch module 130 and the second switch module 230.

[0051] In the exemplary embodiment of the present disclosure, the first switch module 130 and the third switch module 240 are connected through the signal connection line 110, and the connection of the first switch module 130 and the third switch module 240 can connect the power supply end 120 of the memory interface circuit 100 and the power supply end 210 of the processor interface circuit 200, so that after the power supply end 210 of the processor interface circuit 200 is connected to the power supply to generate a voltage, the voltage of the power supply end 210 of the processor interface circuit 200 can be applied to the power supply end 120 of the memory interface circuit 100 through the third switch module 240, the signal connection line 110 and the first switch module 130, thereby avoiding the phenomenon that the voltage at the memory input and output end of the memory interface circuit 100 is higher than the voltage at the power supply end 120, thereby avoiding the generation of latch-up effect and reducing the probability of damage to the memory.

[0052] In actual application, the structure of the first switch module 130 can be various, which can be set according to actual conditions. In the exemplary embodiment of the present disclosure, the structure shown in Figure 1 and Figure 3 is taken as an example, wherein the first switch module 130 includes a memory input and output end, a ground end and the power supply end 120 of the memory interface circuit 100, and the memory input and output end is connected to the power supply end 210 of the processor interface circuit 200, that is, the memory input and output end is connected to the second switch module 230.

[0053] In the exemplary embodiment of the present disclosure, in addition to including the first switch module 130, the memory interface circuit 100 also includes a first diode 140 and a second diode 150, and the first diode 140 is arranged between the memory input and output end of the first switch module 130 and the power supply end 120 of the memory interface circuit 100, and the second diode 150 is arranged between the ground end and the memory input and output end of the first switch module 130.

[0054] Specifically, the anode of the first diode 140 is connected to the memory input / output terminal, and the cathode of the first diode 140 is connected to the power terminal 120 of the memory interface circuit 100; the cathode of the second diode 150 is connected to the memory input / output terminal, and the anode of the second diode 150 is connected to the ground terminal of the first switch module 130.

[0055] In the exemplary embodiment of the present disclosure, the first diode 140 and the second diode 150 can be ESD (Electrostatic Discharge Protection Devices) static diodes, also known as transient suppression diode arrays. The ESD diode is a plurality of diodes made in different layouts to form a specific function of a multi-channel or single-channel ESD protection device.

[0056] In actual application, by connecting the ESD static diode in parallel in the circuit, when the circuit is working normally, it is in the off state (high resistance state) and does not affect the normal work of the circuit. When the circuit appears abnormal overvoltage and reaches its breakdown voltage, it quickly changes from high resistance state to low resistance state, providing a low impedance conduction path for the instantaneous current, and clamping the abnormal high voltage within a safe level, thereby protecting the protected IC or circuit; when the abnormal overvoltage disappears, it returns to the high resistance state and the circuit works normally. Therefore, the protection measures can be taken from the root cause, and the static electricity can be quickly dissipated during production and operation, and the leakage of static electricity, which is one of the effects of the ESD static diode.

[0057] For the memory interface circuit 100 provided by the exemplary embodiment of the present disclosure, before the signal connection line 110 is set, if the processor is powered on, that is, the power terminal 210 of the processor interface circuit 200 is connected to the power supply to generate a voltage, because the anode of the first diode 140 is connected to the memory input / output terminal, the voltage of the power terminal 210 of the processor interface circuit 200 will pass through the memory input / output terminal and the first diode 140 and be applied to the power terminal 120 of the memory interface circuit 100, that is, the first diode 140 is forward biased. In actual application, if the time of such first diode 140 forward bias is too long, it will cause the first diode 140 to overheat and permanently damaged.

[0058] The memory interface circuit 100 provided by the example embodiment of the present disclosure can directly apply the voltage of the power supply end 210 of the processor interface circuit 200 to the power supply end 120 of the memory interface circuit 100 through the signal connection line 110 after the processor CPU is powered on, that is, after the power supply end 210 of the processor interface circuit 200 generates a voltage after being connected to the power supply. Not only can the latch effect caused by the phenomenon that the voltage at the memory input and output end of the memory interface circuit 100 is higher than the voltage of the power supply end 120 be avoided, but also the first diode 140 can be prevented from being forward-biased, thereby reducing the probability of permanent damage of the first diode 140 caused by overheating and prolonging the service life of the first diode 140.

[0059] In the example embodiment of the present disclosure, as shown in Figure 1 and Figure 3 The first switch module 130 can include a first switch tube 131 and a second switch tube 132, wherein the gate of the first switch tube 131 is connected to the memory input and output end, the source of the first switch tube 131 is connected to the power supply end 120 of the memory interface circuit 100, and the drain of the first switch tube 131 is connected to the drain of the second switch tube 132; the gate of the second switch tube 132 is connected to the memory input and output end, and the source of the second switch tube 132 is grounded.

[0060] In actual applications, the first switch tube 131 and the second switch tube 132 can both be MOS tubes or thin film transistors. Further, the MOS tube can be a P-type MOS tube or an N-type MOS tube, and the thin film transistor can be a P-type thin film transistor or an N-type thin film transistor. For example, the first switch tube 131 can be a P-type MOS tube, and the second switch tube 132 can be an N-type MOS tube. For the P-type MOS tube, it is only turned on when the signal input at the gate is low; for the N-type MOS tube, it is only turned on when the signal input at the gate is high.

[0061] In the example embodiment of the present disclosure, after the processor is powered on, that is, after the power supply end 210 of the processor interface circuit 200 generates a high level VDDQ_CPU, the high level enters the gates of the first switch tube 131 and the second switch tube 132, thereby opening the first switch tube 131 or the second switch tube 132, so as to connect the processor and the memory, and facilitate the processor to control the memory.

[0062] In an exemplary embodiment of this disclosure, the first end of the second switch module 230 is connected to the power supply terminal 210 of the processor interface circuit 200, the second end of the second switch module 230 is grounded, and the third end of the second switch module 230 is the processor input / output terminal, which is connected to the memory input / output terminal. After the power supply terminal 210 of the processor interface circuit 200 generates voltage, current will flow from the processor input / output terminal to the memory input / output terminal.

[0063] In practical applications, the second switch module 230 can have various structural forms, which can be set according to the actual situation. In the exemplary embodiment of this disclosure, using... Figure 1 and Figure 3 Taking the illustrated structure as an example, the second switch module 230 may include a third switch 231 and a fourth switch 232. The source of the third switch 231 is connected to the power supply terminal 210 of the processor interface circuit 200, and the drain of the third switch 231 is connected to the processor input / output terminal. After the processor is powered on, i.e., after the power supply terminal 210 of the processor interface circuit 200 generates a high-level signal VDDQ_CPU, the third switch 231 will turn on, and this high-level VDDQ_CPU signal will flow into the memory input / output terminal through the processor input / output terminal. The drain of the fourth switch 232 is connected to the drain of the third switch 231, and the source of the fourth switch 232 is grounded.

[0064] In practical applications, both the third switch 231 and the fourth switch 232 can be MOSFETs or thin-film transistors. Furthermore, MOSFETs are divided into P-type MOSFETs and N-type MOSFETs, and thin-film transistors can be either P-type or N-type thin-film transistors.

[0065] In an exemplary embodiment of this disclosure, the first terminal of the third switch module 240 is connected to the power supply terminal 210 of the processor interface circuit 200, the second terminal of the third switch module 240 is grounded, and the third terminal of the third switch module 240 is connected to the power supply terminal 120 of the memory interface circuit 100 via a signal connection line 110. After a voltage is generated at the power supply terminal 210 of the processor interface circuit 200, current flows directly into the power supply terminal 120 of the memory interface circuit 100 through the signal connection line 110, thereby raising the level of the power supply terminal 120 of the memory interface circuit 100 and preventing latch-up.

[0066] In practical applications, the third switch module 240 can have various structural forms, which can be set according to the actual situation. In the exemplary embodiment of this disclosure, using... Figure 1 and Figure 3The shown structure is an example, the third switch module 240 includes a fifth switch tube 241 and a sixth switch tube 242; wherein the source of the fifth switch tube 241 is connected to the power supply end 210 of the processor interface circuit 200, and the drain of the fifth switch tube 241 is connected to the power supply end 120 of the memory interface circuit 100 through the signal connection line 110; after the processor is powered on, that is, the power supply end 210 of the processor interface circuit 200 generates a high level VDDQ_CPU, the fifth switch tube 241 will be opened, and the high level VDDQ_CPU signal will flow into the power supply end 120 of the memory interface circuit 100 through the signal connection line 110, thereby pulling up the level of the power supply end 120 of the memory interface circuit 100. The drain of the sixth switch tube 242 is connected to the drain of the fifth switch tube 241, and the source of the sixth switch tube 242 is grounded.

[0067] In actual application, the fifth switch tube 241 and the sixth switch tube 242 can be MOS tubes or thin film transistors. Further, the MOS tube is divided into a P-type MOS tube and an N-type MOS tube, and the thin film transistor can be a P-type thin film transistor or an N-type thin film transistor.

[0068] In the example embodiment of the present disclosure, referring to Figure 4 , another structure diagram of the memory interface circuit provided by the example embodiment of the present disclosure is shown. Figure 4 In the example embodiment of the present disclosure, the memory interface circuit 100 further includes a first PMIC 160 and a second PMIC 250, wherein PMIC is the full name of Power Management IC, that is, a power management integrated circuit, which is used to manage the power supply equipment in the host system. The PMIC can integrate multiple functions to more effectively utilize space and manage system power. The functions that can be implemented by the PMIC usually include voltage converters and voltage stabilizers, battery chargers, battery power meters, LED drivers, real-time clocks, power sequencers and power controls, and can provide protection functions in the case of overvoltage, undervoltage, overcurrent, thermal failure, etc.

[0069] In the example embodiment of the present disclosure, the first PMIC 160 is connected to the power supply end 120 of the memory interface circuit 100, and is used to provide power supply for the memory. The second PMIC 250 is connected to the power supply end 210 of the processor interface circuit 200, and is used to provide power supply for the processor.

[0070] In actual application, first, the second PMIC 250 supplies power to the power supply end 210 of the processor interface circuit 200, so that the processor is powered on, and after the processor is powered on, the processor will control the first PMIC 160 to open, and then the first PMIC 160 controls the memory to be powered on.

[0071] It should be noted that the first PMIC 160 can also be arranged on a memory stick DIMM of the memory according to actual needs, so as to reduce the voltage drop of the memory.

[0072] It should be further noted that the connection mentioned in the example embodiments of the present disclosure can be direct connection or coupling, and the coupling here can be indirect connection through other devices, which is not specially limited in the example embodiments of the present disclosure.

[0073] In the example embodiments of the present disclosure, on the one hand, by arranging the signal connection line 110 in the memory interface circuit 100 and connecting the power supply end 120 of the memory interface circuit 100 and the power supply end 210 of the processor interface circuit 200 through the signal connection line 110, after the processor CPU is powered on, that is, after the power supply end 210 of the processor interface circuit 200 is connected to the power supply to generate voltage, the signal connection line 110 can directly apply the voltage of the power supply end 210 of the processor interface circuit 200 to the power supply end 120 of the memory interface circuit 100, thereby avoiding the phenomenon that the voltage at the memory input and output end in the memory interface circuit 100 is higher than the voltage of the power supply end 120, thereby avoiding the generation of latch-up effect and reducing the probability of damage to the memory; on the other hand, by arranging the switch unit 220 on the signal connection line 110, the signal connection line 110 can be cut off by the switch unit 220 after the memory is powered on, thereby reducing the additional power consumption of the system and achieving the purpose of energy saving; on the other hand, the signal connection line 110 is arranged, after the processor CPU is powered on, that is, after the power supply end 210 of the processor interface circuit 200 is connected to the power supply to generate voltage, the signal connection line 110 can directly apply the voltage of the power supply end 210 of the processor interface circuit 200 to the power supply end 120 of the memory interface circuit 100, and the first diode 140 can also be avoided from being forward-biased, thereby reducing the probability of permanent damage of the first diode 140 due to overheating and prolonging the service life of the first diode 140.

[0074] In addition, the example embodiments of the present disclosure also provide a memory control method. The memory control method is used for the memory interface circuit described above. Referring to Figure 5 , the memory control method can specifically include the following steps:

[0075] Step S510, after the system is started, the power supply end of the processor interface circuit is powered to power on the processor, and the voltage of the power supply end of the processor interface circuit is applied to the power supply end of the memory interface circuit through the signal connection line;

[0076] Step S520, power supply to the power supply end of the memory interface circuit to power on the memory.

[0077] In an example embodiment of the present disclosure, the memory control method further includes: after the processor is powered on, turning on the switch unit to connect the signal connection line; and after the memory is powered on, turning off the switch unit to disconnect the signal connection line.

[0078] In an example embodiment of the present disclosure, the memory control method further includes: after the memory is powered on, initializing the memory by the processor and performing read / write operations.

[0079] In an example embodiment of the present disclosure, the memory control method further includes: powering the power supply end of the processor interface circuit by the first PMIC, and powering the power supply end of the memory interface circuit by the second PMIC.

[0080] The specific details of each step of the memory control method have been described in detail in the corresponding memory interface circuit, and thus will not be described here again.

[0081] Further, the example embodiment of the present disclosure also provides an electronic device, which can include the memory interface circuit described above. The specific structure and working principle of the memory interface circuit have been described in detail in the foregoing embodiments, and thus will not be described here again.

[0082] It should be noted that the electronic device described above can be any device that needs to use memory, such as a smart phone, a tablet computer, a solid state drive, a network and a wireless Internet of Things device, and a notebook computer, etc.

[0083] In the foregoing embodiments, all or part of the embodiments can be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present disclosure are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another computer-readable storage medium. The computer-readable storage medium can be any available medium that can be accessed by a computer or include one or more data storage devices such as servers, data centers, etc. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)), etc. In the embodiments of the present disclosure, the computer can include the devices described above.

[0084] Although the present disclosure has been described in connection with certain embodiments, persons skilled in the art will understand and appreciate that many modifications, changes, and substitutions are possible by utilizing no more than the knowledge of what is particularly sought after according to the principles of the present disclosure. Accordingly, the present disclosure is not intended to be limited to the embodiments described herein, but rather is to cover all modifications and variations that fall within the scope of the present disclosure including full use of equivalents thereof. It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the present disclosure should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims, along with their full scope of equivalents.

[0085] Although the present disclosure has been described in connection with specific features thereof, it will be evident to those skilled in the art that various modifications and changes can be made to the present disclosure without departing from the spirit and scope thereof. Accordingly, it is intended that the present disclosure not be limited to the described embodiments, but that it include all modifications and alternatives within the scope of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the disclosure. Thus, it is intended that the present disclosure cover the modifications and variations of this disclosure provided such modifications and variations come within the scope of the appended claims and their equivalents.

Claims

1. A memory interface circuit, comprising: a processor interface circuit; and a signal connection line connecting a power supply end of the memory interface circuit and a power supply end of the processor interface circuit, for applying a voltage of the power supply end of the processor interface circuit to the power supply end of the memory interface circuit after the processor is powered on and before the memory is powered on. 2.The memory interface circuit of claim 1, wherein the memory interface circuit comprises a first switch module, and wherein the first switch module comprises a memory input / output end, a ground end, and the power supply end of the memory interface circuit, and the memory input / output end is connected to the processor interface circuit. 3.The memory interface circuit of claim 2, wherein the memory interface circuit further comprises a first diode and a second diode, and wherein a positive electrode of the first diode is connected to the memory input / output end, and a negative electrode of the first diode is connected to the power supply end of the memory interface circuit, and a negative electrode of the second diode is connected to the memory input / output end, and a positive electrode of the second diode is connected to the ground end. 4.The memory interface circuit of claim 2, wherein the first switch module comprises a first switch tube and a second switch tube, and wherein a gate of the first switch tube is connected to the memory input / output end, a source of the first switch tube is connected to the power supply end of the memory interface circuit, and a drain of the first switch tube is connected to a drain of the second switch tube, and a gate of the second switch tube is connected to the memory input / output end, and a source of the second switch tube is grounded. 5.The memory interface circuit of claim 2, wherein the processor interface circuit comprises a second switch module and a third switch module, and wherein a first end of the second switch module is connected to the power supply end of the processor interface circuit, a second end of the second switch module is grounded, a third end of the second switch module is a processor input / output end, and the processor input / output end is connected to the memory input / output end, and a first end of the third switch module is connected to the power supply end of the processor interface circuit, a second end of the third switch module is grounded, and a third end of the third switch module is connected to the power supply end of the memory interface circuit through the signal connection line. 6.The memory interface circuit of claim 5, wherein the second switch module comprises a third switch tube and a fourth switch tube, and wherein a source of the third switch tube is connected to the power supply end of the processor interface circuit, and a drain of the third switch tube is connected to the processor input / output end, and a drain of the fourth switch tube is connected to the drain of the third switch tube, and a source of the fourth switch tube is grounded. 7.The memory interface circuit of claim 5, wherein the third switch module comprises a fifth switch tube and a sixth switch tube, and wherein a source of the fifth switch tube is connected to the power supply end of the processor interface circuit, and a drain of the fifth switch tube is connected to the third end of the third switch module, and a source of the sixth switch tube is connected to the power supply end of the memory interface circuit through the signal connection line, and a drain of the sixth switch tube is connected to the drain of the fifth switch tube. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The source of the fifth switch tube is connected to the power supply end of the processor interface circuit, and the drain of the fifth switch tube is connected to the power supply end of the memory interface circuit through the signal connection line. The drain of the sixth switch tube is connected to the drain of the fifth switch tube, and the source of the sixth switch tube is grounded.

8. The memory interface circuit of claim 1, further comprising: a first PMIC connected to the power supply end of the memory interface circuit, configured to provide power supply for the memory.

9. The memory interface circuit of claim 8, further comprising: a second PMIC connected to the power supply end of the processor interface circuit, configured to provide power supply for the processor.

10. A memory control method for the memory interface circuit of any one of claims 1-9, comprising: after the system is started, supplying power to the power supply end of the processor interface circuit to power on the processor, and applying the voltage of the power supply end of the processor interface circuit on the power supply end of the memory interface circuit through the signal connection line; supplying power to the power supply end of the memory interface circuit to power on the memory.

11. The memory control method of claim 10, further comprising: after the processor is powered on, opening the switch unit to connect the signal connection line; after the memory is powered on, closing the switch unit to disconnect the signal connection line.

12. The memory control method of claim 10, further comprising: after the memory is powered on, initializing the memory through the processor and performing read-write operation.

13. The memory control method of claim 10, further comprising: supplying power to the power supply end of the processor interface circuit through a first PMIC, and supplying power to the power supply end of the memory interface circuit through a second PMIC.

14. An electronic device, comprising the memory interface circuit of any one of claims 1-9. ​ ​ ​ ​ ​ ​ ​

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