An artificial circuit model structure based on three-dimensional synapse and its preparation method

Abstract

The present invention is an artificial loop model structure based on three-dimensional synapses and a preparation method thereof. The structure is divided into three layers: upper, middle and lower; the bottom layer includes: a substrate, on which second metal oxide doped nanowires are distributed; the vertical sides of the L-shaped first source and first drain are arranged on both sides of the second metal oxide doped nanowires; the middle layer is an ion glue grid dielectric layer, covering the bottom layer; the upper layer includes an L-shaped top source, a first metal oxide doped nanowire, and an L-shaped top drain; wherein the projection position of the top first metal oxide doped nanowire is at an angle of 60 to 90 degrees with the second metal oxide doped nanowire of the bottom layer; the "L-shaped" second source and second drain are placed facing each other. The present invention can realize multi-terminal three-dimensional modulation of synaptic devices and a mutual inhibition mode similar to that in biological neural circuits, which is of great significance to future neural repair and large-scale brain-like integrated computing.

Description

Technical Field

[0001] The present invention relates to the field of electronic devices, in particular to the field of artificial synaptic electronic devices and their systematic applications. Background Art

[0002] A single neuron has the ability to integrate and process information to a certain extent, but to complete a sophisticated and complete neural task, multiple neurons need to form different functional neural microcircuit models through a series of synaptic connection patterns. This is similar to the traditional silicon-based circuits, which use different transistors and logic gates to form a series of complex circuits to ensure that the computer can perform specific functions.

[0003] In real life, neurological dysfunction caused by accidents and diseases may lead to a decline in quality of life or even death. However, since nerve cells are highly differentiated permanent cells, they lose their original decomposition ability, and the nerve sheath cells surrounding nerve cells can secrete an inhibitory factor to inhibit the ability of nerve cells to divide, so nerve cell death is non-regenerative. This makes it difficult to repair and reconstruct the damaged nervous system from a purely medical perspective, which has become a problem that plagues rehabilitation medicine.

[0004] Neuromorphic electronics, which has emerged in recent years, achieves certain neural functions by preparing a series of electronic devices that can simulate the action of biological synapses. However, current research focuses on the simulation of single synapses or the construction of artificial reflex arcs, and the connection and interaction mechanism between multiple neurons has not yet been explored. Therefore, by constructing different artificial synapses and connecting them to form a specific artificial neural circuit model, it can have more complete neural functions, which can bring new hope to neural repair and is expected to achieve reconstruction and repair of missing neural functions in vitro across the lesion area. Summary of the invention

[0005] The purpose of the present invention is to address the deficiencies of current technology and propose an artificial loop model structure based on three-dimensional synapses and a preparation method thereof. The loop model structure is formed into a loop model by printing doped nanowires (upper and lower layers), directional transfer of ion gel gate dielectric layers, connecting the input end of the neuron circuit to the top drain, and connecting the output end of the neuron to the bottom of the gate dielectric. In the preparation method, P-type semiconductor poly 3-hexanethiophene modified by metal nanoparticles is used as a material to constitute the nanowire semiconductor, and its hole conduction function is used to realize the transmission of carriers. The present invention can realize multi-terminal three-dimensional modulation of synaptic devices and a mutual inhibition mode similar to that in biological neural circuits, which is of great significance to future neural repair and large-scale brain-like integrated computing.

[0006] The technical solution of the present invention is as follows:

[0007] A neural circuit model structure based on a three-dimensional synaptic device, the structure is divided into three layers: upper, middle and lower; the bottom layer includes: a substrate, on which a second metal oxide doped nanowire is distributed; the vertical sides of an L-shaped first source and a first drain are arranged on both sides of the second metal oxide doped nanowire, and the bottom sides are opposite, parallel and perpendicular to the nanowire;

[0008] The middle layer is an ion-gel grid dielectric layer, covering the bottom layer;

[0009] The upper layer includes an L-shaped top source, a first metal oxide-doped nanowire, and an L-shaped top drain; wherein the projection position of the top first metal oxide-doped nanowire forms an angle of 60 to 90 degrees with the bottom second metal oxide-doped nanowire; the "L-shaped" second source and second drain are placed facing each other to form a "mouth shape", and the two bottom sides are parallel and perpendicular to the first metal oxide-doped nanowire respectively;

[0010] The artificial neuron outgoing end is connected to the ion glue grid dielectric layer to form an artificial neuron grid, and the incoming end is connected to the L-shaped top drain;

[0011] Wherein, the nanowire semiconductor is poly (3-hexanethiophene) doped with metal oxide nanoparticles, and its diameter is 100nm to 500nm; the doping amount is 0 to 20% (mass variation ratio), preferably 0 or 0.05% to 20%; when the doping amount is 0, it means no doping.

[0012] The ion-gluing dielectric layer is a poly(styrene-b-methyl methacrylate-b-styrene) triblock copolymer containing 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide, with a thickness of 0.5 to 3 mm; the mass ratio is 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide: poly(styrene-b-methyl methacrylate-b-styrene) triblock copolymer = 2 to 5:1;

[0013] Wherein, the source and drain are made of metal, specifically gold or platinum; and their thickness is 80-100 nm;

[0014] The artificial neuron is a leaky integrated and fired model circuit;

[0015] The substrate material is polyethylene naphthalate (PEN) or polyethylene terephthalate (PET);

[0016] The metal oxide is zinc oxide or tungsten oxide;

[0017] The method for preparing a neural circuit phantom based on an artificial synaptic device comprises the following steps:

[0018] 1) Clean and dry the substrate;

[0019] 2) Mixing poly (3-hexanethiophene) with metal oxide nanoparticles and polyethylene oxide in a mass ratio of (9.95-8):(2-0.05):(4-5), and adding the mixture to a mixed solution of trichloroethylene and chlorobenzene in a mass ratio of 4:6-9, wherein the mass fraction of the solid solute is between 4.5% and 6.5%, to form a precursor solution.

[0020] Wherein, the metal oxide nanoparticles are zinc oxide or tungsten oxide;

[0021] 3) After the precursor solution is filled into the printing nozzle, a nanowire semiconductor is obtained by near-field electrodynamic printing, wherein the driving voltage is set to 2-3 kV, the injection speed is set to 100-200 nl / min, and the distance from the nozzle to the PET substrate is set to 2-4 mm, and a single bottom nanowire semiconductor is obtained with a diameter of 100-500 nm;

[0022] 4) using a mask plate to evaporate a single channel electrode on the PET substrate with the bottom nanowire semiconductor attached thereto in 3), wherein the channel width is between 50 and 200 μm and the thickness is between 80 and 100 nm;

[0023] 5) dissolving poly(styrene-b-methyl methacrylate-b-styrene) triblock copolymer and 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide ionic liquid in ethyl acetate, with the mass ratio of each component being 0.7-0.8:9.3-9.2:90. Forming an ion gel gate dielectric layer with a thickness of 0.5-3 mm on a silicon wafer by drop casting;

[0024] 6) Printing a nanowire semiconductor on the upper surface of the ion gel gate medium described in 5) using the printing parameters described in 3), and controlling the driving voltage to obtain a top nanowire with a diameter of 100 to 500 nm;

[0025] 7) evaporating a top electrode on the top nanowire by the method and parameters described in 4);

[0026] 8) The ion gel gate dielectric layer containing the top nanowire semiconductor after vapor deposition in 7) is transferred to the PET substrate with the bottom nanowire semiconductor after vapor deposition described in 4) using a homemade ball-screw directional transfer device, so that the two nanowires form an angle of 60 to 90 degrees.

[0027] 9) Connecting the input end of the neuron circuit to the top drain, and connecting the output end of the neuron to the bottom end of the gate dielectric, to obtain a neural circuit model based on the artificial synaptic device.

[0028] The essential features of the present invention are:

[0029] 1) The performance of nanowire semiconductors is improved by doping with metal oxide nanoparticles;

[0030] 2) A new neuromorphic electronic device structure is designed. The present invention integrates the isolated synaptic devices in structure by constructing a double-layer nanowire artificial synapse stacked vertically on different surfaces, so that there is interaction between the upper and lower layers of devices. This is consistent with the principle that each neural synapse within a specific range in a biological body realizes information transmission and interaction through complex mutual connections.

[0031] 3) An important logical function in biological synapses: mutual inhibition, was successfully achieved by introducing the device design of the present invention and the artificial neuron circuit (previously reported artificial synapses did not have similar functions). This will contribute to the further development of brain-like electronics and has important potential value for nerve replacement and repair.

[0032] The beneficial effects of the present invention are:

[0033] 1) The single artificial synapse is networked into an artificial loop motif through the structure of the present invention, which greatly expands the functional application of the artificial synapse and improves the information processing ability of the artificial synapse.

[0034] 2) Through the interactive relationship between synapses, it is logically more compatible with the organism, making neural replacement and repair based on artificial synapses possible.

[0035] 3) The layered manufacturing and subsequent transfer assembly method of the present invention can achieve multi-layer vertical integration, laying the foundation for large-scale integrated networking of artificial synaptic devices in the future.

[0036] 4) Since the oxide particles tend to take away electrons from the HOMO energy level of poly (3-hexanethiophene), leaving holes to form p-type doping, the carrier concentration in poly (3-hexanethiophene) is increased, thereby improving the performance of the semiconductor nanowires (channel mobility is increased by 11.8 times). BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a schematic diagram of the structure of a neural circuit model based on an artificial synaptic device;

[0038] Figure 2 This is an atomic force microscope topography of a semiconductor nanowire;

[0039] Figure 3 Result plot of line width and height information derived from atomic force microscopy for semiconductor nanowires;

[0040] Figure 4This is a graph showing the result of the neural excitatory postsynaptic current (EPSC) obtained by activating the underlying artificial synapse (synapse 1) alone in Example 1;

[0041] Figure 5 This is a graph showing the result of the excitatory postsynaptic current (EPSC) of the nerve obtained by activating the top artificial synapse (synapse) alone in Example 1;

[0042] Figure 6 This is a graph showing the result of the neural excitatory postsynaptic current (EPSC) of the top synapse when the bottom and top synapses are activated simultaneously, as obtained in Example 1;

[0043] Figure 7 The mobility statistics of semiconductor nanowires at different doping ratios obtained in Examples 1, 2, 3, 4, and 5;

[0044] Figure 8 This is a schematic diagram of neuron circuit connections; DETAILED DESCRIPTION

[0045] The present invention will be specifically described below in conjunction with specific examples. The following examples are helpful for relevant personnel to study and think about the present invention, but will not have any limiting effect on the present invention.

[0046] The structure of the neural circuit model based on the three-dimensional synaptic device of the present invention is as follows: Figure 1 As shown, the structure can be divided into three layers: upper, middle and lower; the bottom layer includes: a flexible PET substrate, on which the second metal oxide doped nanowires 2 are distributed; the vertical sides of the L-shaped first source electrode 1 and the first drain electrode 1 are arranged on both sides of the second metal oxide doped nanowires 2, and the bottom sides are opposite, parallel and perpendicular to the nanowires;

[0047] The middle layer is an ion-gel grid dielectric layer, covering the bottom layer;

[0048] The upper layer includes an L-shaped top source 2, a first metal oxide-doped nanowire 1, and an L-shaped top drain 2; wherein the projection position of the top first metal oxide-doped nanowire is perpendicular to the second metal oxide-doped nanowire 2 of the bottom layer; the "L-shaped" second source and second drain are placed facing each other to form a "mouth shape" (the source and drain are not connected, and there is a gap between them), and the two bottom sides are parallel and respectively perpendicular to the first metal oxide-doped nanowire 1;

[0049] The artificial neuron outgoing end is connected to the ion glue grid dielectric layer to form an artificial neuron grid, and the incoming end is connected to the L-shaped top drain stage 2;

[0050] Embodiment 1:

[0051] An artificial circuit motif structure based on three-dimensional synapse and a preparation method thereof are as follows:

[0052] Loop preparation steps:

[0053] 1) Cleaning a polyethylene terephthalate (PET) sheet with acetone, ethanol, and isopropanol ultrasonically in sequence and then drying the sheet to obtain a flexible PET substrate having a thickness of 0.1 mm;

[0054] 2) poly(3-hexylthiophene), metal oxide nanoparticles, and polyethylene oxide were mixed in a mass ratio of 10:0:5 (i.e., no metal oxide nanoparticles were added in this embodiment), and then added to a mixed solution of trichloroethylene and chlorobenzene in a mass ratio of 4:7, with a solid solute mass fraction of 5%, to form a precursor solution;

[0055] 3) After the precursor solution is filled into the printing nozzle, the nanowire semiconductor is obtained by near-field electrodynamics printing (EHD), wherein the driving voltage is set to 2.7 kV, the injection speed is 150 nl / min, and the distance from the nozzle to the PET substrate is 3 mm, and the bottom nanowire semiconductor is obtained. The atomic force microscope photo of the nanowire semiconductor is shown in the attached figure. Figure 2 As shown in the figure, it is cylindrical in shape and has a relatively uniform surface morphology. The morphological data derived from the results are shown in the attached figure. Figure 3 As shown, it can be seen that the nanowire diameter (i.e., the width of the raised part) is 240 nm;

[0056] 4) Using a mask plate, two L-shaped gold electrodes as described above are deposited on the PET substrate with the bottom nanowire semiconductor attached in 3), namely, the L-shaped bottom source 1 and the L-shaped bottom drain 1. The channel width formed by the two L-shaped electrodes is between 100 and 200 μm, so that the electrodes cover the nanowires with a thickness of 100 nm; the longer side of the L-shaped electrode is 500 μm, the shorter side is 100 μm, and the electrode line width is 15 μm.

[0057] 5) dissolving poly(styrene-b-methyl methacrylate-b-styrene) triblock copolymer and 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide ionic liquid in ethyl acetate, with the mass ratio of each component being 0.7:9.3:90. Forming an ion gel gate dielectric layer with a thickness of 2 mm on a silicon wafer by drop casting;

[0058] 6) Printing nanowire semiconductors on the upper surface of the gel gate dielectric layer using the printing parameters of 3) and the precursor solution of 2), and obtaining a top nanowire 1 with a diameter of 240 nm;

[0059] 7) By the method and parameters described in 4), an L-shaped top gold electrode, i.e., an L-shaped top source 2 and an L-shaped top drain 2, is evaporated on the upper surface of the ion gel to cover the nanowire, the channel width formed by the two L-shaped electrodes is between 100 and 200 μm, the thickness is 100 nm, the longer side of the L-shaped electrode is 500 μm, the shorter side is 100 μm, and the electrode line width is 15 μm 。 The "L-shaped" second source and second drain are placed facing each other to form a "U-shaped" shape, and the two bottom sides are parallel and perpendicular to the first metal oxide-doped nanowires respectively;

[0060] 8) The ion gel gate dielectric layer containing the top nanowire semiconductor after vapor deposition in 7) is peeled off from the silicon wafer using a homemade ball-screw directional transfer device and transferred to the vapor-deposited PET substrate with the bottom nanowire semiconductor attached as described in 4), so that the two nanowires are at a 90° angle.

[0061] 9) The neuron circuit (attached Figure 8 ) is connected to the top drain, and the output of the neuron is connected to the bottom of the gate dielectric to obtain Figure 1 A neural circuit model based on an artificial synaptic device with the structure shown.

[0062] The artificial neuron is a leaky integrated and fired model circuit, which is composed of a LM393 voltage comparator (known and commercially available), a 555 timer (known and commercially available), four 1 kilo-ohm resistors and a 500 μF capacitor according to the following formula: Figure 8 Connect as shown.

[0063] Performance testing and experimental results analysis:

[0064] Using the semiconductor analysis test Keithley 4200A-SCS system, a series of electrical tests were performed on the two-terminal flexible artificial synaptic electronic device prepared in step 9) in a closed glove box filled with nitrogen at an ambient temperature of 25 degrees Celsius to obtain different mobility and synaptic biomimetic behaviors. The test steps are as follows:

[0065] 1) A constant voltage of -0.1v was applied between source 1 and drain 1, and the transfer curve of the device was tested. The input gate 1 scanning voltage was set from -10v to 10v, and the mobility was calculated to be 5×10 -4 cm 2 v -1 s -1

[0066] 2) A constant voltage of -0.1v is applied only between source 1 and drain 1, and five pulse spikes with an amplitude of -3v and a width of 150ms are applied to gate 1 to obtain the postsynaptic current curve of the bottom synapse in the single working state, such as Figure 4 As shown in the figure, it can be seen that as the number of pulses increases, the excitatory current of synapse 1 continues to increase. When the fifth pulse is applied, the excitatory current reaches a maximum value of 1.04 μA, which corresponds to the process of synapse 1 being activated.

[0067] 3) Only a constant voltage of -0.1v is applied between source 2 and drain 2, and 5 pulse spikes with an amplitude of -3v and a width of 150ms are applied to gate 1 to obtain the postsynaptic current curve of the top layer synapse in the single working state, and the activation process of synapse 2 is obtained. The result is similar to 2). However, the maximum current of synapse 2 is 532nA, such as Figure 5 As shown,

[0068] 4) Simultaneously, a source-drain voltage of -0.1v is applied between source 1 and drain 1, and between source 2 and drain 2, and five pulse spikes with an amplitude of -3v and a width of 150ms are applied to gate 1. The postsynaptic current curve of the bottom synapse in the single working state is read. The results are as follows: Figure 6 As shown in Figure 2, we can see that when two layers of synapses are activated at the same time, when the second pulse ends, synapse 1 will be inhibited (i.e., compared to Figure 4 The test results of synapse 1 in the middle show that the 3rd to 5th spikes are significantly reduced). This is because when the top synaptic current exceeds the threshold (500nA), the artificial neuron circuit will emit a 1V positive pulse, which acts on the ion gel medium layer through the neuron gate, thereby inhibiting the bottom synapse. This is consistent with the mutual inhibition loop in biological nerves, which shows that the artificial loop motif in the present invention can play a mutual inhibition role between synapses.

[0069] Example 2

[0070] The other steps are the same as those in Example 1, except that in loop preparation step 2: poly (3-hexanethiophene) is mixed with metal oxide nanoparticles and polyethylene oxide in a mass ratio of 10:0.4:5, and then added to a mixed solution of trichloroethylene and chlorobenzene in a mass ratio of 4:7, with a solid solute mass fraction of 5%, to form a precursor solution; wherein the metal oxide nanoparticles are tungsten oxide with a particle size of 80 nm.

[0071] After the same test as in the performance test and experimental result analysis step 1), the mobility of the nanowire semiconductor field effect transistor synaptic device was calculated to be 9.2×10 -4 cm 2 v -1 s -1

[0072] Example 3

[0073] The other steps are the same as those in Example 2, except that in the loop preparation step 2, poly(3-hexylthiophene), tungsten oxide nanoparticles, and polyethylene oxide are mixed in a mass ratio of 9.2:0.8:5. After the same test as in the performance test and experimental result analysis step 1), the mobility of the nanowire semiconductor field effect transistor synaptic device was calculated to be 5.9×10 - 3 cm 2 v -1 s -1

[0074] Example 4

[0075] The other steps are the same as those in Example 2, except that in the loop preparation step 2, poly(3-hexylthiophene), tungsten oxide nanoparticles, and polyethylene oxide are mixed in a mass ratio of 8.8:1.2:5. After the same test as in the performance test and experimental result analysis step 1), the mobility of the nanowire semiconductor field effect transistor synaptic device was calculated to be 3.4×10 - 3 cm 2 v -1 s -1

[0076] Example 5

[0077] The other steps are the same as those in Example 2, except that in the loop preparation step 2, poly(3-hexylthiophene), tungsten oxide nanoparticles, and polyethylene oxide are mixed in a mass ratio of 8.4:1.6:5. After the same test as in the performance test and experimental result analysis step 1), the mobility of the nanowire semiconductor field effect transistor synaptic device was calculated to be 1.8×10 - 3 cm 2 v -1 s -1

[0078] The mobility calculation results in Examples 1 to 5 are statistically analyzed to obtain the influence of metal oxide nanoparticles on nanowire semiconductors at different doping concentrations. Figure 7 It can be seen that within a certain range, through doping, the oxide particles tend to take away electrons from the HOMO energy level of poly (3-hexanethiophene), leaving holes to form p-type doping, which increases the carrier concentration in poly (3-hexanethiophene) and thus improves the performance of semiconductor nanowires. It can be seen that when the doping amount is 8%, the semiconductor mobility of the nanowire reaches the maximum value of 5.9×10 -3 cm 2 v -1 s-1 , the lowest (undoped, mobility 5×10 -4 cm 2 v -1 s -1 ) increased by 11.8 times.

[0079] The above implementation cases and test results are intended to provide a certain research basis for researchers in related fields. Any other research changes that do not make substantial changes, including modification, simplification, replacement, and other simple changes in experimental conditions, should be within the scope of protection of the present invention.

[0080] Matters not covered by the present invention are known technologies.

Claims

1. A neural circuit model structure based on a three-dimensional synaptic device, characterized by The structure can be divided into three layers: upper, middle and lower. The bottom layer includes: a substrate, on which a second metal oxide doped nanowire is distributed; the vertical sides of the L-shaped first source and the first drain are arranged on both sides of the second metal oxide doped nanowire, and the bottom sides are opposite, parallel and perpendicular to the nanowire; The middle layer is an ion-gel grid dielectric layer, covering the bottom layer; The upper layer includes an L-shaped top source, a first metal oxide-doped nanowire, and an L-shaped top drain; wherein the projection position of the top first metal oxide-doped nanowire forms an angle of 60 to 90 degrees with the bottom second metal oxide-doped nanowire; the "L-shaped" second source and second drain are placed facing each other to form a "square shape", and the two bottom sides are parallel and perpendicular to the first metal oxide-doped nanowire respectively; The outgoing end of the artificial neuron is connected to the ion-gel grid dielectric layer to form the artificial neuron grid, and the incoming end is connected to the L-shaped top drain; Wherein, the nanowire is poly-3-hexanethiophene doped with metal oxide nanoparticles, with a diameter of 100nm~500nm; the doping amount is 0~20%; The ion-gluing dielectric layer is a poly(styrene-b-methyl methacrylate-b-styrene) triblock copolymer containing 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide, with a thickness of 0.5-3 mm; the mass ratio is 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide: poly(styrene-b-methyl methacrylate-b-styrene) triblock copolymer = 2-5:

1.

2. The neural circuit model structure based on the three-dimensional synaptic device according to claim 1, characterized in that the source and drain are made of metal, specifically gold or platinum; and the thickness is 80-100 nm; The artificial neuron is a leaky integrate and fire model circuit; The substrate material is polyethylene naphthalate (PEN) or polyethylene terephthalate (PET); The metal oxide is zinc oxide or tungsten oxide.

3. The neural circuit model structure based on the three-dimensional synaptic device as described in claim 1 is characterized in that the nanowire semiconductor is doped with metal oxide in an amount of 0 or 0.05% to 20%.

4. The method for preparing a neural circuit phantom structure based on a three-dimensional synaptic device according to claim 1, characterized in that the method comprises the following steps: 1) Clean and dry the substrate; 2) Mixing poly (3-hexanethiophene) with metal oxide nanoparticles and polyethylene oxide in a mass ratio of (9.95-8): (2-0.05): (4-5), and adding the mixture to a mixed solution of trichloroethylene and chlorobenzene in a mass ratio of 4:6-9, wherein the mass fraction of the solid solute is between 4.5% and 6.5%, to form a precursor solution; in, The metal oxide nanoparticles are zinc oxide or tungsten oxide; 3) After the precursor solution is filled into the printing nozzle, a nanowire semiconductor is obtained by near-field electrodynamic printing, wherein the driving voltage is set to 2-3 kV, the injection speed is set to 100-200 nl / min, and the distance from the nozzle to the PET substrate is set to 2-4 mm, to obtain a single bottom nanowire semiconductor; 4) using a mask plate to evaporate a single channel electrode on the PET substrate with the bottom nanowire semiconductor attached in 3), wherein the channel width is between 50 and 200 μm and the thickness is between 80 and 100 nm; 5) dissolving poly(styrene-b-methyl methacrylate-b-styrene) triblock copolymer and 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide ionic liquid in ethyl acetate, with the mass ratio of each component being 0.7-0.8:9.3-9.2:90; and forming an ion gel gate dielectric layer with a thickness of 0.5-3 mm on a silicon wafer by drop casting; 6) Printing nanowire semiconductors on the upper surface of the ion gel gate medium described in 5) using the printing parameters described in 3), and obtaining top nanowires by controlling the driving voltage; 7) evaporating a top electrode on the top nanowire using the method and parameters described in 4); 8) The ion gel gate dielectric layer containing the top nanowire semiconductor after evaporation in 7) is transferred to the PET substrate with the bottom nanowire semiconductor after evaporation described in 4) by using a homemade ball-screw directional transfer device, so that the two nanowires are at an angle of 60 to 90 degrees; 9) Connect the input end of the neuron circuit to the top drain, and connect the output end of the neuron to the bottom of the gate dielectric to obtain a neural circuit model structure based on an artificial synaptic device.

Images