Image acquisition method, system and CameraLink acquisition card with built-in JPEG compression algorithm

Abstract

The present invention discloses an image acquisition method, system and CameraLink acquisition card with built-in JPEG compression algorithm, which are based on FPGA. When the JPEG compression algorithm is configured to be disabled, the FPGA only performs transmission processing on the data collected by the CameraLink acquisition card and outputs it through the output end of the CameraLink acquisition card. When the JPEG compression algorithm is configured to be enabled, the following steps are performed: the FPGA receives the CameraLink data and performs preprocessing; the FPGA adjusts the compression effect of the data based on the configured quantization table and executes the JPEG compression algorithm to compress the data into a JPEG file, which is output through the output end of the CameraLink acquisition card; the configuration of the quantization table includes: configuring quantization factors and / or configuring standard quantization tables. The present invention solves the bandwidth requirements for large-capacity data processing, provides a flexible JPEG algorithm parameter setting function, and minimizes the requirements for data processing bandwidth while ensuring detection accuracy, thereby reducing the cost of the entire machine.

Description

Technical Field

[0001] The present invention relates to the technical field of data acquisition systems, and in particular to an image acquisition method and system with a built-in JPEG compression algorithm and a CameraLink acquisition card. Background Art

[0002] The increasing requirements for detection accuracy in the field of machine vision have led to a continuous increase in the amount of data output by a single camera. On the other hand, in order to cope with the detection of large-sized targets (such as large-sized PCB circuit boards), it is necessary to splice the data of multiple cameras together. This results in a very large amount of data received by the computer, and the machine vision industry usually requires real-time detection, that is, the computer must complete the analysis and processing of large-capacity data in real time, so as to give results in real time and guide the industrial production process. In some application scenarios, the detection target actually has very typical characteristics. Through some compression algorithms, the amount of data required to be processed can be greatly reduced without affecting the detection results. At present, these compression algorithms are usually implemented on the computer side through software. Because compression algorithms generally contain a large number of multiplication operations, they will greatly occupy the CPU bandwidth, affect the response rate of the whole machine, and then affect the production efficiency. Therefore, a hardware method is urgently needed, coupled with a flexible configuration solution, to solve this problem.

[0003] Traditional data acquisition systems in the field of machine vision are usually implemented by industrial cameras and acquisition cards. Industrial cameras complete the acquisition and preprocessing of raw data, and then pass the data to the CameraLink acquisition card through the standard CameraLink interface. After the CameraLink acquisition card completes the splicing of image data according to the standard protocol, it passes it to the computer through the PCIe interface to complete the final image processing and recognition. The ideal way is to complete the data compression work in the CameraLink acquisition card, thereby reducing the data processing pressure on the computer side. However, the function completed by the traditional CameraLink acquisition card is only to process the order of data arrangement, and does not interfere with the data content, that is, the CameraLink acquisition card itself does not affect the total data volume.

[0004] Compression algorithms are generally divided into lossy algorithms and lossless algorithms. Lossy compression is a compression algorithm that loses data accuracy. For example, the JPEG compression algorithm is usually a lossy algorithm. The advantage of lossy algorithms is that they can reduce the amount of data as much as possible while meeting application requirements. Unlike the communication field, one of the main application scenarios in the field of machine vision is target object recognition (such as defect recognition), so in principle, it is not necessary to retain a large amount of original data information without distortion. Under the premise of not affecting the recognition accuracy, some lossy processing can be performed on the original data to reduce the requirements for data processing bandwidth, thereby reducing system costs, which is very beneficial for certain application scenarios.

[0005] Field Programmable Gate Array (FPGA) is a very popular programming device. Its flexible configuration and programmability make it widely used in various fields. Because FPGA is a hardware implementation method with high parallel processing degree, it can cope with high-speed data acquisition scenarios. Therefore, FPGA is also widely used in high-speed data acquisition applications. Usually, FPGA completes the entire process of data acquisition, processing, and transmission. For the CameraLink acquisition card widely used in the field of machine vision, because it is necessary to transfer data to the computer for processing in real time, FPGA is usually a key component in the CameraLink acquisition card. In order to reduce the data processing bandwidth requirements on the computer side and maintain the real-time nature of the data, it is required to implement the JPEG real-time compression algorithm in the FPGA, and at the same time, the compression accuracy is required to be controllable to meet the requirements for data (recognition) accuracy in different scenarios. Although the JPEG compression algorithm is usually classified as a lossy algorithm, the core source of its loss is that data accuracy will be lost during the quantization process (not considering the loss of calculation accuracy, such as the limited preservation of decimal places). Quantization is completed using a quantization table. By designing different quantization tables, the data loss accuracy can be controlled, that is, the compression ratio can be controlled. On the other hand, JPEG lossless compression can also be performed through a special quantization table, for example, the quantization coefficients are all set to 1. This reflects the greatest flexibility and can be flexibly adapted to different application scenarios.

[0006] The traditional CameraLink acquisition card does not process the data content, but only reorganizes the data arrangement order according to the CameraLink protocol to complete the construction of the complete image data, so the total amount of data remains unchanged. From the perspective of data flow, the data is sent from the camera end, connected to the acquisition card through the CameraLink interface, passes through various modules in the acquisition card, including DDR, and is finally uploaded to the computer through the PCIe interface.

[0007] In the data flow link, the acquisition card has two main functions. The first is to complete the matching of the data interface. Ordinary computers do not have a CameraLink interface, so they cannot directly receive data from industrial cameras and must use an acquisition card to complete the camera data reception. The second is to complete the data format conversion: the image data sent by the camera is segmented, and the data must be spliced ​​and reorganized by the acquisition card to obtain an image with normal data arrangement, so that the computer can analyze and process it. In general, the acquisition card does not process the data content, that is, the total amount of data does not change. When multiple camera data need to be processed in parallel, high requirements are placed on the computer's data processing bandwidth.

[0008] JPEG is a commonly used compression algorithm currently. It is usually classified as a lossy compression algorithm, but in fact JPEG can also be lossless compression. It’s just that JPEG works in lossy compression mode in most cases to reduce the amount of data. Summary of the invention

[0009] The present invention proposes an image acquisition method with a built-in JPEG compression algorithm, which can solve the conflict between the growing demand for large-capacity data processing bandwidth in the field of machine vision and the limited data processing bandwidth on the computer side.

[0010] To achieve the above object, the present invention adopts the following technical solutions:

[0011] An image acquisition method with built-in JPEG compression algorithm, based on FPGA, the specific steps are as follows:

[0012] When the JPEG compression algorithm is configured to be disabled, the FPGA only performs transmission processing on the data collected by the CameraLink acquisition card and outputs it through the output port of the CameraLink acquisition card;

[0013] When the JPEG compression algorithm is configured to be enabled, the following steps are performed:

[0014] The FPGA receives the data collected and pre-processed by the CameraLink acquisition card;

[0015] The FPGA adjusts the data compression effect based on the configured quantization table and executes the JPEG compression algorithm to compress the data into a PEG file, which is then output through the output port of the CameraLink acquisition card.

[0016] The configuration of the quantization table includes: configuring a quantization factor and / or configuring a standard quantization table.

[0017] Furthermore, the configuration standard quantization table includes: a brightness table in the configuration standard quantization table and / or a chromaticity table in the configuration standard quantization table.

[0018] Furthermore, the configuration of the quantization table includes directly selecting one from several sets of quantization tables with preset parameters.

[0019] Furthermore, the JPEG file includes JPEG header information, compressed data stream, and JPEG trailer information. The header information of the JPEG file is fixedly stored in the CameraLink acquisition card; the FPGA directly reads the header information of the JPEG file when executing the JPEG compression algorithm.

[0020] On the other hand, the present invention also discloses an image acquisition system with a built-in JPEG real-time compression algorithm, comprising:

[0021] A data receiving and processing module is used to receive and pre-process the data captured by the camera;

[0022] The parameter configuration module is used to configure the quantization table in the JPEG compression algorithm and whether the JPEG compression algorithm is enabled or not;

[0023] The JPEG algorithm execution module executes the JPEG compression algorithm in the FPGA and constructs a JPEG file according to the quantization table configured by the quantization table configuration module;

[0024] Output module, used to output data to external devices;

[0025] When the parameter configuration module configures the quantization table in the JPEG compression algorithm, the configuration content includes quantization factors and / or standard quantization tables;

[0026] When the parameter configuration module configures the JPEG compression algorithm to be disabled, the JPEG algorithm execution module does not perform JPEG compression on the data; when the parameter configuration module configures the JPEG compression algorithm to be enabled, the JPEG algorithm execution module performs JPEG compression on the data.

[0027] Furthermore, the standard quantization table includes: a brightness table in the standard quantization table and / or a chrominance table in the standard quantization table.

[0028] Furthermore, the parameter configuration module includes several sets of quantization tables with preset parameters. When the parameter configuration module configures the quantization table in the JPEG compression algorithm, the quantization table with preset parameters is directly selected.

[0029] In another aspect, the present invention further discloses a CameraLink acquisition card with a built-in JPEG real-time compression algorithm, including a CameraLink interface, a DDR, an output interface, and an FPGA for executing the JPEG compression algorithm;

[0030] The FPGA adjusts the effect of data compression according to a quantization table of configurable parameters;

[0031] The quantization table configuration content of the configurable parameters includes quantization factors and / or standard quantization tables;

[0032] When the JPEG compression algorithm is configured to be disabled, the FPGA does not perform JPEG compression on the data; when the JPEG compression algorithm is configured to be enabled, the FPGA performs JPEG compression on the data.

[0033] Furthermore, the configuration of the quantization table includes directly selecting one from several sets of quantization tables with preset parameters; the standard quantization table also includes: a brightness table in the standard quantization table and / or a chromaticity table in the standard quantization table.

[0034] Furthermore, the JPEG file includes JPEG header information, compressed data stream, and JPEG trailer information. The header information of the JPEG file is fixedly stored in the CameraLink acquisition card; the FPGA directly reads the header information of the JPEG file when executing the JPEG compression algorithm.

[0035] It can be seen from the above technical scheme that the image acquisition method, system and CameraLink acquisition card with built-in JPEG compression algorithm of the present invention use FPGA, which is a hardware programmable device. On the basis of completing the functions of the traditional CameraLink data acquisition card, it adds JPEG algorithm support and releases a part of the CPU processing bandwidth on the computer side to solve the conflict between the growing demand for large-capacity data processing bandwidth in the field of machine vision and the limited data processing bandwidth on the computer side. It provides a flexible JPEG algorithm parameter setting function to minimize the requirements for data processing bandwidth while taking into account the detection accuracy, thereby reducing the cost of the entire system.

[0036] In general, the present invention designs a CameraLink acquisition card with a JPEG real-time compression algorithm, which alleviates the conflict between the growing demand for large-capacity data processing bandwidth in the field of machine vision and the limited data processing bandwidth on the computer side, and provides a flexible JPEG algorithm parameter setting function to minimize the amount of data uploaded to the computer while taking into account the detection accuracy, thereby reducing the requirement for the computer side data processing bandwidth and further reducing the cost of the whole machine. This is very effective in certain application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 The present invention is an image acquisition system with built-in JPEG real-time compression algorithm;

[0038] Figure 2 The present invention is a CameraLink acquisition card with built-in JPEG real-time compression algorithm;

[0039] Figure 3It is a data acquisition system based on CameraLink acquisition card;

[0040] Figure 4 It is the basic principle of JPEG compression algorithm;

[0041] Figure 5 Build schematics for standard JPEG files;

[0042] Figure 6 The present invention is a schematic diagram of a specific implementation of a CameraLink acquisition card with a JPEG real-time compression algorithm. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.

[0044] The traditional CameraLink acquisition card mainly completes the data reception of the CameraLink interface, and then completes the data splicing according to the data protocol, and finally transmits the spliced ​​data to the computer through the PCIe interface. In order to ensure the real-time nature of the data, the data must be transmitted to the computer in real time for analysis and processing, so as to control industrial production in real time. Based on this, this embodiment discloses the following invention:

[0045] First, this embodiment discloses an image acquisition method with a built-in JPEG compression algorithm, based on FPGA.

[0046] When the JPEG compression algorithm is configured to be disabled, the FPGA only performs transmission processing on the data collected by the CameraLink acquisition card and outputs it through the output end of the CameraLink acquisition card. This means that when the JPEG compression algorithm is configured to be disabled, the FPGA only performs conventional acquisition card data processing on the data collected by the CameraLink acquisition card. The process is that the acquisition card only receives the image data received by the CameraLink interface, does not compress the data, and sends the original data to the PC through the PCIe interface.

[0047] When the JPEG compression algorithm is configured to be enabled, the following steps are performed:

[0048] FPGA receives data collected and preprocessed by the CameraLink acquisition card; the preprocessing is that the acquisition card receives and processes the CameraLink interface data, and splices the original data, including data rearrangement and data alignment, so that the image is cached in memory in units of lines;

[0049] The FPGA adjusts the data compression effect based on the configured quantization table and executes the JPEG compression algorithm to compress the data into a JPEG file, which is output through the output end of the CameraLink acquisition card, specifically to an external device such as a PC.

[0050] The configuration of the quantization table includes: configuring a quantization factor and / or configuring a standard quantization table, wherein when the quantization factor is configured, it is a simplified mode, and when the quantization factor and the standard quantization table are configured, it is a complex mode;

[0051] The configuration of the standard quantization table includes: configuring a brightness table in the standard quantization table and / or configuring a chromaticity table in the standard quantization table; specifically, configuring the brightness table and / or chromaticity table according to the image format. When the acquisition card acquires black-and-white photos, the quantization factor and the brightness table are configured, and the acquisition card executes the black-and-white mode. When the acquisition card acquires color photos, the quantization factor, the brightness table and the chromaticity table are configured, and the acquisition card executes the color mode.

[0052] The configuration of the quantization table includes directly selecting one from several sets of quantization tables with preset parameters.

[0053] The JPEG file includes JPEG header information, compressed data stream, and JPEG tail information. The header information of the JPEG file is fixedly stored in the CameraLink acquisition card; the FPGA directly reads the header information of the JPEG file when executing the JPEG compression algorithm.

[0054] Accordingly, the present invention also discloses an image acquisition system with a built-in JPEG real-time compression algorithm, such as Figure 1 As shown, including:

[0055] A data receiving and processing module is used to receive and pre-process the data captured by the camera;

[0056] The parameter configuration module is used to configure the quantization table in the JPEG compression algorithm and whether the JPEG compression algorithm is enabled or not;

[0057] The JPEG algorithm execution module executes the JPEG compression algorithm in the FPGA and constructs a JPEG file according to the quantization table configured by the quantization table configuration module;

[0058] Output module, used to output data to external devices;

[0059] When the parameter configuration module configures the quantization table in the JPEG compression algorithm, the configuration content includes quantization factors and / or standard quantization tables;

[0060] When the parameter configuration module configures the JPEG compression algorithm to be disabled, the JPEG algorithm execution module does not perform JPEG compression on the data; when the parameter configuration module configures the JPEG compression algorithm to be enabled, the JPEG algorithm execution module performs JPEG compression on the data.

[0061] The standard quantization table includes: a brightness table in the standard quantization table and / or a chrominance table in the standard quantization table.

[0062] The parameter configuration module includes several sets of quantization tables with preset parameters. When the parameter configuration module configures the quantization table in the JPEG compression algorithm, the quantization table with preset parameters is directly selected.

[0063] In another aspect, the present invention also discloses a CameraLink acquisition card with a built-in JPEG real-time compression algorithm, including a CameraLink interface, a DDR, an output interface, and an FPGA for executing the JPEG compression algorithm, such as Figure 2 shown.

[0064] The FPGA adjusts the effect of data compression according to a quantization table of configurable parameters;

[0065] The quantization table configuration content of the configurable parameters includes quantization factors and / or standard quantization tables;

[0066] When the JPEG compression algorithm is configured to be disabled, the FPGA does not perform JPEG compression on the data; when the JPEG compression algorithm is configured to be enabled, the FPGA performs JPEG compression on the data.

[0067] Likewise, the configuration of the quantization table includes directly selecting one from several sets of quantization tables with preset parameters; the standard quantization table also includes: a brightness table in the standard quantization table and / or a chromaticity table in the standard quantization table.

[0068] The JPEG file includes JPEG header information, compressed data stream, and JPEG tail information. The header information of the JPEG file is fixedly stored in the CameraLink acquisition card; the FPGA directly reads the header information of the JPEG file when executing the JPEG compression algorithm.

[0069] The following is a detailed description with reference to the accompanying drawings:

[0070] Usually data splicing is done by FPGA combined with DDR, see Figure 3 As shown in the figure, the CameraLink acquisition card is mainly divided into the CameraLink interface data receiving module, the data splicing module, and the PCIe interface data sending module:

[0071] The CameraLink interface data receiving module is composed of a CameraLink interface and a driver module thereof;

[0072] The data splicing module is composed of data preprocessing, DDR module, and data post-processing;

[0073] The PCIe interface data sending module is composed of a PCIe interface driving module and a PCIe interface.

[0074] Figure 4 As shown in the typical flow chart of JPEG compression algorithm, the source of loss is Figure 4 The quantization process in the data center has different loss levels and compression ratios depending on the setting of the quantization table coefficients. Of course, the difference in the original data itself will also affect the compression ratio, which requires that the control of the data flow must be flexible enough to cope with the fluctuations in the data rate caused by the instantaneous compression ratio fluctuations, that is, DDR cache is needed, combined with Figure 3 , the hardware structure of the traditional acquisition card can well adapt to the requirements of the JPEG algorithm. The entropy coding in the JPEG compression algorithm process does not lose precision, and entropy coding will also contribute to a certain compression rate, but the main source of JPEG compression rate is the reduced data difference after quantization, so simply adjusting the quantization table can greatly affect the compression rate, that is, between the loss of precision and the compression ratio, a balance can be achieved through the design of the quantization table. Of course, under a special quantization table, JPEG can achieve lossless compression. If the quantization coefficients are all 1, JPEG still has a certain compression ratio at this time, which mainly comes from the entropy coding process. By designing the quantization table to be completely user-configurable: each quantization coefficient can be set separately, requiring professional users; at the same time, multiple sets of quantization tables for typical application scenarios are provided for selection: users choose ready-made quantization tables to reduce the professional requirements for customers; it can adapt to customer needs in different scenarios, while maintaining detection accuracy, reduce the amount of data processed, and improve detection efficiency.

[0075] The original architecture of the CameraLink acquisition card with built-in DDR cache is very suitable for embedding the JPEG compression algorithm. The compression ratio of the JPEG compression algorithm is not only affected by the parameters of the algorithm itself, but also greatly affected by the complexity of the original data. Although on average, the amount of data after JPEG compression can generally be guaranteed to be smaller than the amount of original data, the instantaneous compression rate will still fluctuate or even fluctuate greatly. Therefore, a certain amount of data cache is needed to solve the problem of instantaneous compression rate fluctuations and avoid the problem that when the instantaneous compression rate is less than 1, the amount of compressed data is greater than the original data, resulting in data overflow and then data confusion.

[0076] In order to ensure the real-time data rate and avoid problems caused by interleaving reads and writes, CameraLink acquisition cards generally use a ping-pong cache to process data, that is, writing to one cache while reading another cache. In the absence of the JPEG compression algorithm, the bandwidth of the read end is limited by the DDR read and PCIe interface rates, and is generally much larger than the write end. The write end is mainly limited by the CameraLink interface rate, and the JPEG compression algorithm can usually ensure that the amount of compressed data is less than the original (pre-compression) data. Therefore, within a certain period of time, the amount of data processed at a time is sufficient to smooth out the impact of instantaneous compression fluctuations. Therefore, after adding the JPEG algorithm module, the original acquisition card cache strategy can be slightly modified, that is, to ensure the minimum data amount of the ping-pong cache.

[0077] Another problem that needs to be solved is that the amount of data after the JPEG compression algorithm changes with the complexity of the original data, that is, the result of encoding a fixed-length data stream is a variable-length data stream. The acquisition card simplifies the data receiving logic on the computer side by constructing a complete JPEG file and uploading it to the computer side, so that the computer side can directly process the data stream in the same way as it processes JPEG files. Figure 5 The figure shows the principle diagram of constructing a standard JPEG file. A JPEG file is composed of a series of JPEG headers, compressed data streams, and JPEG trailers. Most of the header information is fixed, so a storage method is used to save this information. It can be saved in DDR and directly read and used when constructing a JPEG file to avoid poor flexibility and code redundancy caused by hard coding.

[0078] The following examples illustrate:

[0079] A specific implementation diagram of a CameraLink acquisition card with a JPEG real-time compression algorithm in the present invention is shown in FIG. Figure 6 shown.

[0080] After the acquisition card is powered on, it will first complete the self-test, and the key core modules will perform self-tests to confirm that all modules are working properly after the acquisition card is powered on; the key core modules include the CameraLink interface data receiving module, the data preprocessing module, the DDR module, and the PCIe interface driver module. After the acquisition card is powered on, it is confirmed that all modules are working properly. Then wait for the computer to turn on the acquisition card device for operation. After the computer turns on the acquisition card device, configure whether the JPEG algorithm is enabled. If it is configured to be disabled, the acquisition card is configured to the normal card mode. At this time, the data stream will skip the JPEG algorithm module and work in the normal CameraLink acquisition card mode. The computer receives the original data stream.

[0081] If the configuration is enabled, two sub-modes are provided for users to choose: one is the simplified mode, in which users only need to configure the quantization factor. The quantization table required in the JPEG algorithm is obtained by multiplying the standard quantization table by the quantization factor. This mode can cope with most scenarios where compression details do not need to be particularly concerned. For general customers, it not only achieves the purpose but also simplifies the configuration process; the other is the complex mode, in which you need to select the color / black and white mode, and then configure the specific quantization table according to the color / black and white mode. For the black and white mode, configure the quantization factor and brightness table, and for the color mode, configure the quantization factor, brightness table and chromaticity table. This mode can control the compression effect more finely and professionally, and is suitable for users with high professionalism. After completing the JPEG quantization table configuration, the configuration of other parameters can be carried out in the same way as for ordinary cards.

[0082] When the JPEG algorithm is enabled, the data received by the computer is no longer a raw data stream, but a series of independent and complete JPEG files. According to the original image resolution configured by the user, the length of each JPEG file is different due to the difference in the original data. That is, after the same amount of original image data is compressed by JPEG, the length of the final JPEG file is different depending on the image content. The JPEG file complies with the JPEG protocol standard and can be used directly, including third-party JPEG tools can read and process it, which greatly simplifies the processing work on the PC side.

[0083] In summary, the embodiment of the present invention designs a CameraLink acquisition card with a JPEG real-time compression algorithm, which alleviates the conflict between the growing demand for large-capacity data processing bandwidth in the field of machine vision and the limited data processing bandwidth on the computer side, and provides a flexible JPEG algorithm parameter setting function to minimize the amount of data uploaded to the computer while taking into account the detection accuracy, thereby reducing the requirement for the data processing bandwidth on the computer side and further reducing the cost of the whole machine. This is very effective in certain application scenarios.

[0084] In yet another aspect, the present invention further discloses a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the processor executes the steps of any of the above methods.

[0085] On the other hand, the present invention further discloses a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of any of the above methods.

[0086] In another embodiment provided by the present application, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute the steps of any method in the above embodiments.

[0087] It is understandable that the system provided by the embodiment of the present invention corresponds to the method provided by the embodiment of the present invention, and the explanation, examples and beneficial effects of the relevant contents can refer to the corresponding parts in the above method.

[0088] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a non-volatile computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0089] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An image acquisition method with built-in JPEG compression algorithm, based on FPGA, characterized by: When the JPEG compression algorithm is configured to be disabled, the FPGA only performs transmission processing on the data collected by the CameraLink acquisition card and outputs it through the output port of the CameraLink acquisition card; When the JPEG compression algorithm is configured to be enabled, the following steps are performed: The FPGA receives the data collected and pre-processed by the CameraLink acquisition card; The preprocessing is that the acquisition card receives and processes the CameraLink interface data, and splices the original data, including data rearrangement and data alignment, so that the image is cached in memory in units of lines; The FPGA adjusts the data compression effect based on the configured quantization table and executes the JPEG compression algorithm to compress the data into a JPEG file, which is then output through the output port of the CameraLink acquisition card. The configuration of the quantization table includes: configuring a quantization factor and / or configuring a standard quantization table; If the JPEG compression algorithm is configured to be disabled, the capture card is configured in normal card mode. In this case, the data stream will skip the JPEG algorithm module and work in the same way as a normal CameraLink capture card. The computer receives the original data stream. If the JPEG compression algorithm is configured as the enable mode, two sub-modes are provided for the user to choose: one is the simplified mode, in which the user only needs to configure the quantization factor. The quantization table required in the JPEG algorithm is obtained by multiplying the standard quantization table by the quantization factor; the other is the complex mode, in which the color / black and white mode needs to be selected, and then the specific quantization table is configured according to the color / black and white mode. For the black and white mode, the quantization factor and brightness table are configured, and for the color mode, the quantization factor, brightness table and chromaticity table are configured; after completing the JPEG quantization table configuration, the configuration of other parameters can be carried out in the same way as for ordinary cards; The JPEG file includes JPEG header information, compressed data stream, and JPEG tail information. The header information of the JPEG file is fixedly stored in the CameraLink acquisition card; the FPGA directly reads the header information of the JPEG file when executing the JPEG compression algorithm.

2. The image acquisition method with built-in JPEG compression algorithm according to claim 1, characterized in that: The configuration of the quantization table includes directly selecting one from several sets of quantization tables with preset parameters.

3. An image acquisition system with built-in JPEG real-time compression algorithm, comprising: A data receiving and processing module is used to receive and pre-process the data captured by the camera; The preprocessing is that the acquisition card receives and processes the CameraLink interface data, and splices the original data, including data rearrangement and data alignment, so that the image is cached in memory in units of lines; The parameter configuration module is used to configure the quantization table in the JPEG compression algorithm and whether the JPEG compression algorithm is enabled or not; The JPEG algorithm execution module executes the JPEG compression algorithm in the FPGA and constructs a JPEG file according to the quantization table configured by the quantization table configuration module; Output module, used to output data to external devices; When the parameter configuration module configures the quantization table in the JPEG compression algorithm, the configuration content includes quantization factors and / or standard quantization tables; When the parameter configuration module configures the JPEG compression algorithm to be disabled, the JPEG algorithm execution module does not perform JPEG compression on the data; when the parameter configuration module configures the JPEG compression algorithm to be enabled, the JPEG algorithm execution module performs JPEG compression on the data; If the JPEG compression algorithm is configured to be disabled, the capture card is configured in normal card mode. In this case, the data stream will skip the JPEG algorithm module and work in the same way as a normal CameraLink capture card. The computer receives the original data stream. If the JPEG compression algorithm is configured as enabled mode, two sub-modes are provided for the user to choose: one is the simplified mode, in which the user only needs to configure the quantization factor. The quantization table to be used in the JPEG algorithm is obtained by multiplying the standard quantization table by the quantization factor; The other is a complex mode, in which case you need to select a color / black and white mode, and then configure a specific quantization table according to the color / black and white mode. For the black and white mode, configure the quantization factor and brightness table, and for the color mode, configure the quantization factor, brightness table, and chromaticity table. After completing the JPEG quantization table configuration, other parameters can be configured in the same way as ordinary cards; The JPEG file includes JPEG header information, compressed data stream, and JPEG tail information. The header information of the JPEG file is fixedly stored in the CameraLink acquisition card; the FPGA directly reads the header information of the JPEG file when executing the JPEG compression algorithm.

4. The image acquisition system with built-in JPEG real-time compression algorithm according to claim 3, characterized in that: The parameter configuration module includes several sets of quantization tables with preset parameters. When the parameter configuration module configures the quantization table in the JPEG compression algorithm, the quantization table with preset parameters is directly selected.

5. A CameraLink acquisition card with built-in JPEG real-time compression algorithm, including a CameraLink interface, DDR, FPGA and output interface, characterized in that: The FPGA adjusts the compression effect of the data according to the quantization table of configurable parameters and executes the JPEG compression algorithm; The quantization table configuration content of the configurable parameters includes quantization factors and / or standard quantization tables; When the JPEG compression algorithm is configured to be disabled, the FPGA does not perform JPEG compression on the data; when the JPEG compression algorithm is configured to be enabled, the FPGA performs the JPEG compression algorithm on the data and constructs a JPEG file; If the JPEG compression algorithm is configured to be disabled, the capture card is configured in normal card mode. In this case, the data stream will skip the JPEG algorithm module and work in the same way as a normal CameraLink capture card. The computer receives the original data stream. If the JPEG compression algorithm is configured as enabled mode, two sub-modes are provided for the user to choose: one is the simplified mode, in which the user only needs to configure the quantization factor. The quantization table to be used in the JPEG algorithm is obtained by multiplying the standard quantization table by the quantization factor; The other is a complex mode, in which case you need to select a color / black and white mode, and then configure a specific quantization table according to the color / black and white mode. For the black and white mode, configure the quantization factor and brightness table, and for the color mode, configure the quantization factor, brightness table, and chromaticity table. After completing the JPEG quantization table configuration, other parameters can be configured in the same way as ordinary cards; The FPGA receives the data collected and pre-processed by the CameraLink acquisition card; The preprocessing is that the acquisition card receives and processes the CameraLink interface data, and splices the original data, including data rearrangement and data alignment, so that the image is cached in memory in units of lines; The JPEG file includes JPEG header information, compressed data stream, and JPEG tail information. The header information of the JPEG file is fixedly stored in the CameraLink acquisition card; the FPGA directly reads the header information of the JPEG file when executing the JPEG compression algorithm.

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