Comparator and decision feedback equalization circuit

Abstract

The application provides a comparator and a decision feedback equalization circuit. The comparator comprises: a first input circuit provided with two pairs of tubes, the two pairs of tubes are different in type, the two pairs of tubes are used for receiving a first input signal and a first reference signal, and are further used for generating a first differential signal according to the first input signal and the first reference signal in a sampling stage, and a first positive feedback circuit is used for accelerating the difference between the first differential signal; a second input circuit provided with two pairs of tubes, the two pairs of tubes are different in type, the two pairs of tubes are used for receiving a second input signal and a second reference signal, and are further used for generating a second differential signal according to the second input signal and the second reference signal in a sampling stage, a second positive feedback circuit is used for accelerating the difference between the second differential signal, and an output circuit is used for amplifying and latching the voltage signals of the output end of the first input circuit and the output end of the second input circuit in a regeneration stage, and outputting a comparison result.

Description

Technical Field

[0001] This application relates to integrated circuits, and more particularly to a comparator and a decision feedback equalization circuit. Background Technology

[0002] Today, people's demand for mobile devices such as smartphones, tablets, and various wearable accessories has increased significantly, greatly enriching our daily lives and work.

[0003] However, due to limited battery life, higher demands are placed on the power consumption of various components in mobile devices. Dynamic Random Access Memory (DRAM) is an essential component in mobile devices, therefore, DRAM also urgently needs to achieve lower operating voltage and lower power consumption. Among these, the comparator is a crucial device for realizing DRAM data read and write operations, and existing comparators cannot meet current usage requirements. Summary of the Invention

[0004] This application provides a comparator and a decision feedback equalization circuit, which aims to improve the comparator's response rate and comparison accuracy, reduce the comparator's power consumption, expand the amplitude range of the comparator's reference signal, and provide a decision feedback equalization circuit that can eliminate inter-symbol interference, thereby improving the accuracy of the circuit output results.

[0005] In a first aspect, this application provides a comparator having four input terminals and two output terminals, including:

[0006] The first input circuit has two pairs of transistors of different types. The control terminals of the two pairs of transistors serve as the input terminals of the comparator. The two pairs of transistors are used to receive the first input signal and the first reference signal, and are also used to generate the first differential signal based on the first input signal and the first reference signal during the sampling stage.

[0007] The first positive feedback circuit is connected to the output of the first input circuit and is used to accelerate the difference between the first differential signals.

[0008] The second input circuit has two pairs of transistors of different types. The control terminals of the two pairs of transistors serve as the input terminals of the comparator. The two pairs of transistors are used to receive the second input signal and the second reference signal, and are also used to generate the second differential signal based on the second input signal and the second reference signal during the sampling stage.

[0009] The second positive feedback circuit is connected to the output of the second input circuit and is used to accelerate the difference between the second differential signals.

[0010] The output circuit has an input terminal and an output terminal. Its output terminal is the output terminal of the comparator, and its input terminal is connected to the output terminal of the first input circuit. It is used to amplify and latch the voltage signal at the output terminal of the first input circuit and the voltage signal at the output terminal of the second input circuit during the regeneration phase, so as to output the comparison result.

[0011] In a second aspect, this application provides a decision feedback equalization circuit, characterized in that it includes four comparators involved in the first aspect and optional schemes, which are sequentially labeled as a first comparator, a second comparator, a third comparator and a fourth comparator;

[0012] The first comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal connected to the first output terminal of the fourth comparator, and a fourth input terminal connected to the second output terminal of the fourth comparator.

[0013] The second comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal connected to the first output terminal of the first comparator, and a fourth input terminal connected to the second output terminal of the first comparator.

[0014] The third comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal connected to the first output terminal of the second comparator, and a fourth input terminal connected to the second output terminal of the second comparator.

[0015] The fourth comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal connected to the first output terminal of the third comparator, and a fourth input terminal connected to the second output terminal of the third comparator.

[0016] This application provides a comparator and a decision feedback equalization circuit. Two sets of transistors of different types receive a first input signal and a first reference signal, or a second input signal and a second reference signal. Because the two sets of transistors pull the voltage in opposite directions, even if the difference between the first input signal and the first reference signal, or the difference between the second input signal and the second reference signal, is small, the pulling capabilities of the transistors in the two sets of transistors will be unbalanced. This can generate differential signals at the two output terminals of the input circuit. The output circuit amplifies and latches the differential signals before outputting the comparison result, thereby improving the comparator's comparison accuracy. Since the first input circuit uses two sets of transistors to receive the first input signal and the first reference signal, or since the second input circuit uses two sets of transistors to receive the second input signal and the second reference signal, the different pulling capabilities of the two sets of transistors in different voltage directions increase the response time of the first or second input circuit. The first or second positive feedback circuit accelerates the difference between the differential signals, shortens the sampling stage time, thereby improving the comparator's response rate and reducing its power consumption. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] Figure 1 A specific circuit diagram of a comparator provided in this application;

[0019] Figure 2 The timing diagram of the comparator provided in this application;

[0020] Figure 3 A structural block diagram of a comparator provided in this application;

[0021] Figure 4 For based on Figure 3 A specific circuit diagram of one type of comparator is provided;

[0022] Figure 5 For based on Figure 3 A specific circuit diagram of another comparator is provided;

[0023] Figure 6 A structural block diagram of a comparator provided in this application;

[0024] Figure 7 For based on Figure 6 A specific circuit diagram of one type of comparator is provided;

[0025] Figure 8 for Figure 7 The specific circuit diagrams of the first and second controllable feedback modules in the provided comparator are shown below.

[0026] Figure 9 For based on Figure 6 A specific circuit diagram of another comparator is provided;

[0027] Figure 10 for Figure 7 The specific circuit diagrams of the first and second controllable feedback modules in the provided comparator are shown below.

[0028] Figure 11 A block diagram of a decision feedback equalization circuit provided in this application;

[0029] Figure 12 A schematic diagram illustrating the effect of the decision feedback equalization circuit provided in this application;

[0030] Figure 13 The timing diagram of the decision feedback equalization circuit provided in this application.

[0031] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0032] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0033] First, combine Figure 1 The comparator shown describes how the comparator works. For example... Figure 1 As shown, the comparator includes an input circuit, an output circuit, and a reset circuit. The output terminal of the input circuit is connected to the input terminal of the output circuit. The reset circuit is also connected to the output circuit.

[0034] The input circuit includes transistors N1, N2, and N3. Transistors N1 and N2 form a differential transistor pair. The gates of transistors N1 and N2 form the first input terminal IP and the second input terminal IN of the input circuit. The drains of transistors N1 and N2 form the two output terminals of the input circuit.

[0035] The output circuit includes transistors P1, P2, N4, and N5, which form a cross-coupled transistor pair. The drains of transistors P1 and N4 form the first output terminal ON, and the drains of transistors P2 and N5 form the second output terminal OP. The reset circuit includes transistors P3 and P4.

[0036] The comparator's operation consists of four stages: reset, sampling, regeneration, and decision. The following section will discuss these stages in conjunction with... Figure 2 describe Figure 1 The working process of the comparator shown is as follows:

[0037] During the reset phase, from time t0 to time t1, the clock signal is low, transistor N3 is cut off, the input and output circuits stop working, transistors P3 and P4 are closed, the reset circuit works, and pulls the drain voltage of transistor N4 and the drain voltage of transistor N5 to high level.

[0038] During the sampling phase, from time t1 to t2, the clock signal is high, transistors P3 and P4 are off, and the reset circuit stops working. Transistor N3 is closed, and the input circuit acquires the input signal through the first input terminal IP and the reference signal through the second input terminal IN. The input signal pulls down the drain voltage of transistor N1, and the reference signal pulls down the drain voltage of transistor N2. The drain of transistor N1 pulls down the drain voltage of transistor N4, and the drain of transistor N2 pulls down the drain voltage of transistor N5. Because the input signal is higher than the reference signal, the rate at which the input signal pulls down the drain voltage of transistor N1 is faster, resulting in the drain voltage of transistor N4 being lower than that of transistor N5.

[0039] During the regeneration phase, from time t2 to t3, the drain voltages of transistor N4 and N5 reach the flip voltage, transistors P2 and N4 are turned on, while transistors P1 and N5 are gradually turned off. Transistor P2 pulls up the drain voltage of transistor N5, and transistor N4 pulls down the drain voltage of transistor N4.

[0040] During the decision-making phase, from time t3 to t4, transistors P2 and N4 are turned on, while transistors P1 and N5 are turned off. The drain voltage of transistor N5 continues to be pulled up, and the drain voltage of transistor N4 continues to be pulled down. After pulling the drain of transistor N5 to a low level and the drain voltage of transistor N4 to a high level, the drain voltages of transistors N4 and N5 are maintained.

[0041] When the next working cycle arrives, the clock signal goes low, and the drain voltages of transistors N4 and N5 are reset to high by transistors P1 and P2.

[0042] like Figure 3 As shown, one embodiment of this application provides a comparator with four input terminals and two output terminals. The four input terminals of the comparator are sequentially labeled as the first input terminal, the second input terminal, the third input terminal, and the fourth input terminal. The two output terminals of the comparator are sequentially labeled as the first output terminal and the second output terminal. The comparator includes a first input circuit 101, a second input circuit 102, a first positive feedback circuit 103, a second positive feedback circuit 104, and an output circuit 105.

[0043] The first input circuit 101 has two input terminals and two output terminals, and the second input circuit 102 also has two input terminals and two output terminals. The two output terminals of the first input circuit 101 and the two output terminals of the second input circuit 102 are connected together. The first input terminal of the first input circuit 101 serves as the first input terminal In1 of a comparator, used to receive a first input signal. The second input terminal of the first input circuit 101 serves as the second input terminal Vref1 of a comparator, used to receive a first reference signal. The first input terminal of the second input circuit 102 serves as the third input terminal Vref2 of a comparator, used to receive a second reference signal. The second input terminal of the second input circuit 102 serves as the fourth input terminal In2 of a comparator, used to receive a second input signal.

[0044] The output circuit 105 also has two input terminals and two output terminals. The two input terminals of the output circuit 105 are connected to the two output terminals of the first input circuit 101, and the two input terminals of the output circuit 105 are also connected to the two output terminals of the second input circuit 102. The two output terminals of the output circuit 105 serve as the two output terminals of a comparator.

[0045] The first input circuit 101 includes two pairs of transistors, labeled as the first pair and the second pair, which have different transistor types. For example, when the first pair is an N-type transistor, the second pair is a P-type transistor. When the first pair is a P-type transistor, the second pair is an N-type transistor.

[0046] Both the first pair of transistors and the second pair receive the first input signal and the first reference signal. Specifically, the first transistor in the first pair receives the first input signal, and the second transistor in the first pair receives the first reference signal. Similarly, the first transistor in the second pair receives the first input signal, and the second transistor in the second pair receives the first reference signal. After receiving the first input signal and the first reference signal, the first and second pairs of transistors are used to generate a first differential signal based on the first input signal and the first reference signal during the sampling phase.

[0047] Because the first pair of transistors and the second pair of transistors have different transistor types, their voltage pull-down directions are different. If the first pair of transistors is an N-type transistor and the second pair is a P-type transistor, then the first pair of transistors has a pull-down capability, and the second pair has a pull-up capability. If the first pair of transistors is a P-type transistor and the second pair is an N-type transistor, then the first pair of transistors has a pull-up capability, and the second pair has a pull-down capability.

[0048] The first input signal and the first reference signal are used to control the voltage pulling capability of the first and second pairs of transistors. By pulling the voltage in different directions with the two pairs of transistors, even a slight difference between the first input signal and the first reference signal can be reflected in the output voltage of the two pairs of transistors, and the output voltages of the two pairs of transistors constitute the first differential signal. By setting two pairs of transistors in the first input circuit, even a small difference between the first input signal and the second reference signal can be identified, thereby improving the accuracy of the comparator.

[0049] For example, if the first pair of transistors are P-type transistors and the second pair are N-type transistors, the first reference signal balances the ability of the second transistor in the first pair to pull up the voltage and the ability of the second transistor in the second pair to pull down the voltage. When the first input signal is slightly greater than the first reference signal, the ability of the first transistor in the second pair to pull down the voltage is greater than the ability of the first transistor in the first pair to pull up the voltage, resulting in the output voltage of the first transistor in both sets of transistors being lower than the output voltage of the second transistor in both sets of transistors.

[0050] The second input circuit 102 includes two pairs of transistors, labeled as the third pair and the fourth pair, which have different transistor types. The third and fourth pairs are used to receive the second input signal and the second reference signal, and also to generate a second differential signal based on the second input signal and the second reference signal during the sampling phase. The principle of the second input circuit is the same as that of the first input circuit, and will not be repeated here.

[0051] Both the first differential signal and the second differential signal are a pair of voltage signals. The first positive feedback circuit 103 is used to accelerate the difference between the first differential signals, and the second positive feedback circuit 104 is used to accelerate the difference between the second differential signals. The first input circuit 101 is also used to output the accelerated first differential signal, and the second input circuit 102 is also used to output the accelerated second differential signal. The output circuit 105 is used to amplify and latch the voltage signals at the output terminals of the first input circuit 101 and the second input circuit 102 during the regeneration phase, and output the comparison result.

[0052] When the first reference signal is not properly selected, the response time of the first input circuit 101 becomes longer, meaning that the first input circuit 101 needs a longer time to present a first differential signal with a relatively large difference at the output. The first positive feedback circuit 103 accelerates the difference between the first differential signals through a positive feedback mechanism, thereby reducing the time it takes for the first input circuit 101 to present a first differential signal with a relatively large difference at the output, which shortens the time the comparator is in the sampling phase, thereby improving the comparator's response rate and reducing its power consumption.

[0053] Similarly, when the second reference signal is not properly selected, the response time of the second input circuit 102 becomes longer, meaning that the second input circuit 102 needs a longer time to present a second differential signal with a relatively large difference at the output. The second positive feedback circuit 104 accelerates the difference between the second differential signals through a positive feedback mechanism, thereby reducing the time that the second input circuit 102 presents a second differential signal with a relatively large difference at the output, which shortens the time the comparator is in the sampling phase, thereby improving the comparator's response rate and reducing its power consumption.

[0054] In one embodiment, the first positive feedback circuit 103 includes a first positive feedback module 1031 and a second positive feedback module 1032. The first positive feedback module 1031 is connected to the output terminal of the first input circuit 101 and is used to pull the voltage at the output terminal of the first input circuit 101 to accelerate the difference between the differential signals. The second positive feedback module 1032 is also connected to the output terminal of the first input circuit 101 and is used to pull the voltage at the output terminal of the first input circuit 101 to accelerate the difference between the differential signals. The voltage pulling directions of the first positive feedback module and the second positive feedback module are different. By using two positive feedback modules to pull the voltage at the output terminal of the first input circuit 101 in different directions, the difference between the differential signals is accelerated, thereby shortening the sampling time of the comparator and improving the response rate of the comparator.

[0055] In one embodiment, the second positive feedback circuit 104 includes a third positive feedback module 1041 and a fourth positive feedback module 1042. The third positive feedback module 1041 is connected to the output terminal of the second input circuit 102 and is used to pull the voltage at the output terminal of the second input circuit 102 to accelerate the difference between the differential signals. The fourth positive feedback module 1044 is also connected to the output terminal of the second input circuit 102 and is used to pull the voltage at the output terminal of the second input circuit 102 to accelerate the difference between the differential signals. The voltage pulling directions of the third positive feedback module and the fourth positive feedback module are different. By using two positive feedback modules to pull the voltage at the output terminal of the second input circuit 102 in different directions, the difference between the differential signals is accelerated, thereby shortening the sampling time of the comparator and improving the response rate of the comparator.

[0056] In one embodiment, the first positive feedback module 1031 includes a first feedback unit 1033 and a second feedback unit 1034, both of which are provided with a control terminal and a first terminal.

[0057] The control terminal of the first feedback unit 1033 is connected to the first output terminal of the first input circuit 101, and the first end of the first feedback unit 1033 is connected to the second output terminal of the first input circuit 101. The control terminal of the second feedback unit 1034 is connected to the second output terminal of the first input circuit 101, and the first end of the second feedback unit 1034 is connected to the first output terminal of the first input circuit 101.

[0058] The first feedback unit 1033 is used to pull the voltage of the second output terminal of the first input circuit 101 according to the voltage of the first output terminal of the first input circuit 101 during the sampling phase, and the second feedback unit 1034 is used to pull the voltage of the first output terminal of the first input circuit 101 according to the voltage of the second output terminal of the first input circuit 101 during the sampling phase.

[0059] Taking the upward pulling of the first feedback unit and the second feedback unit as an example, when the voltage of the first output terminal of the first input circuit 101 is higher than the voltage of the second output terminal of the first input circuit 101, the first feedback unit 1033 has a weaker ability to pull the voltage of the second output terminal of the first input circuit 101 upward, while the second feedback unit 1034 has a stronger ability to pull the voltage of the first output terminal of the first input circuit 101 upward. That is, the voltage rise rate of the first output terminal is higher than the voltage rise rate of the second output terminal, thereby making the voltage difference between the first output terminal and the second output terminal larger and larger, thus achieving positive feedback.

[0060] In one embodiment, the second positive feedback module 1032 includes a third feedback unit 1035 and a third feedback unit 1036, both of which are provided with a control terminal and a first terminal.

[0061] The control terminal of the third feedback unit 1035 is connected to the first output terminal of the first input circuit 101, and the first terminal of the third feedback unit 1035 is connected to the second output terminal of the first input circuit 101. The control terminal of the fourth feedback unit 1036 is connected to the second output terminal of the first input circuit 101, and the first terminal of the fourth feedback unit 1036 is connected to the first output terminal of the first input circuit 101.

[0062] The third feedback unit 1035 is used to pull the voltage of the second output terminal of the first input circuit 101 according to the voltage of the first output terminal of the first input circuit 101 during the sampling phase, and the fourth feedback unit 1036 is used to pull the voltage of the first output terminal of the first input circuit 101 according to the voltage of the second output terminal of the first input circuit 101 during the sampling phase.

[0063] Taking the downward pull of the third and fourth feedback units as an example, when the voltage of the first output terminal of the first input circuit 101 is higher than the voltage of the second output terminal of the first input circuit 101, the third feedback unit 1035 has a stronger ability to pull down the voltage of the second output terminal of the first input circuit 101, while the fourth feedback unit 1036 has a weaker ability to pull down the voltage of the first output terminal of the first input circuit 101. That is, the voltage drop rate of the first output terminal is lower than the voltage drop rate of the second output terminal, thereby making the voltage difference between the first output terminal and the second output terminal larger and larger, thus achieving positive feedback.

[0064] In one embodiment, the third positive feedback module 1041 includes a fifth feedback unit 1043 and a sixth feedback unit 1044, both of which are provided with a control terminal and a first terminal.

[0065] The control terminal of the fifth feedback unit 1043 is connected to the first output terminal of the second input circuit 102, and the first terminal of the fifth feedback unit 1043 is connected to the second output terminal of the second input circuit 102. The control terminal of the sixth feedback unit 1044 is connected to the second output terminal of the second input circuit 102, and the first terminal of the sixth feedback unit 1044 is connected to the first output terminal of the second input circuit 102.

[0066] The fifth feedback unit 1043 is used to pull the voltage of the second output terminal of the second input circuit 102 according to the voltage of the first output terminal of the second input circuit 102 during the sampling phase, and the sixth feedback unit 1044 is used to pull the voltage of the first output terminal of the second input circuit 102 according to the voltage of the second output terminal of the second input circuit 102 during the sampling phase.

[0067] In one embodiment, the fourth positive feedback module 1042 includes a seventh feedback unit 1045 and an eighth feedback unit 1046, both of which are provided with a control terminal and a first terminal.

[0068] The control terminal of the seventh feedback unit 1045 is connected to the first output terminal of the second input circuit 102, and the first terminal of the seventh feedback unit 1045 is connected to the second output terminal of the second input circuit 102. The control terminal of the eighth feedback unit 1046 is connected to the second output terminal of the second input circuit 102, and the first terminal of the eighth feedback unit 1046 is connected to the first output terminal of the second input circuit 102.

[0069] The seventh feedback unit 1045 is used to pull the voltage of the second output terminal of the second input circuit 102 according to the voltage of the first output terminal of the second input circuit 102 during the sampling phase, and the eighth feedback unit 1046 is used to pull the voltage of the first output terminal of the second input circuit 102 according to the voltage of the second output terminal of the second input circuit 102 during the sampling phase.

[0070] The positive feedback principle of the third positive feedback module 1041 is the same as that of the first positive feedback module 1031, and will not be repeated here. The positive feedback principle of the fourth positive feedback module 1042 is the same as that of the second positive feedback module 1032, and will not be repeated here.

[0071] In the above technical solution, even if the difference between the first input signal and the first reference signal is small, or the difference between the second input signal and the second reference signal is small, causing an imbalance in the voltage pull capability of the two transistor pairs in the first or second input circuit, a differential signal is generated between the two transistor pairs. The two positive feedback circuits can accelerate the difference between the differential signals. The output circuit amplifies and latches the accelerated differential signal before outputting the comparison result, thereby improving the comparison accuracy of the comparator. When either or both of the first and second reference signals are not properly selected, it takes a relatively long time to generate a differential signal with a large difference in the corresponding input circuit. The positive feedback circuit in the corresponding input circuit accelerates the difference through a positive feedback mechanism after there is a slight difference between the two output terminals of the input circuit, shortening the sampling stage time, thereby improving the response rate of the comparator and reducing the power consumption of the comparator.

[0072] Figure 4 A circuit diagram of a comparator provided in another embodiment of this application is shown below. Figure 4 As shown, the comparator provided in this application includes a first input circuit 101, a second input circuit 102, a first positive feedback circuit 103, a second positive feedback circuit 104, and an output circuit 105.

[0073] The first input circuit 101 includes a first input transistor P1, a second input transistor P2, a third input transistor N1, a fourth input transistor N2, and a fifth input transistor N3. Each input transistor has a control terminal, a first terminal, and a second terminal.

[0074] The second terminal of the first input transistor P1 and the first terminal of the third input transistor N1 are connected. The control terminals of the first input transistor P1 and the third input transistor N1 serve as the first input terminals of the first input circuit 101, used to receive a first input signal. The first input signal controls the conduction or cutoff of the first input transistor P1 and the third input transistor N1. The second terminal of the first input transistor P1 and the first terminal of the third input transistor N1 serve as the first output terminals of the first input circuit 101.

[0075] The second terminal of the second input transistor P2 is connected to the first terminal of the fourth input transistor N2. The control terminals of the second input transistor P2 and the fourth input transistor N2 serve as the second input terminals of the first input circuit 101, used to receive a first reference signal. The first reference signal causes the second input transistor P2 and the fourth input transistor N2 to be turned on or off. The second terminal of the second input transistor P2 and the first terminal of the fourth input transistor N2 serve as the second output terminals of the first input circuit 101.

[0076] The first terminal of the fifth input transistor N3 is connected to the second terminal of the third input transistor N1 and the second terminal of the fourth input transistor N2, and the second terminal of the fifth input transistor N3 is connected to the ground terminal.

[0077] The control terminal of the fifth input transistor N3 is used to receive a clock signal, thereby controlling whether the first input circuit 101 operates. The first input circuit 101 operates when the fifth input transistor N3 is closed. The first input circuit 101 stops operating when the fifth input transistor N3 is turned off.

[0078] The first input signal is amplified by the first input transistor P1 and / or the third input transistor N1, and the first reference signal is amplified by the second input transistor P2 and / or the fourth input transistor N2, generating a first differential signal at the second terminal of the first input transistor P1 and the second terminal of the second input transistor P2.

[0079] The second input circuit 102 includes a sixth input transistor P3, a seventh input transistor P4, an eighth input transistor N4, a ninth input transistor N5, and a tenth input transistor N6. Each input transistor has a control terminal, a first terminal, and a second terminal.

[0080] The second terminal of the sixth input transistor P3 is connected to the first terminal of the eighth input transistor N4. The control terminals of the sixth input transistor P3 and the eighth input transistor N4 serve as the first input terminals of the second input circuit 102, used to receive the second reference signal. The second reference signal controls the conduction or cutoff of the sixth input transistor P3 and the eighth input transistor N4. The second terminal of the sixth input transistor P3 and the first terminal of the eighth input transistor N4 serve as the first output terminal of the second input circuit 102.

[0081] The second terminal of the seventh input transistor P4 is connected to the first terminal of the ninth input transistor N5. The control terminals of the seventh input transistor P4 and the ninth input transistor N5 serve as the second input terminals of the second input circuit 102, used to receive the second input signal. The second input signal turns the seventh input transistor P4 and the ninth input transistor N5 on or off. The second terminal of the seventh input transistor P4 and the first terminal of the ninth input transistor N5 serve as the second output terminal of the second input circuit 102.

[0082] The first terminal of the tenth input transistor N6 is connected to the second terminal of the eighth input transistor N4 and the second terminal of the ninth input transistor N5, and the second terminal of the tenth input transistor N6 is connected to the ground terminal.

[0083] The control terminal of the tenth input transistor N6 is used to receive a clock signal, thereby controlling whether the second input circuit 102 operates. The second input circuit 102 operates when the tenth input transistor N6 is closed. The second input circuit 102 stops operating when the tenth input transistor N6 is turned off.

[0084] The second input signal is amplified by the sixth input transistor P3 and / or the eighth input transistor N4, and the second reference signal is amplified by the seventh input transistor P4 and / or the ninth input transistor N5, generating a second differential signal at the second terminal of the sixth input transistor P3 and the second terminal of the seventh input transistor P4.

[0085] The output circuit 105 includes a first output transistor N7, a second output transistor N8, a third output transistor P5, and a fourth output transistor P6. The first terminal of the first output transistor N7 is connected to the second terminal of the third output transistor P5, and the first terminal of the second output transistor N8 is connected to the second terminal of the fourth output transistor P6. The control terminal of the first output transistor N7 is connected to the control terminal of the third output transistor P5, and then connected to the second terminal of the fourth output transistor P6. Similarly, the control terminal of the second output transistor N8 is connected to the control terminal of the fourth output transistor P6, and then connected to the second terminal of the third output transistor P5.

[0086] The second terminal of the first output transistor N7 is the first input terminal of the output circuit 105, and the second terminal of the second output transistor N8 is the second input terminal of the output circuit 105. The second terminal of the third output transistor P5 serves as the first output terminal PB of the output circuit 105, and the second terminal of the fourth output transistor P6 serves as the second output terminal P of the output circuit 105.

[0087] When the first input transistor P1 and / or the third input transistor N1 are turned on, and the second input transistor P2 and / or the fourth input transistor N2 are turned on, the voltages at the first terminals of the first output transistor N7 and the second output transistor N8 are pulled down. When the voltage is pulled down to the switching voltage, the transistors turn on. That is, the first output transistor N7 and the fourth output transistor P6 are turned on, or the second output transistor N8 and the third output transistor P5 are turned on. If the first output transistor N7 and the fourth output transistor P6 are turned on, the voltage at the second terminal of the fourth output transistor P6 is pulled up, and the voltage at the second terminal of the third output transistor P5 is pulled down. If the second output transistor N8 and the third output transistor P5 are turned on, the voltage at the second terminal of the fourth output transistor P6 is pulled down, and the voltage at the second terminal of the third output transistor P5 is pulled up, thus amplifying and latching the voltage signal output by the input circuit 101.

[0088] In one embodiment, the first feedback unit 1033 includes a first feedback transistor P7, the control terminal of which is connected to the second terminal of the first input transistor P1, the first terminal of which is connected to the first terminal of the second input transistor P2, and the second terminal of which is connected to the second terminal of the second input transistor P2. The second feedback unit 1034 includes a second feedback transistor P8, the control terminal of which is connected to the second terminal of the second input transistor P2, the second terminal of which is connected to the second terminal of the first input transistor P1, and the first terminal of which is connected to the first terminal of the first input transistor P1.

[0089] In one embodiment, the third feedback unit 1035 includes a third feedback transistor N9. The control terminal of the third feedback transistor N9 is connected to the first terminal of the third input transistor N1, the first terminal of the third feedback transistor N9 is connected to the first terminal of the fourth input transistor N2, and the second terminal of the third feedback transistor N9 is connected to the second terminal of the fourth input transistor N2. The fourth feedback unit 1036 includes a fourth feedback transistor N10. The control terminal of the fourth feedback transistor N10 is connected to the first terminal of the fourth input transistor N2, and the first terminal of the fourth feedback transistor N10 is connected to the first terminal of the third input transistor N1. The second terminal of the fourth feedback transistor N10 is connected to the second terminal of the third input transistor N1. The second terminals of the third feedback transistor N9 and the second terminals of the fourth feedback transistor N10 are also connected to the first terminal of the fifth input transistor N3.

[0090] In one embodiment, the fifth feedback unit 1043 includes a fifth feedback transistor P9. The control terminal of the fifth feedback transistor P9 is connected to the second terminal of the sixth input transistor P3, the first terminal of the fifth feedback transistor P9 is connected to the first terminal of the seventh input transistor P4, and the second terminal of the fifth feedback transistor P9 is connected to the second terminal of the seventh input transistor P4. The sixth feedback unit 104 includes a sixth feedback transistor P10. The control terminal of the sixth feedback transistor P10 is connected to the second terminal of the seventh input transistor P4, the second terminal of the sixth feedback transistor P10 is connected to the second terminal of the sixth input transistor P3, and the first terminal of the sixth feedback transistor P10 is connected to the first terminal of the sixth input transistor P3.

[0091] In one embodiment, the seventh feedback unit 1045 includes a seventh feedback transistor N11. The control terminal of the seventh feedback transistor N11 is connected to the first terminal of the eighth input transistor N4, the first terminal of the seventh feedback transistor N11 is connected to the first terminal of the ninth input transistor N5, and the second terminal of the seventh feedback transistor N11 is connected to the second terminal of the ninth input transistor N5. The eighth feedback unit 1046 includes an eighth feedback transistor N12. The control terminal of the eighth feedback transistor N12 is connected to the first terminal of the ninth input transistor N5, and the first terminal of the eighth feedback transistor N12 is connected to the first terminal of the eighth input transistor N4. The second terminal of the eighth feedback transistor N12 is connected to the second terminal of the eighth input transistor N4, and the second terminals of the seventh feedback transistor N11 and the eighth feedback transistor N12 are also connected to the first terminal of the tenth input transistor N6.

[0092] In one embodiment, the first feedback transistor P7, the second feedback transistor P8, the first input transistor P1, and the second input transistor P2 are of the same type, and the third feedback transistor N9, the fourth feedback transistor N10, the third input transistor N1, the fourth input transistor N2, and the fifth input transistor N3 are of the same type.

[0093] In one embodiment, the fifth feedback transistor P9, the sixth feedback transistor P10, the sixth input transistor P3, and the seventh input transistor P4 are of the same type, and the seventh feedback transistor N11, the eighth feedback transistor N12, the eighth input transistor N4, the ninth input transistor N5, and the tenth input transistor N6 are of the same type.

[0094] In one embodiment, the comparator further includes a first reset circuit 1061, which is connected between a first output terminal of the first input circuit 101 and a second output terminal of the first input circuit 101. The first reset circuit 1061 is used to reset the voltages of the two output terminals of the first input circuit 101 and the voltages of the two output terminals of the second input circuit 102.

[0095] The first reset circuit 1061 includes a first clocked transistor P11 and a second clocked transistor P12. The second terminal of the first clocked transistor P11 is connected to the first output terminal of the first input circuit 101, and the second terminal of the second clocked transistor P12 is connected to the second output terminal of the first input circuit 101. The first terminal of the second clocked transistor P12 is connected to the first terminal of the first clocked transistor P11 and then to a power supply. The control terminals of both the first clocked transistor P11 and the second clocked transistor P12 receive clock signals and are turned on when the clock signal is at a low level, pulling the first and second output terminals of the first input circuit 101 to a high level.

[0096] In one embodiment, the comparator further includes a second reset circuit 1062 and a third reset circuit 1063. The second reset circuit 1062 is connected to the first output terminal of the output circuit 105, and the third reset circuit 1063 is connected to the second output terminal of the output circuit 105. The second reset circuit 1062 is used to reset the voltage at the first output terminal of the output circuit 105. The third reset circuit 1063 is used to reset the voltage at the second output terminal of the output circuit 105.

[0097] The second reset circuit 1062 includes a third clocked transistor P13. The first terminal of the third clocked transistor P13 is connected to the power supply terminal, and the second terminal of the third clocked transistor P13 is connected to the first output terminal of the output circuit 105. The control terminal of the third clocked transistor P13 is used to receive a clock signal and to pull the first output terminal of the output circuit 105 to a high level when the clock signal is low. The third reset circuit 1063 includes a fourth clocked transistor P14. The first terminal of the fourth clocked transistor P14 is connected to the power supply terminal, and the second terminal of the fourth clocked transistor P14 is connected to the second output terminal of the output circuit 105. The control terminal of the fourth clocked transistor P14 is used to receive a clock signal and to pull the second output terminal of the output circuit 105 to a high level when the clock signal is low.

[0098] Compared to the second reset circuit 1062 and the third reset circuit 1063 pulling the voltage of the two output terminals of the first input circuit 101 through the output circuit 105 to achieve reset, the reset time is shorter by setting the first reset circuit 1061 to directly pull the voltage of the two output terminals of the first input circuit 101, thereby improving the response rate of the comparator.

[0099] In one embodiment, when the first feedback transistor P7, the second feedback transistor P8, the first input transistor P1, the second input transistor P2, the fifth feedback transistor P9, the sixth feedback transistor P10, the sixth input transistor P3, and the seventh input transistor P4 are all P-type transistors, the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

[0100] In one embodiment, when the third feedback transistor N9, the fourth feedback transistor N10, the seventh feedback transistor N11, the eighth feedback transistor N12, the third input transistor N1, the fourth input transistor N2, the fifth input transistor N3, the eighth input transistor N4, the ninth input transistor N5, and the tenth input transistor N6 are all N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

[0101] In one embodiment, when both the first output transistor N7 and the second output transistor N8 are N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal. When both the third output transistor P5 and the fourth output transistor P6 are P-type transistors, and both the first clocked transistor P11 to the fourth clocked transistor P14 are P-type transistors, the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

[0102] In one embodiment, the first feedback transistor P7 and the second feedback transistor P8 are the same size, the first input transistor P1 and the second input transistor P2 are the same size, and the size of the first feedback transistor P7 is less than half the size of the first input transistor P1. This avoids the first feedback transistor P7 and the second feedback transistor P8 from affecting the first input transistor P1 and the second input transistor P2 in sensing the first input signal and the first reference signal, thereby improving the accuracy of the comparator output.

[0103] In one embodiment, the third feedback transistor N9 and the fourth feedback transistor N10 are of the same size, and the third input transistor N1 and the fourth input transistor N2 are of the same size. The size of the third feedback transistor N9 is less than half the size of the third input transistor N1, so as to avoid the third feedback transistor N9 and the fourth feedback transistor N10 affecting the sensing of the first input signal and the first reference signal by the third input transistor N1 and the fourth input transistor N2, thereby improving the accuracy of the comparator output result.

[0104] In one embodiment, the fifth feedback transistor P9 and the sixth feedback transistor P10 are of the same size, and the sixth input transistor P3 and the seventh input transistor P4 are of the same size. The size of the fifth feedback transistor P9 is less than half the size of the sixth input transistor P3, so as to avoid the fifth feedback transistor P9 and the sixth feedback transistor P10 from affecting the fifth input transistor P3 and the sixth input transistor P4 in sensing the second input signal and the second reference signal, thereby improving the accuracy of the comparator output result.

[0105] In one embodiment, the seventh feedback transistor N11 and the eighth feedback transistor N12 are of the same size, and the eighth input transistor N4 and the ninth input transistor N5 are of the same size. The size of the seventh feedback transistor N11 is less than half the size of the eighth input transistor N4, so as to avoid the seventh feedback transistor N11 and the eighth feedback transistor N12 affecting the eighth input transistor N4 and the ninth input transistor N5 in sensing the second input signal and the second reference signal, thereby improving the accuracy of the comparator output result.

[0106] In one embodiment, the ratio of the size of the sixth input transistor P3 to the size of the first input transistor P1 is α, where α < 0.5, such that the size of the sixth input transistor P3 is less than half the size of the first input transistor P1. The ratio of the size of the fifth feedback transistor P9 to the size of the first feedback transistor P7 is α < 0.5, such that the size of the fifth feedback transistor P9 is less than half the size of the first feedback transistor P7. The ratio of the size of the eighth input transistor N4 to the size of the third input transistor N1 is α, where α < 0.5, such that the size of the eighth input transistor N4 is less than half the size of the third input transistor N1. The ratio of the size of the seventh feedback transistor N11 to the size of the third feedback transistor N9 is α < 0.5, such that the size of the seventh feedback transistor N11 is less than half the size of the third feedback transistor N9. With the above settings, the influence of the second input circuit 102 on the first input circuit 101 can be avoided to the extent that the first differential signal is reversed. For example, the first input signal and the first reference signal make the voltage at the second terminal of the first input transistor P1 greater than the voltage at the second terminal of the second input transistor P2. Due to the intervention of the second differential signal, the first differential signal is reversed, which means that the voltage at the second terminal of the first input transistor P1 is less than the voltage at the second terminal of the second input transistor P2.

[0107] In one embodiment, the second reference signal and the second input signal at the current moment are determined based on the first input signal and the first reference signal at the previous moment. If the first input signal at the previous moment is greater than the first reference signal, then the second input signal at the current moment is set to be greater than the second reference signal. If the first input signal at the previous moment is less than the first reference signal, then the second input signal at the current moment is set to be less than the second reference signal.

[0108] The following describes the four working stages of a comparator. Figure 4 The working process of the comparator shown is as follows:

[0109] During the reset phase, the clock signal is low, the fifth input transistor N3 and the tenth input transistor N6 are cut off, the first input circuit 101, the second input circuit 102 and the output circuit 105 stop working, the first clock transistor P11 to the second clock transistor P12 are turned on, the first reset circuit 1061 to the second reset circuit 1063 are working, pulling the drain voltage of the third output transistor P5 and the drain voltage of the fourth output transistor P6 to a high level, and pulling the source of the first output transistor N7 and the source of the second output transistor N8 to a low level.

[0110] During the sampling phase, the clock signal is high, the first clock transistor P11 to the fourth clock transistor P14 are cut off, and the first reset circuit 1061 to the third reset circuit 1063 stop working. The fifth input transistor N3 and the tenth input transistor N6 are closed, and the first input circuit 101, the second input circuit 102 and the output circuit 105 are working.

[0111] Figure 4 The circuit shown can realize rail-to-rail detection and eliminate inter-symbol interference. The principle of eliminating inter-symbol interference in the sampling stage is described below by taking different values ​​for two input signals and two reference signals:

[0112] (1) First case: At the current moment, the first input signal is greater than the first reference signal, while at the previous moment, the first input signal was less than the first reference signal. Based on the relationship between the first input signal and the first reference signal at the previous moment, the second input signal is set to be less than the second reference signal. For example: at the previous moment, the first input signal was 0.7V and the first reference signal was 0.8V. At the current moment, the first input signal is 0.9V, the first reference signal is 0.8V, the second input signal is 0V, and the second reference signal is 1.2V.

[0113] When inter-symbol interference (ISI) is present, meaning the first input signal from the previous moment interferes with the first input signal at the current moment, assuming that after ISI, the first input terminal of the first input circuit 101 actually receives a voltage of 0.8V at the current moment, the first input transistor P1 and the second input transistor P2 are cut off, the pull-down capabilities of the third input transistor N1 and the fourth input transistor N2 are equal, and the drain voltages of the third input transistor N1 and the fourth input transistor N2 are equal. In the second input circuit, the sixth input transistor P3 and the seventh input transistor P4 are cut off, and the pull-down capability of the seventh input transistor N4 is higher than that of the eighth input transistor N5. Under the pull of the seventh input transistor N4 and the eighth input transistor N5, and under the pull of the first positive feedback circuit 103 and the second positive feedback circuit 104, the voltage at the second terminal of the first input transistor P1 is less than the voltage at the second terminal of the second input transistor P2.

[0114] In the absence of inter-symbol interference (ISI), the first input signal and the first reference signal will cause the voltage at the second terminal of the first input transistor P1 to be lower than the voltage at the second terminal of the second input transistor P2. That is, ISI is eliminated by adjusting the first input circuit 101 through the second input circuit 102. Typically, the pull-down capabilities of the eighth input transistor N4 and the ninth input transistor N5 are relatively small. When a voltage difference appears between the drains of the eighth input transistor N4 and the ninth input transistor N5, two positive feedback circuits accelerate the voltage difference between their drains, which can shorten the sampling time and reduce power consumption.

[0115] (2) In the second case, at the current time and the previous time, the first input signal is greater than the first reference signal, and the second input signal is set to be greater than the second reference signal. For example, at the previous time, the first input signal was 0.9V and the first reference signal was 0.8V. At the current time, the first input signal is 0.9V, the first reference signal is 0.8V, the second input signal is 1.2V, and the second reference signal is 0V.

[0116] Assuming that after inter-symbol interference, the voltage actually received at the first input terminal In1 of the first input circuit 101 is still 0.9V at the current moment, the first input transistor P1 and the second input transistor P2 are off, the pull-down capability of the third input transistor N1 is greater than that of the fourth input transistor N2, and the drain voltage of the third input transistor N1 is less than that of the fourth input transistor N2. In the second input circuit, the sixth input transistor P3 and the seventh input transistor P4 are off, the pull-down capability of the seventh input transistor N4 is less than that of the eighth input transistor N5, and the second input circuit 102 will pull the voltages of the third input transistor N1 and the fourth input transistor N2 in a direction that makes the voltage of the third input transistor N1 greater than that of the fourth input transistor N2. However, the pull-up capability of the transistors in the second input circuit 102 is α times the pull-up capability of the corresponding transistors in the first input circuit, where α is less than 0.5. The pull-up capability of the transistors in the second input circuit 102 is much weaker than that of the transistors in the first input circuit 101, and the second terminal voltage of the third input transistor N1 is still less than the second terminal voltage of the fourth input transistor N2.

[0117] (3) In the third case, at the previous moment, the first input signal was greater than the first reference signal, and at the current moment, the first input signal is less than the first reference signal. Therefore, the second input signal is set to be greater than the second reference signal. For example, at the previous moment, the first input signal was 0.9V and the first reference signal was 0.8V. At the current moment, the first input signal is 0.7V, the first reference signal is 0.8V, the second input signal is 1.2V, and the second reference signal is 0V.

[0118] Assuming that after inter-symbol interference, the voltage actually received at the first input terminal In1 of the first input circuit 101 is 0.8V at the current moment, the first input transistor P1 and the second input transistor P2 are cut off, the pull-down capability of the third input transistor N1 is equal to the pull-down capability of the fourth input transistor N2, and the drain voltage of the third input transistor N1 is equal to the drain voltage of the fourth input transistor N2. In the second input circuit, the sixth input transistor P3 and the seventh input transistor P4 are cut off, and the pull-down capability of the eighth input transistor N4 is lower than that of the ninth input transistor N5. Under the pull of the eighth input transistor N4 and the ninth input transistor N5, and under the pull of the first positive feedback circuit 103 and the second positive feedback circuit 104, the voltage at the second terminal of the third input transistor N1 is greater than the voltage at the second terminal of the fourth input transistor N2.

[0119] In the absence of inter-symbol interference (ISI), the first input signal and the first reference signal will cause the voltage at the second terminal of the third input transistor N1 to be greater than the voltage at the second terminal of the fourth input transistor N2. That is, ISI is eliminated by adjusting the first input circuit 101 through the second input circuit 102. Typically, the pull-down capabilities of the eighth input transistor N4 and the ninth input transistor N5 are relatively small. When a voltage difference appears between the drains of the eighth input transistor N4 and the ninth input transistor N5, two positive feedback circuits accelerate the voltage difference between their drains, which can shorten the sampling time and reduce power consumption.

[0120] (4) In the fourth case, at the current moment, the first input signal is less than the first reference signal, while at the previous moment, the first input signal was less than the first reference signal. Therefore, the second input signal is set to be less than the first reference signal. For example, at the previous moment, the first input signal was 0.7V and the first reference signal was 0.8V. At the current moment, the first input signal is 0.7V, the first reference signal is 0.8V, the second input signal is 0V, and the second reference signal is 1.2V.

[0121] In the presence of inter-symbol interference, assuming the amplitude of the first input terminal In1 of the first input circuit 101 remains at 0.7V, the first input transistor P1 and the second input transistor P2 are off, the pull-down capability of the third input transistor N1 is less than that of the fourth input transistor N2, and the drain voltage of the third input transistor N1 is greater than that of the fourth input transistor N2. In the second input circuit, the sixth input transistor P3 and the seventh input transistor P4 are off, and the pull-down capability of the eighth input transistor N4 is greater than that of the ninth input transistor N5. The second input circuit 102 will pull the voltage of the third input transistor N1 and the fourth input transistor N2 in a direction that makes the voltage of the third input transistor N1 less than that of the fourth input transistor N2. However, the pull-up capability of the transistors in the second input circuit is α times that of the transistors in the first input circuit, where α is less than 0.5. The pull-up capability of the transistors in the second input circuit is much weaker than that of the transistors in the first input circuit. The second terminal voltage of the third input transistor N1 is still greater than that of the fourth input transistor N2.

[0122] The following explains how this solution can achieve rail-to-rail detection. Specifically, the first reference signal is set to 0.3V, 0.5V, and 0.8V, which can vary from 0 to VDD, where VDD represents the voltage at the power supply terminal. The first reference signal can control the second input transistor P2 and / or the fourth input transistor N2 to turn on.

[0123] (1) In the first case, the first reference signal can only turn on the second input transistor P2. For example, the power supply is 1.2V and the first reference signal is 0.3V.

[0124] When the first input signal can only turn on the first input transistor P1, for example: the first input signal is 0.1V, the first input signal is less than the first reference signal, the pull-up capability of the first input transistor P1 is higher than the pull-up capability of the second input transistor P2, and the voltage of the first output terminal of the first input circuit is slightly greater than the voltage of the second output terminal of the first input circuit.

[0125] When the first input signal can only turn on the first input transistor P1, for example: the first input signal is 0.4V, the first input signal is greater than the first reference signal, the pull-up capability of the first input transistor P1 is lower than the pull-up capability of the second input transistor P2, and the voltage at the first output terminal of the first input circuit is slightly less than the voltage at the second output terminal of the first input circuit.

[0126] When the first input signal enables both the first input transistor P1 and the third input transistor N1 to conduct, for example: the first input signal is 0.6V, the first input signal is greater than the first reference signal, the pull-up capability of the first input transistor P1 is lower than the pull-up capability of the second input transistor P2, the third input transistor N1 is also pulled down, and the voltage at the first output terminal of the first input circuit is less than the voltage at the second output terminal of the first input circuit.

[0127] When the first input signal only turns on the third input transistor N1, for example: the first input signal is 0.8V, the first input signal is greater than the first reference signal, the third input transistor N1 pulls down the voltage of the first output terminal of the first input circuit, the second input transistor P2 pulls up the voltage of the second output terminal of the first input circuit, and the voltage of the first output terminal of the first input circuit is less than the voltage of the second output terminal of the first input circuit.

[0128] (2) In the second case, the first reference signal turns on the second input transistor P2 and the fourth input transistor N2, and balances the pull-up capability of the second input transistor P2 and the pull-down capability of the fourth input transistor N2. For example, the power supply is 1.2V and the first reference signal is 0.5V.

[0129] When the first input signal only turns on the first input transistor P1, for example, when the first input signal is 0.2V and the first input signal is less than the first reference signal, the pull-up capability of the first input transistor P1 is higher than the pull-up capability of the second input transistor P2, and the fourth input transistor N2 is also pulled down, so that the voltage at the first output terminal of the first input circuit is higher than the voltage at the second output terminal of the first input circuit.

[0130] When the first input signal turns on both the first input transistor P1 and the third input transistor N1, for example, when the first input signal is 0.4V and is less than the first reference signal, the pull-down capabilities of the first input transistor P1 and the third input transistor N1 are unbalanced, and the pull-up capability of the first input transistor P1 is stronger than the pull-down capability of the third input transistor N1, so that the voltage at the first output terminal of the first input circuit is slightly higher than the voltage at the second output terminal of the first input circuit.

[0131] When the first input signal turns on both the first input transistor P1 and the third input transistor N1, for example, when the first input signal is 0.6V and is greater than the first reference signal, the pull-down capabilities of the first input transistor P1 and the third input transistor N1 are unbalanced, and the pull-up capability of the first input transistor P1 is weaker than the pull-down capability of the third input transistor N1, resulting in the voltage at the first output terminal of the first input circuit being slightly lower than the voltage at the second output terminal of the first input circuit.

[0132] When the first input signal can only turn on the third input transistor N1, for example: the first input signal is 0.8V, the first input signal is greater than the first reference signal, the pull-down capability of the third input transistor N1 is higher than the pull-down capability of the fourth input transistor N2, and the second input transistor P2 also pulls up the voltage of the second output terminal of the first input circuit, so that the voltage of the first output terminal of the first input circuit is less than the voltage of the second output terminal of the first input circuit.

[0133] (3) In the third case, the first reference signal can only turn on the fourth input transistor N2. For example, the power supply is 1.2V and the first reference signal is 0.8V.

[0134] When the first input signal can only turn on the first input transistor P1, for example: the first input signal is 0.1V, the first input signal is less than the first reference signal, the first input transistor P1 pulls up the voltage of the first output terminal of the first input circuit, the fourth input transistor N2 pulls down the voltage of the second output terminal of the first input circuit, and the voltage of the first output terminal of the first input circuit is greater than the voltage of the second output terminal of the first input circuit.

[0135] When the first input signal enables both the first input transistor P1 and the third input transistor N1 to conduct, for example: the first input signal is 0.6V, the first input signal is less than the first reference signal, the pull-down capability of the third input transistor N1 is lower than the pull-down capability of the fourth input transistor N2, the first input transistor P1 also pulls up the voltage of the first output terminal of the first input circuit, and the voltage of the first output terminal of the first input circuit is greater than the voltage of the second output terminal of the first input circuit.

[0136] When the first input signal only turns on all three input transistors N1, for example: the first input signal is 0.7V, the first input signal is less than the first reference signal, the ability of the third input transistor N1 to pull down the voltage of the first output terminal of the first input circuit is less than the ability of the fourth input transistor N2 to pull down the voltage of the second output terminal of the first input circuit, and the voltage of the first output terminal of the first input circuit is higher than the voltage of the second output terminal of the first input circuit.

[0137] When the first input signal only turns on all three input transistors N1, for example: the first input signal is 0.9V, the first input signal is less than the first reference signal, the ability of the third input transistor N1 to pull down the voltage of the first output terminal of the first input circuit is greater than the ability of the fourth input transistor N2 to pull down the voltage of the second output terminal of the first input circuit, and the voltage of the first output terminal of the first input circuit is lower than the voltage of the second output terminal of the first input circuit.

[0138] Therefore, it can be seen that when the first reference signal changes from 0V to VDD, the first input circuit can sense the magnitudes of both the first input signal and the first reference signal. If inter-symbol interference causes the first input circuit to obtain an inaccurate differential signal based on the first input signal and the first reference signal, the second input circuit adjusts the differential signal of the first input circuit, thereby eliminating the influence of inter-symbol interference.

[0139] During the regeneration phase, due to the pull-down effect of the first input circuit 101 and the second input circuit 102, the drain voltage of the first output transistor N7 and the drain voltage of the second output transistor N8 reach the switching voltage. If the drain voltage of the first output transistor N7 is higher than the drain voltage of the second output transistor N8, the first output transistor N7 and the fourth output transistor P6 gradually turn off, while the second output transistor N8 and the third output transistor P5 gradually turn on. The ability to pull up the drain voltage of the third output transistor P5 becomes stronger and stronger, and the ability to pull down the drain voltage of the fourth output transistor P6 becomes stronger and stronger.

[0140] During the decision-making phase, the first output transistor N7 and the fourth output transistor P6 are turned off, while the second output transistor N8 and the third output transistor P5 are turned on. The drain voltage of the third output transistor P5 continues to be pulled up, and the drain voltage of the fourth output transistor P6 is pulled down. After the drain voltage of the third output transistor P5 is pulled down to a low level and the drain voltage of the fourth output transistor P6 is pulled up to a high level, the drain voltages of the third output transistor P5 and the fourth output transistor P6 are maintained.

[0141] When the next working cycle arrives, the clock signal goes low, the source of the first output transistor N7 and the source of the second output transistor N8 are reset to high, and the drain voltages of the third output transistor P5 and the fourth output transistor P6 are reset to high by the third clock transistor P13 and the fourth clock transistor P14.

[0142] In the above technical solution, setting the second input signal and second reference signal at the current moment based on the first input signal and first reference signal received by the first input circuit at the previous moment can effectively eliminate inter-symbol interference at the first input terminal of the first input circuit and improve the accuracy of the comparator. Due to inter-symbol interference, the difference between the differential signals generated by the first input signal and the second input signal at the two input terminals of the first input circuit becomes smaller. The feedback transistor in the input circuit pulls the voltage at the output terminal of the input circuit at different rates, accelerating the difference between the differential signals at the output terminal, thereby shortening the time the comparator is in the sampling stage and reducing the power consumption of the comparator. Two sets of input transistors of different types receive the input signal and the reference signal, and two sets of feedback transistors of different types perform positive feedback. When the reference signal changes from 0V to VDD, the magnitude of the input signal and the reference signal can be accurately sensed, realizing rail-to-rail detection.

[0143] Figure 5 A circuit diagram of a comparator provided in another embodiment of this application is shown below. Figure 5 As shown, the comparator provided in this application includes a first input circuit 101, a second input circuit 102, a first positive feedback circuit 103, a second positive feedback circuit 104, an output circuit 105, a first reset circuit 1061, a second reset circuit 1062, and a third reset circuit 1063.

[0144] The first input circuit 101 includes a first input transistor N1, a second input transistor N2, a third input transistor P1, a fourth input transistor P2, and a fifth input transistor P3. The second terminal of the first input transistor N1 is connected to the first terminal of the third input transistor P1. The second terminal of the second input transistor N2 is connected to the first terminal of the fourth input transistor P2. The second terminals of the fourth input transistor P2 and the third input transistor P1 are connected to the first terminal of the fifth input transistor P3. The second terminal of the fifth input transistor P3 is connected to the power supply terminal.

[0145] The first feedback unit 1033 includes a first feedback transistor N7. The control terminal of the first feedback transistor N7 is connected to the second terminal of the first input transistor N1. The first terminal of the first feedback transistor N7 is connected to the first terminal of the second input transistor N2. The second terminal of the first feedback transistor N7 is connected to the second terminal of the second input transistor N2.

[0146] The second feedback unit 1034 includes a second feedback transistor N8. The control terminal of the second feedback transistor N8 is connected to the second terminal of the second input transistor N2. The first terminal of the second feedback transistor N8 is connected to the first terminal of the first input transistor N1. The second terminal of the second feedback transistor N8 is connected to the second terminal of the first input transistor N1.

[0147] The third feedback unit 1035 includes a third feedback transistor P9. The control terminal of the third feedback transistor P9 is connected to the first terminal of the third input transistor P1. The first terminal of the third feedback transistor P9 is connected to the first terminal of the fourth input transistor P2. The second terminal of the third feedback transistor P9 is connected to the second terminal of the fourth input transistor P2.

[0148] The fourth feedback unit 1036 includes a fourth feedback transistor N10. The control terminal of the fourth feedback transistor P10 is connected to the second terminal of the fourth input transistor P2. The first terminal of the fourth feedback transistor P10 is connected to the first terminal of the third input transistor P1. The second terminal of the fourth feedback transistor P10 is connected to the second terminal of the third input transistor P1.

[0149] The second input circuit 102 includes a sixth input transistor N3, a seventh input transistor N4, an eighth input transistor P4, a ninth input transistor P5, and a tenth input transistor P6. The second terminal of the sixth input transistor N3 is connected to the first terminal of the eighth input transistor P4, the second terminal of the seventh input transistor N4 is connected to the first terminal of the ninth input transistor P5, the second terminals of the eighth input transistor P4 and the ninth input transistor P5 are connected to the first terminal of the tenth input transistor P6, and the second terminal of the tenth input transistor P6 is connected to the power supply terminal.

[0150] The fifth feedback unit 1043 includes a fifth feedback transistor N9. The control terminal of the fifth feedback transistor N9 is connected to the second terminal of the sixth input transistor N3. The first terminal of the fifth feedback transistor N9 is connected to the first terminal of the seventh input transistor N4. The second terminal of the fifth feedback transistor N9 is connected to the second terminal of the seventh input transistor N4.

[0151] The sixth feedback unit 1044 includes a sixth feedback transistor N10. The control terminal of the sixth feedback transistor N10 is connected to the second terminal of the seventh input transistor N4. The first terminal of the sixth feedback transistor N10 is connected to the first terminal of the sixth input transistor N3. The second terminal of the sixth feedback transistor N10 is connected to the second terminal of the sixth input transistor N3.

[0152] The seventh feedback unit 1045 includes a seventh feedback transistor P11. The control terminal of the seventh feedback transistor P11 is connected to the first terminal of the eighth input transistor P4. The first terminal of the seventh feedback transistor P11 is connected to the first terminal of the ninth input transistor P5. The second terminal of the seventh feedback transistor P11 is connected to the second terminal of the ninth input transistor P5.

[0153] The eighth feedback unit 1046 includes an eighth feedback transistor P12. The control terminal of the eighth feedback transistor 211 is connected to the first terminal of the ninth input transistor P5. The first terminal of the eighth feedback transistor P12 is connected to the first terminal of the eighth input transistor P4. The second terminal of the eighth feedback transistor P12 is connected to the second terminal of the eighth input transistor P4.

[0154] The output circuit 105 includes a first output transistor P7, a second output transistor P8, a third output transistor N5, and a fourth output transistor N6. The first terminal of the first output transistor P7 is connected to the second terminal of the third output transistor N5, and the first terminal of the second output transistor P8 is connected to the second terminal of the fourth output transistor N6. The control terminal of the first output transistor P7 is connected to the control terminal of the third output transistor N5, and then to the second terminal of the fourth output transistor N6. Similarly, the control terminal of the second output transistor P8 is connected to the control terminal of the fourth output transistor N6, and then to the second terminal of the third output transistor N5.

[0155] The first reset circuit 1061 includes a first clocked transistor N11 and a second clocked transistor N12. The second terminal of the first clocked transistor N11 is connected to the second terminal of the first output transistor N7, and the second terminal of the second clocked transistor N12 is connected to the second terminal of the second output transistor N8. The first terminal of the second clocked transistor N12 is connected to the first terminal of the first clocked transistor N11 and then connected to a power supply.

[0156] The second reset circuit 1062 includes a third clocked transistor N13, the second terminal of which is connected to the second terminal of the third output transistor N5. The third reset circuit 1063 includes a fourth clocked transistor N14, the second terminal of which is connected to the second terminal of the fourth output transistor N6.

[0157] In one embodiment, when the third input transistor P1 to the fifth input transistor P3, the eighth input transistor P4 to the tenth input transistor P6, the third feedback transistor P9, the fourth feedback transistor P10, the seventh feedback transistor P11, and the eighth feedback transistor P12 are all P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

[0158] When the first input transistor N1, the second input transistor N2, the sixth input transistor N3, the seventh input transistor N4, the first feedback transistor N7, the second feedback transistor N8, the fifth feedback transistor N9, and the sixth feedback transistor N10 are all N-type transistors, the source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

[0159] In one embodiment, when both the first output transistor P7 and the second output transistor P8 are P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

[0160] When the third output transistor N5 and the fourth output transistor N6 are both N-type transistors, and the first clocked transistor N11, the second clocked transistor N12, the third clocked transistor N13 and the fourth clocked transistor N14 are all N-type transistors, the source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

[0161] and Figure 4 The difference in the comparator shown is that, during the reset phase, after the clock signal is inverted to a high level, it is input to the control terminals of the fifth input transistor P3 and the tenth input transistor P6, causing the first input circuit 101 and the second input circuit 102 to stop working. After the clock signal is inverted to a high level, the first clocked transistor N11 and the second clocked transistor N12 are turned on, pulling the voltages at the first and second output terminals of the first input circuit 101 to a low level. After the clock signal is inverted to a high level, the third clocked transistor N13 and the fourth clocked transistor N14 are turned on, pulling the drain voltages of the third output transistor N5 and the fourth output transistor N6 to a low level.

[0162] and Figure 4 The difference between the comparators shown is that, during the sampling phase, the clock signal is inverted to a low level and then input to each clock-controlled transistor, as well as the third input transistor P3 and the sixth input transistor P6, causing the first reset circuit 1061 to the third reset circuit 1063 to stop working, and the first input circuit 101 and the second input circuit 102 to work.

[0163] The principles of eliminating inter-symbol interference and achieving track-to-track detection in this embodiment are the same. Figure 4 The comparators shown operate on the same principle, so they will not be described again here.

[0164] During the regeneration phase, due to the pull-up effect of the first input transistor P1, the second input transistor P2, the fourth input transistor P4, and the fifth input transistor P5, the drain voltage of the first output transistor P7 and the drain voltage of the second output transistor P8 reach the switching voltage. When the drain voltage of the first input transistor P1 is higher than the drain voltage of the second input transistor P2, the first output transistor P7 and the fourth output transistor N6 gradually turn on, while the second output transistor P8 and the third output transistor N5 gradually turn off. The ability to pull up the drain voltage of the third output transistor N5 becomes stronger, and the ability to pull down the drain voltage of the fourth output transistor N6 becomes stronger.

[0165] During the decision-making phase, the first output transistor P7 and the fourth output transistor N6 are turned on, while the second output transistor P8 and the third output transistor N5 are turned off. The drain voltage of the third output transistor N5 is pulled up, and the drain voltage of the fourth output transistor N6 is pulled down. After the drain voltage of the third output transistor N5 is pulled up to a high level and the drain voltage of the fourth output transistor N6 is pulled down to a low level, the drain voltages of the third output transistor N5 and the fourth output transistor N6 are maintained.

[0166] When the next working cycle arrives, the clock signal is inverted and becomes high. The source of the first output transistor P7 and the source of the second output transistor P8 are reset to low. The drain voltages of the third output transistor N5 and the fourth output transistor N6 are reset to low by the third clock transistor N13 and the fourth clock transistor N14.

[0167] In the above technical solution, inter-symbol interference at the first input terminal of the first input circuit can be effectively eliminated, improving the accuracy of the comparator. Due to inter-symbol interference, the difference between the differential signals generated by the first and second input signals at the two input terminals of the first input circuit decreases. The feedback transistors in the input circuit pull the voltage at the output terminal of the input circuit at different rates, accelerating the difference between the differential signals at the output terminals, thereby shortening the time the comparator spends in the sampling phase and reducing the comparator's power consumption. Two sets of different types of input transistors receive the input signal and the reference signal, and two sets of different types of feedback transistors provide positive feedback. Even when the reference signal varies from 0V to VDD, the magnitudes of the input signal and the reference signal can be accurately sensed, achieving rail-to-rail detection.

[0168] Figure 6 A structural block diagram of a comparator provided in this application, such as... Figure 6 As shown, the comparator includes a first input circuit 101, a second input circuit 102, a first positive feedback circuit 103, a second positive feedback circuit 104, and an output circuit 105.

[0169] The second input circuit 102 includes at least one controllable input module. Each input module includes a sixth input transistor, a seventh input transistor, an eighth input transistor, a ninth input transistor, and a tenth input transistor. The connection relationship of each transistor in the input module is the same as that of the others. Figure 4 and Figure 5 The same applies here, so it will not be repeated. One output terminal of each controllable input module is connected to form a port, which constitutes one output terminal of the second input circuit. The other output terminal of each controllable input module is connected to form another port, which constitutes the other output terminal of the second input circuit. The tenth input transistor is used to receive clock signals, which control whether the controllable input modules are working, thereby controlling the number of controllable input modules in operation and controlling the driving capability of the second input circuit 102.

[0170] The third feedback module 1041 includes at least one first controllable feedback submodule 1047. Each first controllable feedback submodule 1047 includes a fifth feedback unit 1043, a sixth feedback unit 1044, a first switch 1001, and a second switch 1002. The fifth feedback unit 1043 and the sixth feedback unit 1044 are each provided with a control terminal and a first terminal.

[0171] The control terminal of the fifth feedback unit 1043 is connected to the first output terminal of the second input circuit 102 through the first switch 1001, and the first terminal of the fifth feedback unit 1043 is connected to the second output terminal of the second input circuit 101. The fifth feedback unit 1043 is used to pull the voltage of the second output terminal of the second input circuit 102 according to the voltage of the first output terminal of the second input circuit 102 under the control of the first switch 1001.

[0172] The control terminal of the sixth feedback unit 1044 is connected to the second output terminal of the second input circuit 102 through the second switch 1002. The first terminal of the sixth feedback unit 1044 is connected to the first output terminal of the second input circuit 102. The sixth feedback unit 1044 is used to pull the voltage of the first output terminal of the second input circuit 102 according to the voltage of the second output terminal of the second input circuit 102 under the control of the second switch 1002.

[0173] By controlling the closing and opening of the first switch 1001 and the second switch 1002, the first controllable feedback submodule 1047 can be controlled to generate positive feedback. When both the first switch 1001 and the second switch 1002 are closed, the first controllable feedback submodule 1047 can accelerate the difference between the second differential signals at the output of the second input circuit through a positive feedback mechanism. When both the first switch 1001 and the second switch 1002 are open, a positive feedback mechanism cannot be generated at the output of the second input circuit 102.

[0174] The fourth feedback module 1042 includes at least one second controllable feedback submodule 1048. Each second controllable feedback submodule 1048 includes a seventh feedback unit 1045, an eighth feedback unit 1046, a third switch 1003, and a fourth switch 1004. The seventh feedback unit 1045 and the eighth feedback unit 1046 are each provided with a control terminal and a first terminal.

[0175] The control terminal of the seventh feedback unit 1045 is connected to the first output terminal of the second input circuit 102 through the third switch 1003. The first terminal of the seventh feedback unit 1045 is connected to the second output terminal of the second input circuit 102. The seventh feedback unit 1045 is used to pull the voltage of the second output terminal of the second input circuit 102 according to the voltage of the first output terminal of the second input circuit 102 under the control of the third switch 1003.

[0176] The control terminal of the eighth feedback unit 1046 is connected to the second output terminal of the second input circuit 102 through the fourth switch 1004. The first terminal of the eighth feedback unit 1046 is connected to the first output terminal of the second input circuit 102. The eighth feedback unit 1046 is used to pull the voltage of the first output terminal of the second input circuit 102 according to the voltage of the second output terminal of the second input circuit 102 under the control of the fourth switch 1004.

[0177] The working principle of the fourth feedback module 1042 is similar to that of the third feedback module 1041, and will not be described in detail here.

[0178] When the comparator is operating, the number of controllable positive feedback modules generating positive feedback can be controlled, thereby controlling the ability of the second positive feedback circuit to adjust the difference between the second differential signals. This controls the sampling time of the comparator, ensuring its response rate. Furthermore, it balances the ability of the second positive feedback circuit to adjust the voltage at the output of the second input circuit with the ability of the second input signal and the second reference signal to adjust the voltage at the output of the second input circuit, preventing the second positive feedback circuit from affecting the polarity of the second differential signal generated at the output of the second input circuit. The number of controllable input modules in operation can also be controlled, and the number of controllable positive feedback modules generating positive feedback can be controlled based on the number of operating controllable input modules, ensuring that the second differential signal only adjusts the first differential signal without changing its polarity. This guarantees that the comparator can accurately output the comparison result based on the first input signal and the first reference signal.

[0179] Figure 7 and Figure 8 For based on Figure 6The circuit diagram shown represents one specific example of a comparator, wherein the first input circuit 101, the second input circuit 102, the output circuit 105, the first reset circuit 1061, the second reset circuit 1062, and the third reset circuit 1063 are already present. Figure 4 The embodiments shown are described in detail and will not be repeated here.

[0180] The following is combined Figure 7 and Figure 8 Describe the specific circuit structure of each of the first and second controllable positive feedback modules in the second positive feedback circuit 104.

[0181] The fifth feedback unit 1043 includes a fifth feedback transistor P9. The control terminal of the fifth feedback transistor P9 is connected to the second terminal of the sixth input transistor P3 via a first switch 1001. The first terminal of the fifth feedback transistor P9 is connected to the first terminal of the seventh input transistor P4, and the second terminal of the fifth feedback transistor P9 is connected to the second terminal of the seventh input transistor P4. The first switch 1001 includes a first transmission gate G1, which is controlled by a first enable signal EN1. The first enable signal EN1 is generated based on the comparator's operating frequency, the comparator's input common-mode range, and the test mode signal.

[0182] The sixth feedback unit 1044 includes a sixth feedback transistor P10. The control terminal of the sixth feedback transistor P10 is connected to the second terminal of the seventh input transistor P4 via a second switch 1002. The first terminal of the sixth feedback transistor P10 is connected to the first terminal of the sixth input transistor P3, and the second terminal of the sixth feedback transistor P10 is connected to the second terminal of the sixth input transistor P3. The second switch 1002 includes a second transmission gate G2, which is controlled by a second enable signal EN2. The second enable signal EN2 is generated based on the comparator's operating frequency, the comparator's input common-mode range, and the test mode signal.

[0183] The seventh feedback unit 1045 includes a seventh feedback transistor N11. The control terminal of the seventh feedback transistor N11 is connected to the first terminal of the eighth input transistor N4 via a third switch 1003. The first terminal of the seventh feedback transistor N11 is connected to the first terminal of the ninth input transistor N5, and the second terminal of the seventh feedback transistor N11 is connected to the second terminal of the ninth input transistor N5. The third switch 1003 includes a third transmission gate G3, which is controlled by a third enable signal EN3. The third enable signal EN3 is generated based on the comparator's operating frequency, the comparator's input common-mode range, and the test mode signal.

[0184] The eighth feedback unit 1046 includes an eighth feedback transistor N12. The control terminal of the eighth feedback transistor N12 is connected to the first terminal of the ninth input transistor N5 via a fourth switch 1004. The first terminal of the eighth feedback transistor N12 is connected to the first terminal of the eighth input transistor N4, and the second terminal of the eighth feedback transistor N12 is connected to the second terminal of the eighth input transistor N4. The fourth switch 1004 includes a fourth transmission gate G4, which is controlled by a fourth enable signal EN4. The fourth enable signal EN4 is generated based on the comparator's operating frequency, the comparator's input common-mode range, and the test mode signal.

[0185] By controlling the switching states of the first transmission gate G1 to the fourth transmission gate G4 with the enable signal, the number of controllable positive feedback modules participating in the positive feedback can be adjusted.

[0186] In one embodiment, the second positive feedback circuit 104 further includes a first zero switch K10, a zero-zero switch K00, a zero-first switch K01, and a first first switch K11. The control terminal of the fifth feedback unit 1043 is also connected to the power supply terminal through the first zero switch K10. The first zero switch K10 is used to conduct when the first transmission gate G1 is turned off, so that the transistor in the fifth feedback unit 1043 does not float, reducing external interference to the comparator. The control terminal of the sixth feedback unit 1044 is also connected to the power supply terminal through the zero-zero switch K00. The zero-zero switch K00 is used to conduct when the second transmission gate G2 is turned off, so that the transistor in the sixth feedback unit 1044 does not float, reducing external interference to the comparator.

[0187] The control terminal of the seventh feedback unit 1045 is also connected to the ground terminal through the zero-first switch K01. The zero-first switch K01 is used to turn on when the third transmission gate G3 is off, so that the transistor in the seventh feedback unit 1045 is not floating and the interference of external interference to the comparator is reduced. The control terminal of the eighth feedback unit 1046 is also connected to the ground terminal through the first switch K11. The first switch K11 is used to turn on when the fourth transmission gate G4 is off, so that the transistor in the eighth feedback unit 1046 is not floating and the interference of external interference to the comparator is reduced.

[0188] In one embodiment, if the seventh feedback transistor N11, the eighth feedback transistor N12, the zeroth switch K01, and the first switch K11 are N-type transistors, with the drain of the N-type transistor being the first terminal, the source of the N-type transistor being the second terminal, and the gate of the N-type transistor being the control terminal, the first terminal of the zeroth switch K01 is connected to the control terminal of the seventh feedback transistor N11, the first terminal of the first switch K11 is connected to the control terminal of the eighth feedback transistor N12, and the second terminals of the zeroth switch K01 and the first switch K11 are grounded, so as to pull the seventh feedback transistor N11 down to a low level when the third transmission gate G3 is turned off, and pull the eighth feedback transistor N12 down to a low level when the fourth transmission gate G4 is turned off.

[0189] In one embodiment, if the fifth feedback transistor P9, the sixth feedback transistor P10, the first zero switch K10, and the zero-zero switch K00 are P-type transistors, with the drain of the P-type transistor being the first terminal, the source of the P-type transistor being the second terminal, and the gate of the P-type transistor being the control terminal, the first terminal of the zero-first switch K01 is connected to the control terminal of the fifth feedback transistor P9, the first terminal of the zero-zero switch K00 is connected to the control terminal of the sixth feedback transistor P10, and the second terminals of the first zero switch K10 and the zero-zero switch K00 are grounded, so as to pull the fifth feedback transistor P9 to a high level when the third transmission gate G3 is turned off, and pull the sixth feedback transistor P10 to a high level when the fourth transmission gate G4 is turned off.

[0190] Figure 9 and Figure 10 For based on Figure 6 The circuit diagram shown represents one specific example of a comparator, wherein the structures of the first input circuit 101, the second input circuit 102, and the output circuit 105 are identical. Figure 5 The comparators shown are the same, and will not be described again here. The internal structure of each of the first controllable positive feedback modules 1047 and the second controllable positive feedback module 1048 in the second positive feedback circuit 104 has been described in detail. Figure 8 As described in the text, it will not be repeated here.

[0191] In the above embodiments, the first input circuit includes multiple controllable input modules, and the second positive feedback circuit includes multiple controllable positive feedback modules. By controlling the number of controllable positive feedback modules providing the positive feedback mechanism, the ability of the second positive feedback circuit to pull the voltages at the two output terminals of the second input circuit can be adjusted, thereby controlling the time the comparator is in the sampling phase. It can also balance the pulling power of the positive feedback circuit, the input signal, and the reference signal on the output terminal of the second input circuit, improving the comparator's response rate and accuracy. By controlling the number of controllable input modules, the ability of the second input circuit to pull the voltage at the output terminal of the first input circuit can be adjusted, preventing the second input circuit from having an excessively strong pulling power that could affect the polarity of the differential signal at the output terminal of the first input circuit. Furthermore, by setting the second input signal and the second reference signal at the current moment based on the first input signal and the first reference signal received by the first input circuit at the previous moment, inter-symbol interference at the first input terminal of the first input circuit can be effectively eliminated, thereby improving the comparator's accuracy.

[0192] like Figure 11 As shown, an embodiment of this application provides a decision feedback equalization circuit, including the four comparators described in the above embodiment, which are sequentially labeled as first comparator 100, second comparator 200, third comparator 300 and fourth comparator 400.

[0193] In this configuration, the third input terminal Vref2 of the first comparator 100 is connected to the first output terminal P270B of the fourth comparator 400, and the fourth input terminal In2 of the first comparator 100 is connected to the second output terminal P270 of the fourth comparator 400. The third input terminal Vref2 of the second comparator 200 is connected to the first output terminal P0B of the first comparator 100, and the fourth input terminal In2 of the second comparator 200 is connected to the second output terminal P0 of the first comparator 100. The third input terminal Vref2 of the third comparator 300 is connected to the first output terminal P90B of the second comparator 200, and the fourth input terminal In2 of the third comparator 300 is connected to the second output terminal P90 of the second comparator 200. The third input terminal Vref2 of the fourth comparator 400 is connected to the first output terminal P270B of the third comparator 400, and the fourth input terminal In2 of the fourth comparator 400 is connected to the second output terminal P270 of the third comparator 300.

[0194] The first input terminal In1 of the first comparator 100 to the fourth comparator 400 all receive the first input signal, and the second input terminal Vref1 of the first comparator 100 to the fourth comparator 400 all receive the first reference signal.

[0195] Assuming that at the previous moment, when the first input signal was greater than the first reference signal, the fourth register 400 output the number "1", at the current moment, the third input terminal Vref2 of the first register 100 receives a low level, and the fourth input terminal In2 of the first register 100 receives a high level. That is, the signal at the third input terminal Vref2 is less than the signal at the fourth input terminal In2. Assuming that the first input signal is also greater than the first reference signal at the current moment, inter-symbol interference will still make the first input signal greater than the first reference signal, and the first register 100 will still output the number "1".

[0196] Assuming that at the previous moment, when the first input signal was greater than the first reference signal, the fourth register 400 output the number "1". At the current moment, the signal at the third input terminal Vref2 of the first register is less than the signal at the fourth input terminal In2. Assuming that the first input signal is less than the first reference signal at the current moment, if inter-symbol interference makes the first input signal equal to or slightly greater than the first reference signal, the first register 100 will still output the number "0" because the signal at the third input terminal Vref2 is less than the signal at the fourth input terminal In2.

[0197] Assuming that at the previous moment, when the first input signal was less than the first reference signal, the fourth register 400 output the number "0", at the current moment, the signal at the third input terminal Vref2 of the first register 100 is greater than the signal at the fourth input terminal In2. Assuming that the first input signal is also less than the first reference signal at the current moment, inter-symbol interference will still cause the first input signal to be less than the first reference signal, and the first register 100 will still output the number "0".

[0198] Assuming that at the previous moment, when the first input signal was less than the first reference signal, the fourth register 400 output the number "0". At the current moment, the signal Vref2 at the third input terminal of the first register 100 is greater than the signal at the fourth input terminal In2. Assuming that the first input signal is greater than the first reference signal at the current moment, if inter-symbol interference makes the first input signal equal to or slightly less than the first reference signal, the first register 100 will still output the number "1" because the signal at the third input terminal is greater than the signal at the fourth input terminal.

[0199] The working principle of the second register 200 to the fourth register 400 is the same as that of the first register 100, and will not be repeated here.

[0200] Figure 11 The decision feedback equalization circuit shown is a first-order circuit. To achieve better elimination of inter-symbol interference, multi-order circuits are usually used. Figure 12 This is a schematic diagram of the effect of a fourth-order decision feedback equalizer circuit. Tap1 to tap4 represent the first-order to fourth-order decision feedback equalizer circuits, respectively. Figure 12As shown in Figure 1, the actual waveform of the first input signal under inter-symbol interference (ISI) is relatively flat when the first input signal switches from high to low level, indicating a possibility of misidentification of the first input signal as high. The fourth-order decision feedback equalization circuit effectively eliminates ISI, resulting in the equivalent waveform of the first input signal input to the equalization circuit, as shown in Figure 2, with a steeper falling edge.

[0201] In one embodiment, the phase of the first clock signal of the first comparator 100 is 90° earlier than the phase of the second clock signal of the second comparator 200, the phase of the first clock signal of the first comparator 100 is 180° earlier than the phase of the third clock signal of the third comparator 300, and the phase of the first clock signal of the first comparator 100 is 270° earlier than the phase of the fourth clock signal of the fourth comparator 400.

[0202] In one embodiment, the voltage switching time T at the output terminals of the first comparator 100 to the fourth comparator 400 is... FB Both are less than the time interval 1U1 between the first clock signal and the second clock signal, such as Figure 13 As shown, when the switching time of the output voltage of the fourth comparator 400 is less than 1U1, 1UI represents the time interval between the first clock signal and the second clock signal. This ensures that when the clock signal of the first comparator 100 arrives, the fourth comparator 400 has already stably output the comparison result, and the fourth comparator 400 maintains the comparison result, so that the first comparator 100 can eliminate inter-symbol interference based on the comparison result of the fourth comparator 400.

[0203] In one embodiment, the decision feedback equalization circuit further includes four registers, labeled sequentially as first register 500, second register 600, third register 700, and fourth register 800. The input of first register 500 is connected to the two outputs of first comparator 100, the input of second register 600 is connected to the two outputs of second comparator 200, the input of third register 700 is connected to the two outputs of third comparator 300, and the input of fourth register 800 is connected to the two outputs of fourth comparator 400. The four registers are used to store the comparison results of the four corresponding comparators: D0 is the result output by first register 500, D90 is the result output by second register 600, D180 is the result output by third register 700, and D270 is the result output by fourth register 800.

[0204] In the above technical solution, the two output terminals of the fourth register are connected to the two input terminals of the first register, and the two output terminals of the first register are connected to the two input terminals of the second register, and so on, to form a decision feedback equalization circuit. The other two input terminals of the four registers receive the first input signal and the first reference signal. Under the control of the output terminal signals of the four registers, the inter-symbol interference caused by the continuous input of the first input signal in the register can be effectively eliminated.

[0205] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0206] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A decision feedback equalization circuit, characterized in that, It includes four comparators, labeled as the first comparator, the second comparator, the third comparator, and the fourth comparator, respectively. Each of the comparators has four inputs and two outputs, including: The first input circuit has two pairs of transistors of different types. The control terminals of the two pairs of transistors serve as the input terminals of the comparator. The two pairs of transistors are used to receive a first input signal and a first reference signal, and are also used to generate a first differential signal based on the first input signal and the first reference signal during the sampling stage. A first positive feedback circuit is connected to the output of the first input circuit and is used to accelerate the difference between the first differential signals. The second input circuit has two pairs of transistors of different types. The control terminals of the two pairs of transistors serve as the input terminals of the comparator. The two pairs of transistors are used to receive the second input signal and the second reference signal, and are also used to generate a second differential signal based on the second input signal and the second reference signal during the sampling stage. The second positive feedback circuit is connected to the output of the second input circuit and is used to accelerate the difference between the second differential signals. The output circuit has an input terminal and an output terminal. Its output terminal is the output terminal of the comparator, and its input terminal is connected to the output terminal of the first input circuit. It is used to amplify and latch the voltage signal at the output terminal of the first input circuit and the voltage signal at the output terminal of the second input circuit during the regeneration phase, so as to output the comparison result. The first comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal directly connected to the first output terminal of the fourth comparator for receiving a second input signal, and a fourth input terminal directly connected to the second output terminal of the fourth comparator for receiving a second input signal. The second comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal directly connected to the first output terminal of the first comparator for receiving a second input signal, and a fourth input terminal directly connected to the second output terminal of the first comparator for receiving a second input signal. The third comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal directly connected to the first output terminal of the second comparator for receiving a second input signal, and a fourth input terminal directly connected to the second output terminal of the second comparator for receiving a second input signal. The fourth comparator has a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal directly connected to the first output terminal of the third comparator for receiving a second input signal, and a fourth input terminal directly connected to the second output terminal of the third comparator for receiving the second input signal.

2. The decision feedback equalization circuit according to claim 1, characterized in that, The first positive feedback circuit includes: The first feedback module is connected to the output terminal of the first input circuit and is used to pull the voltage at the output terminal of the first input circuit to accelerate the difference between the first differential signals. The second feedback module is connected to the output terminal of the first input circuit and is used to pull the voltage at the output terminal of the first input circuit to accelerate the difference between the first differential signals.

3. The decision feedback equalization circuit according to claim 2, characterized in that, The first input circuit has two output terminals; The first feedback module includes: The first feedback unit has its control terminal connected to the first output terminal of the first input circuit and its first terminal connected to the second output terminal of the first input circuit, and is used to pull the voltage of the second output terminal of the first input circuit according to the voltage of the first output terminal of the first input circuit. The second feedback unit has its control terminal connected to the second output terminal of the first input circuit and its first terminal connected to the first output terminal of the first input circuit. It is used to pull the voltage of the first output terminal of the first input circuit according to the voltage of the second output terminal of the first input circuit. The second feedback module includes: The third feedback unit has its control terminal connected to the first output terminal of the first input circuit and its first terminal connected to the second output terminal of the first input circuit. It is used to pull the voltage of the second output terminal of the first input circuit according to the voltage of the first output terminal of the first input circuit. The fourth feedback unit has its control terminal connected to the second output terminal of the first input circuit and its first terminal connected to the first output terminal of the first input circuit. It is used to pull the voltage of the first output terminal of the first input circuit according to the voltage of the second output terminal of the first input circuit.

4. The decision feedback equalization circuit according to claim 3, characterized in that: The first feedback unit includes: a first feedback transistor, whose control terminal is the control terminal of the first feedback unit, and whose second terminal is the first terminal of the first feedback unit; The second feedback unit includes: a second feedback transistor, whose control terminal is the control terminal of the second feedback unit, and whose second terminal is the first terminal of the second feedback unit; The third feedback unit includes: a third feedback transistor, whose control terminal is the control terminal of the third feedback unit, and whose first terminal is the first terminal of the third feedback unit; The fourth feedback unit includes: a fourth feedback transistor, whose control terminal is the control terminal of the fourth feedback unit, and whose first terminal is the first terminal of the fourth feedback unit.

5. The decision feedback equalization circuit according to claim 4, characterized in that, The first input circuit includes: The first input transistor has a control terminal for receiving the first input signal and a second terminal for serving as the first output terminal of the first input circuit. The second terminal is connected to the control terminal of the first feedback transistor and the second terminal of the second feedback transistor. The second input transistor has a control terminal for receiving the first reference signal and a second terminal for serving as the second output terminal of the first input circuit. The second terminal is connected to the control terminal of the second feedback transistor and the second terminal of the first feedback transistor. The third input transistor has a control terminal for receiving the first input signal, a first terminal connected to the second terminal of the first input transistor, and a first terminal connected to the control terminal of the third feedback transistor and the first terminal of the fourth feedback transistor. The fourth input transistor has a control terminal for receiving the first reference signal, a first terminal connected to the second terminal of the second input transistor, and a first terminal connected to the control terminal of the fourth feedback transistor and the first terminal of the third feedback transistor. The fifth input transistor has a control terminal for receiving clock signals. Its first terminal is connected to the second terminal of the third input transistor, the second terminal of the fourth input transistor, the second terminal of the third feedback transistor, and the second terminal of the fourth feedback transistor. Its second terminal is connected to the ground terminal or the power supply terminal.

6. The decision feedback equalization circuit according to claim 1, characterized in that, The second positive feedback circuit includes: The third feedback module is connected to the output terminal of the second input circuit and is used to accelerate the difference between the second differential signals by pulling the voltage at the output terminal of the second input circuit. The fourth feedback module is connected to the output terminal of the second input circuit and is used to accelerate the difference between the second differential signals by pulling the voltage at the output terminal of the second input circuit.

7. The decision feedback equalization circuit according to claim 6, characterized in that, The second input circuit has two output terminals; The third feedback module includes: The fifth feedback unit has its control terminal connected to the first output terminal of the second input circuit, and its first terminal connected to the second output terminal of the second input circuit. It is used to pull the voltage of the second output terminal of the second input circuit according to the voltage of the first output terminal of the second input circuit. The sixth feedback unit has its control terminal connected to the second output terminal of the second input circuit and its first terminal connected to the first output terminal of the second input circuit. It is used to pull the voltage of the first output terminal of the second input circuit according to the voltage of the second output terminal of the second input circuit. The fourth feedback module includes: The seventh feedback unit has its control terminal connected to the first output terminal of the second input circuit and its first terminal connected to the second output terminal of the second input circuit. It is used to pull the voltage of the second output terminal of the second input circuit according to the voltage of the first output terminal of the second input circuit. The eighth feedback unit has its control terminal connected to the second output terminal of the second input circuit and its first terminal connected to the first output terminal of the second input circuit. It is used to pull the voltage of the first output terminal of the second input circuit according to the voltage of the second output terminal of the second input circuit.

8. The decision feedback equalization circuit according to claim 7, characterized in that: The fifth feedback unit includes: a fifth feedback transistor, whose control terminal is the control terminal of the fifth feedback unit, and whose second terminal is the first terminal of the fifth feedback unit; The sixth feedback unit includes: a sixth feedback transistor, whose control terminal is the control terminal of the sixth feedback unit, and whose second terminal is the first terminal of the sixth feedback unit; The seventh feedback unit includes: a seventh feedback transistor, whose control terminal is the control terminal of the seventh feedback unit, and whose first terminal is the first terminal of the seventh feedback unit; The eighth feedback unit includes an eighth feedback transistor, whose control terminal is the control terminal of the eighth feedback unit, and whose first terminal is the first terminal of the eighth feedback unit.

9. The decision feedback equalization circuit according to claim 8, characterized in that, The second input circuit includes: The sixth input transistor has a control terminal for receiving the second input signal, and its second terminal serves as the first output terminal of the second input circuit. Its second terminal is connected to the control terminal of the fifth feedback transistor and the second terminal of the sixth feedback transistor. The seventh input transistor has a control terminal for receiving the second reference signal, and its second terminal serves as the second output terminal of the second input circuit. Its second terminal is connected to the control terminal of the sixth feedback transistor and the second terminal of the fifth feedback transistor. The eighth input transistor has a control terminal for receiving the second input signal, a first terminal connected to the second terminal of the sixth input transistor, and a first terminal connected to the control terminal of the seventh feedback transistor and the first terminal of the eighth feedback transistor. The ninth input transistor has a control terminal for receiving the second reference signal, a first terminal connected to the second terminal of the seventh input transistor, and a first terminal connected to the control terminal of the eighth feedback transistor and the first terminal of the seventh feedback transistor. The tenth input transistor has a control terminal for receiving clock signals. Its first terminal is connected to the second terminal of the eighth input transistor, the second terminal of the ninth input transistor, the second terminal of the seventh feedback transistor, and the second terminal of the eighth feedback transistor. Its second terminal is connected to the ground terminal or the power supply terminal.

10. The decision feedback equalization circuit according to claim 9, characterized in that: The first feedback transistor, the second feedback transistor, the fifth feedback transistor, the sixth feedback transistor, the first input transistor, the second input transistor, the sixth input transistor, and the seventh input transistor are of the same type; The third feedback transistor, fourth feedback transistor, seventh feedback transistor, eighth feedback transistor, third input transistor, fourth input transistor, fifth input transistor, eighth input transistor, ninth input transistor, and tenth input transistor are of the same type.

11. The decision feedback equalization circuit according to claim 10, characterized in that: The first feedback transistor and the second feedback transistor have the same size, the first input transistor and the second input transistor have the same size, and the size of the first feedback transistor is less than half the size of the first input transistor. The third feedback transistor and the fourth feedback transistor have the same size, and the third input transistor and the fourth input transistor have the same size. The size of the third feedback transistor is less than half the size of the third input transistor. The fifth feedback transistor and the sixth feedback transistor have the same size, and the sixth input transistor and the seventh input transistor have the same size. The size of the fifth feedback transistor is less than half the size of the sixth input transistor. The seventh feedback transistor and the eighth feedback transistor have the same size, and the eighth input transistor and the ninth input transistor have the same size. The size of the seventh feedback transistor is less than half the size of the eighth input transistor. The size of the sixth input transistor is less than half the size of the first input transistor; The size of the eighth input transistor is less than half the size of the third input transistor.

12. The decision feedback equalization circuit according to claim 11, characterized in that: When the first feedback transistor, the second feedback transistor, the fifth feedback transistor, the sixth feedback transistor, the first input transistor, the second input transistor, the sixth input transistor, and the seventh input transistor are P-type transistors, the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal; When the third feedback transistor, fourth feedback transistor, seventh feedback transistor, eighth feedback transistor, third input transistor, fourth input transistor, fifth input transistor, eighth input transistor, ninth input transistor, and tenth input transistor are N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal; or When the first feedback transistor, the second feedback transistor, the fifth feedback transistor, the sixth feedback transistor, the first input transistor, the second input transistor, the sixth input transistor, and the seventh input transistor are N-type transistors, the source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal; When the third feedback transistor, fourth feedback transistor, seventh feedback transistor, eighth feedback transistor, third input transistor, fourth input transistor, fifth input transistor, eighth input transistor, ninth input transistor, and tenth input transistor are P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

13. The decision feedback equalization circuit according to claim 1, characterized in that, The comparator further includes: A first reset circuit is connected between the first output terminal and the second output terminal of the first input circuit, and is used to reset the voltage at the first output terminal and the voltage at the second output terminal of the first input circuit. The second reset circuit is connected to the first output terminal of the output circuit and is used to reset the voltage of the first output terminal of the output circuit. The third reset circuit is connected to the second output terminal of the output circuit and is used to reset the voltage at the second output terminal of the output circuit.

14. The decision feedback equalization circuit according to claim 13, characterized in that, The first reset circuit includes: The first clock-controlled transistor has a control terminal that receives a clock signal and a second terminal that is connected to the first output terminal of the first input circuit. The second clock transistor has a control terminal that receives the clock signal, a second terminal that is connected to the second output terminal of the first input circuit, and a first terminal that is connected to the first terminal of the first clock transistor and then connected to a ground terminal or a power supply terminal. The second reset circuit includes: a third clock transistor, whose control terminal receives a clock signal, and whose second terminal is connected to the first output terminal of the output circuit; The third reset circuit includes a fourth clock transistor, whose control terminal receives a clock signal and whose second terminal is connected to the second output terminal of the output circuit.

15. The decision feedback equalization circuit according to claim 14, characterized in that, The first, second, third, and fourth clocked transistors are of the same type.

16. The decision feedback equalization circuit according to claim 1, characterized in that, The output circuit includes: The first output transistor has its second terminal being the first input terminal of the output circuit. The second output transistor has its second terminal being the second input terminal of the output circuit. The third output transistor has its control terminal connected to the control terminal of the first output transistor, and its control terminal is also connected to the second terminal of the fourth output transistor. The second terminal of the third output transistor serves as the first output terminal of the output circuit. The fourth output transistor has its control terminal connected to the control terminal of the second output transistor, and its control terminal is also connected to the second terminal of the third output transistor. The second terminal of the fourth output transistor serves as the second output terminal of the output circuit.

17. The decision feedback equalization circuit according to claim 16, characterized in that: If both the first output transistor and the second output transistor are N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal; If the third output transistor and the fourth output transistor are both P-type transistors, and the first to fourth clocked transistors are all P-type transistors, the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal. or Both the first output transistor and the second output transistor are P-type transistors, with the drain of the P-type transistor being the first terminal and the gate of the P-type transistor being the control terminal. The third and fourth output transistors are both N-type transistors, and the first to fourth clocked transistors are all N-type transistors. The source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

18. The decision feedback equalization circuit according to claim 6, characterized in that: The third feedback module includes at least one first controllable feedback submodule, and each first controllable feedback submodule includes: The fifth feedback unit has its control terminal connected to the first output terminal of the second input circuit via a first switch, and its first terminal connected to the second output terminal of the second input circuit. Under the control of the first switch, it is used to pull the voltage of the second output terminal of the second input circuit according to the voltage of the first output terminal of the second input circuit. The sixth feedback unit has its control terminal connected to the second output terminal of the second input circuit via a second switch, and its first terminal connected to the first output terminal of the second input circuit. It is used to pull the voltage of the first output terminal of the second input circuit according to the voltage of the second output terminal of the second input circuit under the control of the second switch. The fourth feedback module includes at least one second controllable feedback submodule, and each second controllable feedback submodule includes: The seventh feedback unit has its control terminal connected to the first output terminal of the second input circuit via a third switch, and its first terminal connected to the second output terminal of the second input circuit. Under the control of the third switch, it is used to pull the voltage of the second output terminal of the second input circuit according to the voltage of the first output terminal of the second input circuit. The eighth feedback unit has its control terminal connected to the second output terminal of the second input circuit via a fourth switch, and its first terminal connected to the first output terminal of the second input circuit. Under the control of the fourth switch, it is used to pull the voltage of the first output terminal of the second input circuit according to the voltage of the second output terminal of the second input circuit.

19. The decision feedback equalization circuit according to claim 18, characterized in that: The fifth feedback unit includes: a fifth feedback transistor, whose control terminal is the control terminal of the fifth feedback unit, and whose second terminal is the first terminal of the fifth feedback unit; The sixth feedback unit includes: a sixth feedback transistor, whose control terminal is the control terminal of the sixth feedback unit, and whose second terminal is the first terminal of the sixth feedback unit; The seventh feedback unit includes: a seventh feedback transistor, whose control terminal is the control terminal of the seventh feedback unit, and whose first terminal is the first terminal of the seventh feedback unit; The eighth feedback unit includes an eighth feedback transistor, whose control terminal is the control terminal of the eighth feedback unit, and whose first terminal is the first terminal of the eighth feedback unit.

20. The decision feedback equalization circuit according to claim 18, characterized in that: The first switch includes a first transmission gate, which is controlled by a first enable signal; The second switch includes a second transmission gate, which is controlled by a second enable signal; The third switch includes a third transmission gate, which is controlled by a third enable signal; The fourth switch includes a fourth transmission gate, which is controlled by a fourth enable signal; The first enable signal to the fourth enable signal are generated based on the operating frequency of the comparator, the input common-mode range of the comparator, and the test mode signal.

21. The decision feedback equalization circuit according to claim 18, characterized in that: The control terminal of the fifth feedback unit is also connected to the power supply terminal through the first zero switch; The control terminal of the sixth feedback unit is also connected to the power supply terminal via the zero-zero switch; The control terminal of the seventh feedback unit is also connected to the ground terminal via the zero-first switch; The control terminal of the eighth feedback unit is also connected to the ground terminal via the first switch.

22. The decision feedback equalization circuit according to claim 1, characterized in that: The phase of the first clock signal of the first comparator is 90° earlier than the phase of the second clock signal of the second comparator; The phase of the first clock signal of the first comparator is 180° earlier than the phase of the third clock signal of the third comparator; The phase of the first clock signal of the first comparator is 270° earlier than the phase of the fourth clock signal of the fourth comparator.

23. The decision feedback equalization circuit according to claim 22, characterized in that: The voltage flip time at the output of the first comparator and the voltage flip time at the output of the fourth comparator are both less than the time interval between the first clock signal and the second clock signal.

24. The decision feedback equalization circuit according to any one of claims 1 to 23, characterized in that, Also includes: The four registers are labeled as Register 1, Register 2, Register 3, and Register 4, respectively. The input terminal of the first register is connected to the two output terminals of the first comparator; The input of the second register is connected to the two outputs of the second comparator; The input of the third register is connected to the two outputs of the third comparator; The input of the fourth register is connected to the two outputs of the fourth comparator.

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