An isolated transmission circuit

Abstract

The application discloses an isolated transmission circuit, comprising: a level shift circuit, which is used for converting an input signal into a transmission signal with a first preset voltage; the voltage of the input signal is any voltage value between a first voltage and a second voltage, the first preset voltage is greater than the first voltage and less than the second voltage; an oscillator, which is used for generating a carrier signal; a modulation circuit, which is connected with the output end of the level shift circuit and the oscillator, and is used for mixing the transmission signal and the carrier signal and transmitting them to an isolation circuit; the isolation circuit is used for transmitting the transmission signal to a high-voltage side; a linear voltage regulator, which is connected with the output end of the level shift circuit, the oscillator and the modulation circuit, and is used for reducing the voltage of a driving power supply to a second preset voltage and supplying power to the level shift circuit, the oscillator and the modulation circuit. The circuit in the application can work under a wide range of input signal voltage and driving power supply voltage, and is suitable for a wide range of applications.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of analog integrated circuit technology, in particular to an isolated transmission circuit. BACKGROUND

[0002] Isolation refers to the electrical separation between various functional circuits in a system, so that signals are not transmitted through direct conduction paths between them, but the high-voltage domain and the low-voltage domain are separated by a physical layer, so that in the case where different circuits can have different ground potentials, the mutual influence between the two circuits is minimized. At present, the commonly used method is to use capacitive coupling method, and the corresponding capacitive isolation type driving circuit includes a sending end (a modulation module on the low-voltage side), a receiving end (a demodulation module on the high-voltage side) and an isolation capacitor. The sending end modulates the transmission signal into a signal that can pass through the isolation capacitor module, the receiving end demodulates the signal that passes through the isolation capacitor module into a transmission signal, and the isolation capacitor module connects the sending end and the receiving end.

[0003] At present, the low-voltage side input signal in the isolation type driving circuit is generally stable at a low voltage, but in the case of a large difference between the low-voltage domain and the high-voltage domain in industrial control, automotive electronics and other fields, isolation is required, and in the case of a large input voltage range on the low-voltage side, an isolation circuit with a wide voltage range on the low-voltage side is needed. SUMMARY

[0004] Therefore, in order to solve the above problems in the prior art, the present application provides an isolated transmission circuit.

[0005] To this end, the present application provides an isolated transmission circuit, comprising:

[0006] a level shift circuit for converting an input signal into a transmission signal with a first preset voltage; the voltage of the input signal is any voltage value between a first voltage and a second voltage, and the first preset voltage is greater than the first voltage and less than the second voltage;

[0007] an oscillator for generating a carrier signal;

[0008] a modulation circuit connected to the output end of the level shift circuit and the oscillator, for mixing the transmission signal and the carrier signal and transmitting them to an isolation circuit; the isolation circuit is used to transmit the transmission signal to the high-voltage side;

[0009] a linear voltage regulator connected to the output end of the level shift circuit, the oscillator and the modulation circuit, for reducing the voltage of the driving power supply to a second preset voltage and supplying power to the level shift circuit, the oscillator and the modulation circuit.

[0010] Further, the level shift circuit comprises:

[0011] PMOS transistor MP1 and PMOS transistor MP2, the source of both is connected to input signal after connecting resistor R1 and resistor R2 in series, the gate and drain of PMOS transistor MP1 and the gate of PMOS transistor MP2 are connected to a bias current source;

[0012] PMOS transistor MP3 and PMOS transistor MP4, the source of both is connected to the drain of PMOS transistor MP2, the gate of both is connected to a period control signal;

[0013] NMOS transistor MN1 and NMOS transistor MN2, the source of both is connected to the low level output end of a driving power supply, the drain and gate of NMOS transistor MN1 are connected to the drain of PMOS transistor MP3, the gate of NMOS transistor MN2 is connected to the gate of NMOS transistor MN1;

[0014] NMOS transistor MN3 and NMOS transistor MN4, the source of both is connected to the low level output end of a driving power supply, the drain and gate of NMOS transistor MN3 are connected to the drain of PMOS transistor MP4, the gate of NMOS transistor MN4 is connected to the gate of NMOS transistor MN3;

[0015] PMOS transistor MP5 and PMOS transistor MP6, the source of both is connected to the high level output end of a driving power supply, the gate and drain of PMOS transistor MP5 are connected to the drain of NMOS transistor MN4, the gate of PMOS transistor MP6 is connected to the gate of PMOS transistor MP5, the drain of PMOS transistor MP6 is connected to the drain of NMOS transistor MN2;

[0016] first Schmitt trigger circuit, first inverter and second inverter connected in sequence, the drain of PMOS transistor MP6 is connected to the input end of first Schmitt trigger circuit, the output end of second inverter outputs transmission signal.

[0017] Further, the output end of first inverter is connected to the gate of PMOS transistor MP4, the output signal of first inverter is the period control signal inputted to the gate of PMOS transistor MP4; the output end of second inverter is connected to the gate of PMOS transistor MP3, the output signal of second inverter is the period control signal inputted to the gate of PMOS transistor MP3.

[0018] Further, the level shift circuit further comprises:

[0019] NMOS transistor MN5 and NMOS transistor MN6, the source of both is connected to the low level output end of a driving power supply, the drain of NMOS transistor MN5 and the gate of NMOS transistor MN6 are connected to the drain of PMOS transistor MP3, the drain of NMOS transistor MN6 and the gate of NMOS transistor MN5 are connected to the drain of PMOS transistor MP4.

[0020] Further, the isolation transmission circuit further comprises:

[0021] The dead time generation circuit is connected between the level shift circuit and the modulation circuit.

[0022] Further, the dead time generation circuit comprises:

[0023] The third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the first capacitor, the second capacitor and the NAND gate, the input end of the third inverter is connected to the transmission signal output by the level shift circuit; and the output signal is connected to the input end of the NAND gate; the input end of the fourth inverter is connected to the output end of the third inverter, the output end of the fourth inverter is connected to the input end of the NAND gate and the input end of the fifth inverter, and the output end of the fourth inverter outputs the adjusted transmission signal of the first phase; the output end of the fifth inverter is connected to the input end of the sixth inverter, and the output end of the sixth inverter is connected to the input end of the NAND gate; one end of the first capacitor is connected between the third inverter and the fourth inverter, and the other end is grounded; one end of the second capacitor is connected between the fifth inverter and the sixth inverter, and the other end is grounded; the NAND gate outputs the adjusted transmission signal of the second phase.

[0024] Further, the oscillator comprises:

[0025] The zero-temperature-coefficient bias current source, the positive-temperature-coefficient current source, the positive-temperature-coefficient current sink, the PMOS tube MP7, the NMOS tube MN7, the NMOS tube MN8, the seventh inverter, the eighth inverter and the ninth inverter, the seventh inverter, the eighth inverter and the ninth inverter are connected in series to form a ring inverter chain; the zero-temperature-coefficient bias current source is connected to the drain of the NMOS tube MN7 to provide a bias current for the NMOS tube MN7, and the drain and the gate of the NMOS tube MN7 are connected to the bias end of the positive-temperature-coefficient current sink, the source is connected to the source of the NMOS tube MN8 and the ground end of the positive-temperature-coefficient current sink, and is connected to the low-level output end of the driving power supply; the gate of the NMOS tube MN8 is connected to the gate of the NMOS tube MN7, and the drain is connected to the drain of the PMOS tube MP7; the source of the PMOS tube MP7 is connected to the power supply end of the positive-temperature-coefficient current source, and is connected to the high-level output end of the driving power supply, and the drain and the gate of the PMOS tube MP7 are connected to the bias end of the positive-temperature-coefficient current source; the ground end of the positive-temperature-coefficient current source is connected to the power supply end of the ring inverter chain, and the ground end of the ring inverter chain is connected to the power supply end of the positive-temperature-coefficient current sink.

[0026] The technical scheme provided by the application has the following advantages:

[0027] 1. The transmission isolation circuit provided by the application can work under a wider range (first voltage to second voltage) of input signals by setting the level shift circuit which can convert the input signal (voltage value between the first voltage and the second voltage) into the transmission signal of the first preset voltage (the first preset voltage is between the first voltage and the second voltage); in addition, the transmission isolation circuit can work under a wider range of driving power supply by setting the driving power supply to supply power to other circuits of the transmission isolation circuit after passing through the linear voltage stabilizer, further improving the application range of the transmission isolation circuit.

[0028] 2. The isolation transmission circuit provided by the application reverses the output signals of the first inverter and the second inverter, and the voltage frequency required by the periodic control signal in the level shift circuit is the same, so that the output end of the first inverter is connected with the gate of the PMOS tube MP4, so that the periodic control signal connected with the gate of the PMOS tube MP4 is set, the output end of the second inverter is connected with the gate of the PMOS tube MP3, so that the periodic control signal connected with the gate of the PMOS tube MP3 is set, so that the isolation transmission circuit can realize self-adaptive control without external control signal, thereby reducing the application difficulty of the isolation transmission circuit and further expanding its application range.

[0029] 3. The isolation transmission circuit provided by the application can ensure that only one path in the path of the PMOS tube MP1 and the path of the PMOS tube MP2 is turned on and has current by setting the NMOS tube MN5 and the NMOS tube MN6, thereby improving the working stability of the isolation transmission circuit. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the specific embodiments of the application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0031] Figure 1 The structure diagram of the isolation transmission circuit provided by the embodiment of the application is shown in the figure;

[0032] Figure 2 The structure diagram of another isolation transmission circuit provided by the embodiment of the application is shown in the figure;

[0033] Figure 3 The structure diagram of the level shift circuit provided by the embodiment of the application is shown in the figure;

[0034] Figure 4Another structural schematic diagram of a level shift circuit provided by an embodiment of the present application is shown in FIG. 2.

[0035] Figure 5 A structural schematic diagram of an oscillator provided by an embodiment of the present application is shown in FIG. 3.

[0036] Figure 6 A structural schematic diagram of a dead time generation circuit provided by an embodiment of the present application is shown in FIG. 4.

[0037] Figure 7 A structural schematic diagram of a modulation circuit provided by an embodiment of the present application is shown in FIG. 5. DETAILED DESCRIPTION

[0038] The technical solutions of the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0039] In the description of the present application, it should be noted that the terms "upper", "lower", etc. indicate the orientation or positional relationship shown in the drawings, and are only for the purpose of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0040] Embodiment 1

[0041] Figure 1 A structural schematic diagram of an isolation transmission circuit in an embodiment of the present embodiment is shown, specifically, the isolation transmission circuit is a low-voltage side circuit in an isolation type driving circuit. As shown in FIG. 1, Figure 1 The isolation transmission circuit includes a level shift circuit, an oscillator, a modulation circuit and a linear voltage regulator.

[0042] Among them, as shown in FIG. 2, Figure 1As shown, the level shift circuit is used to convert the input signal into a transmission signal of a first preset voltage. Specifically, the voltage of the input signal is any voltage value between the first voltage and the second voltage, and the first preset voltage is greater than the first voltage and less than the second voltage. For example, the first voltage can be 3V, the second voltage can be 20V, and the first preset voltage can be 5V (and for ease of description, the following description is based on the first voltage, the second voltage and the first preset voltage as corresponding exemplary values). The oscillator is used to generate a carrier signal. The modulation circuit is connected to the output end of the level shift circuit and the oscillator to mix the transmission signal and the carrier signal and transmit it to the isolation circuit, and the isolation circuit is used to transmit the transmission signal to the high-voltage side. The output end of the linear regulator is connected to the level shift circuit, the oscillator and the modulation circuit to step down the voltage of the driving power supply to the second preset voltage and power the level shift circuit, the oscillator and the modulation circuit.

[0043] In practical applications, in order to further improve the applicability of the isolated transmission circuit, the linear regulator can be set as a low-voltage difference linear regulator. For example, the voltage range of the driving power supply can be between 5V and 18V, and the second preset voltage can be 5V.

[0044] Therefore, the transmission isolation circuit in this embodiment is configured to have a level shift circuit that can convert an input signal (voltage value between the first voltage and the second voltage) into a transmission signal of a first preset voltage (the first preset voltage is between the first voltage and the second voltage), so that the transmission isolation circuit can operate under input signals in a wider range (from the first voltage to the second voltage); in addition, by configuring a driving power supply to power other circuits of the transmission isolation circuit after passing through a linear regulator, the transmission isolation circuit can simultaneously operate under a wider range of driving power supplies, thereby further improving the scope of application of the transmission isolation circuit.

[0045] Figure 2 A schematic diagram of the structure of an isolated transmission circuit in another embodiment of the present invention is shown. Figure 1 The circuit structure also includes a dead time generating circuit arranged between the level shifting circuit and the modulation circuit to avoid clock overlap, the problem of erroneous start-up or simultaneous start-up of power tubes in subsequent circuits, and improve the practicality of the isolated transmission circuit.

[0046] Figure 3 FIG. 1 shows a schematic diagram of the structure of a level shift circuit in one implementation of this embodiment. Figure 3As shown, the level shift circuit can include: PMOS MP1 and PMOS MP2, the sources of which are connected to the input signal after the series connection of resistor R1 and resistor R2, and the gate and drain of PMOS MP1 and the gate of PMOS MP2 are connected to a bias current source I1; PMOS MP3 and PMOS MP4, the sources of which are connected to the drain of PMOS MP2, and the gates of which are connected to a period control signal EN; NMOS MN1 and NMOS MN2, the sources of which are connected to the low level output end of a driving power supply (according to Figure 1 It can be known that the driving power supply here and below refers to the driving power supply after being reduced by a linear voltage stabilizer), the drain and gate of NMOS MN1 are connected to the drain of PMOS MP3, and the gate of NMOS MN2 is connected to the gate of NMOS MN1; NMOS MN3 and NMOS MN4, the sources of which are connected to the low level output end of the driving power supply, the drain and gate of NMOS MN3 are connected to the drain of PMOS MP4, and the gate of NMOS MN4 is connected to the gate of NMOS MN3; PMOS MP5 and PMOS MP6, the sources of which are connected to the high level output end VDD of the driving power supply, the gate and drain of PMOS MP5 are connected to the drain of NMOS MN4, the gate of PMOS MP6 is connected to the gate of PMOS MP5, and the drain of PMOS MP6 is connected to the drain of NMOS MN2; a first Schmitt trigger circuit S1, a first inverter U1 and a second inverter U2 connected in sequence, the drain of PMOS MP6 is connected to the input end of the first Schmitt trigger circuit S1, and the output end of the second inverter U2 outputs a transmission signal.

[0047] The resistance R1, the resistance R2, the PMOS tube MP1 and the PMOS tube MP2 are a voltage reduction circuit; when the voltage of the input signal is higher than the first preset voltage (that is, the input voltage is between 5V and 20V), the voltage of the input signal can meet the working needs of the voltage reduction circuit, at this time, the voltage of the input signal is passed through the resistance R1, the resistance R2, the PMOS tube MP1 and the PMOS tube MP2, most of the voltage drop is in the above LDMOS tube and the resistance, and based on the opening and closing of the PMOS tube MP3 and the PMOS tube MP4 (controlled by the periodic control signal EN), the current change is converted into the opening and closing of the NMOS tube MN2 and the NMOS tube MN4 through the current mirror (the NMOS tube MN1, the NMOS tube MN3 and the PMOS tube MP5 are the current mirror, and are respectively mirrored to the NMOS tube MN2, the NMOS tube MN4 and the PMOS tube MP6), and then the transmission signal of 5V is output after the shaping of the first Schmitt trigger circuit S1, the first inverter U1 and the second inverter U2, so as to realize the voltage reduction and voltage stabilization; when the voltage of the input signal is lower than the first preset voltage (that is, the input voltage is between 3V and 5V), the voltage of the input signal cannot meet the working needs of the voltage reduction circuit, but due to the characteristics of the power MOS tube, the voltage drop on the PMOS tube MP2 is also reduced, the voltage remaining margin of the input signal after passing through the PMOS tube MP2 meets the demand of the normal working of the PMOS tube MP3 and the PMOS tube MP4, and the circuit current can still be transmitted to the first Schmitt trigger circuit S1, the first inverter U1 and the second inverter U2 behind through the current mirror, the first Schmitt trigger circuit S1, the first inverter U1 and the second inverter U2 normally work after receiving the current, and output the transmission signal of 5V, so as to realize the voltage increase and voltage stabilization.

[0048] Figure 4 The structure schematic diagram of the level shift circuit in another embodiment of the present embodiment is shown. Figure 4 As shown, compared with the above level shift circuit, the level shift circuit can further include the NMOS tube MN5 and the NMOS tube MN6, the sources of the two are connected with the low level output end of the driving power supply, the drain of the NMOS tube MN5 and the gate of the NMOS tube MN6 are connected with the drain of the PMOS tube MP3, and the drain of the NMOS tube MN6 and the gate of the NMOS tube MN5 are connected with the drain of the PMOS tube MP4.

[0049] Specifically, the gate terminal of the NMOS transistor MN5 is connected to the drain terminal of the PMOS transistor MP4, and the gate terminal of the NMOS transistor MN6 is connected to the drain terminal of the PMOS transistor MP3. When the PMOS transistor MP3 is turned off, the NMOS transistor MN6 is turned on, and when the PMOS transistor MP4 is turned off, the NMOS transistor MN5 is turned on. These transistors are mutually clamped to ensure that only one path between the PMOS transistor MP3 and the NMOS transistor MN5 or the PMOS transistor MP4 and the NMOS transistor MN6 is turned on and current flows, thereby improving the operating stability of the isolated transmission circuit in this embodiment.

[0050] In addition, the output signals of the first inverter U1 and the second inverter U2 are inverted and have the same voltage frequency as the periodic control signal EN in the level shift circuit. Figure 4 As shown, the output end of the first inverter U1 can also be connected to the gate of the PMOS transistor MP4, so that the output signal of the first inverter U1 is the periodic control signal connected to the gate of the PMOS transistor MP4; the output end of the second inverter U2 can be connected to the gate of the PMOS transistor MP3, so that the output signal of the second inverter U2 is the periodic control signal connected to the gate of the PMOS transistor MP3. As a result, the isolated transmission circuit in this embodiment can achieve adaptive control without adding an external control signal, thereby reducing its application difficulty and further expanding its scope of application.

[0051] Figure 5 FIG. 1 shows a schematic diagram of the structure of an oscillator in one implementation of this embodiment. Figure 5 As shown, the oscillator may include: a zero temperature coefficient bias current source I2, a positive temperature coefficient current source, a positive temperature coefficient current sink, a PMOS transistor MP7, an NMOS transistor MN7, an NMOS transistor MN8, a seventh inverter U7, an eighth inverter U8 and a ninth inverter U9, wherein the seventh inverter U7, the eighth inverter U8 and the ninth inverter U9 are connected end to end to form a ring inverter chain; the zero temperature coefficient bias current source I2 is connected to the drain of the NMOS transistor MN7 to provide a bias current for the NMOS transistor MN7, and the drain and gate of the NMOS transistor MN7 are both connected to the bias end of the positive temperature coefficient current sink, and the source of the NMOS transistor MN7 is connected to the The source of the NMOS transistor MN8 is connected to the ground terminal of the positive temperature coefficient current sink and is also connected to the low-level output terminal of the driving power supply; the gate of the NMOS transistor MN8 is connected to the gate of the NMOS transistor MN7, and the drain is connected to the drain of the PMOS transistor MP7; the source of the PMOS transistor MP7 is connected to the power supply terminal of the positive temperature coefficient current source and is connected to the high-level output terminal VDD of the driving power supply, and the drain and gate of the PMOS transistor MP7 are both connected to the bias terminal of the positive temperature coefficient current source; the ground terminal of the positive temperature coefficient current source is connected to the power supply terminal of the ring inverter chain, and the ground terminal of the ring inverter chain is connected to the power supply terminal of the positive temperature coefficient current sink.

[0052] Specifically, based on the discovery that device parameters in the oscillator are affected by temperature, when the bias current is a value independent of temperature, the oscillation frequency is not a fixed value, but will slightly decrease with the temperature value. Based on the fact that the current-starved oscillator has the characteristic that the oscillation frequency will increase with the increase of the inverter bias current, the oscillator in this embodiment is set to be a current-starved oscillator, and the bias current source and current sink therein are set as modules in which the bias current increases with the increase of temperature, that is, they have a positive temperature coefficient, thereby reducing the frequency deviation of the oscillator (when the base frequency is 500 MHz, the deviation frequency of the oscillator in this embodiment will be reduced to 10-20 MHz).

[0053] Figure 6 FIG. 1 shows a schematic diagram of the structure of a dead time generating circuit in one implementation of this embodiment. Figure 6 As shown, the dead time generating circuit may include: a third inverter U3, a fourth inverter U5, a fifth inverter U5, a sixth inverter U6, a first capacitor C1, a second capacitor C2 and a NAND gate N1, the input end of the third inverter U3 is connected to the transmission signal output by the level shift circuit; and the output signal is connected to the input end of the NAND gate N1; the input end of the fourth inverter U4 is connected to the output end of the third inverter U3, the output end of the fourth inverter U4 is connected to the input end of the NAND gate N1 and the input end of the fifth inverter U5, and the fourth The output end of the inverter U4 outputs the adjusted transmission signal (Vout+) of the first phase; the output end of the fifth inverter U5 is connected to the input end of the sixth inverter U6, and the output end of the sixth inverter U6 is connected to the input end of the NAND gate N1; one end of the first capacitor C1 is connected between the third inverter U3 and the fourth inverter U4, and the other end is grounded; one end of the second capacitor C2 is connected between the fifth inverter U5 and the sixth inverter U6, and the other end is grounded; the NAND gate N1 outputs the adjusted transmission signal (Vout-) of the second phase.

[0054] Specifically, the NAND gate N1 includes three inputs, namely the initial transmission signal (the initial here refers to the transmission signal initially transmitted to the dead time generating circuit), the transmission signal that generates a one-time delay (the transmission signal delayed by the third inverter U3 and the fourth inverter U4), and the transmission signal that generates a two-time delay (the transmission signal delayed by the third inverter U3 and the fourth inverter U4, and then delayed by the fifth inverter U5 and the sixth inverter U6). These three inputs jointly determine the output of the NAND gate N1. Specifically, the output of the NAND gate N1 is the input. Output 2 (Vout-) is a signal that is delayed twice and reversed from the initial transmission signal. Output 1 (Vout+) is a transmission signal that is delayed once. Since output 1 (Vout+) is the signal that controls output 2 (Vout-), when output 1 (Vout+) outputs digital logic 1, output 2 (Vout-) cannot output 1 at the same time. That is, output 1 (Vout-) and output 2 (Vout-) are complementary signals, which avoids clock overlap and prevents the problem of subsequent power tube misstart.

[0055] Figure 7 FIG. 1 shows a schematic diagram of the structure of a modulation circuit in one implementation of this embodiment. Figure 7 As shown, the modulation circuit may include: a tenth inverter U10, a second Schmitt shaping circuit S2, a first AND gate A1, a second AND gate A2, a first driver D1 and a second driver D2, wherein the input end of the second Schmitt shaping circuit S2 is connected to the output end of the oscillator, and the output end is connected to the tenth inverter U10 and the second AND gate A2, and the output end of the tenth inverter U10 is connected to the first AND gate A1; the input ends of the first AND gate A1 and the second AND gate A2 are also connected to the transmission signal; the output ends of the first AND gate A1 and the second AND gate A2 are respectively connected to the first driver D1 and the second driver D2, and the fully differential signals output by the output ends of the first driver D1 and the second driver D2 are transmitted to the isolation circuit (such as an isolation capacitor).

[0056] The modulation circuit in this embodiment adopts an OOK modulation scheme and converts the transmission signal into a fully differential signal for transmission to improve the common-mode rejection ratio. Specifically, the signal is shaped into a square wave of the same frequency by the second Schmidt shaping circuit S2, and the transmission signal is inverted by the tenth inverter U10. The inverted signal and the non-inverted signal are then simultaneously ANDed with the initial transmission signal (the initial here refers to the transmission signal initially transmitted to the modulation circuit) to generate a set of fully differential signals for transmission.

[0057] Obviously, the above embodiments are merely example for clearly illustrating but not limitation to the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the embodiments need not and can not be enumerated. The obvious changes or variations derived from the above description are still within the protection scope of the present application.

Claims

1. An isolated transmission circuit, characterized by, The application relates to a level shift circuit, which comprises: a level shift circuit for converting an input signal into a transmission signal with a first preset voltage; the voltage of the input signal is any voltage value between a first voltage and a second voltage, and the first preset voltage is greater than the first voltage and less than the second voltage; an oscillator for generating a carrier signal; a modulation circuit connected with the output terminals of the level shift circuit and the oscillator for mixing the transmission signal and the carrier signal and transmitting them to an isolation circuit; the isolation circuit for transmitting the transmission signal to a high-voltage side; a linear voltage stabilizer connected with the output terminals of the level shift circuit, the oscillator and the modulation circuit for reducing the voltage of a driving power supply to a second preset voltage and supplying power to the level shift circuit, the oscillator and the modulation circuit; the level shift circuit comprises: PMOS tubes MP1 and MP2, the sources of which are connected with the input signal through series connection of a resistor R1 and a resistor R2, and the gate and the drain of the PMOS tube MP1 and the gate of the PMOS tube MP2 are connected to a bias current source; PMOS tubes MP3 and MP4, the sources of which are connected with the drain of the PMOS tube MP2, and the gates of the two are connected with a period control signal; NMOS tubes MN1 and MN2, the sources of which are connected with the low-level output terminal of the driving power supply, the drain and the gate of the NMOS tube MN1 are connected with the drain of the PMOS tube MP3, and the gate of the NMOS tube MN2 is connected with the gate of the NMOS tube MN1; NMOS tubes MN3 and MN4, the sources of which are connected with the low-level output terminal of the driving power supply, the drain and the gate of the NMOS tube MN3 are connected with the drain of the PMOS tube MP4, and the gate of the NMOS tube MN4 is connected with the gate of the NMOS tube MN3; PMOS tubes MP5 and MP6, the sources of which are connected with the high-level output terminal of the driving power supply, the gate and the drain of the PMOS tube MP5 are connected with the drain of the NMOS tube MN4, the gate of the PMOS tube MP6 is connected with the gate of the PMOS tube MP5, and the drain of the PMOS tube MP6 is connected with the drain of the NMOS tube MN2; a first Schmitt trigger circuit, a first inverter and a second inverter connected in sequence, the drain of the PMOS tube MP6 is connected with the input terminal of the first Schmitt trigger circuit, and the output terminal of the second inverter outputs the transmission signal; the output terminal of the first inverter is connected with the gate of the PMOS tube MP4, and the output signal of the first inverter is the period control signal inputted to the gate of the PMOS tube MP4; the output terminal of the second inverter is connected with the gate of the PMOS tube MP3, and the output signal of the second inverter is the period control signal inputted to the gate of the PMOS tube MP3.

2. The isolated transmission circuit of claim 1, wherein, The level shift circuit further includes: The sources of the NMOS transistors MN5 and MN6 are both connected to the low-level output end of the driving power supply, the drain of the NMOS transistor MN5 and the gate of the NMOS transistor MN6 are both connected to the drain of the PMOS transistor MP3, and the drain of the NMOS transistor MN6 and the gate of the NMOS transistor MN5 are both connected to the drain of the PMOS transistor MP4.

3. An isolated transmission circuit according to claim 1 or 2, characterized in that, Also includes: A dead time generating circuit is connected between the level shifting circuit and the modulation circuit.

4. The isolated transmission circuit of claim 3, wherein, The dead time generating circuit comprises: A third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a first capacitor, a second capacitor, and a NAND gate are provided. The input of the third inverter is connected to the transmission signal output by the level shift circuit, and the output signal is connected to the input of the NAND gate. The input of the fourth inverter is connected to the output of the third inverter, the output of the fourth inverter is connected to the input of the NAND gate and the input of the fifth inverter, and the output of the fourth inverter outputs the adjusted transmission signal of the first phase. The output of the fifth inverter is connected to the input of the sixth inverter, and the output of the sixth inverter is connected to the input of the NAND gate. One end of the first capacitor is connected between the third inverter and the fourth inverter, and the other end is grounded. One end of the second capacitor is connected between the fifth inverter and the sixth inverter, and the other end is grounded. The NAND gate outputs the adjusted transmission signal of the second phase.

5. The isolated transmission circuit of claim 1, wherein, The oscillator comprises: A zero temperature coefficient bias current source, a positive temperature coefficient current source, a positive temperature coefficient current sink, a PMOS transistor MP7, an NMOS transistor MN7, an NMOS transistor MN8, a seventh inverter, an eighth inverter, and a ninth inverter, wherein the seventh inverter, the eighth inverter, and the ninth inverter are connected end to end to form a ring inverter chain; the zero temperature coefficient bias current source is connected to the drain of the NMOS transistor MN7 to provide a bias current for the NMOS transistor MN7, and the drain and gate of the NMOS transistor MN7 are both connected to the bias end of the positive temperature coefficient current sink, and the source is connected to the source of the NMOS transistor MN8 and the positive temperature coefficient current sink. The gate of the NMOS transistor MN8 is connected to the gate of the NMOS transistor MN7, and the drain is connected to the drain of the PMOS transistor MP7; the source of the PMOS transistor MP7 is connected to the power supply terminal of the positive temperature coefficient current source and connected to the high level output terminal of the driving power supply, and the drain and gate of the PMOS transistor MP7 are both connected to the bias terminal of the positive temperature coefficient current source; the ground terminal of the positive temperature coefficient current source is connected to the power supply terminal of the ring inverter chain, and the ground terminal of the ring inverter chain is connected to the power supply terminal of the positive temperature coefficient current sink.

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