Display substrate motherboard and leakage test method thereof

Abstract

The present application discloses a display substrate motherboard and a leakage test method thereof, relating to the display field. The display substrate motherboard has a non-display area and multiple display areas, with the non-display areas interspersed between the display areas. The display substrate motherboard includes: a driving circuit located in the display area, the driving circuit including at least one switching transistor; at least one test module located in the non-display area, the test module including at least a first test transistor and a second test transistor, the channel width-to-length ratio of the first test transistor being the same as the channel width-to-length ratio of the switching transistor; the channel width-to-length ratio of the second test transistor being different from the channel width-to-length ratio of the switching transistor, and the channel width of the second test transistor being the same as the channel width of the switching transistor, or the channel area of the second test transistor being the same as the channel area of the switching transistor. According to an embodiment of the present application, the leakage source of the switching transistor of the driving circuit in the display substrate motherboard can be determined.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display substrate motherboard and a leakage testing method thereof. Background Art

[0002] Flicker performance is a key concern in display products driven by thin-film transistors (TFTs). Thin-film transistor leakage is the primary cause of flicker in display products. In the display industry, electrical leakage levels are primarily measured qualitatively using optical and temporal measurements, but the underlying cause cannot be determined. Summary of the Invention

[0003] The embodiments of the present application provide a display substrate motherboard and a leakage testing method thereof, which can determine the leakage-related causes of the display substrate motherboard.

[0004] In a first aspect, an embodiment of the present application provides a display substrate motherboard having a non-display area and multiple display areas, wherein the non-display areas are separated from each other. The display substrate motherboard includes:

[0005] A driving circuit is located in the display area, and the driving circuit includes at least one switching transistor;

[0006] At least one test module is located in the non-display area, and the test module includes at least a first test transistor and a second test transistor, the channel width-to-length ratio of the first test transistor is the same as the channel width-to-length ratio of the switching transistor; the channel width-to-length ratio of the second test transistor is different from the channel width-to-length ratio of the switching transistor, and the channel width of the second test transistor is the same as the channel width of the switching transistor, or the channel area of the second test transistor is the same as the channel area of the switching transistor.

[0007] In a possible implementation of the first aspect, the channel width-to-length ratio of the second test transistor is smaller than the channel width-to-length ratio of the switch transistor, or the channel width-to-length ratio of the second test transistor is larger than the channel width-to-length ratio of the switch transistor.

[0008] In a possible implementation of the first aspect, the test module further includes a third test transistor, wherein the channel width-to-length ratio of the first test transistor is the same as the channel width-to-length ratio of the switching transistor, and the channel width and length of the first test transistor are respectively equal to the channel width and length of the switching transistor; the channel width-to-length ratio of the second test transistor is smaller than the channel width-to-length ratio of the switching transistor, and the channel width of the second test transistor is equal to the channel width of the first test transistor; the channel width-to-length ratio of the third test transistor is greater than the channel width-to-length ratio of the switching transistor, and the channel area of the third test transistor is equal to the channel area of the first test transistor or the second test transistor;

[0009] Preferably, the channel length of the second test transistor is n1 times the channel length of the switch transistor, where n1 is an integer greater than 1;

[0010] Preferably, the channel width of the third test transistor is n2 times the channel width of the switch transistor, where n2 is an integer greater than 1;

[0011] Preferably, the channel length of the third test transistor is n3 times the channel length of the switch transistor, where n3 is an integer greater than or equal to 1;

[0012] Preferably, n1=n2=2, n3=1.

[0013] In a possible implementation of the first aspect, at least one test module is provided around any display area;

[0014] Preferably, at least 12 test modules are arranged around any display area;

[0015] Preferably, 15 test modules are arranged around any display area.

[0016] In a possible implementation of the first aspect, the non-display area includes a cutting area, and the testing module is located in the cutting area.

[0017] In a second aspect, an embodiment of the present application provides a leakage testing method for a display substrate motherboard, for testing the display substrate motherboard as described in the first aspect, the method comprising:

[0018] Controlling each test transistor in each test module to be in an off state, and obtaining the off current corresponding to each test transistor in each test module under the same drain voltage;

[0019] Determine the shape parameters corresponding to each test transistor according to the cut-off current corresponding to each test transistor in each test module, wherein the shape parameters are used to characterize the leakage mechanism of the display substrate motherboard;

[0020] According to the shape parameters, the leakage type of the display substrate motherboard is determined.

[0021] In a possible implementation of the second aspect, the test module further includes a third test transistor, wherein the channel width-to-length ratio of the first test transistor is the same as the channel width-to-length ratio of the switching transistor, and the channel width and length of the first test transistor are respectively equal to the channel width and length of the switching transistor; the channel width-to-length ratio of the second test transistor is smaller than the channel width-to-length ratio of the switching transistor, and the channel width of the second test transistor is equal to the channel width of the first test transistor; the channel width-to-length ratio of the third test transistor is greater than the channel width-to-length ratio of the switching transistor, and the channel area of the third test transistor is equal to the channel area of the first test transistor or the second test transistor; the shape parameter includes a first shape parameter, a second shape parameter, and a third shape parameter, the first test transistor corresponds to the first shape parameter, the second test transistor corresponds to the second shape parameter, and the third test transistor corresponds to the third shape parameter; and determining the leakage type of the display substrate motherboard according to the shape parameter includes:

[0022] When the difference between the first shape parameter and the second shape parameter is greater than a first preset difference, determining that the leakage type of the display substrate motherboard includes an etching process abnormality;

[0023] When the difference between the first shape parameter and the third shape parameter is greater than the second preset difference, or the difference between the second shape parameter and the third shape parameter is greater than the second preset difference, it is determined that the leakage type of the display substrate motherboard includes an abnormal evaporation process.

[0024] In a possible implementation of the second aspect, determining a shape parameter corresponding to each test transistor according to a cutoff current corresponding to each test transistor includes:

[0025] Determine a cumulative probability density graph based on the cutoff current corresponding to each test transistor in each test module;

[0026] According to the cumulative probability density graph, the shape parameters corresponding to each test transistor are determined.

[0027] In a possible implementation of the second aspect, after determining the cumulative probability density map according to the cutoff current corresponding to each test transistor in each test module, the method further includes:

[0028] According to the cumulative probability density graph, a proportional parameter corresponding to each test transistor is determined, and the proportional parameter is used to characterize the magnitude of the intrinsic leakage current of each test transistor.

[0029] In a possible implementation of the second aspect, controlling each test transistor in each test module to be in a cut-off state includes:

[0030] Applying a voltage of 5V to the gate of each test transistor, applying a voltage of 0V to the source of each test transistor, and applying the same voltage within a preset range to the drain of each test transistor;

[0031] Preferably, the preset range includes -10V to 0V.

[0032] An embodiment of the present application provides a display substrate motherboard and a leakage test method thereof. The display substrate motherboard includes at least one test module, the test module including at least a first test transistor and a second test transistor. The channel width-to-length ratio of the first test transistor is the same as the channel width-to-length ratio of the switching transistor; the channel width-to-length ratio of the second test transistor is different from the channel width-to-length ratio of the switching transistor, and the channel width of the second test transistor is the same as the channel width of the switching transistor, or the channel area of the second test transistor is the same as the channel area of the switching transistor. The first test transistor and the second test transistor in the test module are prepared at the same time and process as the switching transistor, and leakage testing is performed on the first test transistor and the second test transistor in the test module. The shape parameters of each test transistor can be determined, and then the leakage source of the switching transistor in the driving circuit of the display substrate motherboard can be determined based on the shape parameters of each test transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0034] Figure 1 A schematic structural diagram of a pixel circuit in related art is shown;

[0035] Figure 2 A schematic structural diagram of a display substrate motherboard provided in an embodiment of the present application is shown;

[0036] Figure 3 A schematic diagram of the structure of the test module provided in an embodiment of the present application is shown;

[0037] Figure 4 Another structural diagram of the test module provided in an embodiment of the present application is shown;

[0038] Figure 5 Another structural schematic diagram of a display substrate motherboard provided in an embodiment of the present application is shown;

[0039] Figure 6 Another structural schematic diagram of a display substrate motherboard provided in an embodiment of the present application is shown;

[0040] Figure 7A schematic diagram showing a flow chart of a leakage testing method for a display substrate motherboard provided by an embodiment of the present application;

[0041] Figure 8 The cumulative probability density diagram provided by the embodiment of the present application is shown. DETAILED DESCRIPTION

[0042] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0043] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0044] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the component is turned over, the layer or region will be "below" or "beneath" the other layer or region.

[0045] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0046] In the embodiments of the present application, the term "connection" may refer to "electrical connection" or "electrical connection without an intermediate transistor". The term "insulation" may refer to "electrical insulation" or "electrical isolation". The term "drive" may refer to "control" or "operation". The term "part" may refer to "local". The term "pattern" may refer to "component". The term "end" may refer to "end segment" or "end edge". The display panel may be a display device or a module / part of a display device.

[0047] In the embodiment of the present application, the first node, the second node and the third node are only defined for the convenience of describing the circuit structure. The first node, the second node and the third node are not actual circuit units.

[0048] It will be apparent to those skilled in the art that various modifications and variations can be made in this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and variations of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the embodiments provided in the examples of this application can be combined with each other without contradiction.

[0049] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0050] Flicker refers to the degree to which the brightness of a display panel changes over a short period of time when the screen is displaying an image. It is an important indicator for measuring the stability of the screen's brightness display.

[0051] like Figure 1 As shown, the inventors have discovered that in a pixel circuit with a voltage threshold (Vth) compensation design, the charge on the capacitor C1 is lost within a frame time, making the gate voltage on the driving transistor M3 unable to stabilize within a frame. The change in the gate voltage of the driving transistor M3 causes its driving current (Ids) to fluctuate, thereby fluctuating the driving current Ids flowing through the light-emitting element OLED within a frame, and the corresponding brightness of the light-emitting element OLED fluctuates, causing the screen of the display panel to show corresponding pixel brightness fluctuations within a frame time. Among them, the main reason for the charge loss on the capacitor C1 within a frame time is the leakage of the switch thin film transistors (STFT) M4, M6, M7 and M8 directly associated with the capacitor.

[0052] The STFT leakage test method in the related art is: set Scan1 and Scan2 to high levels, and verify the leakage speed of different STFTs by changing different Vref values. Specifically, the process of the black state leakage test is to first light up the black screen for a period of time (such as 10s), and then quickly switch to the leakage test screen to measure the brightness change curve; the process of the white state leakage test is to first light up the white screen for a period of time (such as 10s), and then quickly switch to the leakage test screen to test the brightness change curve. The longer the black state test brightness rise time or the white state test brightness fall time, the smaller the STFT leakage.

[0053] The above method of measuring the STFT leakage level through optical quantities and time quantities cannot determine the cause of the leakage, nor can it determine the leakage size of the STFT.

[0054] To solve the above problems, embodiments of the present application provide a display substrate motherboard and a leakage testing method thereof. The following describes various embodiments of the display substrate motherboard and the leakage testing method thereof in conjunction with the accompanying drawings.

[0055] The following first introduces the display substrate motherboard provided by the embodiment of the present application. The display substrate motherboard provided by the embodiment of the present application can be an organic light emitting diode (OLED) display substrate motherboard.

[0056] Figure 2 A schematic top view of a display substrate motherboard provided in an embodiment of the present application is shown. Figure 3 A schematic diagram showing the structure of a test module provided in an embodiment of the present application is shown; Figure 4 Another structural schematic diagram of the test module provided in an embodiment of the present application is shown.

[0057] like Figure 2 and Figure 3 As shown, the display substrate motherboard 100 provided in the embodiment of the present application may have a non-display area NA and multiple display areas AA, with the non-display area NA spaced between the display areas AA. The display substrate motherboard 100 may include a driving circuit 10 and at least one test module 20.

[0058] The driving circuit 10 may be located in the display area AA, and may include at least one switching transistor 11. The driving circuit 10 may be arranged in an array, and may further include components such as capacitors.

[0059] For example, the driving circuit 10 may be a pixel circuit, and its structure may be as follows: Figure 1 The switch transistor 11 can be Figure 1 M4, M6, M7 and M8.

[0060] At least one test module 20 can be located in the non-display area NA. The test module 20 can include at least a first test transistor T1 and a second test transistor T2. The channel width-to-length ratio of the first test transistor T1 can be the same as the channel width-to-length ratio of the switching transistor 11; the channel width-to-length ratio of the second test transistor T2 can be different from the channel width-to-length ratio of the switching transistor 11, and can be the same as the channel width or channel area of the switching transistor 11.

[0061] An embodiment of the present application provides a display substrate motherboard, which includes at least one test module. The test module includes at least a first test transistor and a second test transistor. The channel width-to-length ratio of the first test transistor is the same as that of the switching transistor; the channel width-to-length ratio of the second test transistor is different from that of the switching transistor, and the channel width of the second test transistor is the same as that of the switching transistor, or the channel area of the second test transistor is the same as that of the switching transistor. The first test transistor and the second test transistor in the test module are prepared at the same time and process as the switching transistor, and leakage testing is performed on the first test transistor and the second test transistor in the test module to determine the shape parameters of each test transistor. Then, based on the shape parameters of each test transistor, the leakage source of the switching transistor in the driving circuit of the display substrate motherboard can be determined.

[0062] The channel width-to-length ratio of the second test transistor T2 may be different from that of the switching transistor 11, and the channel width of the second test transistor may be the same as that of the switching transistor 11. This may be understood as including at least one second test transistor T2 that may have a different channel width-to-length ratio from that of the switching transistor 11 and a channel width that is the same as that of the switching transistor. The channel area is determined by the channel width and the channel length. For example, when the channel is rectangular, the channel area is the product of the channel width and the channel length.

[0063] The channel width-to-length ratio can be understood as the ratio of the width to the length of the conductive channel of the transistor.

[0064] The gate width of the first test transistor T1 may be equal to the channel width of the first test transistor T1, the gate width of the second test transistor T2 may be equal to the channel width of the second test transistor T2, the gate length of the first test transistor T1 may be equal to the channel length of the first test transistor T1, and the gate length of the second test transistor T2 may be equal to the channel length of the second test transistor T2.

[0065] For example, the channel width of the switching transistor 11 is 2W, the channel length is L, and the channel width-to-length ratio is 2W / L. Then the channel width-to-length ratio of the first test transistor T1 can be 2W / L, and the channel width of the second test transistor T2 can be W, and the channel length can be 2L. At this time, the channel width-to-length ratio of the second test transistor is W / 2L.

[0066] In some optional implementations, the channel width-to-length ratio of the second test transistor may be smaller than the channel width-to-length ratio of the switch transistor, or the channel width-to-length ratio of the second test transistor may be larger than the channel width-to-length ratio of the switch transistor.

[0067] In this embodiment, the channel width-to-length ratio of the first test transistor is smaller than the channel width-to-length ratio of the switching transistor, or the channel width-to-length ratio of the second test transistor is larger than the channel width-to-length ratio of the switching transistor. The leakage source of the switching transistor of the driving circuit in the display substrate motherboard can be determined according to the test method of the display substrate motherboard introduced below.

[0068] Specifically, when the channel width-to-length ratio of the second test transistor T2 is smaller than the channel width-to-length ratio of the switching transistor 11, the channel width of the second test transistor T2 may be equal to the channel width of the switching transistor 11; when the channel width-to-length ratio of the second test transistor T2 is larger than the channel width-to-length ratio of the switching transistor 11, the channel area of the second test transistor T2 may be equal to the channel area of the switching transistor 11. Alternatively, when the channel width-to-length ratio of the second test transistor T2 is larger than the channel width-to-length ratio of the switching transistor 11, the channel width of the second test transistor T2 may be equal to the channel width of the switching transistor 11; when the channel width-to-length ratio of the second test transistor T2 is smaller than the channel width-to-length ratio of the switching transistor 11, the channel area of the second test transistor T2 may be equal to the channel area of the switching transistor 11.

[0069] like Figure 4 As shown, in some optional embodiments, the test module 20 may further include a third test transistor T3, the channel width-to-length ratio of the first test transistor T1 may be the same as the channel width-to-length ratio of the switching transistor 11, and the channel width and length of the first test transistor T1 may be respectively equal to the channel width and length of the switching transistor 11; the channel width-to-length ratio of the second test transistor T2 may be smaller than the channel width-to-length ratio of the switching transistor 11, and the channel width of the second test transistor T2 may be equal to the channel width of the first test transistor T1; the channel width-to-length ratio of the third test transistor T3 may be greater than the channel width-to-length ratio of the switching transistor 11, and the channel area of the third test transistor T3 may be equal to the channel area of the first test transistor T1 or the second test transistor T2.

[0070] In this embodiment, on the one hand, when the channel width and length of the first test transistor are respectively equal to the channel width and length of the switching transistor, and the channel width of the second test transistor is equal to the channel width of the first transistor but has a different aspect ratio, it is possible to determine whether the leakage source of the switching transistor in the driving circuit of the display substrate motherboard is an abnormality in the evaporation process according to the test method for the display substrate motherboard described below. On the other hand, when the channel width and length of the first test transistor are respectively equal to the channel width and length of the switching transistor, and the channel area of the third test transistor can be equal to the channel area of the first test transistor or the second test transistor but has a different aspect ratio, it is possible to determine whether the leakage source of the switching transistor in the driving circuit of the display substrate motherboard is an abnormality in the etching process according to the test method for the display substrate motherboard described below.

[0071] The channel width-to-length ratio of the first test transistor T1 may be the same as that of the switch transistor 11, the channel width of the first test transistor T1 may be the same as that of the switch transistor 11, and the channel length of the first test transistor T1 may be the same as that of the switch transistor 11. That is, the first test transistor T1 and the switch transistor 11 have the same design.

[0072] The channel area of the third test transistor T3 may be equal to the channel area of the first test transistor T1 or the second test transistor T2. It can be understood that the channel area of the third test transistor T3 may be equal to the channel area of the first test transistor T1, or the channel area of the third test transistor T3 may be equal to the channel area of the second test transistor T2.

[0073] Exemplarily, the channel width of the switching transistor 11 is W and the channel length is L, then the channel width of the first test transistor T1 is W and the channel length is L; the channel width of the second test transistor T2 can be W and the channel length can be 3L; the channel width of the third test transistor T3 can be 3W and the channel length can be L or 1 / 3L.

[0074] Optionally, the channel length of the second test transistor T2 is n1 times the channel length of the switch transistor 11 , where n1 is an integer greater than 1.

[0075] Optionally, the channel width of the third test transistor T3 is n2 times the channel width of the switch transistor 11, where n2 is an integer greater than 1.

[0076] Optionally, the channel length of the third test transistor T3 is n3 times the channel length of the switch transistor 11, where n3 is an integer greater than or equal to 1;

[0077] Optionally, n1=n2=2, n3=1.

[0078] In this embodiment, the channel length of the second test transistor can be n1 times the channel length of the switching transistor, the channel width of the third test transistor can be n2 times the channel width of the switching transistor, and the channel length of the third test transistor can be n3 times the channel length of the switching transistor. This allows the leakage source of the switching transistor in the driving circuit of the display substrate motherboard to be determined according to the display substrate motherboard testing method described below. In addition, the channel length of the second test transistor can be twice the channel length of the switching transistor, the channel width of the third test transistor can be twice the channel width of the switching transistor, and the channel length of the third test transistor can be equal to the channel length of the switching transistor. This can reduce the size of the first test transistor, the second test transistor, and the third test transistor, thereby reducing the size of the test module.

[0079] Exemplarily, the channel width of the switching transistor 11 is W and the channel length is L, then the channel width of the first test transistor T1 is W and the channel length is L; the channel width of the second test transistor T2 can be W and the channel length can be 2L; the channel width of the third test transistor T3 can be 2W and the channel length can be L or 1 / 2L.

[0080] In other optional implementations, the channel width-to-length ratio of the third test transistor T3 may be greater than that of the switch transistor 11 , or the channel width-to-length ratio of the third test transistor T3 may be less than that of the switch transistor 11 .

[0081] Optionally, the channel width-to-length ratio of the first test transistor T1 may be the same as the channel width-to-length ratio of the switching transistor 11, and the channel width and length of the first test transistor T1 may be respectively equal to the channel width and length of the switching transistor 11; the channel width-to-length ratio of the second test transistor T2 may be greater than the channel width-to-length ratio of the switching transistor 11, and the channel width of the second test transistor T2 may be equal to the channel width of the first test transistor T1; the channel width-to-length ratio of the third test transistor T3 may be greater than the channel width-to-length ratio of the switching transistor 11, and the channel area of the third test transistor T3 may be equal to the channel area of the first test transistor T1 or the second test transistor T2.

[0082] Exemplarily, the channel width of the switching transistor 11 is 2W, and the channel length is 2L; the channel width of the first test transistor T1 is 2W, and the channel length is 2L; the channel width of the second test transistor T2 can be 2W, and the channel length can be L; the channel width of the third test transistor T3 can be 4W, and the channel length can be L or 1 / 2L.

[0083] Optionally, the channel width-to-length ratio of the first test transistor T1 may be the same as the channel width-to-length ratio of the switching transistor 11, and the channel width and length of the first test transistor T1 may be respectively equal to the channel width and length of the switching transistor 11; the channel width-to-length ratio of the second test transistor T2 may be smaller than the channel width-to-length ratio of the switching transistor 11, and the channel width of the second test transistor T2 may be equal to the channel width of the first test transistor T1; the channel width-to-length ratio of the third test transistor T3 may be smaller than the channel width-to-length ratio of the switching transistor 11, and the channel area of the third test transistor T3 may be equal to the channel area of the first test transistor T1 or the second test transistor T2.

[0084] For example, the channel width of the switching transistor 11 is 2W and the channel length is 2L, then the channel width of the first test transistor T1 can be 2W and the channel length can be 2L; the channel width of the second test transistor T2 can be 2W and the channel length can be 3L; the channel width of the third test transistor T3 can be W and the channel length can be 4L or 6L.

[0085] Optionally, the channel width-to-length ratio of the first test transistor T1 may be the same as the channel width-to-length ratio of the switching transistor 11, and the channel width and length of the first test transistor T1 may be respectively equal to the channel width and length of the switching transistor 11; the channel width-to-length ratio of the second test transistor T2 may be greater than the channel width-to-length ratio of the switching transistor 11, and the channel width of the second test transistor T2 may be equal to the channel width of the first test transistor T1; the channel width-to-length ratio of the third test transistor T3 may be less than the channel width-to-length ratio of the switching transistor 11, and the channel area of the third test transistor T3 may be equal to the channel area of the first test transistor T1 or the second test transistor T2.

[0086] For example, the channel width of the switch transistor 11 is 2W and the channel length is 2L. The channel width of the first test transistor T1 is 2W and the channel length is 2L. The channel width of the second test transistor T2 can be 2W and the channel length can be L. The channel width of the third test transistor T3 can be W and the channel length can be 4L or 2L. In some optional embodiments, at least one test module 20 can be arranged around any display area AA.

[0087] Optionally, at least 12 test modules 20 are arranged around any display area AA.

[0088] Exemplarily, at least 12 test modules 20 are arranged around any display area AA, so that in the subsequent leakage test method of the display substrate motherboard, the at least 12 test modules 20 are subjected to leakage testing to obtain 12 cut-off currents corresponding to each test transistor, and then an accurate cumulative probability density diagram can be drawn through Minitab software, laying the foundation for subsequently improving the accuracy of determining the leakage type of the display substrate motherboard.

[0089] Optional, such as Figure 5 As shown, 15 test modules 10 may be arranged around any display area AA.

[0090] In this embodiment, the more test modules 20 are set around any display area AA, the more cutoff currents corresponding to each test transistor in each test module obtained by performing leakage tests on the test modules 20 according to the test method for the display substrate motherboard described below, and the more accurate the cumulative probability density graph determined based on the cutoff currents corresponding to each test transistor in each test module, the more accurate the shape parameters corresponding to each test transistor determined based on the cumulative probability density graph, and thus the more accurate the leakage type of the display substrate motherboard determined based on the shape parameters. Therefore, setting 15 test modules in any display area can draw a more accurate cumulative probability density graph using Minitab software compared to setting 1 or 12 test modules in the display area, laying the foundation for subsequently improving the accuracy of determining the leakage type of the display substrate motherboard.

[0091] In some optional embodiments, such as Figure 6 As shown, the non-display area NA includes a cutting area 30 , and the test module 20 can be located in the cutting area 30 .

[0092] The testing modules 20 may be arranged in the cutting area 30 in an interlaced manner.

[0093] In this embodiment, the test module 20 is disposed in the cutting area 30 so as not to occupy the display area of the display substrate motherboard. After the leakage test is performed on the display substrate motherboard, the test module in the cutting area can be directly removed.

[0094] Based on the same inventive concept, the present application also provides a leakage test method for a display substrate motherboard, such as Figure 7 As shown, the display substrate motherboard testing method can be used to test the display substrate motherboard provided by the above embodiment. At least twelve test modules can be set around any display area of the display substrate motherboard, and the display substrate motherboard testing method can include steps S710 to S730.

[0095] S710, controlling each test transistor in each test module to be in a cut-off state, and obtaining a cut-off current corresponding to each test transistor in each test module under the same drain voltage;

[0096] S720, determining shape parameters corresponding to each test transistor according to the cutoff current corresponding to each test transistor in each test module, where the shape parameters are used to characterize the leakage mechanism of the display substrate motherboard;

[0097] S730: Determine the leakage type of the display substrate motherboard according to the shape parameters.

[0098] An embodiment of the present application provides a method for testing leakage of a display substrate motherboard. The display substrate motherboard includes at least one test module, the test module including at least a first test transistor and a second test transistor. The channel width-to-length ratio of the first test transistor is the same as the channel width-to-length ratio of a switching transistor; the channel width-to-length ratio of the second test transistor is different from the channel width-to-length ratio of the switching transistor, and the channel width of the second test transistor is the same as the channel width of the switching transistor, or the channel area of the second test transistor is the same as the channel area of the switching transistor. The first test transistor and the second test transistor in the test module are respectively prepared at the same time and process as the switching transistor, and a leakage test is performed on at least two test transistors in the test module. The shape parameters of each test transistor can be determined, and then, based on the shape parameters of each test transistor, the leakage source of the switching transistor of the driving circuit in the display substrate motherboard can be determined.

[0099] In S710, controlling each test transistor in each test module to be in a cut-off state may include:

[0100] Applying a voltage of 5V to the gate of each test transistor, applying a voltage of 0V to the source of each test transistor, and applying the same voltage within a preset range to the drain of each test transistor;

[0101] Optionally, the preset range includes -10V to 0V.

[0102] In this embodiment, by applying a voltage of 5V to the gate of each test transistor, applying a voltage of 0V to the source of each test transistor, and applying the same voltage within a preset range to the drain of each test transistor, each test transistor in each test module can be controlled to be in a cut-off state, so that the leakage source of the switching transistor of the driving circuit in the display substrate motherboard can be determined according to the test method of the display substrate motherboard introduced below.

[0103] Specifically, a voltage of 5V is applied to the gate of each test transistor, and a voltage of 0V is applied to the source of each test transistor to ensure that the voltage difference Vgs between the gate and the source of the test transistor is 5V.

[0104] Exemplarily, obtaining the corresponding cutoff current of each test transistor at the same drain voltage may be obtaining the corresponding cutoff current of each test transistor at a drain voltage of -10V. The drain voltage may be any one within the range [-10, 0] and is not limited herein. For example, within the drain voltage range [-10, 0], different voltages are applied to the drain of each test transistor multiple times in steps of 0.5V. That is, voltages such as -10V, -9.5V, and -9V are sequentially applied to the drain of each test transistor.

[0105] In S720, after controlling each test transistor in each test module to be in a cut-off state and obtaining the cut-off current corresponding to each test transistor in each test module under the same leakage voltage, the shape parameters corresponding to each test transistor are determined according to the cut-off current corresponding to each test transistor in each test module.

[0106] In some optional implementations, determining the shape parameters corresponding to each test transistor according to the cutoff current corresponding to each test transistor in each test module may include:

[0107] Determine a cumulative probability density graph based on the cutoff current corresponding to each test transistor in each test module;

[0108] According to the cumulative probability density graph, the shape parameters corresponding to each test transistor are determined.

[0109] In this embodiment, the cumulative probability density diagram can be determined by the cutoff current corresponding to each test transistor in each test module, and then the shape parameters corresponding to each test transistor can be accurately determined based on the cumulative probability density diagram, so that the leakage source of the switching transistor of the driving circuit in the display substrate motherboard can be determined according to the test method of the display substrate motherboard introduced below.

[0110] The cumulative probability density plot can include cumulative probability density lines corresponding to each test transistor. The cumulative probability density line corresponds to the cumulative probability density function (CPDF). The CPDF describes the probability that the output value of a random variable will be below a certain value. When a random variable is plotted according to a Weibull distribution, the horizontal axis is displayed in logarithmic form. The slope of the CPDF corresponds to the shape parameter of the CPDF, which reflects the generation mechanism of the random variable. When the CPDF plot exhibits multiple slopes, the values of the random variables on each slope represent that these random variables correspond to the same generation mechanism. For example, if the random variable is leakage current data, each slope corresponds to the same leakage mechanism. In the Weibull distribution CPDF plot, the output value of the random variable corresponding to a cumulative probability value of 63.2% is the eigenvalue of the random variable. Its value is the scale parameter of the CPDF. The scale parameter does not change with changes in the shape parameter of the CPDF, meaning that the eigenvalue is independent of the generation mechanism.

[0111] From the perspective of probability theory and statistics, the Weibull distribution is a continuous probability distribution, and its probability density is:

[0112]

[0113] Wherein, x represents a random variable (i.e., the cutoff current in this application); represents the scale parameter (scaleparameter), k represents a shape parameter, k>0; the value of e is 2.718281828.

[0114] The cumulative probability distribution function of

[0115] After taking the logarithm twice, the above formula is transformed into:

[0116]

[0117] in, n is the number of data to be analyzed (ie, the number of test transistor leakage currents obtained in this application), and i is the serial number corresponding to the data to be analyzed.

[0118] As an example, n=100. After obtaining the cut-off current Ioff1 corresponding to the first test transistor in 100 test modules, the 100 cut-off currents Ioff1 corresponding to the first test transistor are arranged in ascending order. Then the cumulative probability distribution function corresponding to the cut-off current Ioff1 is F(Ioff1)=(i-0.3) / (n+0.4)=(i-0.3) / 100.4. Wherein, i is the serial number corresponding to the cut-off current Ioff1. Use Excel to calculate Ln(Ioff1) and Ln[-Ln(1-F(Ioff1))] corresponding to the 100 cut-off currents Ioff1, and use Ln(Ioff1) as the horizontal coordinate and Ln[-Ln(1-F(Ioff1))] as the vertical coordinate to draw the following picture. Figure 8 The graphic shown. Figure 8 The slope of the first cumulative probability density line y1 corresponds to the first shape parameter.

[0119] Similarly, according to the off-currents Ioff2 and Ioff3 corresponding to the second test transistor and the third test transistor respectively, the second cumulative probability density line y2 and the third cumulative probability density line y3 corresponding to the second test transistor and the third test transistor respectively are determined, thereby determining the cumulative probability density graph.

[0120] In the embodiment of the present application, n=12 is used as an example. That is, the number of leakage currents of the first test transistor is equal to the number of leakage currents of the second test transistor, which is equal to the number of leakage currents of the third test transistor. In actual implementation, the number of leakage currents of the first test transistor, the number of leakage currents of the second test transistor, and the number of leakage currents of the third test transistor may not be equal. For example, the number of leakage currents of the first test transistor is 12, the number of leakage currents of the second test transistor is 15, and the number of leakage currents of the third test transistor is 18.

[0121] As another example, the cutoff currents Ioff1, Ioff2, and Ioff3 corresponding to the first test transistor, the second test transistor, and the third test transistor in each test module are input into Minitab software, and a cumulative probability density graph is drawn using a Weibull distribution to generate a cumulative probability density graph with the cutoff current as the abscissa and the cumulative probability density as the ordinate. The cumulative probability density graph may include a first cumulative probability density line y1 corresponding to the first test transistor in each test module, a second cumulative probability density line y2 corresponding to the second test transistor in each test module, and a third cumulative probability density line y3 corresponding to the third test transistor in each test module.

[0122] After receiving the display parameter instruction, the minitab software displays the shape parameters corresponding to the first test transistor, the second test transistor, and the third test transistor, respectively, to determine the shape parameters corresponding to each test transistor, that is, determining the first shape parameter corresponding to the first test transistor, determining the second shape parameter corresponding to the second test transistor, and determining the third shape parameter corresponding to the third test transistor. Among them, the shape parameter is the slope corresponding to the cumulative probability density line, that is, the first shape parameter is the slope of the first cumulative probability density line y1, the second shape parameter is the slope of the second cumulative probability density line y2, and the third shape parameter is the slope of the third cumulative probability density line y3.

[0123] In some optional implementations, after determining the cumulative probability density map based on the cutoff current corresponding to each test transistor in each test module, the method may further include:

[0124] According to the cumulative probability density graph, a proportional parameter corresponding to each test transistor is determined, and the proportional parameter is used to characterize the magnitude of the intrinsic leakage current of each test transistor.

[0125] In this embodiment, the proportional parameter corresponding to each test transistor is determined through the cumulative probability density graph, so that the leakage level of each test transistor can be quantitatively analyzed.

[0126] As an example, Ln[-Ln(1-F(Ioff1))]=0 can be substituted into Formula 3 to calculate the value of Ln(Ioff1), which can then be further calculated to obtain the value of Ioff1. The value of Ioff1 is the first proportional parameter corresponding to the first test transistor. Similarly, Ln[-Ln(1-F(Ioff2))]=0 can be substituted into Formula 3 to calculate the value of Ln(Ioff2), which can then be further calculated to obtain the value of Ioff2. The value of Ioff2 is the second proportional parameter corresponding to the second test transistor. Ln[-Ln(1-F(Ioff3))]=0 can be substituted into Formula 3 to calculate the value of Ln(Ioff3), which can then be further calculated to obtain the value of Ioff3. The value of Ioff3 is the third proportional parameter corresponding to the third test transistor.

[0127] As another example, after receiving the display parameter instruction, the Minitab software displays the proportional parameters corresponding to the first test transistor, the second test transistor, and the third test transistor, respectively, to determine the shape parameters corresponding to each test transistor, that is, to determine the first proportional parameter corresponding to the first test transistor, the second proportional parameter corresponding to the second test transistor, and the third proportional parameter corresponding to the third test transistor. Among them, the first proportional parameter can be used to characterize the intrinsic leakage current of the first test transistor, the second proportional parameter can be used to characterize the intrinsic leakage current of the second test transistor, and the third proportional parameter can be used to characterize the intrinsic leakage current of the third test transistor. The first proportional parameter, the second proportional parameter, and the third proportional parameter of the same test module can be used to characterize the intrinsic leakage current of the test module.

[0128] This embodiment uses a Weibull distribution cumulative probability density plot as an example. In other embodiments, the cumulative probability density plot may also be a lognormal distribution cumulative probability density plot. When the lognormal distribution cumulative probability density plot is used, the process of determining the shape parameters and scale parameters of each test transistor using Minitab software is the same as the process of determining the shape parameters and scale parameters of each test transistor using Minitab software when the lognormal distribution cumulative probability density plot is used, and will not be repeated here.

[0129] In S730 , after determining the shape parameters corresponding to the test transistors according to the cut-off currents corresponding to the test transistors, the leakage type of the display substrate motherboard is determined according to the shape parameters.

[0130] In some optional embodiments, the test module may further include a third test transistor, wherein the channel width-to-length ratio of the first test transistor may be the same as the channel width-to-length ratio of the switching transistor, and the channel width and length of the first test transistor may be respectively equal to the channel width and length of the switching transistor; the channel width-to-length ratio of the second test transistor may be smaller than the channel width-to-length ratio of the switching transistor, and the channel width of the second test transistor may be equal to the channel width of the first test transistor; the channel width-to-length ratio of the third test transistor may be greater than the channel width-to-length ratio of the switching transistor, and the channel area of the third test transistor may be equal to the channel area of the first test transistor or the second test transistor; the shape parameters include a first shape parameter, a second shape parameter, and a third shape parameter, the first test transistor corresponds to the first shape parameter, the second test transistor corresponds to the second shape parameter, and the third test transistor corresponds to the third shape parameter; determining the leakage type of the display substrate motherboard according to the shape parameters may include:

[0131] When the difference between the first shape parameter and the second shape parameter is greater than a first preset difference, determining that the leakage type of the display substrate motherboard includes an abnormal evaporation process;

[0132] When the difference between the first shape parameter and the third shape parameter is greater than the second preset difference, or the difference between the second shape parameter and the third shape parameter is greater than the second preset difference, it is determined that the leakage type of the display substrate motherboard includes etching process abnormality.

[0133] The first preset difference and the second preset difference can be set according to actual conditions and are not limited here. For example, the first preset difference can be 10% of the first shape parameter, and the second preset difference can also be 10% of the first shape parameter.

[0134] In the application of this embodiment, the leakage intrinsic values of multiple test transistors will be different due to their different aspect ratios. Since the aspect ratio of the first test transistor is the same as that of the switching transistor, and the channel width and channel length are the same, the intrinsic leakage current of the first test transistor is the leakage current level of the switching transistor.

[0135] In the application of this embodiment, the slope values of the Weibull distribution cumulative probability density plot of the off-state current of the first test transistor and the second test transistor are similar, indicating that the leakage mechanism is the same. If the channel width of the first test transistor is the same as the channel width of the second test transistor, and the channel length of the first test transistor is different from the channel length of the second test transistor, and the particle density is the same and the process level is consistent, if the slope values of the two are significantly different, it indicates that the leakage mechanism is different and there is a process risk related to the area.

[0136] In this embodiment, if the slope values of the Weibull distribution cumulative probability density plot for the off-state currents of the second and third test transistors are similar, this indicates the same leakage mechanism. If the channel areas of the second and third test transistors are equal, and the leakage levels caused by particles are similar, a significant difference in their slope values indicates that, in addition to particle-related leakage, there are also potential process risks related to the channel width-to-length ratio.

[0137] On the one hand, since the channel width of the second test transistor is equal to the channel width of the first test transistor, the channel length of the second test transistor is different from the channel length of the first test transistor, and the difference between the first shape parameter and the second shape parameter is greater than the first preset difference, it indicates that the second test transistor and the first test transistor have different leakage mechanisms, and the unit channel area defect is directly related to the evaporation process. Therefore, it can be inferred that the leakage mechanism is related to the evaporation process, that is, there is a process anomaly related to the gate channel evaporation. On the other hand, since the channel area of the third test transistor is equal to the channel area of the first test transistor or the second test transistor, when the difference between the second shape parameter and the third shape parameter is greater than the second preset difference, or the difference between the first shape parameter and the third shape parameter is greater than the second preset difference, it indicates that when the channel area is equal, a new leakage mechanism still exists. Usually, when the channel area is the same, the etching effect of a narrow and long channel is significantly different from that of a flat and thick channel. Therefore, when the difference between the second shape parameter and the third shape parameter is greater than the second preset difference, or the difference between the first shape parameter and the third shape parameter is greater than the second preset difference, it is determined that there is an abnormality in the etching process of the leakage type of the display substrate motherboard, that is, there is a process abnormality related to gate channel etching.

[0138] While the embodiments described above are not exhaustive, they do not limit the present application to the specific embodiments described. Clearly, numerous modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present application, thereby enabling those skilled in the art to better utilize the present application and its modifications. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display substrate motherboard, characterized in that: The motherboard has a non-display area and multiple display areas, wherein the non-display areas are spaced between the display areas. The motherboard includes: A driving circuit is located in the display area, and the driving circuit includes at least one switching transistor; At least one test module is located in the non-display area, and the test module includes at least a first test transistor and a second test transistor, the channel width-to-length ratio of the first test transistor is the same as the channel width-to-length ratio of the switching transistor; the channel width-to-length ratio of the second test transistor is different from the channel width-to-length ratio of the switching transistor, and the channel width of the second test transistor is the same as the channel width of the switching transistor, or the channel area of the second test transistor is the same as the channel area of the switching transistor.

2. The display substrate motherboard according to claim 1, wherein: The channel width-to-length ratio of the second test transistor is smaller than the channel width-to-length ratio of the switch transistor, or the channel width-to-length ratio of the second test transistor is larger than the channel width-to-length ratio of the switch transistor.

3. The display substrate motherboard according to claim 2, characterized in that: The test module also includes a third test transistor, wherein the channel width-to-length ratio of the first test transistor is the same as the channel width-to-length ratio of the switching transistor, and the channel width and length of the first test transistor are respectively equal to the channel width and length of the switching transistor; the channel width-to-length ratio of the second test transistor is smaller than the channel width-to-length ratio of the switching transistor, and the channel width of the second test transistor is equal to the channel width of the first test transistor; the channel width-to-length ratio of the third test transistor is greater than the channel width-to-length ratio of the switching transistor, and the channel area of the third test transistor is equal to the channel area of the first test transistor or the second test transistor.

4. The display substrate motherboard according to claim 3, wherein: The channel length of the second test transistor is n1 times the channel length of the switch transistor, where n1 is an integer greater than 1.

5. The display substrate motherboard according to claim 4, characterized in that: The channel width of the third test transistor is n2 times the channel width of the switch transistor, where n2 is an integer greater than 1.

6. The display substrate motherboard according to claim 5, characterized in that: The channel length of the third test transistor is n3 times the channel length of the switch transistor, where n3 is an integer greater than or equal to 1.

7. The display substrate motherboard according to claim 6, characterized in that: n1=n2=2, n3=1.

8. The display substrate motherboard according to any one of claims 1 to 7, characterized in that: At least one of the test modules is arranged around any one of the display areas.

9. The display substrate motherboard according to claim 8, characterized in that: At least 12 test modules are arranged around any one of the display areas.

10. The display substrate motherboard according to claim 8, wherein: Fifteen test modules are arranged around any one of the display areas.

11. The display substrate motherboard according to any one of claims 1 to 7, characterized in that: The non-display area includes a cutting area, and the test module is located in the cutting area.

12. A method for testing leakage of a display substrate motherboard, characterized in that: For testing the display substrate motherboard according to any one of claims 1 to 11, the method comprising: Controlling each of the test transistors in each of the test modules to be in an off state, and obtaining an off current corresponding to each of the test transistors in each of the test modules under the same drain voltage; determining shape parameters corresponding to the respective test transistors according to the cut-off currents corresponding to the respective test transistors in the respective test modules, wherein the shape parameters are used to characterize the leakage mechanism of the display substrate motherboard; The leakage type of the display substrate motherboard is determined according to the shape parameters.

13. The method for testing leakage of a display substrate motherboard according to claim 12, wherein: The test module further includes a third test transistor, wherein the channel width-to-length ratio of the first test transistor is the same as that of the switch transistor, and the channel width and length of the first test transistor are respectively equal to the channel width and length of the switch transistor; the channel width-to-length ratio of the second test transistor is smaller than that of the switch transistor, and the channel width of the second test transistor is equal to the channel width of the first test transistor; the channel width-to-length ratio of the third test transistor is larger than that of the switch transistor, and the channel area of the third test transistor is equal to the channel area of the first test transistor or the second test transistor; the shape parameters include a first shape parameter, a second shape parameter, and a third shape parameter, the first test transistor corresponds to the first shape parameter, the second test transistor corresponds to the second shape parameter, and the third test transistor corresponds to the third shape parameter; The determining of the leakage type of the display substrate motherboard according to the shape parameter includes: When the difference between the first shape parameter and the second shape parameter is greater than a first preset difference, determining that the leakage type of the display substrate motherboard includes an abnormal evaporation process; When the difference between the first shape parameter and the third shape parameter is greater than the second preset difference, or the difference between the second shape parameter and the third shape parameter is greater than the second preset difference, it is determined that the leakage type of the display substrate motherboard includes etching process abnormality.

14. The method for testing leakage of a display substrate motherboard according to claim 12, wherein: Determining the shape parameters corresponding to the respective test transistors according to the cut-off currents corresponding to the respective test transistors in the respective test modules includes: Determining a cumulative probability density graph according to the cut-off current corresponding to each test transistor in each of the test modules; According to the cumulative probability density graph, shape parameters corresponding to each test transistor are determined.

15. The leakage testing method for a display substrate motherboard according to claim 14, characterized in that: After determining the cumulative probability density map according to the cut-off current corresponding to each test transistor in each test module, the method further includes: According to the cumulative probability density graph, a proportional parameter corresponding to each test transistor is determined, and the proportional parameter is used to characterize the magnitude of the intrinsic leakage current of each test transistor.

16. The method for testing leakage of a display substrate motherboard according to claim 12, wherein: The controlling each of the test transistors in each of the test modules to be in a cut-off state includes: A voltage of 5V is applied to the gate of each test transistor, a voltage of 0V is applied to the source of each test transistor, and the same voltage within a preset range is applied to the drain of each test transistor.

17. The method for testing leakage of a display substrate motherboard according to claim 16, wherein: The preset range includes -10V to 0V.

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