Circuit structure and layout structure of magnetoresistive random access memory

Abstract

The present invention discloses a circuit structure and layout structure of a magnetoresistive random access memory, wherein a storage unit in the magnetoresistive random access memory circuit structure has three transistors and four magnetic tunnel junctions connected in series in sequence, wherein the connection point between the first transistor and the third transistor is a first node, the connection point between the second transistor and the third transistor is a second node, the other ends of the first transistor and the third transistor are connected to a common source line, the first magnetic tunnel junction and the second magnetic tunnel junction are connected in series to form a first magnetic tunnel junction group, one end of which is connected to the first node, and the third magnetic tunnel junction and the fourth magnetic tunnel junction are connected in series to form a second magnetic tunnel junction group, one end of which is connected to the second node.

Description

Technical Field

[0001] The present invention relates to a circuit structure and layout structure of a magnetoresistive random access memory (MRAM), and more specifically, to a circuit structure and layout structure of a spin transfer torque (STT) magnetoresistive random access memory (MRAM) in which each memory unit cell has three transistors and four magnetic tunneling junctions (3T4M). Background Art

[0002] Magnetoresistive random access memory (MRAM) is a new type of memory that has garnered significant attention in recent years. It combines the advantages of various existing memory technologies, such as access speed comparable to static random access memory (SRAM), the non-volatility and low power consumption of flash memory (Flash), and the high density and durability of dynamic random access memory (DRAM). Furthermore, it can be integrated with current semiconductor back-end manufacturing processes, giving it the potential to become a primary memory device used in semiconductor chips. MRAM consists of a memory stack structure, including a magnetic tunneling junction (MTJ), disposed between upper and lower interconnect structures. Unlike traditional memory, which stores data by storing charge, MRAM operates by applying an external magnetic field to the MTJ to control its magnetization direction, thereby generating different tunneling magnetoresistances (TMR) to store digital data.

[0003] Among magnetoresistive random access memories, spin-transfer torque magnetoresistive random access memory (STT-MRAM) uses the spin energy of electrons to generate torque on ferromagnetic atoms, flipping their magnetization direction and thus storing data. Compared to conventional magnetoresistive random access memory (MRAM) that uses magnetic fields to flip charge carriers, STT-MRAM offers advantages such as low power consumption and good scalability, making it a promising candidate for development.

[0004] Some current spin-transfer magnetoresistive random access memories (STMs) utilize a dual-bit 1T2M or 2T2M architecture, meaning each memory cell consists of one transistor and two series-connected magnetic tunneling junctions, or two transistors and two series-connected magnetic tunneling junctions. This design suffers from slow read and write speeds. Furthermore, with the increasing miniaturization of electronic products, accommodating more memory cells within a limited layout area is a pressing research and development challenge for those skilled in the art. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art and the current needs of the invention, the present invention proposes a novel circuit structure and layout structure of a magnetoresistive random access memory. The novel circuit structure and layout structure adopt a dual-bit 3T4M circuit architecture to significantly increase the read and write speeds, and the required layout area can be further reduced.

[0006] One aspect of the present invention is to provide a magnetoresistive random access memory circuit structure having a plurality of memory cells, wherein each memory cell includes three transistors, namely a first transistor, a third transistor, and a second transistor connected in series in sequence, wherein the connection point between the first transistor and the third transistor is a first node, and the connection point between the second transistor and the third transistor is a second node, and the other ends of the first transistor and the second transistor are connected to a common source line and four magnetic tunnel junctions, namely a first magnetic tunnel junction, a second magnetic tunnel junction, a third magnetic tunnel junction, and a fourth magnetic tunnel junction, wherein the first magnetic tunnel junction and the second magnetic tunnel junction are connected in series to form a first magnetic tunnel junction group, one end of which is connected to the first node, and the third magnetic tunnel junction and the fourth magnetic tunnel junction are connected in series to form a second magnetic tunnel junction group, one end of which is connected to the second node.

[0007] Another aspect of the present invention is to provide a magnetoresistive random access memory layout structure having a plurality of memory cells, wherein each memory cell includes a substrate on which a plurality of active regions are formed, a first word line, a second word line, and a third word line are formed, each extending across the active regions, wherein the active region located outside the first word line is a first active region, the active region located between the first and second word lines is a second active region, the active region located between the second and third word lines is a third active region, the active region located outside the third word line is a fourth active region, and four magnetic tunnel junctions are provided, namely, a first magnetic tunnel junction, a second magnetic tunnel junction, a third magnetic tunnel junction, and a fourth magnetic tunnel junction. The first magnetic tunnel junction has two ends connected to the second active region and one end of the second magnetic tunnel junction, respectively; the third magnetic tunnel junction has two ends connected to the third active region and one end of the fourth magnetic tunnel junction, respectively; and the first and second bit lines are connected to the other end of the second magnetic tunnel junction and the other end of the fourth magnetic tunnel junction, respectively.

[0008] These and other objects of the present invention will become more readily apparent after reading the following detailed description of the preferred embodiment which is illustrated in various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] This specification includes accompanying drawings, which constitute a part of this specification and provide a further understanding of embodiments of the present invention. These drawings depict some embodiments of the present invention and, together with the description herein, illustrate the principles thereof. In these drawings:

[0010] Figure 1 FIG1 is a circuit diagram of a 3T4M architecture spin-transfer torque magnetoresistive random access memory (STT-MRAM) according to a preferred embodiment of the present invention;

[0011] Figure 2 A layout diagram of a 3T4M-architected STT-MRAM in a preferred embodiment of the present invention;

[0012] Figure 3 A three-dimensional diagram of a 3T4M-structured STT-MRAM in a preferred embodiment of the present invention;

[0013] Figure 4 Schematic diagram of the layout of the memory cell of the 3T4M architecture STT-MRAM in a preferred embodiment of the present invention;

[0014] Figure 5 A schematic diagram of a circuit of a 3T4M STT-MRAM in a read operation according to a preferred embodiment of the present invention;

[0015] Figure 6A schematic diagram of a circuit of a 3T4M STT-MRAM in a preferred embodiment of the present invention in a high-performance read mode and a low-power read mode;

[0016] Figure 7 A schematic diagram of a circuit of a 3T4M STT-MRAM in a symmetric write operation according to a preferred embodiment of the present invention;

[0017] Figure 8 A schematic circuit diagram of a 3T4M STT-MRAM in a complementary write operation in a preferred embodiment of the present invention; and

[0018] Figure 9 FIG. 4 is a circuit diagram of a 24-bit memory array composed of six memory cells in a preferred embodiment of the present invention.

[0019] Description of main component symbols

[0020] AA Active area

[0021] BL, BL1~BL4 bit lines

[0022] CT contacts

[0023] D1 First direction

[0024] D2 Second direction

[0025] L length

[0026] M1 first metal layer

[0027] M2 second metal layer

[0028] M4 fourth metal layer

[0029] MTJ1~MTJ4 Magnetic Tunnel Junction

[0030] N1 first node

[0031] N2 first node

[0032] P pitch

[0033] R1, R2 resistance values

[0034] S1, S2 magnetic tunnel junction group

[0035] SL, SL1~SL3 source line

[0036] STI shallow trench isolation structure

[0037] T1~T3 transistors

[0038] UC Storage Unit

[0039] V1~V3 guide hole parts

[0040] W1~W4 distribution section

[0041] WL, WL1~WL6 character lines DETAILED DESCRIPTION

[0042] The following will now describe in detail exemplary embodiments of the present invention, which are illustrated in the accompanying diagrams so that the reader can understand and practice the present disclosure and appreciate its technical efficacy. It should be noted that the following description is provided by way of example only and is not intended to limit the disclosure of the present invention. The various embodiments and the various features of these embodiments in this disclosure can be combined and rearranged in a variety of different ways without conflicting with each other. Without departing from the spirit and scope of this disclosure, various modifications, counterparts, or improvements to the disclosure of the present invention should be understood by those skilled in the art and are intended to be included within the scope of the disclosure of the present invention.

[0043] It should be easily understood that the meanings of “on,” “over,” and “above” in this document should be interpreted in the broadest manner, so that “on” not only means “directly on something,” but also includes being on something with intermediate features or layers between the two, and “on” or “above” not only means being on something or above something, but also includes having no intermediate features or layers between the two (i.e., directly on something).

[0044] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used in the specification to describe the relationship of one element or feature to another element or features, as illustrated in the drawings. These spatially relative terms are intended to encompass different orientations or positions of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used in the specification should be interpreted accordingly.

[0045] As used herein, the term "substrate" refers to the material onto which subsequent materials are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or left unpatterned. Furthermore, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0046] First, please refer to Figure 1This is a circuit diagram of a 3T4M spin-transfer magnetoresistive random access memory (STT-MRAM) according to a preferred embodiment of the present invention. The figure shows a memory unit cell (UC) of the STT-MRAM, which includes three transistors T1-T3, four magnetic tunnel junctions (MTJ1-MTJ4), a source line SL1, two bit lines BL1 and BL2, and three word lines WL1-WL3. The three transistors T1-T3 are a first transistor T1, a third transistor T3, and a second transistor T2 connected in series. The junction between the first transistor T1 and the second transistor is a first node N1, and the junction between the second transistor T2 and the third transistor T3 is a second node N2. The other ends of the first transistor T1 and the second transistor T2 are connected to a common source line SL1.

[0047] Re-reference Figure 1 The present invention adopts a dual architecture. As shown in the figure, the first magnetic tunnel junction MTJ1 and the second magnetic tunnel junction MTJ2 are connected in series to form the first magnetic tunnel junction group S1, and the third magnetic tunnel junction MTJ3 and the fourth magnetic tunnel junction MTJ4 are connected in series to form the second magnetic tunnel junction group S2. The first magnetic tunnel junction MTJ1 and the third magnetic tunnel junction MTJ3 are smaller and have higher resistance, while the second magnetic tunnel junction MTJ2 and the fourth magnetic tunnel junction MTJ4 are larger and have lower resistance. The size difference of the magnetic tunnel junctions in a magnetic tunnel junction group makes it possible to read and write them individually. One end of the first magnetic tunnel junction group S1 is connected to the first node N1 (i.e., between the first transistor T1 and the third transistor T3), and the other end is connected to the first bit line BL1. The second magnetic tunnel junction group S2 has one end connected to the second node N2 (i.e., between the second transistor T2 and the third transistor T3), and the other end is connected to the second bit line BL2.

[0048] Re-reference Figure 1As shown in the figure, in a preferred embodiment of the present invention, three word lines WL1 to WL3 extend in a first direction D1 through the memory cell UC, wherein the first word line WL1 is connected to the gate of the first transistor T1, the second word line WL2 is connected to the gate of the third transistor T3, and the third word line WL3 is connected to the gate of the second transistor T2 to control the switching of these transistors. The source line SL1 and the two bit lines BL1 and BL2 extend in a second direction D2 orthogonal to the first direction D1 through the memory cell UC. In this embodiment of the present invention, the first transistor T1 and the first magnetic tunnel junction group S1 can basically be regarded as the first part, and the second transistor T2 and the second magnetic tunnel junction group S2 can be regarded as the second part. The two ends of these two parts are connected to the bit line and the source line respectively, and the conduction of these parts is controlled by the word line. The third transistor T3 is connected between the two parts as an additional selectable current channel.

[0049] Please also refer to Figure 2 and Figure 3 , which are respectively the layout diagram and the stereogram of the STT-MRAM of the 3T4M architecture according to the preferred embodiment of the present invention. Figure 2 A plurality of memory cells UC are shown in FIG, and the hierarchical structure of the fourth metal layer M4 is independently separated in Figure 2 The right half of the figure is used to represent the present invention so that readers can clearly understand the layout of each layer of the present invention. Figure 3 It roughly shows the vertical structure of each layer of components in a storage unit UC.

[0050] As shown in the figure, the STT-MRAM structure of the present invention is constructed on a substrate. The substrate can be a silicon substrate, and a well region (well) such as a p-type well region can be formed in advance using a doping process. A plurality of conductive active areas AA are defined on the substrate, such as Figure 2 Multiple active regions AA extending in the second direction D2 can be electrically isolated from each other by forming a shallow trench isolation structure STI made of silicon oxide. Multiple word lines, such as WL1 to WL6 shown in the figure, extend in the first direction D1 across multiple active regions AA, which serve as the gate of the transistor to control the switching of the transistor. The active regions AA on both sides of the word lines WL1 to WL6 can be formed into the source and drain of the transistor using a doping process. Figure 3 As can be seen, the word line WL4 and the source / drain on both sides correspond to Figure 1 The first transistor T1, the word line WL5 and the source / drain on both sides thereof correspond to Figure 1 The third transistor T3 in the word line WL6 and the source / drain on both sides thereof correspond to Figure 1The source / drain electrodes on both sides of word lines WL4 and WL6 can be connected upward to the first metal layer M1 and a common source line SL through contacts CT, respectively. The source line SL can be located at the M1 level. The source / drain electrodes on both sides of word line WL5 can be connected upward to the first metal layer M1 through contacts CT, and then connected to a larger magnetic tunnel junction above, such as magnetic tunnel junction MTJ2, through vias V1.

[0051] Re-reference Figure 2 and Figure 3 The source line SL and a plurality of bit lines BL extend in the second direction D2 above the active area AA, wherein each memory cell UC corresponds to one source line SL and two bit lines BL. The source line SL may be located at the first metal layer M1 level, and the bit line BL may be located at the second metal layer M2 level and may partially overlap or completely overlap with the source line SL. In a preferred embodiment of the present invention, the magnetic tunneling junction is located at the third metal layer M3 level. Figure 3 As shown, the source / drain on both sides of the word line WL5 (corresponding to Figure 1 The third transistor T3 in the circuit is connected to a larger magnetic tunnel junction above, such as the magnetic tunnel junction MTJ2, through interconnect structures such as the contact CT, the via V1, and the via V2. The magnetic tunnel junction MTJ2 is further connected to the fourth metal layer M4 above via the via V3. Figure 2 As shown in the right half, each magnetic tunnel junction corresponds to a rectangular block of the fourth metal layer M4 with equal area. For the magnetic tunnel junctions in the same double bit group, the fourth metal layer M4 blocks above them are connected to form a magnetic tunnel junction group, as shown in the figure below. Figure 3 As shown, the larger magnetic tunnel junction MTJ2 is connected to the smaller magnetic tunnel junction MTJ1 via the fourth metal layer M4 to form a first magnetic tunnel junction group S1. The first magnetic tunnel junction group S1 is further connected to the bit line BL via the via V3 below the magnetic tunnel junction MTJ1.

[0052] Please also refer to Figure 4 , which is a schematic diagram of the layout of the memory cell of the STT-MRAM of the 3T4M architecture according to the preferred embodiment of the present invention. In the embodiment of the present invention, each memory cell UC will include three word lines WL and four magnetic tunnel junctions, wherein each larger magnetic tunnel junction MTJ2 will be connected in series with a smaller magnetic tunnel junction MTJ1 to form a magnetic tunnel junction group. As shown in the figure, the length L of each memory cell UC is equal to three times the word line pitch P (i.e., the gate pitch). Therefore, each magnetic tunnel junction will require an average layout length of 0.75 word line pitches P (3 / 4 pitch P). Compared to the existing 1T2M architecture and 2T2M architecture of STT-MRAM, where each magnetic tunnel junction requires a layout length of 1 word line pitch P, the design of the present invention can significantly reduce the layout area required for the memory cell UC.

[0053] Please also refer to Figure 5 , which is a circuit diagram of the STT-MRAM with a 3T4M architecture during the read operation according to a preferred embodiment of the present invention, wherein the horizontal axis represents the resistance value and the vertical axis represents the distribution of the measured resistance value. In the read operation of the STT-MRAM, its state is determined by measuring the resistance value of the magnetic tunnel junction. For the STT-MRAM with a dual bits architecture, since each two magnetic tunnel junctions (such as magnetic tunnel junctions MTJ1 and MTJ2) are connected in series to form a magnetic tunnel junction group, it will have four state combinations: RL / RL, RH / RL, RL / RH and RH / RH. Therefore, in actual measurement, the measured resistance can be divided into four distribution segments W1 to W4 as shown in the figure. Among them, W1 represents that the two magnetic tunnel junctions in series are both in the low state (RL / RL). W2 represents that the larger magnetic tunnel junction of the two magnetic tunnel junctions in series is in the high state and the smaller magnetic tunnel junction is in the low state (RH / RL). W3 represents that the larger of the two series-connected magnetic tunnel junctions is in a low state and the smaller one is in a high state (RL / RH). W4 represents that both of the two series-connected magnetic tunnel junctions are in a high state (RH / RH).

[0054] In an embodiment of the present invention, each read operation requires two read steps to determine the state of the four magnetic tunnel junctions in each memory cell UC. The first read step, as shown in the left half of the figure, will first use the middle value R1 of the distribution segment W1 to W4 as the standard to determine the state of a magnetic tunnel junction group. For example, when the measured R value is greater than R1, it means that the magnetic tunnel junction group is in a high state. When the measured R value is less than R1, it means that the magnetic tunnel junction group is in a low state. However, executing the above steps alone can only determine the common state of the magnetic tunnel junction group, and cannot determine the individual states of the two magnetic tunnel junctions contained therein. A second read step is required to determine the states of the individual magnetic tunnel junctions. Taking the first read step as an example, where the magnetic tunnel junction group is in a low state, in the second read step, as shown in the right half of the figure, the middle value R2 between distribution segments W1 and W2 can be used as the level for determination. For example, when the measured R value is greater than R2, it means that the magnetic tunnel junction group is in distribution segment W2 (i.e., RH / RL). When the measured R value is less than R2, it means that the magnetic tunnel junction group is in distribution segment W1 (i.e., RL / RL). Therefore, through the above two read steps, the individual states of the four magnetic tunnel junctions in each memory cell UC can be determined.

[0055] Re-reference Figure 5During each read step, the three transistors T1-T3 in each memory cell are turned on via their respective word lines WL (1V), and a voltage (0.15V) is applied to the bit lines BL1 and BL2, causing current to flow from the bit lines BL1 and BL2 through the first magnetic tunneling junction group MTJ1 / MTJ2 and the second magnetic tunneling junction group MTJ3 / MTJ4, respectively, to the common source line SL (0V). The difference between the two read steps lies only in the determination levels R1 and R2 used. The advantage of the above-described read operation of the present invention is that, because two bit lines are simultaneously applied with voltage measurement, the two read steps can read the individual states of the four magnetic tunneling junction groups. Compared to existing 1T2M or 2T2M STT-MRAM architectures, which can only read the individual states of one or two magnetic tunneling junction groups in two read steps, the present design doubles the read speed. Furthermore, because the magnetoresistive random access memory of the present invention utilizes a three-transistor series architecture, the read current is larger, further improving the read speed. In addition, the current passes through three transistors during the reading process, which can prevent the resistance value of individual transistors from varying too much and affecting the measurement results.

[0056] Please refer to the following Figure 6 , which is a circuit diagram of the 3T4M architecture STT-MRAM in high-performance read mode and low-power read mode according to a preferred embodiment of the present invention. Another advantage of the design of the present invention is that it can adopt two operating modes: high-performance read mode and low-power read mode. When the battery capacity is sufficient, the system can set the memory to operate in high-performance read mode, such as Figure 6 As shown on the left, in this mode of operation, the three bit lines in the memory cell are connected to a common bit line WL and a voltage (1V) is applied to turn on the three transistors T1-T3. With all three transistors T1-T3 turned on, a voltage (0.15V) can be applied to both bit lines BL1 and BL2, allowing current to flow through the two magnetic tunnel junctions MTJ1 / MTJ2 and MTJ3 / MTJ4, respectively, and their respective resistances can be measured. Because this mode requires driving three word lines and two bit lines simultaneously, it is recommended to operate with sufficient battery capacity.

[0057] On the other hand, the re-reference Figure 6 In low power mode, such as Figure 6As shown in the right half, only one of the three word lines in the memory cell is powered (1V) to turn on the corresponding first transistor T1 or second transistor T2. Since only one transistor (e.g., transistor T1) is turned on, a voltage (0.15V) is applied to one bit line BL1, allowing current to flow through its corresponding magnetic tunneling junction (MTJ1 / MTJ2) and measuring their respective resistances. The other bit line BL2 is left floating (0V). Because this mode only requires driving one word line and one bit line, it requires much lower power consumption, making it suitable for use in low-battery situations.

[0058] Please refer to the following Figure 7 , which is a circuit diagram of the symmetrical write operation of the 3T4M structure STT-MRAM according to the preferred embodiment of the present invention. For the dual bits structure STT-MRAM, since every two magnetic tunnel junctions (such as magnetic tunnel junctions MTJ1 / MTJ2) are connected in series to form a magnetic tunnel junction group, its write operation also requires two write steps, one of which is to write to both magnetic tunnel junctions in the magnetic tunnel junction group, and the other is to flip one of the magnetic tunnel junctions in the magnetic tunnel junction group, so that the two magnetic tunnel junctions in series can have separate states. Figure 7 As shown in the left half, in the first write step, a voltage (1V) is applied to the common bit line WL to fully turn on the three transistors T1 to T3. Current will flow from the bit lines BL1 and BL2, which are pressed (1V), through the first magnetic tunnel junction group MTJ1 / MTJ2 and the second magnetic tunnel junction group MTJ3 / MTJ4 to the common source line SL (0V). The current value will be greater than the individual current of each magnetic tunnel junction, thus completing the write step for the four magnetic tunnel junctions. After completing the first write step, as shown in the figure, Figure 7 As shown in the right half, during the second write step, a voltage of only 0.5V is applied to the common bit line WL. This small voltage only causes the three transistors T1-T3 to be half-on, which means that the current flowing through the magnetic tunnel junction group will become smaller, and this small current will be set to a value greater than the current value of the smaller magnetic tunnel junction (such as MTJ1) but less than the current value of the larger magnetic tunnel junction (such as MTJ2). In this way, only the magnetic tunnel junction MTJ2 in the magnetic tunnel junction group will be flipped back to its pre-write state in this step, while the magnetic tunnel junction MTJ1 will maintain its pre-write state. Therefore, through the above two write steps, the four magnetic tunnel junctions in each memory cell UC can be written to a specific individual state.

[0059] Please refer to the following Figure 8, which is a circuit diagram of the STT-MRAM of the 3T4M architecture in the complementary write operation according to the preferred embodiment of the present invention. In some cases, we would like the write current to flow from the common source line end to the bit line end to achieve a better current configuration. For such a demand, the supply voltages of the two bit lines in each memory cell UC can be set to 1V and -1V respectively, and the supply voltage of the source line can be set to 0V (the middle value between the voltage range of 1V and -1V). With such a setting, it can be seen from the figure that on the one hand, the current will flow from the bit line BL1 with an applied voltage (1V) through the first magnetic tunnel junction group MTJ1 / MTJ2 to the common source line (0V), and on the other hand, the current will also flow from the common source line with an applied voltage (0V) through the second magnetic tunnel junction group MTJ3 / MTJ4 to the bit line BL2 (-1V), thereby achieving a complementary write mechanism. The write action of this embodiment is the same as Figure 7 The embodiment is the same as that of FIG. 2 , in which different voltages (1V and 0.5V) are applied to the common bit line WL in the two writing steps to achieve the effect of writing the individual magnetic tunneling junctions into specific bit states.

[0060] Finally, please refer to Figure 9 , which is a circuit diagram of a 24-bit memory array consisting of six memory cells according to a preferred embodiment of the present invention. This memory array has a 2×3 memory cell arrangement, where the top three memory cells share word lines WL1–WL3, and the bottom three memory cells share word lines WL4–WL6. Furthermore, two bit lines (e.g., BL1 and BL2) can be shared by the memory cells on the left and right sides, significantly reducing the number of required bit lines.

[0061] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A magnetoresistive random access memory circuit structure having a plurality of memory cells, wherein each memory cell comprises: three transistors, namely a first transistor, a third transistor, and a second transistor connected in series in sequence, wherein a connection point between the first transistor and the third transistor is a first node, a connection point between the second transistor and the third transistor is a second node, and the other ends of the first transistor and the second transistor are connected to a common source line; and Four magnetic tunnel junctions, namely a first magnetic tunnel junction, a second magnetic tunnel junction, a third magnetic tunnel junction and a fourth magnetic tunnel junction, wherein the first magnetic tunnel junction and the second magnetic tunnel junction are connected in series to form a first magnetic tunnel junction group, one end of the first magnetic tunnel junction group is connected to the first node, the third magnetic tunnel junction and the fourth magnetic tunnel junction are connected in series to form a second magnetic tunnel junction group, one end of the second magnetic tunnel junction group is connected to the second node, The first magnetic tunnel junction and the second magnetic tunnel junction in the first magnetic tunnel junction group are respectively a smaller magnetic tunnel junction and a larger magnetic tunnel junction, and the third magnetic tunnel junction and the fourth magnetic tunnel junction in the second magnetic tunnel junction group are respectively a smaller magnetic tunnel junction and a larger magnetic tunnel junction. 2 . The magnetoresistive random access memory circuit structure as claimed in claim 1 , wherein the other end of the first magnetic tunnel junction group is connected to a first bit line, and the other end of the second magnetic tunnel junction group is connected to a second bit line. 3 . The magnetoresistive random access memory circuit structure as claimed in claim 2 , wherein the first bit line and the second bit line are shared by the memory cells on both sides of the first bit line and the second bit line. 4 . The magnetoresistive random access memory circuit structure as claimed in claim 2 , wherein in a symmetric write mode, voltages of the first bit line and the second bit line are greater than a voltage of the source line. 5 . The magnetoresistive random access memory circuit structure as claimed in claim 2 , wherein in a complementary write mode, a voltage of the source line is between a voltage of the first bit line and a voltage of the second bit line. 6 . The magnetoresistive random access memory circuit structure as claimed in claim 1 , wherein gates of the first transistor, the second transistor and the third transistor are connected to a first word line, a second word line and a third word line, respectively. 7 . The magnetoresistive random access memory circuit structure as claimed in claim 6 , wherein the first word line, the second word line and the third word line are further connected to a common word line.

8. The magnetoresistive random access memory circuit structure of claim 1, wherein in a high-performance mode, the first transistor, the second transistor, and the third transistor are all turned on, so that the first magnetic tunneling junction group and the second magnetic tunneling junction group are both subjected to a read or write operation.

9. The magnetoresistive random access memory circuit structure as claimed in claim 1, wherein in a power-saving mode, only one of the first transistor and the third transistor is turned on, so that only one of the first magnetic tunnel junction group and the second magnetic tunnel junction group is subjected to a read or write operation.

10. A magnetoresistive random access memory layout structure having the magnetoresistive random access memory circuit structure according to claim 1, wherein the magnetoresistive random access memory layout structure has a plurality of memory cells, wherein each memory cell comprises: a substrate having a plurality of active regions formed thereon; A first word line, a second word line, and a third word line extend across the active regions, respectively, wherein the active region outside the first word line is a first active region, the doped region between the first word line and the second word line is a second active region, the active region between the second word line and the third word line is a third active region, and the active region outside the third word line is a fourth active region; four magnetic tunnel junctions, namely a first magnetic tunnel junction, a second magnetic tunnel junction, a third magnetic tunnel junction, and a fourth magnetic tunnel junction, wherein two ends of the first magnetic tunnel junction are respectively connected to the second active region and one end of the second magnetic tunnel junction, and two ends of the third magnetic tunnel junction are respectively connected to the third active region and one end of the fourth magnetic tunnel junction; and The first bit line and the second bit line are connected to the other end of the second magnetic tunnel junction and the other end of the fourth magnetic tunnel junction respectively. 11 . The magnetoresistive random access memory layout structure as claimed in claim 10 , wherein the first active region and the fourth active region are connected to a common source line.

12. The magnetoresistive random access memory layout structure as claimed in claim 11, wherein the source line is located at a first metal layer (M1) level. 13 . The magnetoresistive random access memory layout structure as claimed in claim 10 , wherein the first bit line and the second bit line are located at a second metal layer ( M2 ) level.

14. The magnetoresistive random access memory layout structure as claimed in claim 10, wherein the four magnetic tunneling junctions are located at a third metal layer (M3) level.

15. The magnetoresistive random access memory layout structure as claimed in claim 14, wherein the first magnetic tunnel junction is connected to one end of the second magnetic tunnel junction via a fourth metal layer (M4), and the third magnetic tunnel junction is connected to one end of the fourth magnetic tunnel junction via the fourth metal layer.

16. The magnetoresistive random access memory layout structure as claimed in claim 10, wherein the first magnetic tunnel junction and the second magnetic tunnel junction are respectively a smaller magnetic tunnel junction and a larger magnetic tunnel junction, and the third magnetic tunnel junction and the fourth magnetic tunnel junction are respectively a smaller magnetic tunnel junction and a larger magnetic tunnel junction. 17 . The magnetoresistive random access memory layout structure as claimed in claim 10 , wherein the active regions and the word lines extend in a first direction, and the first bit line and the second bit line extend in a second direction orthogonal to the first direction.

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