Multilayer ceramic electronic components

Abstract

The present invention provides a highly reliable laminated ceramic electronic component. The laminated ceramic electronic component comprises: a laminate having a plurality of laminated ceramic layers and a plurality of internal conductor layers laminated on the ceramic layers, and including a first main surface and a second main surface opposite to each other in the height direction, a first side surface and a second side surface opposite to each other in the width direction orthogonal to the height direction, and a first end surface and a second end surface opposite to each other in the length direction orthogonal to the height direction and the width direction; and an external electrode connected to the internal conductor layer, wherein a plurality of holes having different area equivalent diameters exist in the internal conductor layer, and when the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the plurality of holes existing in the internal conductor layer becomes 99% is set as the area equivalent diameter D99, the area equivalent diameter D99 is 8.0 μm or less.

Description

Technical Field

[0001] The present invention relates to a laminated ceramic electronic component. Background Art

[0002] In the past, there are known laminated ceramic capacitors. Generally, a laminated ceramic capacitor includes a laminated body in which a plurality of dielectric layers and internal electrode layers are alternately laminated. For example, Patent Document 1 discloses a laminated ceramic capacitor including: a laminated body in which a plurality of dielectric layers and internal electrode layers are alternately laminated; and a plurality of auxiliary electrodes.

[0003] Prior Art Literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2018-46086

[0006] In the multilayer ceramic capacitor of Patent Document 1, a plurality of auxiliary electrodes are provided to suppress electric field concentration and improve product reliability. However, Patent Document 1 does not consider the influence of holes in the internal electrode layer on the reliability of the multilayer ceramic capacitor. Summary of the invention

[0007] Problem that the invention aims to solve

[0008] An object of the present invention is to provide a highly reliable multilayer ceramic electronic component that suppresses electric field concentration.

[0009] Technical solutions to solve problems

[0010] The stacked ceramic electronic component involved in the present invention comprises: a stacked body having a plurality of stacked ceramic layers and a plurality of internal conductor layers stacked on the ceramic layers, and including a first main surface and a second main surface opposite to each other in a height direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction and the width direction; and an external electrode connected to the internal conductor layer, wherein a plurality of holes having different area equivalent diameters are present in the internal conductor layer, and when the area equivalent diameter at which the cumulative value in the cumulative distribution of the area equivalent diameters of the plurality of holes present in the internal conductor layer becomes 99% is set as the area equivalent diameter D99, the area equivalent diameter D99 is less than 8.0 μm.

[0011] Effects of the Invention

[0012] According to the present invention, it is possible to provide a highly reliable multilayer ceramic electronic component that suppresses electric field concentration. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a perspective view of the appearance of a multilayer ceramic capacitor according to an embodiment.

[0014] Figure 2 yes Figure 1 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor taken along line II-II.

[0015] Figure 3 yes Figure 2 FIG. 1 is a cross-sectional view of a multilayer ceramic capacitor taken along line III-III.

[0016] Figure 4A yes Figure 2 A cross-sectional view of the multilayer ceramic capacitor taken along line IVA-IVA is shown.

[0017] Figure 4B yes Figure 2 A cross-sectional view of the multilayer ceramic capacitor taken along line IVB-IVB is shown.

[0018] Figure 5 yes Figure 4A An enlarged view of the V portion of the multilayer ceramic capacitor 1 is shown.

[0019] Figure 6 This is a diagram showing area-equivalent diameter distribution data of a plurality of pores existing in the internal electrode layer.

[0020] Fig. 7A : is a figure which shows the model of the internal electrode layer used in the first simulation.

[0021] Figure 7B 1 is a diagram showing the electric field intensity distribution near the hole of the internal electrode layer.

[0022] Figure 8 This is a graph in which the maximum electric field intensity in the model calculated in each simulation model with the value of the area equivalent diameter D99 changed is plotted.

[0023] Fig. 9 This is a graph in which the maximum electric field intensity in the model calculated in each simulation model with the coverage of the internal electrode layer changed is plotted.

[0024] Fig.10 This is a graph in which the maximum electric field intensity in the model calculated in each simulation model with the thickness of the internal electrode layer changed is plotted.

[0025] Fig.11A : is a diagram showing a model of holes in the internal electrode layer used in the fourth simulation.

[0026] Fig. 11B 1 is a diagram showing the electric field intensity distribution near the hole of the internal electrode layer.

[0027] Fig.12 This is a graph in which the values ​​of the maximum electric field intensity generated near holes having different roundnesses are standardized and plotted.

[0028] Fig.13 : is a graph showing the values ​​of the standardized maximum electric field intensity of the first model and the second model.

[0029] Fig.14 is with Figure 3 The scanning electron microscope image corresponding to the enlarged view of the XIV portion of the multilayer ceramic capacitor shown is a diagram showing a burnout state of the multilayer body at the time of dielectric breakdown when an accelerated life test is performed.

[0030] Fig.15A FIG. 1 is a diagram showing a two-layer structured multilayer ceramic capacitor.

[0031] Fig. 15B FIG. 1 is a diagram showing a triple-structured multilayer ceramic capacitor.

[0032] Fig. 15C FIG. 1 is a diagram showing a quadruple-structured multilayer ceramic capacitor.

[0033] Description of Reference Numerals

[0034] 1: Multilayer ceramic capacitors (multilayer ceramic electronic components);

[0035] 10: laminate;

[0036] LS1: first end surface;

[0037] LS2: second end surface;

[0038] WS1: first side;

[0039] WS2: second side;

[0040] TS1: first main surface;

[0041] TS2: Second main surface;

[0042] 20: dielectric layer (ceramic layer);

[0043] 30: internal electrode layer (internal conductor layer);

[0044] 31: first internal electrode layer (first internal conductor layer);

[0045] 32: second internal electrode layer (second internal conductor layer);

[0046] H: hole;

[0047] WE1: first side;

[0048] WE2: Second side;

[0049] WE3: Third Side;

[0050] WE4: Fourth Side;

[0051] A1: first area;

[0052] A2: Second area;

[0053] A3: The third area;

[0054] A4: Area 4;

[0055] 40: external electrode;

[0056] 40A: first external electrode;

[0057] 40B: second external electrode;

[0058] L: length direction;

[0059] W: width direction;

[0060] T: height direction. DETAILED DESCRIPTION

[0061] Hereinafter, a multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to an embodiment of the present disclosure will be described. Figure 1 It is a perspective view of the appearance of the multilayer ceramic capacitor 1 according to the present embodiment. Figure 2 yes Figure 1 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line II-II. Figure 3 yes Figure 2 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III. Figure 4A yes Figure 2 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line IVA-IVA. Figure 4B yes Figure 2 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line IVB-IVB.

[0062] The multilayer ceramic capacitor 1 includes a multilayer body 10 and external electrodes 40 .

[0063] exist Figure 1 to Figure 4B The XYZ orthogonal coordinate system is shown. The length direction L of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the X direction. The width direction W of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the Y direction. The height direction T of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the Z direction. Here, Figure 2 The section shown is also referred to as the LT section. Figure 3The section shown is also referred to as the WT section. Figure 4A as well as Figure 4B The section shown is also referred to as the LW section.

[0064] like Figure 1 to Figure 4B As shown, the stack 10 includes a first main surface TS1 and a second main surface TS2 opposite to each other in the height direction T, a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction W perpendicular to the height direction T, and a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction L perpendicular to the height direction T and the width direction W.

[0065] like Figure 1 As shown, the stack 10 has a substantially rectangular parallelepiped shape. In addition, the dimension in the length direction L of the stack 10 is not necessarily longer than the dimension in the width direction W. It is preferred that the corners and ridges of the stack 10 are rounded. The corner is the portion where three faces of the stack intersect, and the ridge is the portion where two faces of the stack intersect. In addition, a part or all of the surface constituting the stack 10 may be formed with concave and convex portions.

[0066] The size of the laminate 10 is not particularly limited. If the size in the length direction L of the laminate 10 is set to L size, the L size is preferably 0.2 mm or more and 6 mm or less. In addition, if the size in the height direction T of the laminate 10 is set to T size, the T size is preferably 0.05 mm or more and 5 mm or less. In addition, if the size in the width direction W of the laminate 10 is set to W size, the W size is preferably 0.1 mm or more and 5 mm or less.

[0067] like Figure 2 as well as Figure 3 As shown, the laminate 10 includes an inner layer portion 11 , and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged in the height direction T so as to sandwich the inner layer portion 11 .

[0068] The inner layer portion 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers, and a plurality of internal electrode layers 30 as a plurality of internal conductor layers. The inner layer portion 11 includes the internal electrode layer 30 located closest to the first main surface TS1 side to the internal electrode layer 30 located closest to the second main surface TS2 side in the height direction T. In the inner layer portion 11, the plurality of internal electrode layers 30 are arranged opposite to each other with the dielectric layer 20 interposed therebetween. The inner layer portion 11 is a portion that generates electrostatic capacitance and substantially functions as a capacitor.

[0069] The plurality of dielectric layers 20 are composed of dielectric materials. The dielectric material may be, for example, a dielectric ceramic containing BaTiO3, CaTiO3, SrTiO3, or CaZrO3. In addition, the dielectric material may be a material containing Mn compounds, Fe compounds, Cr compounds, Co compounds, Ni compounds, and other secondary components added to these main components. The dielectric material is particularly preferably a material containing BaTiO3 as a main component.

[0070] The thickness of the dielectric layer 20 is preferably 0.2 μm or more and 10 μm or less. The number of laminated dielectric layers 20 is preferably 15 or more and 1200 or less. The number of dielectric layers 20 is the sum of the number of dielectric layers of the inner layer portion 11 and the number of dielectric layers of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0071] The plurality of internal electrode layers 30 (internal conductor layers 30) include a plurality of first internal electrode layers 31 (first internal conductor layers 31) and a plurality of second internal electrode layers 32 (second internal conductor layers 32). The plurality of first internal electrode layers 31 are arranged on the plurality of dielectric layers 20. The plurality of second internal electrode layers 32 are arranged on the plurality of dielectric layers 20. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are arranged alternately with the dielectric layers 20 interposed therebetween in the height direction T of the laminate 10. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the dielectric layer 20.

[0072] The first internal electrode layer 31 includes a first opposing portion 31A opposing the second internal electrode layer 32 and a first lead portion 31B led out from the first opposing portion 31A to the first end surface LS1. The first lead portion 31B is exposed at the first end surface LS1.

[0073] The second internal electrode layer 32 includes a second opposing portion 32A opposing the first internal electrode layer 31 and a second lead portion 32B led out from the second opposing portion 32A to the second end surface LS2. The second lead portion 32B is exposed at the second end surface LS2.

[0074] In the present embodiment, the first opposing portion 31A and the second opposing portion 32A are opposed to each other via the dielectric layer 20 , thereby forming capacitance and exhibiting capacitor characteristics.

[0075] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed obliquely. The shapes of the first lead-out portion 31B and the second lead-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed obliquely.

[0076] The size of the first opposing portion 31A in the width direction W and the size of the first lead portion 31B in the width direction W may be formed to be the same size, or one of the sizes may be formed to be smaller. The size of the second opposing portion 32A in the width direction W and the size of the second lead portion 32B in the width direction W may be formed to be the same size, or one of the sizes may be formed to be smaller.

[0077] like Figure 4A As shown, the first internal electrode layer 31 has a first side WE1 on the first side surface WS1 and a second side WE2 on the second side surface WS2. Figure 4B As shown, the second internal electrode layer 32 has a third side WE3 on the first side surface WS1 side and a fourth side WE4 on the second side surface WS2 side.

[0078] The first internal electrode layer 31 and the second internal electrode layer 32 include, for example, a metal such as Ni, Cu, Ag, Pd, Au, or an alloy containing at least one of these metals, or other appropriate conductive material. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may include, for example, an Ag-Pd alloy.

[0079] The thickness of each of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably about 0.2 μm or more and 2.0 μm or less, for example. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 15 or more and 1000 or less.

[0080] The first main surface side outer layer portion 12 is located on the first main surface TS1 side of the stacked body 10. The first main surface side outer layer portion 12 is an aggregate of a plurality of dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layer 20 used in the first main surface side outer layer portion 12 may be the same as the dielectric layer 20 used in the internal layer portion 11.

[0081] The second main surface side outer layer portion 13 is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer portion 13 is an aggregate of a plurality of dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layer 20 used in the second main surface side outer layer portion 13 may be the same as the dielectric layer 20 used in the inner layer portion 11.

[0082] As described above, the laminated body 10 includes a plurality of laminated dielectric layers 20 and a plurality of internal electrode layers 30 laminated on the dielectric layers 20. That is, the laminated ceramic capacitor 1 includes the laminated body 10 in which the dielectric layers 20 and the internal electrode layers 30 are alternately laminated.

[0083] The laminate 10 also includes an opposing electrode portion 11E. The opposing electrode portion 11E is a portion where the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 face each other. The opposing electrode portion 11E is configured as a part of the inner layer portion 11. Figure 4A as well as Figure 4B , the range of the opposing electrode portion 11E in the width direction W and the length direction L is shown. In addition, the opposing electrode portion 11E is also referred to as a capacitor effective portion.

[0084] In addition, the stacked body 10 has a side outer layer portion. The side outer layer portion has a first side outer layer portion WG1 and a second side outer layer portion WG2. The first side outer layer portion WG1 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the first side WS1. The second side outer layer portion WG2 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the second side WS2. Figure 3 , Figure 4A as well as Figure 4B In FIG. 1 , the range of the first side outer layer portion WG1 and the second side outer layer portion WG2 in the width direction W is shown. In addition, the side outer layer portion is also referred to as a W interval or a side interval.

[0085] In addition, the stacked body 10 has an end surface side outer layer portion. The end surface side outer layer portion has a first end surface side outer layer portion LG1 and a second end surface side outer layer portion LG2. The first end surface side outer layer portion LG1 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the first end surface LS1. The second end surface side outer layer portion LG2 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the second end surface LS2. Figure 2 , Figure 4A as well as Figure 4B , the ranges of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 in the length direction L are shown. In addition, the end surface side outer layer portion is also referred to as an L interval or an end interval.

[0086] The external electrode 40 includes a first external electrode 40A arranged on the first end surface LS1 side, and a second external electrode 40B arranged on the second end surface LS2 side.

[0087] The first external electrode 40A is arranged on the first end surface LS1. The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A may also be arranged on a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. In the present embodiment, the first external electrode 40A is formed to extend from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0088] The second external electrode 40B is arranged on the second end surface LS2. The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B may also be arranged on a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. In the present embodiment, the second external electrode 40B is formed to extend from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0089] As described above, in the laminate 10, the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 are opposed to each other via the dielectric layer 20, thereby forming a capacitor. Therefore, the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32 exhibit capacitor characteristics.

[0090] The first external electrode 40A includes a first foundation electrode layer 50A and a first plating layer 60A disposed on the first foundation electrode layer 50A.

[0091] The second external electrode 40B includes a second foundation electrode layer 50B and a second plating layer 60B disposed on the second foundation electrode layer 50B.

[0092] The first foundation electrode layer 50A is arranged on the first end surface LS1. The first foundation electrode layer 50A is connected to the first internal electrode layer 31. In the present embodiment, the first foundation electrode layer 50A is formed to extend from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0093] The second base electrode layer 50B is arranged on the second end surface LS2. The second base electrode layer 50B is connected to the second internal electrode layer 32. In the present embodiment, the second base electrode layer 50B is formed to extend from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0094] The first base electrode layer 50A and the second base electrode layer 50B of the present embodiment are sintered layers. The sintered layer preferably includes a metal component and either a glass component or a ceramic component, or includes both of them. The metal component, for example, includes at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The glass component, for example, includes at least one selected from B, Si, Ba, Mg, Al, Li, etc. The ceramic component can use the same type of ceramic material as the dielectric layer 20, or a ceramic material of a different type from the dielectric layer 20. The ceramic component, for example, includes at least one selected from BaTiO3, CaTiO3, (Ba, Ca)TiO3, SrTiO3, CaZrO3, etc.

[0095] The sintered layer is, for example, a sintered layer in which a conductive paste containing glass and metal is applied to the laminate and sintered. The sintered layer can be a sintered layer in which a stacked chip (chip) having an internal electrode and a dielectric layer and a conductive paste applied to the stacked chip are simultaneously sintered, or it can be a sintered layer in which a conductive paste is applied to the laminate and sintered after the stacked chip having the internal electrode and the dielectric layer is sintered to obtain the laminate. In addition, in the case where the stacked chip having the internal electrode and the dielectric layer and the conductive paste applied to the stacked chip are simultaneously sintered, the sintered layer is preferably formed by sintering a paste to which a ceramic material is added instead of a glass component. In this case, as the added ceramic material, it is particularly preferred to use a ceramic material of the same type as the dielectric layer 20. The sintered layer can also be a plurality of layers.

[0096] The thickness of the first foundation electrode layer 50A in the longitudinal direction located at the first end surface LS1 is preferably about 3 μm or more and 200 μm or less in the central portion in the height direction T and the width direction W of the first foundation electrode layer 50A, for example.

[0097] The thickness of the second foundation electrode layer 50B in the longitudinal direction located at the second end surface LS2 is preferably about 3 μm or more and 200 μm or less in the center portion in the height direction T and the width direction W of the second foundation electrode layer 50B, for example.

[0098] When the first base electrode layer 50A is also provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness in the height direction of the first base electrode layer 50A provided on the portion is preferably greater than 3 μm and less than 25 μm in the central portion in the length direction L and the width direction W of the first base electrode layer 50A provided on the portion.

[0099] When the first base electrode layer 50A is also provided in a portion of at least one surface of the first side surface WS1 or the second side surface WS2, the thickness in the width direction of the first base electrode layer 50A provided in the portion is preferably, for example, greater than 3 μm and less than 25 μm in the central portion in the length direction L and the height direction T of the first base electrode layer 50A provided in the portion.

[0100] When a second base electrode layer 50B is also provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness in the height direction of the second base electrode layer 50B provided on the portion is preferably, for example, greater than 3 μm and less than 25 μm in the central portion in the length direction L and the width direction W of the second base electrode layer 50B provided on the portion.

[0101] When a second base electrode layer 50B is also provided in a portion of at least one surface of the first side surface WS1 or the second side surface WS2, the thickness in the width direction of the second base electrode layer 50B provided in the portion is preferably, for example, greater than 3 μm and less than 25 μm in the central portion in the length direction L and the height direction T of the second base electrode layer 50B provided in the portion.

[0102] In addition, the first base electrode layer 50A and the second base electrode layer 50B are not limited to the sintered layer. The first base electrode layer 50A and the second base electrode layer 50B include at least one selected from a sintered layer, a conductive resin layer, a thin film layer, etc. For example, the first base electrode layer 50A and the second base electrode layer 50B may also be a thin film layer. The thin film layer is formed by a thin film forming method such as a sputtering method or a vapor deposition method. The thin film layer is a layer of less than 10 μm on which metal particles are deposited.

[0103] The first plating layer 60A is arranged to cover the first base electrode layer 50A.

[0104] The second plating layer 60B is arranged to cover the second base electrode layer 50B.

[0105] The first plating layer 60A and the second plating layer 60B may include, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may also be formed of a plurality of layers. The first plating layer 60A and the second plating layer 60B are preferably a two-layer structure in which a Sn plating layer is formed on a Ni plating layer.

[0106] The first plating layer 60A is arranged to cover the first base electrode layer 50A. In the present embodiment, the first plating layer 60A includes a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0107] The second plating layer 60B is arranged to cover the second base electrode layer 50B. In the present embodiment, the second plating layer 60B includes a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0108] The Ni plating layer prevents the first base electrode layer 50A and the second base electrode layer 50B from being corroded by the solder when mounting the multilayer ceramic capacitor 1. In addition, the Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. Thus, the mounting of the multilayer ceramic capacitor 1 becomes easy. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B, and the second Sn plating layer 62B is preferably 2 μm or more and 10 μm or less.

[0109] In addition, the first external electrode 40A and the second external electrode 40B of the present embodiment may also have a conductive resin layer containing conductive particles and a thermosetting resin, for example. When a conductive resin layer is provided as a base electrode layer (the first base electrode layer 50A, the second base electrode layer 50B), the conductive resin layer may be configured to cover the sintered layer, or may be directly provided on the stack 10 without providing the sintered layer. When the conductive resin layer is configured to cover the sintered layer, the conductive resin layer is provided between the sintered layer and the plating layer (the first plating layer 60A, the second plating layer 60B). The conductive resin layer may completely cover the sintered layer, or may cover a portion of the sintered layer.

[0110] The conductive resin layer containing a thermosetting resin is more flexible than a conductive layer composed of, for example, a plated film or a fired product of a conductive paste. Therefore, even when a physical impact or an impact caused by a thermal cycle is applied to the multilayer ceramic capacitor 1, the conductive resin layer functions as a buffer layer. Therefore, the conductive resin layer suppresses the generation of cracks in the multilayer ceramic capacitor 1.

[0111] The metal constituting the conductive particles may also be Ag, Cu, Ni, Sn, Bi or an alloy containing them. The conductive particles preferably contain Ag. The conductive particles are, for example, Ag metal powder. Ag has the lowest resistivity among metals and is therefore suitable for electrode materials. In addition, Ag is a noble metal and is therefore not easily oxidized and has high weather resistance. Therefore, Ag metal powder is suitable as the conductive particles.

[0112] In addition, the conductive particles may be metal powders coated with Ag on the surface of the metal powders. When using metal powders coated with Ag on the surface of the metal powders, the metal powders are preferably Cu, Ni, Sn, Bi or alloy powders thereof. In order to make the metal of the base material a cheap metal while maintaining the characteristics of Ag, it is preferred to use metal powders coated with Ag.

[0113] Furthermore, the conductive particles may be conductive particles in which Cu and Ni have been subjected to an oxidation prevention treatment. In addition, the conductive particles may be metal powders in which Sn, Ni, and Cu are coated on the surface of the metal powder. When a metal powder in which Sn, Ni, and Cu are coated on the surface of the metal powder is used, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof.

[0114] The shape of the conductive particles is not particularly limited. The conductive particles may be spherical or flat, but preferably, a mixture of spherical metal powder and flat metal powder is used.

[0115] The conductive particles contained in the conductive resin layer mainly play a role in ensuring the conductivity of the conductive resin layer. Specifically, a plurality of conductive particles are in contact with each other, thereby forming a conductive path inside the conductive resin layer.

[0116] The resin constituting the conductive resin layer may also include at least one selected from various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, polyimide resin, etc. Among them, epoxy resin, which is particularly excellent in heat resistance, moisture resistance, adhesion, etc., is one of the most suitable resins. In addition, the resin of the conductive resin layer preferably includes a curing agent together with the thermosetting resin. When epoxy resin is used as the base resin, the curing agent of the epoxy resin may also be various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide.

[0117] In addition, the conductive resin layer may be formed of a plurality of layers. The thickness of the thickest portion of the conductive resin layer is preferably 10 μm or more and 150 μm or less.

[0118] Alternatively, the following structure may be adopted, that is, instead of providing the first base electrode layer 50A and the second base electrode layer 50B, the first plating layer 60A and the second plating layer 60B described later may be directly disposed on the laminate 10. That is, the laminated ceramic capacitor 1 may also have a structure including a plating layer that is directly electrically connected to the first internal electrode layer 31 and the second internal electrode layer 32. In such a case, the plating layer may be formed after a catalyst is disposed on the surface of the laminate 10 as a pretreatment.

[0119] In this case, the plating layer is also preferably a plurality of layers. The lower plating layer and the upper plating layer are preferably respectively, for example, at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi or Zn, or an alloy containing these metals. The lower plating layer is more preferably formed using Ni having solder resistance. The upper plating layer is more preferably formed using Sn or Au having good solder wettability. In addition, for example, when Ni is used to form the first internal electrode layer 31 and the second internal electrode layer 32, the lower plating layer is preferably formed using Cu having good bonding properties with Ni. In addition, the upper plating layer can be formed as needed, and the external electrode 40 can also only include the lower plating layer. In addition, the plating layer can use the upper plating layer as the outermost layer, or other plating layers can be further formed on the surface of the upper plating layer.

[0120] The thickness of each plating layer disposed without providing a base electrode layer is preferably 2 μm or more and 10 μm or less. In addition, the plating layer preferably does not contain glass. The metal ratio per unit volume of the plating layer is preferably 99 volume % or more.

[0121] In addition, when the plating layer is directly formed on the laminated body 10, the thickness of the base electrode layer can be reduced. Therefore, the dimension of the laminated ceramic capacitor 1 in the height direction T can be reduced according to the reduction in the thickness of the base electrode layer, and the height of the laminated ceramic capacitor 1 can be reduced. Alternatively, the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 can be increased according to the reduction in the thickness of the base electrode layer, and the thickness of the green body can be increased. In this way, by directly forming the plating layer on the laminated body 10, the degree of freedom in design of the laminated ceramic capacitor can be improved.

[0122] In addition, if the dimension in the length direction of the multilayer ceramic capacitor 1 including the stacked body 10 and the external electrode 40 is set to L dimension, the L dimension is preferably 0.2 mm or more and 6 mm or less. In addition, if the dimension in the height direction of the multilayer ceramic capacitor 1 is set to T dimension, the T dimension is preferably 0.05 mm or more and 5 mm or less. In addition, if the dimension in the width direction of the multilayer ceramic capacitor 1 is set to W dimension, the W dimension is preferably 0.1 mm or more and 5 mm or less.

[0123] The inventors of the present application have accumulated research, experiments, and simulations and have come to the conclusion that, in order to improve the reliability of a multilayer ceramic capacitor, it is preferable to set the holes in the internal electrode layer to an appropriate state. This will be described below.

[0124] In the past, various methods have been adopted to improve the reliability of multilayer ceramic capacitors. For example, Patent Document 1 discloses a multilayer ceramic capacitor comprising: a multilayer body in which a plurality of dielectric layers and internal electrode layers are alternately stacked; and a plurality of auxiliary electrodes. In the multilayer ceramic capacitor of Patent Document 1, by providing a plurality of auxiliary electrodes, electric field concentration is suppressed, thereby improving the reliability of the product. However, the multilayer ceramic capacitor of Patent Document 1 has a plurality of auxiliary electrodes, so it is difficult to ensure the area of ​​the effective part of the capacitor that generates electrostatic capacitance. Therefore, it is difficult to improve reliability while suppressing the decrease in electrostatic capacitance.

[0125] The inventors of the present application have considered the above contents and have conducted intensive research on the structure of the internal electrode layer that can improve reliability. As a result, the inventors of the present application have obtained the following insights, that is, according to the structure of the present embodiment, it is possible to suppress the decrease in electrostatic capacitance while suppressing the concentration of the electric field, thereby improving the reliability of the product. Specifically, the inventors of the present application have found that when insulation breakdown occurs in a stacked ceramic capacitor, burning starts from the location where there are holes in the internal electrode layer. Moreover, the inventors of the present application have found that by adjusting the size of the area equivalent diameter D99 described later of the multiple holes in the internal electrode layer, the reliability of the stacked ceramic capacitor can be improved. Below, the internal electrode layer 30 of the present embodiment is described in detail.

[0126] Figure 5 yes Figure 4A The enlarged view of the V portion of the multilayer ceramic capacitor 1 shown in FIG. 1 is a view exemplarily showing the state of the first internal electrode layer 31 as the internal electrode layer 30. In more detail, Figure 5 This is a diagram when the internal electrode layer 30 in the WT section of the multilayer ceramic capacitor 1 of the present embodiment is observed in the height direction T connecting the first main surface TS1 and the second main surface TS2, that is, it is a diagram when the internal electrode layer 30 in the WT section of the multilayer ceramic capacitor 1 of the present embodiment is viewed from above. In addition, the covering state of the first internal electrode layer 31 on the dielectric layer 20 and the covering state of the second internal electrode layer 32 on the dielectric layer 20 when observed in the height direction T connecting the first main surface TS1 and the second main surface TS2 become basically the same state. Therefore, in the following description, the first internal electrode layer 31 and the second internal electrode layer 32 are collectively described as the internal electrode layer 30 as needed.

[0127] Figure 5 1 is a diagram showing the internal electrode layer 30 in the vicinity of the first side WE1 which is a side of the internal electrode layer 30. Figure 5 As shown, a plurality of holes H having different area equivalent diameters exist in the internal electrode layer 30. Figure 5 The thickness of the internal electrode layer 30 shown is 0.6 μm, and the coverage of the internal electrode layer to the dielectric layer 20 is 82%. In addition, the inside of the hole H of the internal electrode layer 30 may be a void, or a glass component such as a dielectric or silicon dioxide may exist. When the inside of the hole H of the internal electrode layer 30 is a void, the dielectric layer 20 can be seen through the hole H.

[0128] Figure 6 : is a graph showing area-equivalent diameter distribution data of a plurality of holes H present in the internal electrode layer 30. Figure 6 In, the cumulative % of the area equivalent diameter is shown. Figure 6 The horizontal axis is the area equivalent diameter of hole H, Figure 6 The vertical axis is cumulative %, which represents the value obtained by dividing the number of holes H below the area equivalent diameter (the cumulative value of the number of holes) by the total number (the number of holes forming the parent set). That is, Figure 6 The area equivalent diameter distribution data shown are area equivalent diameter distribution data based on the number of pieces. Figure 6 The data is the area equivalent diameter distribution data in the measurement target area near the edge of the internal electrode layer 30, which is the area equivalent diameter distribution data in the measurement target area near the edge of the internal electrode layer 30. Figure 5 The data is when the holes in the larger area shown in the figure are used as the parent set.

[0129] In the multilayer ceramic capacitor 1 of the present embodiment, when the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the plurality of holes H existing in the internal electrode layer 30 becomes 99% is set as the area equivalent diameter D99, the area equivalent diameter D99 is 8.0 μm or less. Figure 6 In the example of the area equivalent diameter distribution data shown, the area equivalent diameter D99 is 4.4 μm.

[0130] In addition, when the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the plurality of holes H existing in the internal electrode layer 30 becomes 90% is defined as the area equivalent diameter D90, the area equivalent diameter D90 is preferably 4.0 μm or less, for example. Figure 6 In the area equivalent diameter distribution data of , the area equivalent diameter D90 is 2.8 μm. This can suppress electric field concentration and improve product reliability.

[0131] The area equivalent diameter is the value of the diameter of a perfect circle having an area equal to the area of ​​the hole defined by the hole contour. For example, when the area of ​​the hole defined by the hole contour is 50 μm 2 When , the area equivalent diameter becomes 8.0 μm.

[0132] In addition, as mentioned above, the area equivalent diameter D99 is the area equivalent diameter at which the cumulative value in the cumulative distribution of the area equivalent diameters of multiple holes becomes 99%. That is, the value at which the ratio of holes with area equivalent diameters below this area equivalent diameter becomes 99% is called the area equivalent diameter D99. In addition, the area equivalent diameter D90 is the area equivalent diameter at which the cumulative value in the cumulative distribution of the area equivalent diameters of multiple holes becomes 90%. That is, the value at which the ratio of holes with area equivalent diameters below this area equivalent diameter becomes 90% is called the area equivalent diameter D90. In addition, the area equivalent diameter D50 is also called the median diameter, which is the area equivalent diameter at which the cumulative value in the cumulative distribution of the area equivalent diameters of multiple holes becomes 50%. That is, the value at which the ratio of holes with area equivalent diameters below this area equivalent diameter becomes 50% is called the area equivalent diameter D50. In other words, when the plurality of holes H are divided into two parts based on a certain area equivalent diameter, the area equivalent diameter at which the number of holes larger than the reference and the number of holes smaller than the reference become the same is called the area equivalent diameter D50.

[0133] Next, a case where the above-mentioned effect can be obtained will be described using simulation.

[0134] <First Simulation>

[0135] Fig. 7A is a model of the internal electrode layer 30 used in the first simulation. In this model, the internal electrode layer 30 is provided on the dielectric layer 20. In addition, in this model, Fig. 7A As shown, a plurality of holes H are randomly arranged. In addition, the area equivalent diameters of the plurality of holes H have deviations. In addition, in this model, the plurality of holes H are formed by perfect circles. In addition, in this model, on the back side of the dielectric layer 20, as on the front side, an internal electrode layer 30 with a plurality of holes H randomly arranged is provided.

[0136] In the first simulation, a plurality of holes H are set in the internal electrode layer 30 so that the area equivalent diameter D99 described above becomes 8.0 μm. In addition, the thickness of the internal electrode layer 30 is set to 0.6 μm, the coverage of the internal electrode layer 30 to the dielectric layer 20 is set to 88%, the thickness of the dielectric layer 20 is set to 2.0 μm, and the applied voltage is set to 37.5 V. In the simulation, a voltage is applied between the internal electrode layer 30 on the surface side sandwiching the dielectric layer 20 and the internal electrode layer 30 on the back side.

[0137] As a result of performing a simulation under the present setting conditions, a tendency that the electric field is likely to be concentrated around the contour of the hole H was confirmed. Figure 7B is a diagram showing the electric field intensity distribution near the hole H. Figure 7B In the figure, the electric field strength is shown in grayscale, and the higher the electric field strength, the lighter the color. Figure 7B , it can be confirmed that the electric field is concentrated around the outline of the hole H. In addition, the following tendency can be confirmed, that is, Figure 7B Compared with the smaller hole outline shown on the right, the electric field is more likely to concentrate around Figure 7B The left side shows the contour of the larger hole.

[0138] Under this setting condition, the electric field strength generated in the model was calculated, and the result was that although the parts with high electric field strength were concentrated around the relatively large holes as mentioned above, the maximum electric field strength in the model was less than 72 MV / m. This maximum electric field strength value is a value that can be allowed while ensuring the reliability of the multilayer ceramic capacitor.

[0139] Next, the electric field intensity generated in each model was calculated using a model in which the value of the area equivalent diameter D99 was changed. In addition, the thickness of the internal electrode layer 30, the coverage of the internal electrode layer 30 to the dielectric layer 20, the thickness of the dielectric layer 20, and the applied voltage were set to fixed values ​​for simulation. Figure 8 The following is a graph showing the results. Figure 8 The horizontal axis is the area equivalent diameter D99 value in the model. Figure 8 The vertical axis is the maximum electric field strength in the model. Figure 8 In FIG. 1 , an approximate curve obtained by fitting the plotted points is shown.

[0140] First, in the case where there are relatively large holes like in the conventional internal electrode layer 30, specifically, when the area equivalent diameter D99 of the plurality of holes H existing in the internal electrode layer 30 exceeds 8.0 μm, it is confirmed that the value of the maximum electric field strength in the model becomes higher. For example, in the case where the area equivalent diameter D99 is 14.0 μm or more, the value of the maximum electric field strength in the model exceeds 80 MV / m. More specifically, the maximum electric field strength in the model when the area equivalent diameter D99 is 14.0 μm, 16.0 μm, 18.0 μm, and 20.0 μm is 80.7 MV / m, 86.9 MV / m, 87.5 MV / m, and 89.0 MV / m, respectively, all exceeding 80 MV / m.

[0141] On the other hand, if the area equivalent diameter D99 is 8.0 μm or less, the value of the maximum electric field strength generated in the model is less than 72 MV / m, confirming that the electric field concentration can be suppressed. For example, if the area equivalent diameter D99 is 4.0 μm or 2.0 μm, the value of the maximum electric field strength becomes about 60 MV / m or less, confirming that the electric field concentration can be further suppressed. More specifically, the maximum electric field strength when the area equivalent diameter D99 is 8.0 μm, 7.5 μm, 4.0 μm, and 2.0 μm is 70.7 MV / m, 71.3 MV / m, 56.0 MV / m, and 52.0 MV / m, respectively, all of which are less than 72 MV / m.

[0142] from Figure 8 From the trend of the data, it can be understood that, for example, even in the case where the area equivalent diameter D99 is 4.7μm, 3.2μm, or 2.2μm as also exists in the examples of this embodiment described later, the maximum electric field intensity can be suppressed to a low level and the electric field concentration can be suppressed.

[0143] In addition, according to Figure 8 From the data, it can be confirmed that if the area equivalent diameter D99 is 2.0 μm or more and 8.0 μm or less, the electric field concentration can be suppressed. In addition, it can be confirmed that when the area equivalent diameter D99 is 2.0 μm or more and 4.7 μm or less, 2.0 μm or more and 4.0 μm or less, or 2.0 μm or more and 3.2 μm or less, the electric field concentration can be further suppressed. In addition, if the area equivalent diameter D99 is 2.0 μm or more and 4.7 μm or less, the electric field concentration can be further suppressed. Figure 8 Considering the tendency of the data, it can be considered that the electric field concentration can be suppressed even when the area equivalent diameter D99 is 2.0μm or less. For example, it can be considered that the electric field concentration can be suppressed even if the area equivalent diameter D99 is 1.5μm. For example, it can be considered that the electric field concentration can be suppressed even if the area equivalent diameter D99 is 1.5μm or more and 8.0μm or less. In addition, it can be considered that the electric field concentration can be further suppressed when the area equivalent diameter D99 is 1.5μm or more and 4.7μm or less, 1.5μm or more and 4.0μm or less, or 1.5μm or more and 3.2μm or less.

[0144] In addition, the area equivalent diameter D90 of the model in which the area equivalent diameter D99 in this simulation becomes 8.0 μm is 4.0 μm, the area equivalent diameter D90 of the model in which the area equivalent diameter D99 becomes 7.5 μm is 3.8 μm, the area equivalent diameter D90 of the model in which the area equivalent diameter D99 becomes 4.0 μm is 2.6 μm, and the area equivalent diameter D90 of the model in which the area equivalent diameter D99 becomes 2.0 μm is 1.9 μm. The area equivalent diameter D90 is preferably 4.0 μm or less. The area equivalent diameter D90 is more preferably 2.6 μm or less. In addition, the area equivalent diameter D90 is preferably 1.9 μm or more and 4.0 μm or less. The area equivalent diameter D90 is more preferably 1.9 μm or more and 2.6 μm or less.

[0145] As described above, by setting the area equivalent diameter D99 to 8.0 μm or less as in the present embodiment, it is possible to suppress electric field concentration and improve product reliability.

[0146] Here, in order to confirm whether the maximum electric field strength is dependent on the average pore size, the area equivalent diameter D99 of the multiple holes H present in the internal electrode layer 30 is fixed, and a supplementary simulation using a model in which the average diameter is changed is performed. Specifically, a model in which the area equivalent diameter D99 of the hole H is 7.5μm and the average diameter of the hole H is 3.0μm, and a model in which the area equivalent diameter D99 of the hole H is 7.5μm and the average diameter of the hole H is 2.0μm are made. At this time, in any model, the coverage of the dielectric layer 20 by the internal electrode layer 30 is adjusted to 88%. In addition, in any model, the thickness of the internal electrode layer 30 is set to 0.6μm, the thickness of the dielectric layer 20 is set to 2.0μm, and the applied voltage is set to 37.5V. As a result, the value of the maximum electric field strength in the model of any model is 70MV / m, and no difference is found. Thus, it is confirmed that the maximum electric field strength has a low dependence on the average pore size.

[0147] <Second Simulation>

[0148] Next, a second simulation as an additional simulation will be described. In the second simulation, the electric field intensity generated in each model was calculated using a model in which the coverage of the dielectric layer 20 by the internal electrode layer 30 was changed.

[0149] In the second simulation, the area equivalent diameter D99 was set to 7.5 μm, the thickness of the internal electrode layer 30 was set to 0.6 μm, the thickness of the dielectric layer 20 was set to 2.0 μm, and the applied voltage was set to 37.5 V, and the maximum electric field intensity generated in the model was confirmed. Fig. 9 The following is a graph showing the results. Fig. 9 The horizontal axis is the coverage of the internal electrode layer 30 in the model, Fig. 9 The vertical axis is the maximum electric field intensity in the model.

[0150] like Fig. 9 As shown, the dependence of the value of the maximum electric field strength on the value of the coverage ratio was not confirmed. Specifically, it was confirmed that the value of the maximum electric field strength was 72 MV / m or less when the coverage ratio was 70% to 99%. For example, it was confirmed that the value of the maximum electric field strength was 72 MV / m or less when the coverage ratio was 70%, 77%, 82%, 86%, 88%, 93%, 97%, and 99%.

[0151] In order to ensure the electrostatic capacitance, it is preferred that the coverage is high. According to the second simulation, it can be confirmed that even in the case of a relatively high coverage, for example, even in the case of a coverage of 70% or more and 99% or less, by adopting the structure of the present embodiment, it is possible to improve the reliability of the product while suppressing the decrease in electrostatic capacitance. In addition, it can be confirmed that even in the case of a coverage of 86% or more and 93% or less, which is a range where the coverage is high and the productivity is also good, by adopting the structure of the present embodiment, it is possible to improve the reliability of the product while suppressing the decrease in electrostatic capacitance.

[0152] <Third Simulation>

[0153] Next, a third simulation as an additional simulation will be described. In the third simulation, the electric field intensity generated in each model was calculated using the model in which the thickness of the internal electrode layer 30 was changed.

[0154] In the third simulation, the area equivalent diameter D99 was set to 7.5 μm, the coverage of the internal electrode layer 30 on the dielectric layer 20 was set to 88%, the thickness of the dielectric layer 20 was set to 2.0 μm, the applied voltage was set to 37.5 V, and the maximum electric field intensity generated in the model was confirmed. Fig.10 The following is a graph showing the results. Fig.10 The horizontal axis is the thickness of the internal electrode layer 30 in the model. Fig.10 The vertical axis is the maximum electric field intensity in the model.

[0155] like Fig.10 As shown, it is not confirmed that the value of the maximum electric field strength depends on the thickness of the internal electrode layer 30. Specifically, it can be confirmed that when the thickness of the internal electrode layer 30 is 0.2 μm or more and 2.0 μm or less, the value of the maximum electric field strength is 72 MV / m or less. For example, it can be confirmed that when the thickness of the internal electrode layer 30 is 0.2 μm, 0.3 μm, 0.6 μm, 0.8 μm, 1.0 μm, 1.5 μm, and 2.0 μm, the value of the maximum electric field strength is 72 MV / m or less.

[0156] By reducing the thickness of the internal electrode layer 30, the number of stacked sheets can be increased even for a stack of the same size, thereby ensuring the electrostatic capacitance. According to the third simulation, it can be confirmed that even if the thickness of the internal electrode layer 30 is thin, for example, even if the thickness of the internal electrode layer 30 is greater than 0.2 μm and less than 2.0 μm, by adopting the structure of the embodiment, it is possible to improve the reliability of the product while suppressing the decrease in electrostatic capacitance. In addition, according to Fig.10 From the data, it can be confirmed that the thickness of the internal electrode layer 30 may be 0.2 μm to 1.0 μm, 0.2 μm to 0.8 μm, 0.2 μm to 0.6 μm, or 0.2 μm to 0.3 μm.

[0157] In addition, the thickness of the internal electrode layer 30 may be smaller than the value of the area equivalent diameter D99 described above. For example, the area equivalent diameter D99 is greater than or equal to 2.0 μm and less than or equal to 8.0 μm, and accordingly, the thickness of the internal electrode layer 30 may be smaller than or equal to 2.0 μm. For example, the area equivalent diameter D99 is greater than or equal to 1.5 μm and less than or equal to 8.0 μm, and accordingly, the thickness of the internal electrode layer 30 may be smaller than or equal to 0.8 μm. In this case, the area equivalent diameter D99 becomes a value greater than the thickness of the internal electrode layer 30. By setting the area equivalent diameter D99 to a given value or less and making the thickness of the internal electrode layer 30 smaller than the value of the area equivalent diameter D99, it is possible to suppress electric field concentration while adopting a structure that easily ensures electrostatic capacitance.

[0158] In addition, the thickness of the internal electrode layer 30 may be less than half the value of the area equivalent diameter D99. For example, the area equivalent diameter D99 is greater than or equal to 2.0 μm and less than or equal to 8.0 μm, and the thickness of the internal electrode layer 30 may be less than or equal to 0.8 μm. For example, the area equivalent diameter D99 is greater than or equal to 1.5 μm and less than or equal to 8.0 μm, and the thickness of the internal electrode layer 30 may be less than or equal to 0.6 μm. By setting the area equivalent diameter D99 to a value less than or equal to a given value and setting the thickness of the internal electrode layer 30 to a value less than or equal to half the value of the area equivalent diameter D99, it is possible to suppress electric field concentration while adopting a structure that is easy to ensure electrostatic capacitance.

[0159] In addition, the thickness of the internal electrode layer 30 may be smaller than the value of the area equivalent diameter D90. In this case, the area equivalent diameter D90 becomes a value larger than the thickness of the internal electrode layer 30. For example, the area equivalent diameter D90 may be 4.0 μm or less, 3.8 μm or less, or 2.6 μm or less, and the thickness of the internal electrode layer 30 may be smaller than the value of the area equivalent diameter D90. By setting the area equivalent diameter D90 to a given value or less and making the thickness of the internal electrode layer 30 smaller than the value of the area equivalent diameter D90, it is possible to suppress electric field concentration while adopting a structure that is easy to ensure electrostatic capacitance.

[0160] In addition, the thickness of the internal electrode layer 30 may be less than half the value of the area equivalent diameter D90. For example, the area equivalent diameter D90 may be less than 4.0 μm, less than 3.8 μm, or less than 2.6 μm, and the thickness of the internal electrode layer 30 may be less than half the value of the area equivalent diameter D90. By making the area equivalent diameter D90 less than a given value and making the thickness of the internal electrode layer 30 less than half the value of the area equivalent diameter D90, it is possible to suppress electric field concentration while adopting a structure that is easy to ensure electrostatic capacitance.

[0161] <Fourth Simulation>

[0162] Next, a fourth simulation as an additional simulation will be described. In the fourth simulation, it was confirmed whether the electric field concentration can be further suppressed by adjusting the shape of the holes present in the internal electrode layer 30 .

[0163] Fig.11A The figure on the left is a model of the holes in the internal electrode layer 30 used in the fourth simulation. In this model, the shapes of the multiple holes are different. In addition, the model of the holes shown in this figure is based on Fig.11A The contour of the hole formed in the actual internal electrode layer 30 shown in the figure on the right side of the figure was modeled. In the fourth simulation, the thickness of the internal electrode layer was set to 0.6μm, the thickness of the dielectric layer was set to 2.0μm, the applied voltage was set to 37.5V, and the maximum electric field intensity generated near each of the six holes H1 to H6 in the model was confirmed. In addition, the area equivalent diameters of the six holes H1 to H6 are all the same, all set to 3.0μm.

[0164] First, the roundness of the holes was calculated as a hole shape index. The roundness of hole H1 was 0.456, the roundness of hole H2 was 0.204, the roundness of hole H3 was 0.995, the roundness of hole H4 was 0.272, the roundness of hole H5 was 0.321, and the roundness of hole H6 was 0.704.

[0165] Next, a simulation was performed to confirm the maximum electric field intensity generated near each of the holes H1 to H6 . Fig. 11B 1 is a diagram showing, as examples, the electric field intensity distribution near the hole H3 having a high roundness and the electric field intensity distribution near the hole H5 having a lower roundness than the hole H3. Fig. 11B In the figure, the electric field strength is shown in grayscale, and the higher the electric field strength, the lighter the color. Fig. 11B As shown, it can be confirmed that the maximum electric field intensity generated around the contour of the hole H5 with low roundness has a lower value than the maximum electric field intensity generated around the contour of the hole H3 with high roundness.

[0166] Fig.12 This is a graph that plots the values ​​of the maximum electric field strength generated near each of the holes H1 to H6 having different roundnesses. Fig.12 The horizontal axis is the roundness of the hole. Fig.12 The vertical axis of shows a numerical value that is a standard value for the maximum electric field strength, that is, an index when the maximum electric field strength generated near the hole H3 that is close to a perfect circle is set to 1. Fig.12 In FIG. 1 , a straight line obtained by fitting the plotted points is shown.

[0167] like Fig.12 As shown, it can be confirmed that the value of the maximum electric field strength depends on the roundness of the hole. Specifically, it can be confirmed that the lower the roundness of the hole, the lower the value of the maximum electric field strength becomes. For example, if the roundness of the hole is less than 0.7, the maximum electric field strength decreases by about 15% compared to the case where the hole is almost a perfect circle. In addition, if the roundness is less than 0.46, the maximum electric field strength decreases by about 30% compared to the case where the hole is almost a perfect circle.

[0168] As described above, there is a tendency that the electric field concentration can be further suppressed by reducing the roundness of the holes existing in the internal electrode layer 30 .

[0169] Here, based on the previous simulation results, it can be expected that the roundness of holes with a relatively large area equivalent diameter contributes to the suppression of the maximum electric field strength. Therefore, using a model in which the distribution of the roundness is changed, it is confirmed whether the maximum electric field strength can be reduced. Specifically, when the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the plurality of holes H present in the internal electrode layer 30 becomes 90% is set as the area equivalent diameter D90, as a first model, a model is prepared as follows, that is, the average value of the roundness of holes with an area equivalent diameter of more than the area equivalent diameter D90 is 0.99, and the average value of the roundness of holes with an area equivalent diameter smaller than the area equivalent diameter D90 is 0.59. In addition, as a second model, a model is prepared as follows, that is, the average value of the roundness of holes with an area equivalent diameter of more than the area equivalent diameter D90 is 0.59, and the average value of the roundness of holes with an area equivalent diameter smaller than the area equivalent diameter D90 is 0.99.

[0170] In addition, in the first model and the second model, the area equivalent diameter D99 was set to 7.5 μm, the thickness of the internal electrode layer was set to 0.6 μm, the coverage of the internal electrode layer to the dielectric layer was set to 88%, the thickness of the dielectric layer was set to 2.0 μm, the applied voltage was set to 37.5 V, and the maximum electric field strength generated in the model was confirmed. Fig.13 is a graph showing the results. Fig.13 The vertical axis of shows a numerical value that is a standard of the maximum electric field strength, that is, an index when the maximum electric field strength in the first model is set to 1.

[0171] like Fig.13 As shown in FIG. 1 , it can be confirmed that the value of the maximum electric field intensity in the second model is lower than that in the first model. Specifically, it can be confirmed that the value of the maximum electric field intensity in the second model is about 25% lower than that in the first model. In other words, it can be confirmed that the roundness of the hole with a relatively large area equivalent diameter particularly contributes to the suppression of the maximum electric field intensity.

[0172] According to the above, by reducing the roundness of holes with an area equivalent diameter of D90 or more, the average value is set to less than 0.7, so that the maximum electric field strength can be further reduced. That is, by setting the average value of the roundness of multiple holes in the first mother set consisting of holes with an area equivalent diameter of more than D90 to less than 0.7, the maximum electric field strength can be further reduced. Thus, the reliability of the stacked ceramic capacitor can be further improved. It is more preferred to set the average value of the roundness of holes with an area equivalent diameter of D90 or more to less than 0.46. Thus, the maximum electric field strength can be further reduced. Thus, the reliability of the stacked ceramic capacitor can be further improved. In addition, the average value of the roundness of holes with an area equivalent diameter of D90 or more can also be greater than 0.2 and less than 0.7, or greater than 0.2 and less than 0.46.

[0173] The following describes the measurement methods of various parameters. Various parameters can be confirmed by the following methods.

[0174] First, the measurement target region when measuring parameters such as the area equivalent diameter D99, the area equivalent diameter D90, and the average value of the circularity will be described.

[0175] The inventors of the present application have accumulated research, experiments, and simulations, and have obtained the following insights: in order to improve the reliability of laminated ceramic electronic components such as laminated ceramic capacitors, it is particularly preferred to set the holes in a given area of ​​the internal electrode layer to a suitable state. Specifically, the inventors of the present application have obtained the following insights by repeatedly performing analysis after accelerated life tests on laminated ceramic capacitors, and have obtained the following insights: the burnout position of the laminated body of the laminated ceramic capacitor during insulation breakdown is often near the outer layer portion on the side, and is a region slightly separated from the edge (end) of the internal electrode layer, and it is preferred to set the holes in this region to a suitable state.

[0176] Fig.14 is with Figure 3 The scanning electron microscope (SEM) image corresponding to the enlarged view of the XIV portion of the WT cross section of the multilayer ceramic capacitor shown is a diagram showing the burnout state of the multilayer body 10 during the insulation breakdown during the accelerated life test. As described above, in the multilayer ceramic capacitor 1, the burnout portion D of the multilayer body 10 is likely to occur in the vicinity of the side outer layer portion WG and in a region slightly separated from the edge of the internal electrode layer 30.

[0177] Therefore, it is preferable to set the plurality of holes H of the internal electrode layer 30 in this region to an appropriate state. The above-mentioned measurement target region is preferably set near the side outer layer portion WG and in a region slightly away from the side of the internal electrode layer 30 .

[0178] Specifically, the region from the position of 10 μm to the position of 50 μm from the first side WE1 in the first internal electrode layer 31 is set as the first region A1, the region from the position of 10 μm to the position of 50 μm from the second side WE2 is set as the second region A2, the region from the position of 10 μm to the position of 50 μm from the third side in the second internal electrode layer 32 is set as the third region A3, and the region from the position of 10 μm to the position of 50 μm from the fourth side is set as the fourth region A4. In this case, it is preferable that the first region A1, the second region A2, the third region A3, and the fourth region A4 are used as the measurement target regions. In addition, when the linearity of the first side WE1 to the fourth side WE4 is low, the first region A1 to the fourth region A4 are defined on the basis of defining each side as a straight line by linear fitting based on linear regression or the like.

[0179] exist Figure 4A Schematically shows the first area A1 and the second area A2 as the measurement target areas. Figure 4B Schematically showing the third area A3 and the fourth area A4 as the measurement target areas.

[0180] In the first area A1 , the second area A2 , the third area A3 , and the fourth area A4 as the measurement target areas, a measurement target range for actually measuring parameters based on SEM observation is set.

[0181] In SEM observation, the observation range within an observation field is set to a range of 40μm×40μm to 80μm×80μm. Then, the analysis object range is set to the range of 40μm×40μm therein. Then, based on the set of analysis object ranges of 12 parts, parameters such as area equivalent diameter are measured. Specifically, in each of the first area A1, the second area A2, the third area A3 and the fourth area A4, analysis object ranges a of 3 parts are set respectively. The analysis object ranges a of the 3 parts are set within the range of the opposing electrode part 11E. Among the analysis object ranges a of the 3 parts, the analysis object range a set on the side closest to the first end face LS1 is set at a position 10μm away from the outer layer part LG1 on the first end face side. Among the analysis object ranges a of the 3 parts, the analysis object range a set on the side closest to the second end face LS2 is set at a position 10μm away from the outer layer part LG2 on the second end face side. The analysis target range a set at the center of the three analysis target ranges a is set at the center of the stacked body 10 in the longitudinal direction L. The three analysis target ranges a are set at equal intervals in the longitudinal direction L of the stacked ceramic capacitor. Figure 4A, as an example, the analysis target range a set at three locations in the second area A2 is shown. Then, the measurement target range for measuring parameters such as the area equivalent diameter D99 is set by a collection of the analysis target ranges a of 12 locations in total, 4 regions×3 locations.

[0182] In addition, when the sheet size of the laminated ceramic electronic component is small, the first area A1 to the fourth area A4 can also be set at overlapping positions. In addition, each analysis target range a can also be set at an overlapping position. In this case, each area is overlapped and set at a different position, and each analysis target range is set to a region as large as possible that covers the internal electrode layer.

[0183] <Measurement Method of Area Equivalent Diameters D99 and D90>

[0184] A method for measuring the area-equivalent diameters D99 and D90 of the pores present in the internal electrode layer 30 will be described.

[0185] First, the internal electrode layer 30 and the dielectric layer 20 located in the center of the stack 10 in the height direction are peeled off by electric field stripping, thereby exposing the internal electrode layer 30. Next, a portion of the first region A1 to the fourth region A4 of the internal electrode layer 30 as the measurement target region is set as the above-mentioned analysis target range a, and SEM observation is performed. In addition, when the first internal electrode layer 31 is exposed, first, a portion of the first region A1 and the second region A2 of the first internal electrode layer 31 are set as the above-mentioned analysis target range a, and SEM observation is performed. Then, the second internal electrode layer 32 is exposed by FIB (focused ion beam) processing. Then, a portion of the third region A3 and the fourth region A4 of the second internal electrode layer 32 is set as the above-mentioned analysis target range a, and SEM observation is performed. In addition, the SEM observation of the first internal electrode layer 31 can also be performed after the SEM observation of the second internal electrode layer 32 is performed.

[0186] In the SEM observation, the SEM image is analyzed to identify the contours of each hole formed in the internal electrode layer 30. Then, for each hole formed in the internal electrode layer 30, the area equivalent diameter of the hole is calculated based on the area of ​​the hole specified by the hole contour. The area equivalent diameter is the value of the diameter of a perfect circle having an area equal to the area of ​​the hole specified by the hole contour.

[0187] The area equivalent diameter of each of the above-mentioned holes is calculated for the analysis target range a of the 12 locations constituting the measurement target range. Here, the area of ​​the hole is smaller than 1.0 μm. 2 The "hole" in the value of may not be a hole but noise. Therefore, in order to eliminate the influence of noise, it is excluded from the analysis object in the subsequent analysis.

[0188] All the holes identified in the measurement target range, that is, the analysis target range of the 12 sites (except the holes with an area smaller than 1.0 μm) were 2 The set of "holes" with values ​​other than is set as the parent set of holes.

[0189] Based on the data of the area equivalent diameter of the parent set of holes in the measurement target range, the area equivalent diameter D99 and the area equivalent diameter D90 are calculated. The area equivalent diameter D99 is calculated as the area equivalent diameter at which the cumulative value in the cumulative distribution based on the number of holes in the measurement target area becomes 99%. The area equivalent diameter D90 is calculated as the area equivalent diameter at which the cumulative value in the cumulative distribution based on the number of holes in the measurement target area becomes 90%.

[0190] <Method for measuring hole roundness>

[0191] A method for measuring the circularity of the holes present in the internal electrode layer 30 will be described.

[0192] First, the internal electrode layer 30 and the dielectric layer 20 located in the center of the stack 10 in the height direction are peeled off by electric field stripping, thereby exposing the internal electrode layer 30. Next, a portion of the first region A1 to the fourth region A4 of the internal electrode layer 30 as the measurement target region is set as the above-mentioned analysis target range a, and SEM observation is performed. In addition, when the first internal electrode layer 31 is exposed, first, a portion of the first region A1 and the second region A2 of the first internal electrode layer 31 are set as the above-mentioned analysis target range a, and SEM observation is performed. Then, the second internal electrode layer 32 is exposed by FIB (focused ion beam) processing. Then, a portion of the third region A3 and the fourth region A4 of the second internal electrode layer 32 is set as the above-mentioned analysis target range a, and SEM observation is performed. In addition, the SEM observation of the first internal electrode layer 31 can also be performed after the SEM observation of the second internal electrode layer 32 is performed.

[0193] In the SEM observation, the SEM image is analyzed to identify the contours of each hole formed in the internal electrode layer 30. Then, for each hole formed in the internal electrode layer 30, the area equivalent diameter of the hole is calculated based on the area of ​​the hole specified by the hole contour. The area equivalent diameter is the value of the diameter of a perfect circle having an area equal to the area of ​​the hole specified by the hole contour.

[0194] The area equivalent diameter of each of the above-mentioned holes is calculated for the 12 analysis target ranges constituting the measurement target range a. Here, the area of ​​the hole is smaller than 1.0 μm.2 The "hole" in the value of may not be a hole but noise. Therefore, in order to eliminate the influence of noise, it is excluded from the analysis object in the subsequent analysis.

[0195] All the holes identified in the measurement target range, that is, the analysis target range of the 12 sites (except the holes with an area smaller than 1.0 μm) were 2 The set of "holes" with values ​​other than is set as the parent set of holes.

[0196] For each hole in the parent set of holes, the circularity of the hole is calculated by the following formula (1) based on the area of ​​the hole and the length of the circumference defined by the hole contour.

[0197] Circularity = 4π×(area) / (circumference length) 2 …(1)

[0198] Furthermore, the mother set of holes existing in the measurement target area is divided into a first mother set consisting of holes having an area equivalent diameter of not less than the area equivalent diameter D90, and a second mother set consisting of holes having an area equivalent diameter smaller than the area equivalent diameter D90. Then, the average value of the roundness of the plurality of holes in the first mother set consisting of holes having an area equivalent diameter of not less than the area equivalent diameter D90 is calculated. This is taken as the average value of the roundness of the plurality of holes in the first mother set of the present embodiment.

[0199] <Method for measuring coverage>

[0200] A method for measuring the coverage ratio, which is the coverage ratio of the internal electrode layer 30 to the dielectric layer 20 , will be described.

[0201] First, the internal electrode layer 30 and the dielectric layer 20 located in the center of the stack 10 in the height direction are peeled off by electric field stripping, thereby exposing the internal electrode layer 30. Next, a portion of the first region A1 to the fourth region A4 of the internal electrode layer 30 as the measurement target region is set as the above-mentioned analysis target range a, and SEM observation is performed. In addition, when the first internal electrode layer 31 is exposed, first, a portion of the first region A1 and the second region A2 of the first internal electrode layer 31 are set as the above-mentioned analysis target range a, and SEM observation is performed. Then, the second internal electrode layer 32 is exposed by FIB (focused ion beam) processing. Then, a portion of the third region A3 and the fourth region A4 of the second internal electrode layer 32 is set as the above-mentioned analysis target range a, and SEM observation is performed. In addition, the SEM observation of the first internal electrode layer 31 can also be performed after the SEM observation of the second internal electrode layer 32 is performed.

[0202] Then, by analyzing the SEM image, the region of the internal electrode layer 30 in the analysis target range a is identified. Then, based on the area of ​​the analysis target range a and the area of ​​the region of the internal electrode layer 30, the coverage of the dielectric layer 20 by the internal electrode layer 30 is calculated by the following formula (2).

[0203] Coverage rate (%) = (area of ​​internal electrode layer / area of ​​analysis target range) × 100 (2)

[0204] The coverage of the dielectric layer 20 by the internal electrode layer 30 was calculated for the 12 analysis target areas constituting the measurement target area, and the average value thereof was taken as the coverage of the dielectric layer 20 by the internal electrode layer 30 in the present embodiment.

[0205] <Method for measuring thickness of internal electrode layer>

[0206] A method for measuring the thickness of the plurality of internal electrode layers 30 will be described.

[0207] First, the cross section of the multilayer ceramic capacitor is polished to a position of 1 / 2 of the L dimension to expose a specific WT cross section. Then, the WT cross section of the multilayer body 10 exposed by polishing is observed using a SEM.

[0208] Next, the thickness of the internal electrode layer 30 is measured on a total of five lines, namely, a center line along the stacking direction passing through the center of the cross section of the stacked body 10 and two lines drawn at equal intervals from the center line to both sides. Here, the thickness of the internal electrode layer 30 at the five locations is measured at three locations in the stacking direction of the stacked body 10. Then, the average value of the thickness of the internal electrode layer 30 at a total of 15 locations, namely, 3 locations × 5 locations, is taken as the thickness of the internal electrode layer 30 in the present embodiment.

[0209] Next, a method for manufacturing the multilayer ceramic capacitor 1 according to the present embodiment will be described.

[0210] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and the solvent may be known binders and solvents.

[0211] On the dielectric sheet, a conductive paste for the internal electrode layer 30 is printed in a predetermined pattern by screen printing, gravure printing, etc. Thus, a dielectric sheet having a pattern of the first internal electrode layer 31 and a dielectric sheet having a pattern of the second internal electrode layer 32 are prepared.

[0212] By stacking a predetermined number of dielectric sheets without printing the pattern of the internal electrode layer, a portion of the first main surface side outer layer portion 12 on the first main surface TS1 side is formed. By stacking a dielectric sheet with a pattern of the first internal electrode layer 31 printed thereon and a dielectric sheet with a pattern of the second internal electrode layer 32 printed thereon in sequence, a portion of the inner layer portion 11 is formed. By stacking a predetermined number of dielectric sheets without printing the pattern of the internal electrode layer on the portion that becomes the inner layer portion 11, a portion of the second main surface side outer layer portion 13 on the second main surface TS2 side is formed. In this way, a laminated sheet is produced.

[0213] The laminated sheets are pressed in the height direction by isostatic pressing or the like to produce a laminated block.

[0214] The stacked blocks are cut into predetermined sizes to produce stacked small pieces. At this time, the corners and ridges of the stacked small pieces may be rounded by barrel grinding or the like.

[0215] The stacked small pieces are fired to produce the stacked body 10. The firing temperature depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably 900°C or higher and 1400°C or lower.

[0216] Here, the above-mentioned manufacturing conditions may be adjusted to set the area-equivalent diameter D99 of the pores existing in the internal electrode layer 30 to a given value or less, for example, 8.0 μm or less, 4.7 μm or less, or 3.2 μm or less, and to make it fall within a given range.

[0217] Specifically, the pressure, temperature, and pressing time when stacking dielectric sheets printed with the pattern of the internal electrode layer 30 are adjusted so that the area-equivalent diameter D99 of the holes existing in the internal electrode layer 30 becomes less than a given value. For example, when the internal electrode layer 30 is relatively thin, the pressure when pressing the stacked sheets is set to be higher.

[0218] In addition, in order to set the area equivalent diameter D99 of the holes existing in the internal electrode layer 30 to a given value or less, the material of the conductive paste used for the internal electrode layer 30 may be adjusted. For example, when the main component of the internal electrode layer 30 is Ni, by using particles with a larger average particle size as Ni particles that become the raw material of the conductive paste, the bonding start temperature of the Ni particles and the sintering shrinkage start temperature of the ceramic can be made close. As a result, the spheroidization of the internal electrode layer 30 can be suppressed and the area equivalent diameter D99 can be adjusted to be below a given value. In addition, when the same ceramic powder as the ceramic powder contained in the dielectric layer 20 is added as a common material to the conductive paste for the internal electrode layer 30, by using a common material with a larger average particle size, the bonding start temperature of the Ni particles and the sintering shrinkage start temperature of the ceramic can be made close. As a result, the spheroidization of the internal electrode layer 30 can be suppressed and the area equivalent diameter D99 can be adjusted to be below a given value. Furthermore, the dispersibility of the common material can be improved by controlling the affinity between the Ni particles, the common material, and the solvent of the conductive paste for the internal electrode layer 30. Thus, the spheroidization of the internal electrode layer 30 can be suppressed, and the area equivalent diameter D99 of the pores can be adjusted to be less than a given value.

[0219] In addition, when the stacked small pieces are fired, the temperature uniformity of the small pieces during firing can be improved by arranging the stacked small pieces densely. Thus, the spheroidization of the internal electrode layer 30 can be suppressed, and the area equivalent diameter D99 can be adjusted to be less than a given value. In addition, the stacked small pieces can be fired in a state of being buried in ceramic powder, thereby improving the temperature uniformity inside and outside the small pieces during firing. Thus, the spheroidization of the internal electrode layer 30 can be suppressed, and the area equivalent diameter D99 can be adjusted to be less than a given value. In addition, during firing, the temperature of the portion of the stacked small pieces close to the first side surface and the second side surface, for example, the edge on the first side surface WS1 side of the internal electrode layer 30 and the edge on the second side surface WS2 side of the internal electrode layer is likely to rise. Therefore, the spheroidization of the internal electrode layer 30 is likely to occur in this portion. However, by the above method, the spheroidization of the first area A1 to the fourth area A4 of the internal electrode layer 30 can be suppressed, and the area equivalent diameter D99 of the hole existing in the internal electrode layer 30 can be set to be less than a given value.

[0220] In addition, the internal electrode layer 30 can also be formed by printing in two steps, so that the internal electrode layer 30 is formed so that the area equivalent diameter D99 of the holes existing in at least the portion close to the first side surface and the second side surface of the stacked small piece, for example, the first area A1 to the fourth area A4 becomes less than a given value. In this case, a conductive paste containing Ni particles with a large average particle size and a common material with a large average particle size is printed at least in the first area A1 to the fourth area A4. Moreover, in other areas including the central area of ​​the internal electrode layer 30, a conductive paste containing Ni particles with a relatively small average particle size and a common material with a relatively small average particle size is printed. Thus, at least for the holes existing in the first area A1 to the fourth area A4, their area equivalent diameter D99 can be set to be less than a given value.

[0221] In addition, the above-mentioned method of setting the area equivalent diameter D99 of the holes existing in the internal electrode layer 30 to a given value or less can be appropriately combined. Thus, the area equivalent diameter D99 of the holes existing in the internal electrode layer 30 can be adjusted to a given value or less, for example, 8.0 μm or less, 4.7 μm or less, or 3.2 μm or less, or can be adjusted to a given range. Similarly, by the above-mentioned method, the area equivalent diameter D90 of the holes existing in the internal electrode layer 30 can be adjusted to a given value or less or within a given range.

[0222] In addition, in order to set the roundness of the plurality of holes existing in the internal electrode layer 30 to a given value or less, for example, in order to set the average value of the roundness of the holes with an area equivalent diameter of D90 or more to 0.7 or less, or 0.46 or less, the material of the conductive paste used for the internal electrode layer 30 may also be adjusted. For example, in the case where the main component of the internal electrode layer 30 is Ni, particles with a deviation in particle size may be used as the raw material of the conductive paste. Thus, a hole with a flattened shape as if a plurality of small holes are connected can be formed, and the roundness of a larger hole can be reduced. In addition, in the case where the same ceramic powder as the ceramic powder included in the dielectric layer 20 is added as a common material, a common material with a deviation in particle size may be used as a common material. Thus, a hole with a flattened shape as if a plurality of small holes are connected can be formed, and the roundness of a larger hole can be reduced. By using these methods, the average value of the roundness of the holes with an area equivalent diameter of D90 or more can be set to a given value or less.

[0223] In addition, the internal electrode layer 30 can also be formed by printing in two steps, so that the internal electrode layer 30 is formed so that the roundness of the holes existing in at least the portion close to the first side surface and the second side surface of the stacked small piece, for example, the first area A1 to the fourth area A4 becomes less than a given value. In this case, at least in the first area A1 to the fourth area A4, a conductive paste using Ni particles with a deviation in particle size and a common material with a deviation in particle size is printed. Moreover, in other areas including the central area of ​​the internal electrode layer 30, a conductive paste containing Ni particles with suppressed particle size deviation and a common material with suppressed particle size deviation is printed. Thus, at least for the holes existing in the first area A1 to the fourth area A4, the average value of the roundness of the holes with an area equivalent diameter of more than D90 can be set to less than a given value. In addition, such a method can also be used to form the internal electrode layer 30 so that the average value of the roundness of the holes existing in the first area A1 to the fourth area A4 is lower than the average value of the roundness of the holes existing in the central area of ​​the internal electrode layer 30.

[0224] A conductive paste that becomes a base electrode layer (a first base electrode layer 50A and a second base electrode layer 50B) is applied to both end surfaces of the stack 10. In the present embodiment, the base electrode layer is a sintered layer. The conductive paste containing a glass component and a metal is applied to the stack 10 by, for example, a dipping method. Then, a sintering treatment is performed to form the base electrode layer. The temperature of the sintering treatment at this time is preferably 700° C. or higher and 900° C. or lower.

[0225] In addition, when the stacked small pieces before firing and the conductive paste applied to the stacked small pieces are fired at the same time, the sintered layer is preferably formed by firing a paste to which a ceramic material is added instead of a glass component. At this time, as the added ceramic material, it is particularly preferred to use a ceramic material of the same type as the dielectric layer 20. In this case, the conductive paste is applied to the stacked small pieces before firing, and the stacked small pieces and the conductive paste applied to the stacked small pieces are fired at the same time, thereby forming a stacked body 10, which forms a sintered layer.

[0226] Then, a plating layer is formed on the surface of the base electrode layer. In the present embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. In addition, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In the present embodiment, a Ni plating layer and a Sn plating layer are formed as plating layers. When performing the plating process, either electrolytic plating or electroless plating may be used. However, with respect to electroless plating, in order to increase the deposition rate of the plating layer, pretreatment using a catalyst or the like is required, so there is a disadvantage that the process is complicated. Therefore, it is generally preferred to use electrolytic plating. The Ni plating layer and the Sn plating layer are formed in sequence, for example, by roller plating.

[0227] In addition, when the base electrode layer is formed by a thin film layer, a thin film layer as the base electrode layer is formed at a portion where an external electrode is to be formed by performing mask setting, etc. The thin film layer is formed by a thin film forming method such as sputtering or evaporation. The thin film layer is a layer of 1.0 μm or less in which metal particles are deposited.

[0228] In addition, when a conductive resin layer is provided as the base electrode layer, the conductive resin layer can be configured to cover the sintered layer, or it can be directly configured on the laminate 10 without providing the sintered layer. When a conductive resin layer is provided, a conductive resin paste containing a thermosetting resin and a metal component is applied on the sintered layer or the laminate 10, and then heat-treated at a temperature of 250 to 550° C. or above. Thus, the thermosetting resin is heat-cured to form a conductive resin layer. The atmosphere during the heat treatment is preferably an N2 atmosphere. In addition, in order to prevent the scattering of the resin and the oxidation of various metal components, the oxygen concentration is preferably 100 ppm or less.

[0229] In addition, the plating layer may be directly arranged on the exposed portion of the internal electrode layer 30 of the stack 10 without providing the base electrode layer. In this case, the plating process is implemented on the first end face LS1 and the second end face LS2 of the stack 10 to form the plating layer on the exposed portion of the internal electrode layer 30. When performing the plating process, either electrolytic plating or electroless plating may be used. However, regarding electroless plating, in order to increase the deposition speed of the plating layer, it is necessary to perform pretreatment using a catalyst, etc., so there is a disadvantage that the process is complicated. Therefore, electrolytic plating is usually preferably used. As a plating method, drum plating is preferably used. In addition, as needed, an upper plating layer may be formed by the same process as the lower plating layer, and the upper plating layer is formed on the surface of the lower plating layer.

[0230] Through such manufacturing steps, the multilayer ceramic capacitor 1 can be manufactured.

[0231] The structure of the multilayer ceramic capacitor 1 is not limited to Figure 1 to Figure 4B For example, the multilayer ceramic capacitor 1 may also be as follows Fig.15A , Fig. 15B , Fig. 15C The following are the multilayer ceramic capacitors with two-cell structure, three-cell structure, and four-cell structure.

[0232] Fig.15A The illustrated multilayer ceramic capacitor 1 is a duplex structure multilayer ceramic capacitor 1 and includes, as the internal electrode layer 30 , a floating internal electrode layer 35 that is not extended to either the first end surface LS1 or the second end surface LS2 in addition to the first internal electrode layer 33 and the second internal electrode layer 34 . Fig. 15BThe illustrated multilayer ceramic capacitor 1 is a triple-structured multilayer ceramic capacitor 1 , and includes a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as the floating internal electrode layers 35 . Fig. 15C The illustrated multilayer ceramic capacitor 1 is a multilayer ceramic capacitor 1 of a quadruple structure, and includes a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C as floating internal electrode layers 35. In this way, by providing the floating internal electrode layer 35 as the internal electrode layer 30, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into a plurality of parts. Thus, a plurality of capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components have a structure connected in series. Therefore, the voltage applied to each capacitor component becomes lower, and the multilayer ceramic capacitor 1 can be made to have a high withstand voltage. In addition, it is self-evident that the multilayer ceramic capacitor 1 of the present embodiment can also be a multi-connection structure of four or more.

[0233] Furthermore, the multilayer ceramic capacitor 1 may be a two-terminal multilayer ceramic capacitor having two external electrodes, or may be a multi-terminal multilayer ceramic capacitor having a plurality of external electrodes.

[0234] In addition, in the above-mentioned embodiment, as a stacked ceramic electronic component, the following stacked ceramic capacitor is exemplified, that is, as a ceramic layer, a dielectric layer 20 composed of dielectric ceramics is used. However, the stacked ceramic electronic component disclosed in the present invention is not limited to this. For example, the ceramic electronic component disclosed in the present invention can also be applied to various stacked ceramic electronic components such as piezoelectric components using piezoelectric ceramics as ceramic layers and thermistors using semiconductor ceramics as ceramic layers. As piezoelectric ceramics, PZT (lead zirconate titanate) ceramics and the like can be listed, and as semiconductor ceramics, spinel ceramics and the like can be listed.

[0235] According to the multilayer ceramic electronic component of the present embodiment, the following effects are achieved.

[0236] (1) The laminated ceramic electronic component 1 of the present embodiment comprises: a laminated body 10 having a plurality of laminated ceramic layers 20 and a plurality of internal conductor layers 30 laminated on the ceramic layers 20, and having a first main surface TS1 and a second main surface TS2 opposite to each other in the height direction, a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction perpendicular to the height direction, and a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction perpendicular to the height direction and the width direction; and an external electrode 40 connected to the internal conductor layer 30, wherein a plurality of holes having different area equivalent diameters are present in the internal conductor layer 30, and when the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the plurality of holes present in the internal conductor layer 30 becomes 99% is set as the area equivalent diameter D99, the area equivalent diameter D99 is 8.0 μm or less. Thus, it is possible to provide a laminated ceramic electronic component that suppresses electric field concentration and has high reliability.

[0237] (2) In the multilayer ceramic electronic component 1 of the present embodiment, the area-equivalent diameter D99 of the plurality of holes existing in the internal conductor layer 30 is 4.7 μm or less. This can provide a multilayer ceramic electronic component that suppresses electric field concentration and has high reliability.

[0238] (3) In the multilayer ceramic electronic component 1 of the present embodiment, the area-equivalent diameter D99 of the plurality of holes existing in the internal conductor layer 30 is 3.2 μm or less. This can provide a multilayer ceramic electronic component that suppresses electric field concentration and has high reliability.

[0239] (4) In the multilayer ceramic electronic component 1 of the present embodiment, the area equivalent diameter D99 of the plurality of holes existing in the internal conductor layer 30 is 2.0 μm to 8.0 μm. This can provide a multilayer ceramic electronic component that suppresses electric field concentration and has high reliability.

[0240] (5) In the multilayer ceramic electronic component 1 of the present embodiment, the area equivalent diameter D99 of the plurality of holes existing in the internal conductor layer 30 is 2.0 μm to 4.0 μm. This can provide a multilayer ceramic electronic component with high reliability while suppressing electric field concentration.

[0241] (6) In the multilayer ceramic electronic component 1 of the present embodiment, the coverage of the ceramic layer 20 by the internal conductor layer 30 is 70% or more and 99% or less. This can improve product reliability while suppressing a decrease in electrostatic capacitance.

[0242] (7) In the multilayer ceramic electronic component 1 of the present embodiment, the coverage of the ceramic layer 20 by the internal conductor layer 30 is 86% or more and 93% or less. This can improve the reliability of the product while suppressing a decrease in electrostatic capacitance.

[0243] (8) In the multilayer ceramic electronic component 1 of the present embodiment, the thickness of the internal conductor layer 30 is 0.2 μm or more and 2.0 μm or less. This makes it possible to suppress electric field concentration while adopting a structure that makes it easy to ensure electrostatic capacitance.

[0244] (9) In the multilayer ceramic electronic component 1 of the present embodiment, the thickness of the internal conductor layer 30 is 0.2 μm or more and 0.3 μm or less. This can suppress electric field concentration while adopting a structure that easily ensures electrostatic capacitance.

[0245] (10) In the multilayer ceramic electronic component 1 of the present embodiment, the thickness of the internal conductor layer 30 is smaller than the value of the area equivalent diameter D99. This makes it possible to suppress electric field concentration while adopting a structure that easily ensures electrostatic capacitance.

[0246] (11) In the multilayer ceramic electronic component 1 of the present embodiment, when the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the plurality of holes existing in the internal conductor layer 30 becomes 90% is set as the area equivalent diameter D90, the thickness of the internal conductor layer 30 is set to a size that is less than half of the value of the area equivalent diameter D90. Thus, it is possible to suppress electric field concentration while adopting a structure that is easy to ensure electrostatic capacitance.

[0247] (12) In the multilayer ceramic electronic component 1 of the present embodiment, when the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the plurality of holes existing in the internal conductor layer 30 becomes 90% is set as the area equivalent diameter D90, the average value of the roundness of the plurality of holes in the first mother group consisting of holes having an area equivalent diameter equal to or larger than the area equivalent diameter D90 is 0.7 or less. Thus, the electric field concentration can be further suppressed.

[0248] (13) In the multilayer ceramic electronic component 1 of the present embodiment, when the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the plurality of holes existing in the internal conductor layer 30 becomes 90% is set as the area equivalent diameter D90, the average value of the roundness of the plurality of holes in the first mother group consisting of holes having an area equivalent diameter equal to or larger than the area equivalent diameter D90 is 0.2 or more and 0.7 or less. Thus, the electric field concentration can be further suppressed.

[0249] (14) In the multilayer ceramic electronic component 1 of the present embodiment, when the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the plurality of holes existing in the internal conductor layer 30 becomes 90% is set as the area equivalent diameter D90, the average value of the roundness of the plurality of holes in the first mother group consisting of holes having an area equivalent diameter equal to or larger than the area equivalent diameter D90 is 0.2 or more and 0.46 or less. Thus, the electric field concentration can be further suppressed.

[0250] (15) In the multilayer ceramic electronic component 1 of the present embodiment, the area-equivalent diameter D99 of the plurality of holes existing in the internal conductor layer 30 is 8.0 μm or less, and the area-equivalent diameter D90 of the plurality of holes existing in the internal conductor layer 30 is 4.0 μm or less. This can suppress electric field concentration.

[0251] (16) In the multilayer ceramic electronic component 1 of the present embodiment, the area-equivalent diameter D99 of the plurality of holes existing in the internal conductor layer 30 is greater than or equal to 2.0 μm and less than or equal to 8.0 μm, and the area-equivalent diameter D90 of the plurality of holes existing in the internal conductor layer 30 is greater than or equal to 1.9 μm and less than or equal to 4.0 μm. This can suppress electric field concentration.

[0252] (17) The external electrode 40 of the laminated ceramic electronic component 1 of the present embodiment includes a first external electrode 40A arranged on the first end surface LS1 side and a second external electrode 40B arranged on the second end surface LS2 side. The plurality of internal conductor layers 30 include a plurality of first internal conductor layers 31 electrically connected to the first external electrode 40A and a plurality of second internal conductor layers 32 electrically connected to the second external electrode 40B. The first internal conductor layer 31 includes a first edge WE1 on the first side surface WS1 side and a second edge WE2 on the second side surface WS2 side. The second internal conductor layer 32 includes a third edge WE3 on the first side surface WS1 side and a fourth edge WE4 on the second side surface WS2 side. The first internal conductor layer 31 is provided with a portion of the first internal conductor layer 31 extending from a position 10 μm away from the first edge WE1 to a portion 50 μm away from the first edge WE1. The area at the position of m is set as the first area A1, the area from the position 10 μm away from the second side WE2 to the position 50 μm away from the second side WE2 is set as the second area A2, the area from the position 10 μm away from the third side WE3 to the position 50 μm away from the third side WE3 in the second internal conductor layer 32 is set as the third area A3, the area from the position 10 μm away from the fourth side WE4 to the position 50 μm away from the fourth side WE4 is set as the fourth area A4, and the set of holes existing in the first area A1, the second area A2, the third area A3 and the fourth area A4 is set as the parent set of holes, at this time, the area equivalent diameter D99 is the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the holes in the parent set of holes becomes 99%. Thus, it is possible to provide a laminated ceramic electronic component with high reliability and suppressed electric field concentration.

[0253] (18) The laminated ceramic electronic component 1 of the present embodiment comprises: a laminated body 10 having a plurality of laminated ceramic layers 20 and a plurality of internal conductor layers 30 laminated on the ceramic layers 20, and having a first main surface TS1 and a second main surface TS2 opposite to each other in the height direction, a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction perpendicular to the height direction, and a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction perpendicular to the height direction and the width direction; and an external electrode 40 connected to the internal conductor layer 30, wherein the internal conductor layer 30 has a plurality of holes having different area equivalent diameters, the external electrode 40 having a first external electrode 40A arranged on the first end surface LS1 side and a second external electrode 40B arranged on the second end surface LS2 side, the plurality of internal conductor layers 30 having a plurality of first internal conductor layers 31 electrically connected to the first external electrode 40A and a plurality of second internal conductor layers 32 electrically connected to the second external electrode 40B, the first internal conductor layer 31 having a first side WE1 on the first side surface WS1 side and a second side WE2 on the second side surface WS2 side, The inner conductor layer 32 has a third side WE3 on the first side WS1 side and a fourth side WE4 on the second side WS2 side. The first inner conductor layer 31 has a region from a position 10 μm away from the first side WE1 to a position 50 μm away from the first side WE1 as a first region A1, a region from a position 10 μm away from the second side WE2 to a position 50 μm away from the second side WE2 as a second region A2, and a region from a position 10 μm away from the third side WE3 to a position 50 μm away from the second side WE3 as a second region A2. The area at the position 50 μm apart is set as the third area A3, the area from the position 10 μm away from the fourth side WE4 to the position 50 μm away from the fourth side WE4 is set as the fourth area A4, the set of holes existing in the first area A1, the second area A2, the third area A3 and the fourth area A4 is set as the parent set of holes, and the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the holes in the parent set of holes becomes 99% is set as the area equivalent diameter D99, and at this time, the area equivalent diameter D99 is 8.0 μm or less. Thus, it is possible to provide a laminated ceramic electronic component that suppresses electric field concentration and has high reliability.

[0254] <Example>

[0255] According to the manufacturing method described in this embodiment, multiple batches (first batch to third batch) of multilayer ceramic capacitors were produced as samples of the embodiment, and the multiple batches were produced so that the area equivalent diameter D99 became different values. Then, a reliability test based on an accelerated life test (HALT test) was carried out using the produced samples.

[0256] <Manufacturing of Multilayer Ceramic Capacitors>

[0257] First, according to the manufacturing method described in this embodiment, a multilayer ceramic capacitor having the following specifications was produced as a sample of an example.

[0258] Dimensions of multilayer ceramic capacitors: L×W×T=2.15mm×1.41mm×1.45mm

[0259] Capacitance: 4.7μF

[0260] Rated voltage: 25V

[0261] Dielectric layer: BaTiO3

[0262] Internal electrode layer: Ni

[0263] Base electrode layer: an electrode containing conductive metal (Cu) and glass components

[0264] Plating layer: Two-layer structure of 2μm Ni plating layer and 2μm Sn plating layer

[0265] ·Batch of multilayer ceramic capacitors

[0266] (First batch) Area equivalent diameter D99 of the pores in the internal electrode layer: 2.2 μm

[0267] (Second batch) Area equivalent diameter D99 of the pores in the internal electrode layer: 3.2 μm

[0268] (Third batch) Area equivalent diameter D99 of the pores in the internal electrode layer: 4.7 μm

[0269] Here, the first batch to the third batch are batches manufactured by different manufacturing methods, and the area equivalent diameter D99 of the multiple holes existing in the internal electrode layer is different. In addition, according to each batch, 5 samples for measuring the area equivalent diameter D99 are prepared, and the average value of the measured values ​​of the area equivalent diameter D99 of the 5 samples is calculated as the value of the area equivalent diameter D99 of the batch. In addition, according to each batch, 40 samples for accelerated life test (HALT test) are prepared.

[0270] <Accelerated life test>

[0271] An accelerated life test (HALT) was performed at an ambient temperature of 150°C with a DC voltage of 64V applied. The point in time when the insulation resistance dropped below 10kΩ was considered a failure. The mean time to failure (MTTF) was calculated by applying Weibull analysis to the results. The results of the accelerated life test are shown in Table 1.

[0272] [Table 1]

[0273] batch First batch Second batch The third batch MTTF (hours) 149 120 98

[0274] As shown in Table 1, it can be confirmed that the average failure time of the second batch is longer than that of the third batch, and the average failure time of the first batch is longer than that of the second batch. In other words, it can be confirmed that the average failure time of the batch with an area equivalent diameter D99 of 8.0 μm or less and a smaller area equivalent diameter D99 has a longer average failure time and higher reliability.

[0275] The present invention is not limited to the configuration of the above-described embodiment, and can be applied with appropriate changes within the scope of the present invention. In addition, a configuration combining two or more of the preferred configurations described in the above-described embodiment is also the present invention.

Claims

1. A laminated ceramic electronic component comprising: A laminate having a plurality of stacked ceramic layers and a plurality of internal conductor layers stacked on the ceramic layers, and having a first main surface and a second main surface opposite to each other in a height direction, a first side surface and a second side surface opposite to each other in a width direction orthogonal to the height direction, and a first end surface and a second end surface opposite to each other in a length direction orthogonal to the height direction and the width direction; and an external electrode connected to the internal conductor layer, The coverage of the ceramic layer by the internal conductor layer is 70% or more and 99% or less, The inner conductor layer has a plurality of holes having different area equivalent diameters. When the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the plurality of holes in the inner conductor layer becomes 99% is set as the area equivalent diameter D99, and the area equivalent diameter at which the cumulative value of the cumulative distribution of the area equivalent diameters of the plurality of holes in the inner conductor layer becomes 90% is set as the area equivalent diameter D90, The area equivalent diameter D99 is greater than or equal to 2.0 μm and less than or equal to 4.0 μm, and the area equivalent diameter D90 is greater than or equal to 1.9 μm and less than or equal to 2.6 μm, and the thickness of the internal conductor layer is less than or equal to half of the value of the area equivalent diameter D90.

2. The multilayer ceramic electronic component according to claim 1, wherein The area equivalent diameter D99 is 3.2 μm or less.

3. The multilayer ceramic electronic component according to claim 1 or 2, wherein: The coverage of the ceramic layer by the internal conductor layer is 86% or more and 93% or less.

4. The multilayer ceramic electronic component according to claim 1 or 2, wherein: The thickness of the internal conductor layer is greater than or equal to 0.2 μm and less than or equal to 0.3 μm.

5. The multilayer ceramic electronic component according to claim 1 or 2, wherein: The average value of the circularity of the plurality of holes in the first mother set consisting of holes having an area equivalent diameter equal to or greater than the area equivalent diameter D90 is 0.7 or less.

6. The multilayer ceramic electronic component according to claim 1 or 2, wherein: The average value of the circularity of the plurality of holes in the first mother set consisting of holes having an area equivalent diameter equal to or greater than the area equivalent diameter D90 is greater than or equal to 0.2 and less than or equal to 0.

7.

7. The multilayer ceramic electronic component according to claim 1 or 2, wherein: The average value of the circularity of the plurality of holes in the first mother set consisting of holes having an area equivalent diameter equal to or greater than the area equivalent diameter D90 is greater than or equal to 0.2 and less than or equal to 0.46.

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