Display panel and electronic device

Abstract

A display panel and an electronic device, the display panel comprising: a substrate; and a plurality of pixels arranged in an array on the substrate, the plurality of pixels including a first pixel and a second pixel, the first pixel including a first light-transmitting region and a first display region arranged in sequence along a first direction, the second pixel including a second light-transmitting region and a second display region arranged in sequence along the first direction, the first pixel and the second pixel being adjacent in a second direction substantially perpendicular to the first direction, the first light-transmitting region and the second light-transmitting region being adjacent in the second direction; the display panel further comprising: a first gate line and a second gate line, disposed between the first light-transmitting region and the second light-transmitting region adjacent in the second direction, the first gate line and the second gate line both extending along the first direction, the first light-transmitting region being adjacent to the first gate line, and the second light-transmitting region being adjacent to the second gate line.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a display panel and an electronic device. Background Art

[0002] As a brand-new display technology, transparent display enables an observer to see the background behind the display screen through the display screen. This novel display effect broadens the application fields of the display, and thus has received extensive attention.

[0003] Disclosed content

[0004] Some embodiments of the present disclosure provide a display panel, including: a substrate; and a plurality of pixels arranged in an array on the substrate, the plurality of pixels including a first pixel and a second pixel. The first pixel includes a first light-transmitting region and a first display region arranged in sequence along a first direction, and the second pixel includes a second light-transmitting region and a second display region arranged in sequence along the first direction. The first pixel and the second pixel are adjacent in a second direction substantially perpendicular to the first direction, and the first light-transmitting region and the second light-transmitting region are adjacent in the second direction; the display panel further includes: a first gate line and a second gate line, disposed between the first light-transmitting region and the second light-transmitting region adjacent in the second direction, the first gate line and the second gate line both extending along the first direction, the first light-transmitting region being adjacent to the first gate line, and the second light-transmitting region being adjacent to the second gate line.

[0005] In some embodiments, the display panel further includes: a wiring region, disposed between the adjacent first light-transmitting region and second light-transmitting region, the length of the wiring region in the first direction, the length of the first light-transmitting region in the first direction, and the length of the second light-transmitting region in the first direction being equal, the wiring region being aligned with and adjacent to the adjacent first light-transmitting region and second light-transmitting region, and the first gate line and the second gate line both passing through the wiring region along the first direction.

[0006] In some embodiments, the display panel includes a planarization layer and a pixel definition layer sequentially disposed on the substrate, and the orthographic projection of the planarization layer on the substrate and the orthographic projection of the pixel definition layer on the substrate do not overlap with any of the orthographic projection of the first light-transmitting region on the substrate, the orthographic projection of the second light-transmitting region on the substrate, and the orthographic projection of the wiring region on the substrate.

[0007] In some embodiments, there is a gap between the first gate line and the second gate line. The display panel further includes a light-shielding layer extending in the first direction and located between the adjacent first light-transmitting region and the second light-transmitting region. The projection of the portion of the gap located in the routing region on the substrate falls within the orthographic projection of the light-shielding layer on the substrate.

[0008] In some embodiments, the first gate line and the second gate line are disposed on the same layer, and the light-shielding layer is located on a different layer from the first gate line and the second gate line.

[0009] In some embodiments, the light-shielding layer is located on the side of the first gate line and the second gate line facing the substrate.

[0010] In some embodiments, for the display panel, the width of the routing region in the second direction is greater than or equal to the width of the light-shielding layer in the second direction.

[0011] In some embodiments, the length of the light-shielding layer in the first direction is greater than or equal to the length of the routing region in the first direction.

[0012] In some embodiments, the orthographic projection of the light-shielding layer on the substrate does not overlap with the orthographic projection of the first light-transmitting region on the substrate and also does not overlap with the orthographic projection of the second light-transmitting region on the substrate.

[0013] In some embodiments, the material of the light-shielding layer is an opaque metal material.

[0014] In some embodiments, the display panel further includes: a gate insulating layer disposed on the side of the first gate line and the second gate line facing the substrate and located on the side of the light-shielding layer away from the substrate. In the routing region, the gate insulating layer includes a first portion and a second portion. The orthographic projection of the first portion on the substrate coincides with the orthographic projection of the first gate line on the substrate, and the orthographic projection of the second portion on the substrate coincides with the orthographic projection of the second gate line on the substrate.

[0015] In some embodiments, the display panel further includes: a second power supply line extending in the second direction. The second power supply line is configured to provide a constant voltage to the first pixel and the second pixel. The light-shielding layer is electrically connected to the second power supply line through a via hole.

[0016] In some embodiments, the light-shielding layer extends an extension portion in the second direction from the overlapping portion with the second power supply line. The orthographic projection of the via hole on the substrate falls within the orthographic projection of the extension portion on the substrate.

[0017] In some embodiments, the extension extends from the overlapping portion of the light-shielding layer and the second power line towards the first pixel.

[0018] In some embodiments, the extension extends from the overlapping portion of the light-shielding layer and the second power line towards the second pixel.

[0019] In some embodiments, the second power line provides a VSS voltage signal.

[0020] In some embodiments, the first pixel further includes a sub-pixel driving circuit located in a first display area, and the second pixel further includes a sub-pixel driving circuit located in a second display area. The first gate line is electrically connected to the sub-pixel driving circuit of the first pixel to provide a first control signal to the first pixel, and the second gate line is electrically connected to the sub-pixel driving circuit of the second pixel to provide a second control signal to the second pixel.

[0021] In some embodiments, the display panel is an OLED display panel.

[0022] Some embodiments of the present disclosure provide an electronic device, including the display panel described in the foregoing embodiments. Description of the Drawings

[0023] Other features, objects, and advantages of the present disclosure will become more apparent by reading the detailed description of the non-limiting embodiments with reference to the following drawings:

[0024] Figure 1 A plan view of a transparent display panel according to some embodiments of the present disclosure;

[0025] Figure 2 is Figure 1 An enlarged view of region A in

[0026] Figure 3 A cross-sectional structural view of a display area of a pixel according to some embodiments of the present disclosure;

[0027] Figure 4 is Figure 2 A cross-sectional structural view along line A-A in

[0028] Figure 5 is Figure 2 A cross-sectional structural view along line A-A in

[0029] Figure 6 A partial plan view of a transparent display panel provided according to some embodiments of the present disclosure;

[0030] Figure 7 is Figure 6 A cross-sectional structural view along line B-B in

[0031] Figure 8 is Figure 6 An enlarged schematic view of region B in

[0032] Figure 9 is Figure 8 A schematic cross-sectional structure view along line C-C in

[0033] Figure 10 A circuit diagram of a single sub-pixel according to some embodiments of the present disclosure;

[0034] Figure 11 A schematic plan view of a single pixel of a transparent display panel according to some embodiments of the present disclosure;

[0035] Figure 12 A schematic plan view of a single pixel of a transparent display panel after forming a pattern of a first metal layer during the manufacturing process according to some embodiments of the present disclosure;

[0036] Figure 13 is Figure 12 A schematic cross-sectional structure view along line A-A in

[0037] Figure 14 A schematic plan view of a single pixel of a transparent display panel after forming a pattern of an active material layer during the manufacturing process according to some embodiments of the present disclosure;

[0038] Figure 15 is Figure 14 A schematic cross-sectional structure view along line A-A in

[0039] Figure 16 A schematic plan view of a single pixel of a transparent display panel after forming a pattern of a second metal layer during the manufacturing process according to some embodiments of the present disclosure;

[0040] Figure 17 is Figure 16 A schematic cross-sectional structure view along line A-A in

[0041] Figure 18 A schematic plan view of a single pixel of a transparent display panel after forming a pattern of a third insulating layer during the manufacturing process according to some embodiments of the present disclosure;

[0042] Figure 19 is Figure 18 A schematic cross-sectional structure view along line A-A in

[0043] Figure 20 is Figure 11 A schematic cross-sectional structure view along line A-A in

[0044] Figure 21Schematic plan view of a single pixel after forming patterns of a fourth insulating layer and a planarization layer during the manufacturing process of a transparent display panel according to some embodiments of the present disclosure;

[0045] Figure 22 is Figure 21 schematic cross-sectional view along line A-A in

[0046] Figure 23 Schematic plan view of a single pixel after forming a pattern of an anode layer during the manufacturing process of a transparent display panel according to some embodiments of the present disclosure;

[0047] Figure 24 is Figure 23 schematic cross-sectional view along line A-A in

[0048] Figure 25 Schematic plan view of a single pixel after forming patterns of a pixel defining layer, a light-emitting material layer, a cathode, and a packaging layer during the manufacturing process of a transparent display panel according to some embodiments of the present disclosure;

[0049] Figure 26 is Figure 25 schematic cross-sectional view along line A-A in. Detailed Description of the Invention

[0050] The present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely for explaining the relevant invention and not for limiting the invention. Additionally, it should be noted that for the sake of description, only parts related to the invention are shown in the drawings.

[0051] It should be noted that, without conflict, the embodiments and features in the present disclosure can be combined with each other.

[0052] In addition, in the following detailed description, for the sake of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is obvious that one or more embodiments can be implemented without these specific details.

[0053] It should be understood that although the terms first, second, etc. can be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, the first element can be named the second element, and similarly, the second element can be named the first element. As used herein, the term "and / or" includes any combination and all combinations of one or more of the related listed items.

[0054] It should be understood that when an element or layer is referred to as being "formed on" another element or layer, the element or layer can be formed directly or indirectly on the other element or layer. That is, for example, there can be intermediate elements or intermediate layers. In contrast, when an element or layer is referred to as being "directly formed on" another element or layer, there are no intermediate elements or intermediate layers. Other words used to describe the relationship between elements or layers should be interpreted in a similar manner (e.g., "between" and "directly between", "adjacent" and "directly adjacent", etc.).

[0055] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the embodiments. As used herein, unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. It will also be understood that when the terms "comprises" and / or "comprising" are used herein, it indicates the presence of the stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0056] In this document, unless otherwise specified, the expressions "located in the same layer" and "arranged in the same layer" generally mean that: the first component and the second component can use the same material and can be formed by the same lithography process. The expressions "located in different layers" and "arranged in different layers" generally mean that: the first component and the second component are formed by different lithography processes.

[0057] In the following embodiments of this document, the transparent display panel is taken as an example of an OLED display panel. Those skilled in the art can understand that the transparent display panel can also be other types of display panels, such as a PLED display panel, a quantum dot display panel, etc.

[0058] Some embodiments of the present disclosure provide a display panel, specifically a transparent display panel. Figure 1 A plan view of a transparent display panel according to some embodiments of the present disclosure is shown, as Figure 1 shown, the transparent display panel 100 includes a substrate 10 and a plurality of pixels P arranged in an array on the substrate 10. The row direction of the pixel array is, for example, the first direction X, and the column direction is, for example, the second direction Y, and the first direction X and the second direction Y are perpendicular to each other.

[0059] Figure 2 For Figure 1 an enlarged schematic view of region A in Figure 2 only four pixels P are shown. As Figure 2As shown, each pixel P includes a light-transmitting area TA and a display area DA. The shapes and areas of the light-transmitting areas TA of the respective pixels P are the same. In each pixel P, the light-transmitting area TA and the display area DA are arranged side by side in the first direction. In the present embodiment, as Figure 2 shown, in each pixel P, the light-transmitting area TA and the display area DA are arranged left and right, and the light-transmitting area TA is located on the left side of the display area DA. Those skilled in the art can understand that in other embodiments, the light-transmitting area TA may be located on the right side of the display area DA. In some embodiments, in some pixels, the light-transmitting area TA may be located on the left side of the display area DA, and in other pixels, the light-transmitting area TA may be located on the right side of the display area DA.

[0060] As Figure 2 shown, a wiring area WA is provided between any two adjacent light-transmitting areas TA in the second direction Y. As a whole, a plurality of wiring areas WA are also arranged in an array on the substrate 10. Taking the wiring area WA (circled by a dotted line in Figure 2 ) provided between the first light-transmitting area TA1 of the first pixel P1 and the second light-transmitting area TA2 of the second pixel P2 as an example. The first pixel P1 includes a first light-transmitting area TA1 and a first display area DA1, the second pixel P2 includes a second light-transmitting area TA1 and a second display area DA2. The wiring area WA is located between the first light-transmitting area TA1 and the second light-transmitting area TA2, and is adjacent to both the first light-transmitting area TA1 and the second light-transmitting area TA2, that is, the edge of the wiring area WA far from the second light-transmitting area TA2 contacts the edge of the first light-transmitting area TA1 close to the second light-transmitting area TA2, and the edge of the wiring area WA far from the first light-transmitting area TA1 contacts the edge of the second light-transmitting area TA2 close to the first light-transmitting area TA1. The wiring area WA is aligned with both the first light-transmitting area TA1 and the second light-transmitting area TA2. That is to say, the wiring area WA is located between two display area columns adjacent to the first light-transmitting area TA1 and the second light-transmitting area TA2, where the two display area columns are respectively located on both sides of the first light-transmitting area TA1 and the second light-transmitting area TA2, and the width of the wiring area WA in the first direction is equal to the width of the first light-transmitting area TA1 in the first direction and the width of the second light-transmitting area TA2 in the first direction.

[0061] The transparent display panel 100 further includes a plurality of first gate lines GL1 and a plurality of second gate lines GL2. A first gate line GL1 and a second gate line GL2 are provided between any two adjacent light-transmitting regions TA in the second direction Y. Taking the first gate line GL1 and the second gate line GL2 disposed between the first light-transmitting region TA1 and the second light-transmitting region TA2 as an example, both the first gate line GL1 and the second gate line GL2 extend along the first direction and pass through the wiring region WA, and they are arranged substantially in parallel. There is a gap M between the first gate line GL1 and the second gate line GL2, and the width of the gap M is approximately 4 to 6 micrometers. As Figure 2 shown, the gap M also extends along the first direction X. The first gate line GL1 is used to drive the pixel P in the first light-transmitting region TA1, and the second gate line GL2 is used to drive the pixel P in the second light-transmitting region TA2.

[0062] Each pixel P corresponds to a first gate line GL1 and a second gate line GL2. When the distance d in the second direction Y between the first gate line G1 and the second gate line G2 corresponding to each pixel P is a predetermined value, the length of the light-transmitting region TA in the second direction is determined by the position of the boundary between the light-transmitting region TA and the adjacent wiring region WA. The smaller the width of the wiring region WA in the second direction Y, the larger the length of the light-transmitting region TA in the second direction Y.

[0063] Figure 3 shows a schematic cross-sectional structure of the display area of a pixel according to some embodiments of the present disclosure. As Figure 3 shown, in the display area DA of the pixel P, as Figure 3 shown, a first metal layer 20, a first insulating layer 30, an active material layer 40, a second insulating layer 50, a second metal layer 60, a third insulating layer 70, a third metal layer 80, a fourth insulating layer 90, a fifth insulating layer 110, a first electrode layer 120, a pixel defining layer 130, a light-emitting material layer 140, a second electrode layer 150, a packaging layer 160, a color filter layer CF, a black matrix layer BM, and a packaging cover plate 170 are sequentially disposed on the substrate 10. In some embodiments, the fourth insulating layer 90 can be omitted.

[0064] The substrate 10 and the encapsulation cover plate 170 are made of, for example, a glass material with good light-transmitting properties. The first insulating layer 30 is, for example, a buffer layer, which can also be referred to as the buffer layer 30 in this text. The second insulating layer 50 is, for example, a gate insulating layer, which can also be referred to as the gate insulating layer 50 in the text. The third insulating layer 70 is, for example, an interlayer dielectric layer, which can also be referred to as the interlayer dielectric layer 70 in this text. The fourth insulating layer 90 is, for example, a passivation layer, which can also be referred to as the passivation layer 90 in this text. The fifth insulating layer 110 is, for example, a planarization layer, which can also be referred to as the planarization layer 110 in this text. The planarization layer 110 is formed of an organic material such as resin, and the pixel defining layer 130 is also formed of an organic material. In some embodiments, since the planarization layer 110 itself has an insulating function, the passivation layer 90 may not be provided.

[0065] It can be understood that Figure 3 The cross-sectional layer structure of a single sub-pixel in the pixel display area is schematically shown, which is only used to show the layers in the display area and does not reflect the specific positions of the layers in the plan view.

[0066] As Figure 3 shown, a single sub-pixel includes a driving transistor DT. The first metal layer 20 includes a shielding layer 21. The active material layer 40 includes an active layer 41 of the driving transistor DT. The shielding layer can be used to shield the active layer 41 of the driving transistor DT to prevent external light from incident on the active layer 41 of the driving transistor DT, which may have an adverse effect on the display of the sub-pixel. For example, the projection of the active layer 41 of the driving transistor DT on the substrate is located within the projection of the shielding layer 21 on the substrate. For example, a single sub-pixel further includes a plurality of switching transistors. The projections of the active layers of the driving transistor and the switching transistors on the substrate are all located within the projection of the shielding layer 21 on the substrate, or the projections of the active layers of the driving transistor and the switching transistors on the substrate overlap with the projection of the shielding layer 21 on the substrate. The second metal layer 60 includes a gate 61 of the driving transistor DT. The third metal layer 80 includes a first pole 81 of the driving transistor DT, for example, a drain, and a second pole 82, for example, a source. The first electrode layer 120 is, for example, an anode layer, which is also referred to as the anode layer 120 in this text, and includes an anode of the light-emitting element D in the sub-pixel. The second electrode layer 150 is, for example, a cathode layer, which is also referred to as the cathode layer 150 in this text, and includes a cathode of the light-emitting element D in the sub-pixel. The encapsulation layer 160 may include a first inorganic layer 161, an organic layer 162, and a second inorganic layer 163 stacked on one side.

[0067] In some embodiments, the color filter layer CF and the black matrix BM may be pre-formed on the cover plate 170, and then the cover plate 170 with the color filter layer CF and the black matrix BM is aligned and bonded to the display substrate after the encapsulation layer 160 is formed on the substrate 10 to form the transparent display panel 100. In some alternative embodiments, the color filter layer CF may be disposed on the display substrate including the substrate 10, for example, directly on the encapsulation layer 160 or between the planarization layer 110 and the third metal layer 80. In some embodiments, the black matrix BM may also be replaced by stacked color filter layers CF of different colors.

[0068] In some embodiments, the light-emitting material layer 140 is formed over the entire surface by evaporation, as Figure 3 shown. For example, all the light-emitting elements D emit white light, and the color filter layer CF transmits different colors in corresponding different sub-pixel regions, thereby achieving color display.

[0069] In some embodiments, the light-emitting material layer 140 may be formed in the opening regions of the pixel defining layer 130 by printing. Light-emitting material layers 140 emitting different colors of light may be printed for different-color sub-pixels. In this case, the color filter layer CF may be omitted, and even the cover plate 170 and the black matrix may also be omitted.

[0070] In some embodiments, at least one of the first metal layer 20, the second metal layer 60, the third metal layer 80, the anode layer 120, the planarization layer 110, the pixel defining layer 130, the black matrix BM, and the color filter layer CF that is opaque or has poor light-transmitting effect is not disposed in the light-transmitting region TA. For example, none of the above layers is disposed in the light-transmitting region TA to ensure the transparency effect of the light-transmitting region TA.

[0071] Figure 4 For Figure 2 is a schematic cross-sectional structure diagram along line A-A in Figure 4 shown. In the light-transmitting region TA, a buffer layer 30, an interlayer defining layer 70, and a passivation layer 90 are sequentially stacked on the substrate 10. In the wiring region WA, a buffer layer 30, a gate insulating layer 50, a second metal layer 60, an interlayer defining layer 70, a passivation layer 90, a planarization layer 110, a pixel defining layer 130, and a black matrix BM are sequentially stacked on the substrate 10. The first gate line GL1 and the second gate line GL2 are located in the second metal layer 60. Those skilled in the art should understand that, in order to clearly show the relationship between the first gate line GL1 and the second gate line GL2 and the light-transmitting region TA and the wiring region WA, Figure 2The planarization layer 110, the pixel defining layer 130, and the black matrix BM are not shown. Those skilled in the art can understand that in some embodiments, in the manufacturing process of the transparent display panel, the cathode layer 150 and the encapsulation layer 160 entirely cover the substrate 10, that is, in the light-transmitting region TA, the cathode layer 150 and the encapsulation layer 160 provided on the passivation layer 90 are further included, and in the wiring region WA, the cathode layer 150 and the encapsulation layer 160 provided between the pixel defining layer 130 and the black matrix BM are further included. Figure 4 In order to highlight the difference in the layer structures in the light-transmitting region TA and the wiring region WA, the cathode layer 150 and the encapsulation layer 160 are omitted.

[0072] Combined Figure 3 with Figure 4 As shown, in some embodiments, in the light-transmitting region TA, the first metal layer 20, the second metal layer 60, the third metal layer 80, the anode layer 120, the planarization layer 110, the pixel defining layer 130, the black matrix BM, and the color filter layer CF that are opaque or have poor light-transmitting effects may not exist to ensure the transparency of the light-transmitting region TA. The materials of the first metal layer 20, the second metal layer 60, and the third metal layer 80 may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloy materials composed of the above metals. The anode layer 120 may adopt a reflective electrode, for example, it may be a stacked structure of aluminum (Al), ITO, and aluminum (Al). The planarization layer 110 and the pixel defining layer 130 are both organic material layers with relatively large thicknesses and poor light-transmitting performance. Compared with the light-transmitting region TA, in the wiring region WA, in addition to the first gate line GL1 and the second gate line GL2 arranged for wiring, the gate insulating layer 50, the planarization layer 110, the pixel defining layer 130, and the black matrix BM are further added.

[0073] The width of the wiring area WA is determined by the widths of the planarization layer 110, the pixel defining layer 130, and the black matrix BM in the wiring area WA. The widths of the planarization layer 110, the pixel defining layer 130, and the black matrix BM in the wiring area WA also determine the boundary between the wiring area WA and the light-transmitting area TA. Generally, the planarization layer 110, the pixel defining layer 130, and the black matrix BM in the wiring area WA need to completely cover the first gate line GL1 and the second gate line GL2 in the wiring area WA to prevent the first gate line GL1 and the second gate line GL2 from reflecting light. Due to the large process deviation in forming the pixel defining layer 130, generally, the end of the pixel defining layer 130 formed in the wiring area WA near the first light-transmitting area TA1 is closer to the first light-transmitting area TA1 than the end of the first gate line GL1 in the wiring area WA near the first light-transmitting area TA1, and the end of the pixel defining layer 130 in the wiring area WA near the second light-transmitting area TA2 is closer to the second light-transmitting area TA2 than the end of the second gate line GL2 in the wiring area WA near the second light-transmitting area TA2. It can be considered that the width of the wiring area WA is determined by the width of the pixel defining layer 130 in the wiring area W.

[0074] As Figure 4 shown, the boundary between the wiring area WA and the first light-transmitting area TA1 is determined by the position of the end of the pixel defining layer 130 in the wiring area WA near the first light-transmitting area TA1, and the boundary between the wiring area W and the second light-transmitting area TA2 is determined by the position of the end of the pixel defining layer 130 in the wiring area WA near the second light-transmitting area TA2. That is, the orthographic projection of the first light-transmitting area TA1 on the substrate 10 is adjacent to the orthographic projection of the pixel defining layer 130 in the wiring area WA on the substrate 10, and the orthographic projection of the second light-transmitting area TA2 on the substrate 10 is adjacent to the orthographic projection of the pixel defining layer 130 in the wiring area WA on the substrate 10.

[0075] As Figure 4 shown, within the wiring area WA, the orthographic projection of the gate insulating layer 60 on the substrate 10 substantially coincides with the orthographic projection of the combination of the first gate line GL1 and the second gate line GL2 on the substrate 10. That is to say, the gate insulating layer 60 includes a first part and a second part. The orthographic projection of the first part on the substrate coincides with the orthographic projection of the first gate line GL1 on the substrate 10, and the orthographic projection of the second part on the substrate coincides with the orthographic projection of the second gate line GL2 on the substrate 10. During the manufacturing process of the transparent display panel 100, the second electrode layer 60 including the first gate line GL1 and the second gate line GL2 and the gate insulating layer 50 can be formed using the same mask, and they have the same profile, thereby reducing the number of mask plates.

[0076] To increase the area of the light-transmitting region TA and enable the light-transmitting display panel 100 to have a better light-transmitting effect, in some embodiments of the present disclosure, on the basis of the structure shown in Figure 4 , the planarization layer 110, the pixel definition layer 130, and the black matrix BM are removed. As shown in Figure 5 , no planarization layer 110, pixel definition layer 130, and black matrix BM are provided in the wiring region WA. As a result, the width of the wiring region WA is reduced, and thus the light-transmitting region TA is increased. The boundary between the wiring region WA and the first light-transmitting region TA1 is determined by the position of the end of the first gate line GL1 in the wiring region WA close to the first light-transmitting region TA1, and the boundary between the wiring region WA and the second light-transmitting region TA2 is determined by the position of the end of the second gate line GL2 in the wiring region WA close to the second light-transmitting region TA2. That is, the orthographic projection of the first light-transmitting region TA1 on the substrate 10 is adjacent to the orthographic projection of the first gate line GL1 in the wiring region WA on the substrate 10, and the orthographic projection of the second light-transmitting region TA2 on the substrate 10 is adjacent to the orthographic projection of the second gate line GL2 in the wiring region WA on the substrate 10. In some embodiments, the width of the wiring region W in the second direction Y is about 1 / 10 of the length of the first light-transmitting region TA1 in the second direction Y.

[0077] In some embodiments, when no planarization layer 110, pixel definition layer 130, and black matrix BM are provided in the wiring region WA, in order to overcome the problem of light reflection of the first gate line GL1 and the second gate line GL2 in the wiring region WA, an anti-reflection film can be attached to the light-emitting surface of the light-transmitting display panel 100.

[0078] The applicant found that in the structure shown in Figure 5 , since there is a gap M between the first gate line GL1 and the second gate line GL2, and the planarization layer 110, the pixel definition layer 130, and the black matrix BM are removed from the wiring region WA, the gap M between the first gate line GL1 and the second gate line GL2 may cause slit diffraction, affecting the display effect.

[0079] It should be noted that in the above exemplary structure, the black matrix BM is not an essential structure and can be set according to actual light-shielding requirements. In some embodiments, the above display panel 100 may not include the black matrix BM.

[0080] Based on this, on the basis of the structure shown in Figure 5 , in some embodiments of the present disclosure, a light-shielding layer is provided to shield the gap M between the first gate line GL1 and the second gate line GL2. Figure 6 FIG. is a partial plan view of a transparent display panel provided according to some embodiments of the present disclosure. Figure 7 is Figure 6 a cross-sectional structure diagram taken along line B-B in FIG.

[0081] As Figure 6 shown in FIG. 7, compared with the structure shown in Figure 5 , a light-shielding layer 22 is added to the display panel 100 in this embodiment to shield the gap M between the first gate line GL1 and the second gate line GL2 in the wiring region W. The light-shielding layer 22 is located on the side of the first gate line GL1 and the second gate line GL2 facing the substrate 10, and the light-shielding layer 22 can be formed by the first metal layer 20, that is, it is provided on the same layer as the shielding layer 21 in the display area DA. In other embodiments, the light-shielding layer can also be formed by other layers, as long as the light-shielding layer 22 can shield the gap M between the first gate line GL1 and the second gate line GL2 in the wiring region W. For example, the light-shielding layer can be formed by the third metal layer 80, and at this time, the light-shielding layer is provided on the same layer as the source and drain electrodes of the transistor. For example, the light-shielding layer is formed by the first electrode layer 120, and at this time, the light-shielding layer is provided on the same layer as the anode of the light-emitting element. In some embodiments, the light-shielding layer can be made of a metal material or a non-metal material, as long as the light-shielding layer is made of a light-shielding material.

[0082] As Figure 6 shown in FIG. 7, the light-shielding layer 22 extends along the first direction X, and its length in the first direction X is greater than or equal to the length of the wiring region WA in the first direction X, and its width in the second direction Y is smaller than the width of the wiring region WA in the second direction Y. In this embodiment, the length of the light-shielding layer 22 in the first direction X is slightly greater than the length of the wiring region WA in the first direction X, and its width in the second direction Y is equal to the width of the wiring region WA in the second direction Y. As Figure 6 shown, the light-shielding layers 22 corresponding to adjacent pixels P in the same row are disconnected in this embodiment. In other embodiments, the light-shielding layer 22 can also continuously extend along the first direction through multiple pixel columns.

[0083] As Figure 6 shown in FIG. 7, the orthographic projection of the light-shielding layer 22 on the substrate 10 does not overlap with the orthographic projections of the first light-transmitting region TA1 and the second light-transmitting region TA2 on the substrate. For example, the orthographic projection of the light-shielding layer 22 on the substrate 22 is adjacent to the orthographic projections of the first light-transmitting region TA1 and the second light-transmitting region TA2 on the substrate. For another example, the end of the light-shielding layer 22 close to the first light-transmitting region TA1 is farther from the first light-transmitting region TA1 than the end of the first gate line GL1 in the wiring region W close to the first light-transmitting region TA1, and the end of the light-shielding layer 22 close to the second light-transmitting region TA2 is farther from the second light-transmitting region TA2 than the end of the second gate line GL2 in the wiring region WA close to the second light-transmitting region TA2.

[0084] The width of the light-shielding layer 22 in the second direction Y is not specifically limited, as long as it can shield the gap M between the first gate line GL1 and the second gate line GL2 in the wiring area WA. That is, the positive projection of the part of the gap M in the wiring area WA on the substrate 10 falls within the positive projection of the light-shielding layer 22 on the substrate.

[0085] In some embodiments, Figure 8 shows Figure 6 an enlarged schematic view of area B in Figure 8 mainly showing the specific structure of a pixel P. As Figure 8 shown, the transparent display panel 100 further includes a second power supply line VSSL, which extends along the second direction Y and is configured to provide a constant voltage, such as the VSS voltage, to the pixel P. Specifically, the second power supply line VSSL is located in the third metal layer 80 and is configured to be electrically connected to the cathode of the light-emitting element D of the pixel P. As Figure 8 shown, taking the pixel P where the first light-transmitting area TA1 is located as an example. The second power supply line VSSL is located at the edge of the display area DA of the pixel P close to the first light-transmitting area TA1.

[0086] Figure 9 is Figure 8 a cross-sectional structure schematic view along line C-C in Figure 8 and 9 shown. In order to prevent the light-shielding layer 22 from being in a floating state and causing crosstalk to the signals on the first gate line GL1 and the second gate line GL2, the light-shielding layer 22 can be electrically connected to the second power supply line VSSL to access a constant VSS voltage. Specifically, the light-shielding layer 22 extends along the first direction X and overlaps with the second power supply line VSSL, and an extension portion 221 extends from the overlapping portion along the second direction. The extension portion 221 is electrically connected to the second power supply line VSSL through a via 31. The positive projection of the via 31 on the substrate 10 falls within the positive projection of the extension portion 221 on the substrate 10.

[0087] Although Figure 8 , Figure 9 shows that the extension portion 221 extends from the overlapping portion of the light-shielding layer 22 and the second power supply line VSSL towards the pixel where the first light-transmitting area TA1 is located. Those skilled in the art can understand that in other embodiments, the extension portion 221 can also extend from the overlapping portion of the light-shielding layer 22 and the second power supply line VSSL towards the pixel where the second light-transmitting area TA2 is located.

[0088] Those skilled in the art can understand that the extension portion 221 is not necessary. In some embodiments, the extension portion can be not provided, and the light-shielding layer 22 is in a floating state.

[0089] Figure 8The schematic plan view of the display area of a single pixel according to some embodiments of the present disclosure is shown. As Figure 8 shown, the display area DA of the pixel P includes four sub-pixels, namely a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. The four sub-pixels can be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel respectively. Those skilled in the art can understand that each sub-pixel includes a sub-pixel driving circuit and a light-emitting element D located on the sub-pixel driving circuit, and the light-emitting elements of the four sub-pixels can be adjusted in shape and arrangement according to actual needs, as long as it is ensured that the sub-pixel driving circuit of each sub-pixel can drive its corresponding light-emitting element D. In the art, the pixel defining layer is used to define the position and shape of the light-emitting area of the light-emitting element, and the light-emitting material layer of the light-emitting element is disposed in the opening of the pixel defining layer. The position and shape of the opening of the pixel defining layer can be adjusted according to actual needs to adjust the position and shape of the light-emitting material layer of the organic light-emitting element.

[0090] To clearly show the structure and positional relationship of each sub-pixel, Figure 8 the light-emitting elements of each sub-pixel and the pixel defining layer surrounding each light-emitting element are not shown. The sub-pixel driving circuits of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are mainly shown, that is, the first sub-pixel driving circuit SPCI, the second sub-pixel driving circuit SPC2, the third sub-pixel driving circuit SPC3, and the fourth sub-pixel driving circuit SPC4. As Figure 4 shown, the first sub-pixel driving circuit SPC1, the second sub-pixel driving circuit SPC2, the third sub-pixel driving circuit SPC3, and the fourth sub-pixel driving circuit SPC4 all extend along the second direction Y and are arranged side by side in sequence along the first direction X in the pixel P. The first sub-pixel driving circuit SPC1, the second sub-pixel driving circuit SPC2, the third sub-pixel driving circuit SPC3, and the fourth sub-pixel driving circuit SPC4 constitute the pixel driving circuit of the pixel P. Thus, Figure 8 can also be used as the schematic structural view of the pixel driving circuit of a single pixel according to some embodiments of the present disclosure. In this embodiment, the first sub-pixel driving circuit SPCI, the second sub-pixel driving circuit SPC2, the third sub-pixel driving circuit SPC3, and the fourth sub-pixel driving circuit SPC4 are arranged away from the light-transmitting area TA of the pixel P in sequence.

[0091] In this embodiment, a pixel structure with four sub-pixels is used as an example for illustration. Those skilled in the art can understand that in other embodiments, a single pixel can have other numbers of sub-pixels, such as three, namely a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0092] Figure 10The following is a circuit diagram of a single sub-pixel according to an embodiment of the present disclosure. In combination with Figure 8 and Figure 10 the single pixel P in the embodiment of the present disclosure will be explained.

[0093] As Figure 4 shown, each pixel P corresponds to a first gate line GL1, a second gate line GL2, a first power supply line VDDL, a second power supply line VSSL, a detection line SL, and four data lines DL. As Figure 5 shown, each of the first sub-pixel driving circuit SPC1, the second sub-pixel driving circuit SPC2, the third sub-pixel driving circuit SPC3, and the fourth sub-pixel driving circuit SPC4 includes a first transistor T1 (also referred to as a switching transistor T1), a second transistor T2 (also referred to as a driving transistor T2), and a third transistor T3 (also referred to as a detection transistor T1), and a storage capacitor Cst. The first gate line GL1 provides a first control signal G1 for each sub-pixel driving circuit, the second gate line GL2 provides a second control signal G2 for each sub-pixel, the first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4 respectively provide data signals Data for the first sub-pixel driving circuit SPC1, the second sub-pixel driving circuit SPC2, the third sub-pixel driving circuit SPC3, and the fourth sub-pixel driving circuit SPC4. The first power supply line VDDL provides a constant first voltage signal for each sub-pixel driving circuit, for example, a VDD voltage signal, and the second power supply line VSSL provides a constant second voltage signal for each sub-pixel driving circuit, for example, a VSS voltage signal. The detection line SL is used to provide a reset signal to each pixel driving circuit and is used to sample and detect the electrical characteristics of each sub-pixel driving circuit, such as the threshold voltage of the second transistor T2, to achieve external compensation and obtain a better display effect.

[0094] Specifically, each sub-pixel driving circuit includes a switching transistor T1, a driving transistor T2, a detection transistor T3, and a storage capacitor Cst. Among them, the driving transistor T2 is the Figure 3 driving transistor DT in. The gate of the switching transistor T1 receives the first control signal G1 provided by the first gate line GL1. The first pole of the switching transistor T1, for example, the drain, receives the data signal Data provided by the data line DL. The second pole of the switching transistor T1, for example, the source, is electrically connected to the second capacitor electrode CstE2 of the storage capacitor Cst and the gate of the driving transistor T2. The three are electrically connected at the first node G. The switching transistor T1 is configured to write the data signal Data into the gate of the driving transistor T2 and the storage capacitor Cst in response to the first control signal G1.

[0095] The first pole of the driving transistor T2, for example, the drain, is electrically connected to the first power supply line VDDL through the first power supply connection line VDDLS, receives the first voltage signal provided by the first power supply line VDDL, for example, the VDD voltage signal, and the second pole of the driving transistor T2, for example, the source, is electrically connected to the first capacitive electrode CstE1 of the storage capacitor Cst and is configured to be electrically connected to the anode of the light-emitting element D. The driving transistor T2 is configured to control the current for driving the light-emitting element D under the control of the voltage of the gate of the driving transistor T2.

[0096] The gate of the detection transistor T3 receives the second control signal G2 provided by the second gate line GL2. The first pole of the detection transistor T3, for example, the source, is electrically connected to the second pole of the driving transistor T2 and the second capacitive electrode CstE2 of the storage capacitor Cst, and the three are electrically connected at the second node S. The second pole of the detection transistor T3, for example, the drain, is electrically connected to the detection line SL through the detection connection line SLS, obtains the reset signal from the detection line SL, and provides the sampling detection signal SEN to the detection line SL. The detection transistor T3 is configured to detect the electrical characteristics of the sub-pixel driving circuit to which it belongs in response to the second control signal G2 to achieve external compensation; the electrical characteristics include, for example, the threshold voltage and / or carrier mobility of the switching transistor T1, or the threshold voltage, driving current, etc. of the light-emitting element.

[0097] The anode of the light-emitting element D is electrically connected to the second pole of the driving transistor T2, for example, the source, and the cathode of the light-emitting element D is electrically connected to the second power supply line VSSL, for example, through a via, to access the VSS voltage signal. The light-emitting element D emits light based on the current flowing through it, and the light-emitting intensity is determined by the intensity of the current flowing through the light-emitting element D.

[0098] In some embodiments, the storage capacitor Cst may include a third capacitive electrode CstE3 electrically connected to the first capacitive electrode CstE1. The first capacitive electrode CstE1, the second capacitive electrode CstE2, and the third capacitive electrode CstE2 are sequentially stacked on the substrate 10. The first capacitive electrode CstE1 and the second capacitive electrode CstE2 have an overlapping region, and the first capacitive electrode CstE1 and the second capacitive electrode CstE2 form the first capacitor. The third capacitive electrode CstE3 and the second capacitive electrode CstE2 have an overlapping region, and the third capacitive electrode CstE3 and the second capacitive electrode CstE2 form the second capacitor. The storage capacitor Cst can be regarded as the parallel connection of the first capacitor and the second capacitor, thereby increasing the capacitance of the storage capacitor Cst.

[0099] In the embodiments of the present disclosure, the transistors employed can all be thin-film transistors or field-effect transistors or other switching devices with the same characteristics. In the embodiments of the present disclosure, thin-film transistors are taken as examples for illustration. The source and drain of the transistors adopted here can be symmetric in structure, so there can be no difference between the source and drain in structure. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one of the poles is directly described as the first pole and the other as the second pole. In addition, according to the characteristics of the transistors, the transistors can be classified into N-type and P-type transistors. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other appropriate voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other appropriate voltages); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (for example, 5V, 10V or other appropriate voltages), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other appropriate voltages). It should be noted that in the descriptions herein, N-type transistors are taken as examples for illustration, but this does not limit the present disclosure.

[0100] In the following embodiments, Figure 8 the pixel structure shown is taken as an example to introduce in detail the single-pixel structure and the pixel driving circuit of a single pixel in the transparent display panel.

[0101] Figure 11 shows a schematic plan view of the display area of a single pixel according to some embodiments of the present disclosure. Figure 11 can be considered as Figure 8 a more refined schematic diagram of the pixel structure in Figure 11 As shown, the display area DA of pixel P includes four sub-pixels, namely a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. The four sub-pixels can be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel respectively. Those skilled in the art can understand that each sub-pixel includes a sub-pixel driving circuit and a light-emitting element D located on the sub-pixel driving circuit, and the light-emitting elements of the four sub-pixels can be adjusted in shape and arrangement according to actual needs, as long as the sub-pixel driving circuit of each sub-pixel can drive its corresponding light-emitting element D. In the art, the pixel defining layer is used to define the position and shape of the light-emitting area of the light-emitting element, and the light-emitting material layer of the light-emitting element is disposed in the opening of the pixel defining layer. The position and shape of the opening of the pixel defining layer can be adjusted according to actual needs to adjust the position and shape of the light-emitting material layer of the organic light-emitting element.

[0102] To clearly show the structure and positional relationship of each sub-pixel, Figure 11The light-emitting elements of each sub-pixel and the pixel defining layer surrounding each light-emitting element are not shown. The sub-pixel driving circuits of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are mainly shown, that is, the first sub-pixel driving circuit SPCI, the second sub-pixel driving circuit SPC2, the third sub-pixel driving circuit SPC3, and the fourth sub-pixel driving circuit SPC4, as Figure 15 shown, the first sub-pixel driving circuit SPCI, the second sub-pixel driving circuit SPC2, the third sub-pixel driving circuit SPC3, and the fourth sub-pixel driving circuit SPC4 all extend along the second direction Y, and are arranged side by side in sequence along the first direction X in the pixel P. The first sub-pixel driving circuit SPCI, the second sub-pixel driving circuit SPC2, the third sub-pixel driving circuit SPC3, and the fourth sub-pixel driving circuit SPC4 constitute the pixel driving circuit of the pixel P. Thus, it can also be Figure 11 used as a schematic structural diagram of the pixel driving circuit of a single pixel according to some embodiments of the present disclosure. In this embodiment, the first sub-pixel driving circuit SPCI, the second sub-pixel driving circuit SPC2, the third sub-pixel driving circuit SPC3, and the fourth sub-pixel driving circuit SPC4 are arranged away from the light-transmitting region TA of the pixel P in sequence.

[0103] In this embodiment, a pixel structure with four sub-pixels is used as an example for illustration. Those skilled in the art can understand that in other embodiments, a single pixel can have other numbers of sub-pixels, for example, three, namely a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0104] Figure 10 is a circuit diagram of a single sub-pixel according to an embodiment of the present disclosure. The following will be combined with Figure 11 and Figure 10 to explain a single pixel P in the embodiments of the present disclosure.

[0105] As Figure 11 shown, each pixel P corresponds to a first gate line GL1, a second gate line GL2, a first power supply line VDDL, a second power supply line VSSL, a detection line SL, and four data lines DL. As Figure 10As shown, each of the first sub-pixel driving circuit SPCI, the second sub-pixel driving circuit SPC2, the third sub-pixel driving circuit SPC3, and the fourth sub-pixel driving circuit SPC4 includes a first transistor T1 (also referred to as a switching transistor T1), a second transistor T2 (also referred to as a driving transistor T2), and a third transistor T3 (also referred to as a detecting transistor T3), as well as a storage capacitor Cst. The first gate line GL1 provides a first control signal G1 for each sub-pixel driving circuit, the second gate line GL2 provides a second control signal G2 for each sub-pixel, the first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4 provide data signals Data for the first sub-pixel driving circuit SPC1, the second sub-pixel driving circuit SPC2, the third sub-pixel driving circuit SPC3, and the fourth sub-pixel driving circuit SPC4 respectively, the first power supply line VDDL provides a constant first voltage signal for each sub-pixel driving circuit, such as a VDD voltage signal, and the second power supply line VSSL provides a constant second voltage signal for each sub-pixel driving circuit, such as a VSS voltage signal. The detection line SL is used to provide a reset signal to each pixel driving circuit and is used to sample and detect the electrical characteristics of each sub-pixel driving circuit, such as the threshold voltage of the second transistor T2, so as to achieve external compensation and obtain a better display effect.

[0106] Specifically, each sub-pixel driving circuit includes a switching transistor T1, a driving transistor T2, a detecting transistor T3, and a storage capacitor Cst. Among them, the driving transistor T2 is the Figure 3 driving transistor DT in. The gate of the switching transistor T1 receives the first control signal G1 provided by the first gate line GL1. The first pole of the switching transistor T1, such as the drain, receives the data signal Data provided by the data line DL. The second pole of the switching transistor T1, such as the source, is electrically connected to the first capacitor electrode CstE1 of the storage capacitor Cst and the gate of the driving transistor T2, and the three are electrically connected at the first node G. The switching transistor T1 is configured to write the data signal Data into the gate of the driving transistor T2 and the storage capacitor Cst in response to the first control signal G1.

[0107] The first pole of the driving transistor T2, such as the drain, is electrically connected to the first power supply connection line VDDLS and the first power supply line VDDL, and receives the first voltage signal provided by the first power supply line VDDL, such as a VDD voltage signal. The second pole of the driving transistor T2, such as the source, is electrically connected to the second capacitor electrode CstE2 of the storage capacitor Cst and is configured to be electrically connected to the anode of the light-emitting element D. The driving transistor T2 is configured to control the current for driving the light-emitting element D under the control of the voltage of the gate of the driving transistor T2.

[0108] The gate of the detection transistor T3 receives a second control signal G2 provided by the second gate line GL2. The first pole of the detection transistor T3, for example, the source, is electrically connected to the second pole of the driving transistor T2 and the second capacitive electrode CstE2 of the storage capacitor Cst. The three are electrically connected at the second node S. The second pole of the detection transistor T3, for example, the drain, is electrically connected to the detection line SL through the detection connection line SLS. A reset signal is obtained from the detection line SL, and a sampled detection signal SEN is provided to the detection line SL. The detection transistor T3 is configured to detect the electrical characteristics of the sub-pixel driving circuit to which it belongs in response to the second control signal G2 to achieve external compensation; the electrical characteristics include, for example, the threshold voltage and / or carrier mobility of the switching transistor T1, or the threshold voltage, driving current, etc. of the light-emitting element.

[0109] The anode of the light-emitting element D is electrically connected to the second pole of the driving transistor T2, for example, the source. The cathode of the light-emitting element D is electrically connected to the second power supply line VSSL, for example, through a via, to access the VSS voltage signal. The light-emitting element D emits light based on the current flowing through it, and the light-emitting intensity is determined by the current intensity flowing through the light-emitting element D.

[0110] In some embodiments, the storage capacitor Cst may include a third capacitive electrode CstE3 electrically connected to the first capacitive electrode CstE1. The first capacitive electrode CstE1, the second capacitive electrode CstE2, and the third capacitive electrode CstE2 are sequentially stacked on the substrate 10. The first capacitive electrode CstE1 and the second capacitive electrode CstE2 have an overlapping region, and the first capacitive electrode CstE1 and the second capacitive electrode CstE2 form a first capacitor. The third capacitive electrode CstE3 and the second capacitive electrode CstE2 have an overlapping region, and the third capacitive electrode CstE3 and the second capacitive electrode CstE2 form a second capacitor. The storage capacitor Cst can be regarded as the parallel connection of the first capacitor and the second capacitor, thereby increasing the capacitance of the storage capacitor Cst.

[0111] As Figure 11 shown, within the region corresponding to a single pixel P, that is, between the two ends of a single pixel in the first direction X, both the first gate line GL1 and the second gate line GL2 extend along the first direction X, for example, in a straight line shape. The first gate line GL1 and the second gate line GL2 are respectively disposed on both sides of the light-transmitting region TA, that is, the light-transmitting region TA is sandwiched between the first gate line GL1 and the second gate line GL2. In other embodiments, the first gate line GL1 and the second gate line GL2 may also pass through the light-transmitting region TA. Within the region corresponding to a single pixel P, that is Figure 11Within the range shown, the first power supply line VDDL, the second power supply line VSSL, the detection line SL, and the four data lines DL all extend along the second direction Y, for example, in a straight line. Specifically, the detection line SL is located between the second sub-pixel driving circuit SPC2 and the third sub-pixel driving circuit SPC3. The first data line DL1 and the second data line DL2 are arranged between the first sub-pixel driving circuit SPCI and the second sub-pixel driving circuit SPC2. The first data line DL1 is closer to the first sub-pixel driving circuit SPCI than the second data line DL2, and the second data line DL2 is closer to the second sub-pixel driving circuit SPC2 than the first data line DL1. That is, the first data line DL1 is located between the first sub-pixel driving circuit SPCI and the second data line DL2, and the second data line DL2 is located between the first data line DL1 and the second sub-pixel driving circuit SPC2. The third data line DL3 and the fourth data line DL4 are arranged between the third sub-pixel driving circuit SPC3 and the fourth sub-pixel driving circuit SPC4. The third data line DL3 is closer to the third sub-pixel driving circuit SPC3 than the fourth data line DL4, and the fourth data line DL4 is closer to the fourth sub-pixel driving circuit SPC4 than the third data line DL3. That is, the third data line DL3 is located between the third sub-pixel driving circuit SPC3 and the fourth data line DL4, and the fourth data line DL4 is located between the third data line DL3 and the fourth sub-pixel driving circuit SPC4. The second power supply line VSSL is located on the side of the first sub-pixel driving circuit SPCI away from the first data line DL1, that is, between the light-transmitting area TA and the first sub-pixel driving circuit SPCI. The first power supply line VDDL is located on the side of the fourth sub-pixel driving circuit SPC4 away from the fourth data line DL4. In this embodiment, the structure of the first sub-pixel driving circuit SPCI and the structure of the fourth sub-pixel driving circuit SPC4 are approximately mirror-symmetrical with respect to the position of the detection line SL, and the structure of the second sub-pixel driving circuit SPC2 and the structure of the third sub-pixel driving circuit SPC3 are approximately mirror-symmetrical with respect to the position of the detection line SL.

[0112] It should be noted that the mirror symmetry in the present disclosure means that the positional relationships of the respective structures, such as the left-right positional relationship, are approximately symmetrical. For example, for the structures of two sub-pixels that are approximately mirror-symmetrical, in one sub-pixel, the A structure is on the left side of the B structure, and in the other sub-pixel, the A structure is on the right side of the B structure. For example, the mirror symmetry can also mean that the shapes, sizes, or orientations of the respective structures are approximately symmetrical with respect to a certain straight line (such as a row direction line or a column direction line). For example, for the structures of two sub-pixels that are approximately mirror-symmetrical, in one sub-pixel, the A' structure protrudes to the left side, and in the other sub-pixel, the corresponding A' structure protrudes to the right side. The corresponding A' structure can be a pattern in the same layer as the A structure and having the same function as the A structure.

[0113] Figures 11 to 26 This is a schematic diagram illustrating the display panel fabrication process in some embodiments of the present disclosure, showing the structure of a single pixel P in a transparent display panel. This embodiment uses a top-emission OLED display panel as an example. A single pixel P includes a display area DA and a light-transmitting area TA. Within the display area DA are disposed a first subpixel driver circuit SPCI, a second subpixel driver circuit SPC2, a third subpixel driver circuit SPC3, and a fourth subpixel driver circuit SPC4, arranged sequentially away from the light-transmitting area TA. Each subpixel's driver circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst.

[0114] Figure 12 FIG2 is a schematic diagram of a planar structure of a single pixel after a pattern of a first metal layer is formed in a manufacturing process of a transparent display panel according to some embodiments of the present disclosure. Figure 13 for Figure 12 Schematic diagram of the cross-section structure along line AA (it should be noted that Figure 12 The section position indicated by line AA in FIG is consistent with the section position indicated by line AA in subsequent drawings). Figure 12 and 13 As shown, a pattern of a first metal layer 20 is first formed on a base substrate. Specifically, a first metal film is deposited on a base substrate 10 and patterned using a patterning process to form a pattern of the first metal layer 20 on the base substrate 10. The pattern of the first metal layer 20 includes a shielding layer 21 and a detection connection line SLS. Each sub-pixel driving circuit includes a shielding layer 21. The detection connection line SLS is a strip-shaped structure that spans four sub-pixel driving circuits and extends along a first direction X. The detection connection line SLS is configured to connect to a subsequently formed detection line SL, so that the detection line SL provides a reset signal to each sub-pixel driving circuit and is used to sample and detect the electrical characteristics of each sub-pixel driving circuit, such as the threshold voltage of the second transistor T2, to achieve external compensation. In some embodiments, the shielding layer 21 is an elongated rectangular strip and extends along a second direction Y. The shielding layer 21 is configured to shield the channels of each subsequently formed transistor, reducing the intensity of light impinging on the transistor, reducing leakage current, and thereby reducing the impact of light on transistor characteristics. At least the middle portion of the shielding layer 21 (circled by the dotted box) serves as a capacitor electrode of the first capacitor, namely the first capacitor electrode CstE1, which is configured to form a first capacitor with the second capacitor electrode CstE2 formed subsequently. In the second direction Y, the length of the shielding layer 21 is greater than the distance between the gate of the switching transistor T1 formed subsequently and the gate of the detection transistor T3. In some embodiments, the length of the shielding layer 21 is greater than the distance between the drain of the switching transistor T1 formed subsequently and the drain of the third transistor T3. Combined Figure 11 andFigure 12 As shown, the pattern of the first metal layer 20 in the first sub-pixel driving circuit SPCI and the pattern of the first metal layer 20 in the fourth sub-pixel driving circuit SPC4 are mirror-symmetrical with respect to the subsequently formed detection line SL. The pattern of the first metal layer 20 in the second sub-pixel driving circuit SPC2 and the pattern of the first metal layer 20 in the third sub-pixel driving circuit SPC3 are substantially mirror-symmetrical with respect to the position of the subsequently formed detection line SL. After this lithography process, the shielding layer 21 and the detection connection line SLS are formed in the display area DA, and the first metal layer is not provided in the light-transmitting area TA.

[0115] Figure 14 It is a schematic plan view of a single pixel after forming a pattern of an active material layer during the manufacturing process of a transparent display panel according to some embodiments of the present disclosure. Figure 15 is Figure 14 a schematic cross-sectional structure view along line A-A in Figure 14 、 15 As shown, a pattern of the active material layer 40 is formed. Specifically, on the substrate 10 having the aforementioned pattern formed thereon, a first insulating film and an active material film, such as a metal oxide film, are sequentially deposited, and the active material film is patterned through a lithography process to form a first insulating layer 30 covering the pattern of the first metal layer 20, and a pattern of the active material layer 40 formed on the first insulating layer 30. The active material layer 40 includes an active layer (also referred to as the first active layer T1a) of the switching transistor T1 provided in each sub-pixel driving circuit, an active layer (also referred to as the second active layer T2a) of the driving transistor T2, an active layer (also referred to as the third active layer T3a) of the detection transistor T3, and a second capacitor electrode CstE2. There is an overlapping area between the orthographic projection of the second capacitor electrode CstE2 on the substrate 10 and the orthographic projection of the first capacitor electrode CstE1 on the substrate 10, and the first capacitor electrode CstE1 and the second capacitor electrode CstE2 form a first capacitor.

[0116] In some embodiments, the orthographic projections of the first active layer T1a, the second active layer T2a, and the third active layer T3a on the substrate 10 and the orthographic projection of the shielding layer 21 on the substrate 10 have an overlapping area, such that the shielding layer 21 can shield the channel regions of the switching transistor T1, the driving transistor T2, and the detection transistor T3, preventing light from affecting the channels and thus avoiding the channel from affecting the display effect due to the generation of photocurrent leakage. Any two of the first active layer T1a, the second active layer T2a, the third active layer T3a, and the second capacitor electrode CstE2 are spaced apart, that is, there is no overlapping area between any two of the orthographic projection of the first active layer T1a on the substrate 10, the orthographic projection of the second active layer T2a on the substrate 10, the orthographic projection of the third active layer T3a on the substrate 10, and the orthographic projection of the second capacitor electrode CstE2 on the substrate 10, which is beneficial for designing the channel width-to-length ratios of the switching transistor T1, the driving transistor T2, and the detection transistor T3 according to relevant requirements. In some embodiments, as Figure 14 and 15 shown, there is a spaced area 42 between the second capacitor electrode CstE2 and the third active layer T3a in the first sub-pixel driving circuit SPC1 and the fourth sub-pixel driving circuit SPC4, and there is also a space between the second capacitor electrode CstE2 and the third active layer T3a in the second sub-pixel driving circuit SPC2 and the third sub-pixel driving circuit SPC3, as Figure 14 shown, and the spaced area 42 in the first sub-pixel driving circuit SPC1 and the fourth sub-pixel driving circuit SPC4 is larger than the space in the second sub-pixel driving circuit SPC2 and the third sub-pixel driving circuit SPC3, which is beneficial for forming vias at the spaced area 42 in the first sub-pixel driving circuit SPC1 and the fourth sub-pixel driving circuit SPC4 later. A notch area 43 is provided in the middle of the second capacitor electrode CstE2 of the second sub-pixel driving circuit SPC2 and the third sub-pixel driving circuit SPC3, and there is no active material layer 40 in the spaced area 42 and the notch area 43. In some embodiments, as Figure 11 combined Figure 14 shown, the pattern of the active material layer 40 in the first sub-pixel driving circuit SPC1 and the pattern of the active material layer 40 in the fourth sub-pixel driving circuit SPC4 are substantially mirror-symmetrical with respect to the position of the subsequently formed detection line SL, and the pattern of the active material layer 40 in the second sub-pixel driving circuit SPC2 and the pattern of the active material layer 40 in the third sub-pixel driving circuit SPC3 are substantially mirror-symmetrical with respect to the position of the subsequently formed detection line SL. After this patterning process, the pattern of the active material layer 40 is formed in the display area DA and not in the light-transmitting area TA, and the light-transmitting area TA includes the substrate 10 and the first insulating layer 30 provided on the substrate 10.

[0117] Figure 16 Schematic plan view of a single pixel after forming a pattern of a second metal layer during the manufacturing process of a transparent display panel according to some embodiments of the present disclosure, Figure 17 is Figure 16 Schematic cross-sectional structure view along line A-A in Figure 16 and 17 As shown in Figure 16 and Figure 20 shown, a pattern of the second metal layer 60 is then formed, including: depositing a second insulating film and a second metal film in sequence on the substrate 10 having the aforementioned pattern, patterning the second insulating film and the second metal film through a lithography process to form a pattern of the second insulating layer 50 and a pattern of the second metal layer 60 disposed on the second insulating layer 50. In some embodiments, the pattern of the second insulating layer 50 and the pattern of the second metal layer 60 are formed using the same mask and have the same pattern. The pattern of the second metal layer 60 includes first gate lines GL1, second gate lines GL2, first power connection lines VDDLS, first auxiliary lines 62, second auxiliary lines 63 formed corresponding to each pixel P, and gates (also referred to as first gates T1g) of switching transistors T1, gates (also referred to as second gates T2g) of driving transistors T2, and gates (also referred to as third gates T3g) of detection transistors T3 formed in each sub-pixel driving circuit. The pattern of the second metal layer 60 further includes first gate connection lines 64 and second gate connection lines 65 formed in each sub-pixel driving circuit. As shown in

[0118] The first gate T1g extends along the first direction X and straddles the first active layer T1a, and is electrically connected to the first gate line GL1 through a first gate connection line 64 extending along the second direction Y. Specifically, the first gate T1g includes a connection end T1g1 and a free end T1g2, and the first gate connection line 64 includes a first end 641 and a second end 642. The first end 641 of the first gate connection line 64 is electrically connected to the first gate line GL1, and the second end 642 of the first gate connection line 64 is electrically connected to the connection end T1g1 of the first gate T1g. In some embodiments, the first gate T1g1, the first gate connection line 64, and the first gate line GL1 are an integral structure. The second gate T2g extends along the first direction X, straddles the second active layer T2a, and has an overlapping region with the second capacitive electrode CstE2. The third gate T3g extends along the first direction X, straddles the third active layer T3a, and is electrically connected to the second gate line GL2 through a second gate connection line 65 extending along the second direction Y. Specifically, the third gate T3g includes a connection end T3g1 and a free end T3g2, and the second gate connection line 65 includes a first end 651 and a second end 652. The first end 651 of the second gate connection line 65 is electrically connected to the second gate line GL2, and the second end 652 of the second gate connection line 65 is electrically connected to the connection end T3g1 of the third gate T3g. In some embodiments, the third gate T3g, the second gate connection line 65, and the second gate line GL2 are an integral structure.

[0119] The first auxiliary line 62 is formed in the region where the second power supply line VSSL is located, extends along the second direction Y, and is configured to electrically connect the subsequently formed second power supply line VSSL. Thus, the subsequently formed second power supply line VSSL is arranged in parallel with the first auxiliary line 62 through vias, thereby effectively reducing the impedance of the second power supply line VSSL. In some embodiments, in the second direction Y, the first auxiliary line 62 is located between the first gate T1g and the third gate T3g. Those skilled in the art can understand that the first auxiliary line 62 is not necessary, and in some embodiments, the first auxiliary line 62 can be omitted.

[0120] The second auxiliary line 63 is formed in the region where the first power supply line VDDL is located, extends along the second direction Y, and is configured to electrically connect the subsequently formed first power supply line VDDL. Thus, the subsequently formed first power supply line VDDL is arranged in parallel with the second auxiliary line 63 through vias, thereby effectively reducing the impedance of the first power supply line VDDL. In some embodiments, in the second direction Y, the second auxiliary line 63 is located between the first gate T1g and the third gate T3g. Those skilled in the art can understand that the second auxiliary line 63 is not necessary, and in some embodiments, the second auxiliary line 63 can be omitted.

[0121] The first power connection line VDDLS extends along the first direction X and straddles four sub-pixel driving circuits, and is configured to be electrically connected to the first power line VDDL formed subsequently. In some embodiments, the first power connection line VDDLS may be electrically connected to the second auxiliary line 63, and the two are, for example, an integral structure.

[0122] As Figure 17 shown, the pattern of the second insulating layer 50 is the same as the pattern of the second metal layer 60, that is, the second insulating layer 50 is located below the second metal layer 60, and there is no second insulating layer 50 in the area outside the second metal layer 60. As Figure 16 shown, except for the first power connection line VDDLS, the pattern of the second metal layer in the first sub-pixel driving circuit SPCI and the pattern of the second metal layer in the fourth sub-pixel driving circuit SPC4 are substantially mirror-symmetrical with respect to the position of the subsequently formed detection line SL, and the pattern of the second metal layer in the second sub-pixel driving circuit SPC2 and the pattern of the second metal layer in the third sub-pixel driving circuit SPC3 are substantially mirror-symmetrical with respect to the position of the subsequently formed detection line SL.

[0123] In some embodiments, this process further includes a conductorization process. The conductorization process is to perform plasma processing using the pattern of the second metal layer 60 including the first gate T1g, the second gate T2g, and the third gate T3g as a mask after forming the pattern of the second metal layer 60. The active material layer 40 in the areas blocked by the first gate T1g, the second gate T2g, and the third gate T3g (i.e., the area where the active material layer 40 overlaps with the first gate T1g, the second gate T2g, and the third gate T3g) serves as the channel region of the transistor respectively. The active material layer 40 in the area not blocked by the second metal layer 60 is conductorized to form a conductorized second capacitor electrode CstE2 and a conductorized source-drain region. After this patterning process, the pattern of the second metal layer 60 is formed in the display area DA and not in the light-transmitting area TA. The light-transmitting area TA includes the substrate 10 and the first insulating layer 30 provided on the substrate 10.

[0124] Figure 18 FIG. is a schematic plan view of a single pixel after forming the pattern of the third insulating layer in the manufacturing process of a transparent display panel according to some embodiments of the present disclosure. Figure 19 is Figure 18 a schematic cross-sectional structure along line A-A in Figure 18 and Figure 19As shown, a pattern of the third insulating layer 70 is then formed. Forming the pattern of the third insulating layer 70 includes: depositing a third insulating thin film on the substrate 10 having the aforementioned pattern formed thereon, patterning the third insulating thin film through a patterning process to form a pattern of the third insulating layer 70 covering the aforementioned structure, and a plurality of vias are formed in the third insulating layer 70. The plurality of vias include: a first via V1 and a second via V2 on both sides of the first gate T1g, a third via V3 and a fourth via V4 on both sides of the second gate T2g, a fifth via V5 and a sixth via V6 on both sides of the third gate T3g, a seventh via at the overlapping position of the detection connection line SLS and the detection line, an eighth via V8 at the overlapping position of the detection connection line SLS and the drain of the detection transistor T3, a ninth via V9 at the junction of the second gate T2g and the second capacitor electrode CstE2, a tenth via V10 at the position of the shielding layer 21 not covered by the active material layer 40, such as at the position of the spacer region 42 or the notch region 43, and a fourteenth via V14. A plurality of eleventh vias V11 are located at the position of the first auxiliary line 62, and a plurality of twelfth vias V12 are located at the position of the second auxiliary line 63.

[0125] The third insulating layer 70 within the first vias V1 and the second vias V2 is etched away, exposing the surfaces at both ends of the first active layer T1a. The third vias V3 are provided at the junction of the first power connection line VDDLS and the second active layer T2a. The third insulating layer 70 within the third vias V3 is etched away, simultaneously exposing the surface of the second active layer T2a and the surface of the first power connection line VDDLS. The third insulating layer 70 within the fourth vias V4 is etched away, exposing the surface of the second active layer T2a. The third insulating layer 70 within the fifth vias V5 and the sixth vias V6 is etched away, exposing the surfaces at both ends of the third active layer T3a. The seventh vias V7 are located at the position where the detection connection line SLS overlaps with the subsequently formed detection line SL. An eighth via V8 is formed within each sub-pixel driving circuit. The first insulating layer 30 and the third insulating layer 70 within the seventh vias V7 and the eighth vias V8 are etched away, exposing the surface of the detection connection line SLS. The ninth vias V9 are located at the junction of the second gate T2g and the second capacitor electrode CstE2. The third insulating layer 70 within the ninth vias V9 is etched away, exposing the surface of the second gate T2g and the surface of the second capacitor electrode CstE2. The orthographic projection of the tenth vias V10 in the first sub-pixel driving circuit SPC1 and the fourth sub-pixel driving circuit SPC4 on the substrate 10 is located within the orthographic projection on the substrate 10 of the spaced area 42 between the second capacitor electrode CstE2 and the third active layer T3a. The orthographic projection of the tenth vias V10 in the second sub-pixel driving circuit SPC2 and the third sub-pixel driving circuit SPC3 on the substrate is located within the orthographic projection on the substrate 10 of the notch area 43 in the middle of the second capacitor electrode CstE2. The first insulating layer 30 and the third insulating layer 70 within the tenth vias V10 are etched away, exposing the surface of the shielding layer 21.

[0126] The third insulating layer 70 within the fourteenth via V14 is etched away to expose the first insulating layer 30. The fourteenth via V14 is designed for process symmetry and is formed only in the second sub-pixel driving circuit SPC2 and the third sub-pixel driving circuit SPC3. The orthographic projection of the fourteenth via V14 on the substrate 10 is located within the orthographic projection of the notch region 43 in the middle of the second capacitive electrode CstE2 on the substrate 10, and it does not exist in the first sub-pixel driving circuit SPCI and the fourth sub-pixel driving circuit SPC4. In subsequent processes, a thirteenth via V13 for connecting to the anode is formed in each sub-pixel driving circuit. In the first sub-pixel driving circuit SPCI and the fourth sub-pixel driving circuit SPC4, the subsequently formed thirteenth via V13 covers the sixth via V6 that only penetrates the third insulating layer 70 to form a nested via, while in the second sub-pixel driving circuit SPC2 and the third sub-pixel driving circuit SPC3, the subsequently formed thirteenth via V13 is located at the notch region 43 and is close to the tenth via V10. For the process symmetry of the sub-pixel driving circuit, a fourteenth via V14 similar to the sixth via V6 in the first sub-pixel driving circuit SPCI and the fourth sub-pixel driving circuit SPC4 is formed at the position where the thirteenth via V13 is located in the second sub-pixel driving circuit SPC2 and the third sub-pixel driving circuit SPC3, so that the subsequently formed thirteenth via V13 covers the fourteenth via V14 to form a nested via. The fourteenth via V14 is not necessary, and in some embodiments, the fourteenth via can be not provided.

[0127] The eleventh via V11 is located on the first auxiliary line 62, that is, the orthographic projections of multiple eleventh vias V11 on the substrate 10 fall within the orthographic projection of the first auxiliary line 62 on the substrate 10. The multiple eleventh vias V11 are arranged at intervals, and the third insulating layer 70 within the eleventh via V11 is etched away to expose the surface of the first auxiliary line 62.

[0128] Multiple twelfth vias V12 are located on the second auxiliary line 63, and the orthographic projections of the multiple twelfth vias V12 on the substrate 10 fall within the orthographic projection of the second auxiliary line 63 on the substrate 10. The multiple twelfth vias V12 are arranged at intervals, and the third insulating layer 70 within the twelfth via V12 is etched away to expose the surface of the second auxiliary line 63. After this patterning process, multiple via patterns are formed in the display area DA, and the light-transmitting area TA includes the first insulating layer 30 and the third insulating layer 70 stacked on the substrate 10.

[0129] Figure 11 It is a schematic plan view of a single pixel after forming the pattern of the third metal layer during the manufacturing process of a transparent display panel according to some embodiments of the present disclosure. Figure 20 is Figure 11 the cross-sectional structure schematic diagram along line A-A in Figure 11 andFigure 20 As shown, the pattern of the third metal layer 80 is then formed. Specifically, on the substrate on which the aforementioned pattern is formed, a third metal thin film is deposited, and the third metal thin film is patterned through a patterning process to form a third metal layer pattern on the third insulating layer 70. The third metal layer 80 includes: a first power supply line VDDL, a second power supply line VSSL, a detection line SL, and four data lines DL corresponding to each pixel P, and the source and drain of the switching transistor T1 formed in each sub-pixel, also referred to as the first source T1s and the first drain T1d, the source and drain of the driving transistor T2, also referred to as the second source T2s and the second drain T2d, the source and drain of the detection transistor T3, also referred to as the third source T3s and the third drain T3d, and a third capacitor electrode CstE3. Figure 20 is Figure 11 a cross-sectional schematic view along line A-A in. As Figure 11 and 20 shown, the first drain T1d and the first source T1s are respectively electrically connected to the conductive ends of the first active layer T1a on both sides of the first gate T1g through the first via V1 and the second via V2 to form the switching transistor T1. The second drain T2d and the second source T2s are respectively electrically connected to the conductive ends of the second active layer T2a on both sides of the second gate T2g through the third via V3 and the fourth via V4 to form the driving transistor T2. At the same time, the second drain T2d is also electrically connected to the first power supply connection line VDDLS through the third via V3. The third drain T3d and the third source T3s are respectively electrically connected to the conductive ends of the third active layer T3a on both sides of the third gate T3g through the fifth via V5 and the sixth via V6 to form the detection transistor T3. In addition, the third drain T3d is also electrically connected to the detection connection line SLS through the eighth via V8, and the detection line SL is electrically connected to the detection connection line SLS through the seventh via, so that the detection line is electrically connected to the drain T3d of the detection transistor T3 of each sub-pixel driving circuit. The first source T1s is also electrically connected to the second gate T2g and the second capacitor electrode CstE2 through the ninth via V9. It can be understood that at the ninth via V9 Figure 10 the first node G in. The third capacitor electrode CstE3 is electrically connected to the shielding layer 21 through the tenth via V10 and fills the fourteenth via V14. The third capacitor electrode CstE3 is electrically connected to the second source T2s and the third source T3s and can be an integral structure. The second power supply line VSSL is electrically connected to the first auxiliary line 62 through a plurality of eleventh vias V11 to reduce the transmission resistance of the second power supply line VSSL. The first power supply line VDDL is electrically connected to the second auxiliary line 63 through a plurality of twelfth vias V12 to reduce the transmission resistance of the first power supply line VDDL, and the VDD voltage signal is transmitted to the second drain T2d of the driving transistor T2 through the second auxiliary line 63 via the first power supply connection line VDDLS. AsFigure 11 As shown, the pattern of the third metal layer 80 in the first sub-pixel driving circuit SPCI and the pattern of the third metal layer 80 in the fourth sub-pixel driving circuit SPC4 are substantially mirror-symmetrical with respect to the position of the formed detection line SL. The pattern of the third metal layer 80 in the second sub-pixel driving circuit SPC2 and the pattern of the third metal layer 80 in the third sub-pixel driving circuit SPC3 are substantially mirror-symmetrical with respect to the position of the formed detection line SL.

[0130] After this patterning process, the pattern of the third metal layer 80 is formed in the display area DA and not in the light-transmitting area TA. The light-transmitting area TA includes the substrate 10 and the first insulating layer 30 and the third insulating layer 70 provided on the substrate 10.

[0131] Figure 21 FIG. is a schematic plan view of a single pixel after forming the patterns of the fourth insulating layer and the planarization layer in the manufacturing process of a transparent display panel according to some embodiments of the present disclosure. Figure 22 is Figure 21 a schematic cross-sectional structure along line A-A in FIG. Then, as Figure 21 and Figure 22 shown, the patterns of the fourth insulating layer 90 and the planarization layer 110 are formed. Specifically, on the substrate 10 having the aforementioned patterns formed thereon, a fourth insulating thin film is first deposited, and through a patterning process of the fourth insulating thin film, such as exposure, development, etching, etc., the pattern of the fourth insulating layer 90 is formed. The pattern of the fourth insulating layer 90 has vias in each pixel sub-driving circuit. Then, a planarization film is coated on the substrate 10 on which the pattern of the fourth insulating layer 90 is formed, and through a patterning process of the planarization film, such as exposure, development, etching, etc., the pattern of the planarization layer 110 is formed. The pattern of the planarization layer 110 is only provided in the display area DA of the pixel P and not in the light-transmitting area TA. The pattern of the planarization layer 110 also has vias in each pixel sub-driving circuit. In each sub-pixel driving circuit, the via of the planarization layer 110 is aligned with the via of the fourth insulating layer 90, and the two together form a thirteenth via V13 that penetrates the planarization layer 110 and the fourth insulating layer 90. The size of the thirteenth via V13 is significantly larger than other vias. In some embodiments, as Figure 21 、 22As shown, in the first sub-pixel driving circuit SPCI and the fourth sub-pixel driving circuit SPC4, the thirteenth via V13 is located at the position where the source T3s of the detection transistor T3 is located. Specifically, the thirteenth via V13 covers the sixth via V6, that is, the orthographic projection of the sixth via V6 on the substrate 10 falls within the orthographic projection of the thirteenth via V13 on the substrate 10. Thereby, the layout space can be saved, and the opening area of the subsequent formed pixel defining layer can be made as large as possible. The fourth insulating layer 90 and the planarization layer 110 in the thirteenth via V13 are etched away, exposing the surface of the source T3s of the detection transistor T3. In the second sub-pixel driving circuit SPC2 and the third sub-pixel driving circuit SPC3, the thirteenth via V13 is located at the position where the opening 43 of the second capacitor electrode CstE2 is located, adjacent to the tenth via V10. In some embodiments, the thirteenth via V13 covers the fourteenth via V14, that is, the orthographic projection of the fourteenth via V14 on the substrate 10 falls within the orthographic projection of the thirteenth via V13 on the substrate 10. Thereby, a nested via structure similar to that in the first sub-pixel driving circuit SPCI and the fourth sub-pixel driving circuit SPC4 is formed, improving the process uniformity. The fourth insulating layer 90 and the planarization layer 110 in the thirteenth via V13 are etched away, exposing the surface of the third capacitor electrode CstE3. In each sub-pixel driving circuit, the thirteenth via V13 is adjacent to the tenth via V10, and the two are aligned in the second direction Y, that is, the straight line connecting the centers of the thirteenth via V13 and the tenth via V10 is parallel to the second direction Y. In the first sub-pixel driving circuit SPCI and the fourth sub-pixel driving circuit SPC4, the thirteenth via V13 is closer to the second gate line GL2 than the tenth via V10. In the second sub-pixel driving circuit SPC2 and the third sub-pixel driving circuit SPC3, the thirteenth via V13 is farther from the second gate line GL2 than the tenth via V10. Those skilled in the art should understand that the tenth via V10 of each sub-pixel driving circuit should be shielded by the fourth insulating layer 90 and the planarization layer 110. However, in order to clearly show the positional relationship between the tenth via V10 and the thirteenth via V13, Figure 21 the tenth via V10 of each sub-pixel driving circuit is shown in a dotted pattern in Figure 21As shown, the patterns of the fourth insulating layer 90 and the planarization layer 110 in the first sub-pixel driving circuit SPC1 and the patterns of the fourth insulating layer 90 and the planarization layer 110 in the fourth sub-pixel driving circuit SPC4 are substantially mirror-symmetrical with respect to the position of the detection line SL. The patterns of the fourth insulating layer 90 and the planarization layer 110 in the second sub-pixel driving circuit SPC2 and the patterns of the fourth insulating layer 90 and the planarization layer 110 in the third sub-pixel driving circuit SPC3 are substantially mirror-symmetrical with respect to the position of the detection line SL. After this patterning process, the light-transmitting region TA includes the first insulating layer 30, the third insulating layer 70, and the fourth insulating layer 90 stacked on the substrate 10.

[0132] Figure 23 FIG. is a schematic plan view of a single pixel after forming a pattern of an anode layer during the manufacturing process of a transparent display panel according to some embodiments of the present disclosure. Figure 24 is Figure 23 a schematic cross-sectional structure diagram along line A-A in FIG. Then, as Figure 23 and Figure 24 shown, a pattern of the anode layer 120 is formed. Specifically, on the substrate having the aforementioned pattern, a conductive thin film is deposited, such as a stacked structure of aluminum, ITO, and aluminum. The transparent conductive thin film is patterned through a patterning process to form a pattern of the anode layer 120 on the planarization layer 110. The anode layer 120 includes at least anodes 1200 of light-emitting elements D of each sub-pixel, that is, a first anode 1201 of a first light-emitting element of the first sub-pixel, a second anode 1202 of a second light-emitting element of the second sub-pixel, a third anode 1203 of a third light-emitting element of the third sub-pixel, and a fourth anode 1204 of a fourth light-emitting element of the fourth sub-pixel. The source electrodes T2s of the driving transistors T2, the source electrodes T3s of the detection transistors T3, and the third capacitor electrodes CstE3 in each sub-pixel driving circuit are integrally connected. In each sub-pixel, the anode 1200 is electrically connected to this integral structure through a thirteenth via V13 (also referred to as an anode via V13 in this article) in the corresponding sub-pixel driving circuit. Thus, the electrical connection between the anode 1200 of each sub-pixel and the source electrode T2s of the driving transistor T2 of its sub-pixel driving circuit is achieved. In Figure 23 FIG., the thirteenth vias V13 of each sub-pixel driving circuit should be shielded by the anode 1200. However, in order to clearly show the positional relationship between the thirteenth via V13 and the anode 1200, Figure 23 FIG. shows the thirteenth vias V13 of each sub-pixel driving circuit in a dashed pattern. In some embodiments, all four anodes 1200 are located within the display area DA. Each anode 1200 may be rectangular, and the four anodes 1200 are arranged in a 2×2 matrix within the display area DA. In some embodiments, as Figure 23 and 24As shown, the first anode 1201 is located in the upper left corner and is electrically connected to the source electrode T3s of the detection transistor T3 of the first sub-pixel driving circuit SPCI through the thirteenth via V13 of the first sub-pixel driving circuit SPCI. The second anode 1202 is located in the lower left corner and is electrically connected to the third capacitor electrode CstE3 of the second sub-pixel driving circuit SPC2 through the thirteenth via V13 of the second sub-pixel driving circuit SPC2. The third anode 1203 is located in the lower right corner and is electrically connected to the third capacitor electrode CstE3 of the third sub-pixel driving circuit SPC3 through the thirteenth via V13 of the third sub-pixel driving circuit SPC3. The fourth anode 1204 is located in the upper right corner and is electrically connected to the source electrode T3s of the detection transistor T3 of the fourth sub-pixel driving circuit SPC4 through the thirteenth via V13 of the fourth sub-pixel driving circuit SPC4.

[0133] In some possible embodiments, the arrangement of the anodes 1200 in the display area DA can be adjusted according to actual needs, and the present disclosure does not make specific limitations here. The anode layer 120 is generally not disposed in the light-transmitting area TA to ensure the light transmittance of the light-transmitting area TA. After this patterning process, the film layer structure of the light-transmitting area TA remains unchanged.

[0134] Figure 25 FIG. is a schematic plan view of a single pixel after forming patterns of a pixel defining layer, a light-emitting material layer, a cathode, and a packaging layer during the manufacturing process of a transparent display panel according to some embodiments of the present disclosure. Figure 26 is Figure 25 a schematic cross-sectional structure view along line A-A in Figure 25 For clarity, the pixel defining layer, the light-emitting material layer, the cathode, and the packaging layer patterns are omitted, and only the opening of the pixel defining layer is shown. The pixel defining layer, the light-emitting material layer, the cathode, and the packaging layer are shown in Figure 26 FIG. Figure 25, as shown in FIG. 26, a pixel defining layer, a light-emitting material layer, a cathode, and an encapsulation layer pattern are formed. Specifically, a pixel defining film layer is coated on the substrate 10 on which the aforementioned patterns are formed, and the pattern of the pixel defining layer 130 is formed through a mask, exposure, and development process. The pixel defining layer 130 has openings 1300 corresponding to the anodes 1200 of each sub-pixel, that is, the first opening 1301, the second opening 1302, the third opening 1303, and the fourth opening 1304 corresponding to the first anode 1201, the second anode 1202, the third anode 1203, and the fourth anode 1204, respectively. The first opening 1301, the second opening 1302, the third opening 1303, and the fourth opening 1304 respectively define the light-emitting regions of the first light-emitting element, the second light-emitting element, the third light-emitting element, and the fourth light-emitting element. The orthographic projection of each opening 1300 on the substrate 10 falls within the orthographic projection of its corresponding anode 1200 on the substrate, and each opening 1300 exposes a part of its corresponding anode 1200. Subsequently, in some embodiments, a light-emitting material layer 140 is formed in the aforementioned formed openings 1300, and the light-emitting material layer 140 is electrically connected to the corresponding anode 1200. Optionally, in other embodiments, the light-emitting material layer 140 is deposited on the upper surface of the substrate 10 on which the pixel defining layer 130 having the openings 1300 is formed substantially over the entire surface, and the light-emitting material layer 140 located in the openings 1300 corresponds to the light-emitting regions of each sub-pixel. Subsequently, a cathode thin film is deposited, and the pattern of the cathode layer 150 is formed through a patterning process. The cathode layer 150 at least includes the cathodes of the light-emitting elements D of each sub-pixel, and the cathode layer 150 is electrically connected to the light-emitting material layer 140 and the second power supply line VSSL, respectively. In some embodiments, such as Figure 25 and 26As shown, the cathodes of the light-emitting elements D of each sub-pixel are of an integrated structure. In some embodiments, the cathodes of the light-emitting elements D of each sub-pixel of multiple pixels P are integrally formed, being an integrated structure that covers the light-transmitting regions TA and the display regions DA of multiple pixels P. Subsequently, a packaging layer 160 is formed on the cathode layer 150. The packaging layer 160 is, for example, a stacked structure including an inorganic material / an organic material / an inorganic material. In some embodiments, the cathode layer 150 can be electrically connected to the second power supply line VSSL in various ways, such as by laser drilling. In some embodiments, the cathode layer 150 can be electrically connected to the second power supply line VSSL through vias. An anode layer can be used in the vias to form a connection electrode to electrically connect the second power supply line VSSL and the cathode. In some embodiments, the cathode 150 substantially covers the entire surface of the substrate 10. There are peripheral wirings in the peripheral region of the display panel, and the peripheral wirings also receive the VSS voltage signal. In the peripheral region of the display panel, the cathode layer 150 is also electrically connected to the peripheral wirings. After this process, in some embodiments, the light-transmitting region TA can include the substrate 10 and the first insulating layer 30, the third insulating layer 70, the fourth insulating layer 90, the cathode layer 150, and the packaging layer 160 provided on the substrate 10. Those skilled in the art can understand that the first insulating layer 30, the third insulating layer 70, the fourth insulating layer 90, the cathode layer 150, and the packaging layer 160 in the light-transmitting region TA are not necessary. In some embodiments, in the formation processes of the above layers, the above layers in the light-transmitting region TA can be removed according to actual needs.

[0135] In some embodiments, the light-transmitting region TA of the pixel P is surrounded by its corresponding first gate line GL1, second gate line GL2, second power supply line VSSL, and the first power supply line VDDL corresponding to another pixel P adjacent to the pixel P.

[0136] Some embodiments of the present disclosure provide an electronic device, specifically a transparent electronic device, including the transparent display panel described in any of the embodiments. The transparent electronic device can be used for products or components with functions of perspective and display, such as perspective windows and vehicle windows.

[0137] The above description is only for the preferred embodiments of the present disclosure and the description of the applied technical principles. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solutions formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the technical solutions formed by mutually replacing the above features with the (but not limited to) technical features with similar functions disclosed in the present disclosure.

Claims

1. A display panel, comprising: a substrate substrate; and a plurality of pixels arranged in an array on the substrate substrate, the plurality of pixels including a first pixel and a second pixel, the first pixel includes a first light-transmitting region and a first display region arranged in sequence along a first direction, the second pixel includes a second light-transmitting region and a second display region arranged in sequence along the first direction, the first pixel and the second pixel are adjacent in a second direction substantially perpendicular to the first direction, and the first light-transmitting region and the second light-transmitting region are adjacent in the second direction; the display panel further includes: a first gate line and a second gate line, disposed between the first light-transmitting region and the second light-transmitting region adjacent in the second direction, the first gate line and the second gate line both extend along the first direction, the first light-transmitting region is adjacent to the first gate line, and the second light-transmitting region is adjacent to the second gate line; the display panel further includes a light-shielding layer extending along the first direction and located between the adjacent first light-transmitting region and second light-transmitting region, a second power line, extending along the second direction, the second power line is configured to provide a constant voltage to the first pixel and the second pixel, and the light-shielding layer is electrically connected to the second power line through a via hole; the light-shielding layer extends an extension portion along the second direction from the overlapping portion with the second power line, and the orthographic projection of the via hole on the substrate substrate falls within the orthographic projection of the extension portion on the substrate substrate.

2. The display panel according to claim 1, wherein, It further includes: a wiring region, disposed between the adjacent first light-transmitting region and second light-transmitting region, the length of the wiring region in the first direction, the length of the first light-transmitting region in the first direction, and the length of the second light-transmitting region in the first direction are equal, the wiring region is aligned and adjacent to the adjacent first light-transmitting region and second light-transmitting region, and the first gate line and the second gate line both pass through the wiring region along the first direction.

3. The display panel according to claim 2, wherein, The display panel includes a planarization layer and a pixel defining layer sequentially disposed on the substrate substrate, and the orthographic projection of the planarization layer on the substrate substrate and the orthographic projection of the pixel defining layer on the substrate substrate do not overlap with any of the orthographic projection of the first light-transmitting region on the substrate substrate, the orthographic projection of the second light-transmitting region on the substrate substrate, and the orthographic projection of the wiring region on the substrate substrate.

4. The display panel according to claim 2 or 3, wherein, There is a gap between the first gate line and the second gate line, and the projection of the portion of the gap located in the wiring region on the substrate substrate falls within the orthographic projection of the light-shielding layer on the substrate substrate.

5. The display panel according to claim 4, wherein, The first gate line and the second gate line are disposed on the same layer, and the light-shielding layer is located on a different layer from the first gate line and the second gate line.

6. The display panel according to claim 5, wherein, The light-shielding layer is located on the side of the first gate line and the second gate line facing the substrate substrate.

7. The display panel according to claim 4, wherein, the width of the wiring region in the second direction is greater than or equal to the width of the light-shielding layer in the second direction.

8. The display panel according to claim 4, wherein, the length of the light-shielding layer in the first direction is greater than or equal to the length of the wiring region in the first direction.

9. The display panel according to claim 4, wherein, The orthographic projection of the light-shielding layer on the substrate does not overlap with the orthographic projection of the first light-transmitting region on the substrate and also does not overlap with the orthographic projection of the second light-transmitting region on the substrate.

10. The display panel according to claim 4, wherein the material of the light-shielding layer is an opaque metal material.

11. The display panel according to claim 4, further comprising: a gate insulating layer disposed on a side of the first gate line and the second gate line facing the substrate and located on a side of the light-shielding layer away from the substrate, wherein within the routing region, the gate insulating layer includes a first portion and a second portion, the orthographic projection of the first portion on the substrate coincides with the orthographic projection of the first gate line on the substrate, and the orthographic projection of the second portion on the substrate coincides with the orthographic projection of the second gate line on the substrate.

12. The display panel according to claim 1, wherein the extension extends from the overlapping portion of the light-shielding layer and the second power supply line toward the first pixel.

13. The display panel according to claim 1, wherein the extension extends from the overlapping portion of the light-shielding layer and the second power supply line toward the second pixel.

14. The display panel according to claim 1, wherein, The second power supply line provides a VSS voltage signal.

15. The display panel according to any one of claims 1-3, wherein the first pixel further includes a sub-pixel driving circuit located within the first display region, the second pixel further includes a sub-pixel driving circuit located within the second display region, the first gate line is electrically connected to the sub-pixel driving circuit of the first pixel to provide a first control signal to the first pixel, and the second gate line is electrically connected to the sub-pixel driving circuit of the first pixel to provide a second control signal to the second pixel.

16. The display panel according to any one of claims 1-3, wherein, The display panel is an OLED display panel.

17. An electronic device, comprising the display panel according to any one of claims 1-16.

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